Method of manufacturing shielded gate field effect transistor and semiconductor structure

Abstract

The application relates to a preparation method of a shield gate field effect transistor and a semiconductor structure. The preparation method of the shield gate field effect transistor comprises the following steps: providing a substrate; forming a first dielectric layer with a first doping concentration on the substrate, forming a second dielectric layer with a second doping concentration; forming a third dielectric layer with a third doping concentration; the thickness of the second dielectric layer is smaller than the thickness of the first dielectric layer and the third dielectric layer, and the second doping concentration is smaller than the first doping concentration and the third doping concentration; opening a groove, forming a fourth dielectric layer in the groove, forming a source polysilicon and a gate polysilicon; forming a first conductive type doped region and a second conductive type doped region; and forming a contact line connected with the first conductive type doped region. Thus, the peak electric field can be broken at the bottom, the on-resistance can only be slightly changed, and other process conditions can be ensured to be adjusted without affecting other performance parameters of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, in particular to a preparation method of a shielded gate field effect transistor and a semiconductor structure. Background Art

[0002] The advantages of vertical MOSFETs (trench MOS) in manufacturing, reliability, current handling capability, and cell density have proven them to be competitive candidates for various power applications. In recent years, the pressing demand for higher speed, lower cost, and higher efficiency has necessitated a better trade-off between on-resistance (Rsp) and gate charge (Qg). However, because the gate of a vertical MOSFET (trench MOS) is placed within the trench, the area directly opposite the control gate and drain is increased, resulting in a higher gate-to-drain charge (Qgd).

[0003] In practice, short-channel shielded-gate field-effect transistor (SGT MOS) devices shorten the Pbody and Npuls junction depths, reducing the area between the gate and source, as well as the gate and drain, within the device. This reduces gate-source capacitance (Cgs) and Miller capacitance (Cgd), thereby increasing the device's switching speed. However, as a MOSFET, the shortening of the Pbody and Npuls junction depths in the vertical direction of the SGT MOS is equivalent to a reduction in the size of a planar MOSFET. This results in the DIBL (Distributed Black) (DIBL) effect, which is highly susceptible to small-scale planar MOSFETs. The DIBL effect, a barrier-lowering effect introduced at the drain end, is a common problem in small-scale field-effect transistors (FETs). Summary of the Invention

[0004] Based on this, it is necessary to provide a shielded gate field effect transistor preparation method and semiconductor structure to address the problem that the short channel SGT MOS in the traditional technology is very prone to DIBL.

[0005] A method for preparing a shielded gate field effect transistor, the method comprising:

[0006] providing a substrate;

[0007] forming a first dielectric layer with a first doping concentration on the substrate, forming a second dielectric layer with a second doping concentration on the first dielectric layer; and forming a third dielectric layer with a third doping concentration on the second dielectric layer; wherein the thickness of the second dielectric layer is smaller than that of the first dielectric layer and the third dielectric layer, and the second doping concentration is smaller than the first doping concentration and the third doping concentration;

[0008] Opening a trench, forming a fourth dielectric layer in the trench, and forming source polysilicon and gate polysilicon in the fourth dielectric layer;

[0009] forming a first conductive type doped region in the third dielectric layer, and forming a second conductive type doped region on top of the first conductive type doped region by ion implantation;

[0010] A contact line is formed to connect the first conductive type doping region.

[0011] In one embodiment, forming the second conductive type doping region on top of the first conductive type doping region by ion implantation includes:

[0012] A pair of second conductive type doping regions separated by a gap are formed on top of the first conductive type doping region by ion implantation.

[0013] In one embodiment, forming a contact line to connect the first conductive type doped region includes:

[0014] forming an interlayer dielectric layer on the first conductive type doped region;

[0015] A contact line is formed, the contact line passing through the interlayer dielectric layer and a space between a pair of the second conductive type doping regions and contacting the first conductive type doping regions.

[0016] In one embodiment, the gate polysilicon is located directly above the source polysilicon with a gap therebetween.

[0017] In one embodiment, the depth of the gate polysilicon is lower than the bottom of the first conductive type doping region and higher than the top of the first dielectric layer.

[0018] In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0019] In one embodiment, the concentration difference among the second doping concentration, the first doping concentration, and the third doping concentration at least satisfies the requirement that the resistance of the second dielectric layer is greater than the resistance of the first dielectric layer and the resistance of the first conductive type doping region.

[0020] In one embodiment, the method further comprises:

[0021] A source electrode is formed, wherein the source electrode is electrically connected to the contact line.

[0022] In a second aspect, the present application also provides a semiconductor structure prepared by the method described.

[0023] In one embodiment, the semiconductor structure is applied to a voltage of 60V, wherein the thickness of the third dielectric layer is 0.6-0.8 μm, and the thickness of the second dielectric layer is 0.6-0.8 μm.

[0024] In the above-mentioned method for fabricating a shielded-gate field-effect transistor, a first dielectric layer with a first doping concentration is formed on a substrate, a second dielectric layer with a second doping concentration is formed on the first dielectric layer, and a third dielectric layer with a third doping concentration is formed on the second dielectric layer. The second doping concentration is less than the first and third doping concentrations, so that the resistance of the second dielectric layer is greater than that of the first and third dielectric layers. This ensures that the peak electric field breakdown occurs at the bottom while minimizing the change in the specific on-resistance. Furthermore, it eliminates the need to adjust other process conditions and ensures that other performance parameters of the device are not affected. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a flow chart of a method for preparing a shielded gate field effect transistor in one embodiment;

[0026] Figure 2 is a schematic diagram of forming a first dielectric layer in one embodiment;

[0027] Figure 3 A schematic diagram of forming a second dielectric layer and a first conductivity type doped region in one embodiment;

[0028] Figure 4 FIG1 is a schematic diagram of forming gate polysilicon and source polysilicon in one embodiment;

[0029] Figure 5 is a schematic diagram of forming a second conductivity type doping region in one embodiment;

[0030] Figure 6 A schematic diagram of forming an interlayer dielectric layer and a contact line in one embodiment;

[0031] Figure 7 FIG. 1 is a schematic diagram of forming a source electrode in one embodiment.

[0032] Description of reference numerals:

[0033] 1. Substrate; 2. First dielectric layer; 3. Second dielectric layer; 4. Third dielectric layer; 5. Gate polysilicon; 6. Fourth dielectric layer; 7. Source polysilicon; 8. Second conductivity type doped region; 9. Interlayer dielectric layer; 10. Contact line; 11. Source electrode. DETAILED DESCRIPTION

[0034] To make the above-mentioned objects, features, and advantages of the present invention more readily apparent, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. The following description sets forth numerous specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0035] The DIBL effect, or drain-induced barrier lowering, is an undesirable phenomenon in small field-effect transistors (FETs). The mechanism is as follows: the Pbody and Npuls junction depths shorten, meaning the channel length decreases. As the voltage applied to the drain and source increases, the depletion layers of the drain and source junctions draw closer together. This forces electric lines of force in the channel to cross from the drain to the source, lowering the source barrier height. This increases the number of electrons injected from the source into the channel, leading to increased drain current and channel leakage or premature breakdown. The shorter the channel length, the more severe the DIBL (Drain-Induced Barrier Lowering) effect. In vertical shielded-gate FETs, this is manifested as a shortened Pbody (P-body region) and Npuls (N+ doped region) junction depth, making the DIBL effect more severe.

[0036] In order to alleviate the problem of channel leakage or a significant drop in device breakdown voltage caused by the shortened Pbody and Npuls junction depths, one solution is to control the two electric field peaks of the shielded gate field-effect transistor (SGT MOS), change the charge balance conditions, reduce the electric field peak at the source PN junction, ensure that the peak electric field breaks down at the bottom, and prevent the PN junction electric field peak from being too high, causing the power lines to cross into the source region.

[0037] By controlling the two electric field peaks of the SGT MOS, the charge balance condition is changed, the electric field peak near the source PN junction is reduced, and the electric field peak near the drain is increased, causing breakdown at the bottom of the peak electric field. This prevents the PN junction electric field peak from being too high, causing the depletion region to enter the ohmic contact region.

[0038] The most common approach is to reduce the drift region doping concentration, but this significantly degrades the device's specific on-resistance. It also requires readjusting the implantation conditions for the Pbody / Nplus / CON steps.

[0039] See also Figure 1 The present application provides a method for preparing a shielded gate field effect transistor, which includes the following steps S11 to S15.

[0040] S11, such as Figure 2 As shown, a substrate 1 is provided.

[0041] Exemplarily, the substrate 1 may be a silicon substrate.

[0042] S12, such as Figure 2 and Figure 3 As shown, a first dielectric layer 2 with a first doping concentration is formed on a substrate 1, a second dielectric layer 3 with a second doping concentration is formed on the first dielectric layer 2; a third dielectric layer 4 with a third doping concentration is formed on the second dielectric layer 3; the second doping concentration is less than the first doping concentration and the third doping concentration.

[0043] Exemplarily, the first dielectric layer 2 may be an N-type epitaxial layer.

[0044] For example, doping concentration refers to the amount or concentration of a dopant (usually another element) added to a semiconductor material. Doping aims to alter the electrical conductivity of a semiconductor material, typically by adding impurity atoms with different electronic structures (e.g., phosphorus, boron, etc.). These dopants affect the material's carrier concentration (free electrons or holes), thereby adjusting the semiconductor's conductivity. Higher doping concentrations generally result in stronger semiconductor conductivity.

[0045] For example, the doping type of the first dielectric layer 2, the doping type of the second dielectric layer 3, and the doping type of the third dielectric layer 4 are the same. If the first dielectric layer is N-type doped, the second dielectric layer is also N-type doped, and the third dielectric layer is also N-type doped. If the first dielectric layer is P-type doped, the second dielectric layer is also P-type doped, and the third dielectric layer is also P-type doped.

[0046] For example, in this application, for the silicon substrate 1, P or As doping is used to realize N-type semiconductors, and B doping is used to realize P-type semiconductors. Both NMOS and PMOS will encounter problems of source-drain punchthrough and short channel leakage, so this applies not only to NMOS but also to PMOS. NMOS uses N-type epitaxy and is doped with elements such as P and As; PMOS uses P-type epitaxy and is doped with elements such as B. Because the second doping concentration is less than the first doping concentration and the third doping concentration, the resistance of the second dielectric layer 3 is less than the resistance of the first dielectric layer 2 and also less than the resistance of the third dielectric layer 4.

[0047] S13, such as Figure 4 As shown, a trench is opened, a fourth dielectric layer 6 is formed in the trench, and a source polysilicon 7 and a gate polysilicon 5 are formed in the fourth dielectric layer 6 .

[0048] By way of example, the fourth dielectric layer 6 may be an oxide layer.

[0049] A gate polysilicon 5 is located above as a control gate, and a source polysilicon 7 is located below as a shield gate. The shield gate can shield the electric field, and the shield gate is located between the control gate and the drain. The shield gate / insulating layer / semiconductor form a structure similar to a field plate. This structure can adjust the electric field distribution of the drift region. As a result, the concentration of the drift region can be increased to achieve a lower on-resistance. Therefore, compared with a conventional trench MOS, the SGT-MOS can obtain a lower on-resistance at the same breakdown voltage level.

[0050] S14, as shown in the third dielectric layer, a first conductive type doped region is formed, and a second conductive type doped region 8 is formed in the first conductive type doped region by ion implantation. Figure 5

[0051] Exemplarily, when the first dielectric layer 2 and the second dielectric layer 3 are N-type, the first conductive type doped region is P-type, a P-type body region is formed, and the second conductive type doped region 8 is N-type.

[0052] Exemplarily, the first conductive type can be P-type, and the second conductive type can be N-type. The second conductive type doped region 8 is formed by implanting P or As in the first conductive type doped region.

[0053] S15, as shown in the figure, Figure 6 a contact line 10 is formed to connect the first conductive type doped region.

[0054] Exemplarily, the contact line 10 is conductive, which can be metal.

[0055] When the SGTMOS encounters a leakage problem, the conventional solution is to reduce the entire epitaxial layer concentration while ensuring breakdown, but this brings new problems: 1. The on-resistance will increase a lot (the concentration and the on-resistance are inversely proportional); 2. Adjusting the entire epitaxial concentration, if the adjustment value is too large, it will affect the breakdown voltage.

[0056] The application uses a three-layer epitaxial layer, the concentration of the first epitaxial layer and the third epitaxial layer is unchanged, only the concentration of the second epitaxial layer is reduced, that is, the resistivity of the second epitaxial layer is increased, and the on-resistance changes less than the conventional technology; at the same time, because the thickness of the second epitaxial layer is thin, the adjustment of the concentration has less effect on the breakdown voltage.

[0057] ​In the above-described method for fabricating a shielded-gate field-effect transistor, a first dielectric layer 2 having a first doping concentration is formed on a substrate 1, a second dielectric layer 3 having a second doping concentration is formed on the first dielectric layer 2, and a third dielectric layer 4 having a third doping concentration is formed on the second dielectric layer 3. The second doping concentration is less than both the first and third doping concentrations, resulting in a greater resistance of the second dielectric layer 3 than the first and third dielectric layers 2 and 4. This ensures that the peak electric field breakdown occurs at the bottom while minimizing the change in the specific on-resistance. Furthermore, it eliminates the need to adjust other process conditions, ensuring that other device performance parameters are not affected.

[0058] In some embodiments, forming the second conductive type doping region 8 on top of the first conductive type doping region by ion implantation includes: forming a pair of second conductive type doping regions 8 separated by a gap on top of the first conductive type doping region by ion implantation.

[0059] like Figure 5 As shown, the trench divides the first conductive type doping region into two sides, and a pair of spaced second conductive type doping regions 8 are formed on each side.

[0060] In some embodiments, as Figure 6 As shown, forming a contact line 10 to connect the first conductive type doped region includes: forming an interlayer dielectric layer 9 on the first conductive type doped region; forming a contact line 10, the contact line 10 passes through the gap between the interlayer dielectric layer 9 and a pair of second conductive type doped regions 8, and contacts the first conductive type doped region.

[0061] The contact line 10 contacts the first conductive type doped region, ensuring electrical connection between the source electrode 11 and the first conductive type doped region.

[0062] In some embodiments, the gate polysilicon 5 is located directly above the source polysilicon 7 with a gap therebetween. For example, the source polysilicon 7 and the gate polysilicon 5 are separated by an insulating layer, that is, the shield gate and the control gate are separated by an insulating layer.

[0063] In some embodiments, the depth of the gate polysilicon 5 is lower than the bottom of the first conductive type doping region and higher than the top of the first dielectric layer 2. This results in better device performance.

[0064] In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. Thus, the first conductivity type doped region is P-type, and the N-type doped region is formed by implantation.

[0065] In some embodiments, the first conductive type is N type, the second conductive type is P type, and the P type doped region is formed by ion implantation on the first conductive type doped region.

[0066] In some embodiments, the concentration difference between the second doping concentration, the first doping concentration and the third doping concentration at least satisfies that the resistance of the second dielectric layer 3 is greater than the resistance of the first dielectric layer 2 and the resistance of the first conductive type doped region. In this way, it can be ensured that the peak electric field occurs at the bottom of the breakdown, solving the problem of short channel leakage, while the on-resistance will not bring huge deterioration, only a slight difference, in addition, it can also ensure that other process conditions do not need to be adjusted, and the performance parameters of the device are not affected.

[0067] In some embodiments, the method further comprises: Figure 7 As shown, the source electrode 11 is formed, and the source electrode 11 is electrically connected with the contact line 10.

[0068] The application also provides a semiconductor structure prepared by the method provided by any of the above embodiments.

[0069] In some embodiments, the thickness of the second dielectric layer 3 can be adjusted according to the actual voltage platform, for example, the semiconductor structure is applied to 60V voltage, wherein the thickness of the third dielectric layer is 0.6-0.8μm, and the thickness of the second dielectric layer 3 is 0.6-0.8μm.

[0070] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0071] In addition, the terms "first" and "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0072] In the present invention, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0073] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0074] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementation methods.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for preparing a shielded gate field effect transistor, characterized in that: The method comprises: providing a substrate; A first dielectric layer with a first doping concentration is formed on the substrate, a second dielectric layer with a second doping concentration is formed on the first dielectric layer, and a third dielectric layer with a third doping concentration is formed on the second dielectric layer; the thickness of the second dielectric layer is less than that of the first dielectric layer and the third dielectric layer, and the second doping concentration is less than the first doping concentration and the third doping concentration; the first dielectric layer is an epitaxial layer; the first dielectric layer, the second dielectric layer, and the third dielectric layer have the same doping type, which is the second conductivity type; Opening a trench, forming a fourth dielectric layer in the trench, and forming source polysilicon and gate polysilicon in the fourth dielectric layer; forming a first conductive type doped region in the third dielectric layer, and forming a second conductive type doped region on top of the first conductive type doped region by ion implantation; the first conductive type doped region is a body region; A contact line is formed to connect the first conductive type doping region.

2. The method according to claim 1, characterized in that The forming of the second conductive type doping region on top of the first conductive type doping region by ion implantation comprises: A pair of second conductive type doping regions separated by a gap are formed on top of the first conductive type doping region by ion implantation.

3. The method according to claim 2, characterized in that The forming of a contact line connecting the first conductive type doping region includes: forming an interlayer dielectric layer on the first conductive type doped region; A contact line is formed, the contact line passing through the interlayer dielectric layer and a space between a pair of the second conductive type doping regions and contacting the first conductive type doping regions.

4. The method according to claim 1, wherein The gate polysilicon is located directly above the source polysilicon, with a gap between them.

5. The method according to claim 1, wherein The depth of the gate polysilicon is lower than the bottom of the first conductive type doping region and higher than the top of the first dielectric layer.

6. The method according to claim 1, characterized in that The first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type.

7. The method according to claim 1, characterized in that The concentration difference among the second doping concentration, the first doping concentration, and the third doping concentration at least satisfies the requirement that the resistance of the second dielectric layer is greater than the resistance of the first dielectric layer and the resistance of the first conductive type doping region.

8. The method according to claim 1, characterized in that The method further comprises: A source electrode is formed, wherein the source electrode is electrically connected to the contact line.

9. A semiconductor structure, characterized in that The method is prepared by any one of claims 1 to 8.

10. The semiconductor structure according to claim 9, wherein: The semiconductor structure is applied to a voltage of 60V, wherein the thickness of the third dielectric layer is 0.6-0.8 μm, and the thickness of the second dielectric layer is 0.6-0.8 μm.

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