Pixel driving circuit, driving method thereof and display device

Abstract

The invention discloses a pixel driving circuit, a driving method thereof and a display device, and the pixel driving circuit comprises a first node control sub-circuit which is configured to provide a signal of a first initial signal end (Vinit1) for a first node (N1) under the control of a signal of a first scanning signal end (Gate1) and a signal of a second scanning signal end (Gate2), and provide a signal of a second initial signal end (Vinit2) for a second node (N1); the signal of the first node (N1) is driven by the signal of the second node (N2); the second node control sub-circuit is configured to drive a signal of a second node (N2) through a signal of a write-in signal end (WS) under the control of signals of at least one scanning signal end (Gate) and a voltage stabilizing signal end (V); the first node control sub-circuit comprises at least one capacitor, the second node control sub-circuit comprises at least two capacitors and at least one transistor, and the at least one capacitor in the first node control sub-circuit is electrically connected with the at least one transistor of the second node control sub-circuit through the at least one capacitor in the second node control sub-circuit.

Description

Pixel driving circuit and driving method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and specifically to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present invention discloses a pixel driving circuit, comprising: a first node control subcircuit, a second node control subcircuit, and a driving subcircuit;

[0006] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to provide a driving signal to the second node under the control of the signals of the first node and the third node;

[0007] The first node control subcircuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the first initial signal terminal, the first node, and the second node, respectively, and is configured to provide the signal of the first initial signal terminal to the first node under the control of the signals of the first scan signal terminal and the second scan signal terminal, and drive the signal of the first node through the signal of the second node;

[0008] The second node control subcircuit is electrically connected to at least one scan signal terminal, the second node, the voltage stabilization signal terminal, and the write signal terminal, respectively, and is configured to drive the signal of the second node through the signal of the write signal terminal under the control of the signal of the at least one scan signal terminal and the voltage stabilization signal terminal;

[0009] The write signal terminal includes: a data signal terminal and a reference signal terminal, or the write signal terminal is a data signal terminal in at least part of the time period and is a reference signal terminal in at least part of the time period;

[0010] The first node control subcircuit includes: at least one capacitor, the second node control subcircuit includes: at least two capacitors and at least one transistor, and the at least one capacitor in the first node control subcircuit is electrically connected to the at least one transistor in the second node control subcircuit through the at least one capacitor in the second node control subcircuit.

[0011] In an exemplary embodiment, the present invention further comprises: an anode reset subcircuit and a light emitting control subcircuit;

[0012] The anode reset sub-circuit is electrically connected to the third scan signal terminal, the second initial signal terminal and the fourth node respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the signal of the third scan signal terminal;

[0013] The light-emitting control subcircuit is electrically connected to the first light-emitting signal terminal, the second light-emitting signal terminal, the first power supply terminal, the second node, the third node and the fourth node, respectively, and is configured to provide the signal of the first power supply terminal to the third node and provide the signal of the second node to the fourth node under the control of the signals of the first light-emitting signal terminal and the second light-emitting signal terminal.

[0014] In an exemplary embodiment, the first node control subcircuit includes: a node reset subcircuit and a node compensation subcircuit;

[0015] The node reset sub-circuit is electrically connected to the first scan signal terminal, the first initial signal terminal and the first node respectively, and is configured to provide the signal of the first initial signal terminal to the first node under the control of the signal of the first scan signal terminal;

[0016] The node compensation subcircuit is electrically connected to the first node, the second node and the second scan signal terminal, respectively, and is configured to drive the signal of the first node through the signal of the second node under the control of the signal of the second scan signal terminal.

[0017] In an exemplary embodiment, the node reset subcircuit includes: a first transistor;

[0018] The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

[0019] In an exemplary embodiment, the node compensation subcircuit includes: a first capacitor and a second transistor;

[0020] One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the first electrode of the second transistor;

[0021] The control electrode of the second transistor is electrically connected to the second scan signal terminal, and the second electrode of the second transistor is electrically connected to the second node.

[0022] In an exemplary embodiment, the node compensation subcircuit includes: a first capacitor and a second transistor;

[0023] One end of the first capacitor is electrically connected to the second node, and the other end of the first capacitor is electrically connected to the second electrode of the second transistor;

[0024] The control electrode of the second transistor is electrically connected to the second scan signal terminal, and the first electrode of the second transistor is electrically connected to the first node.

[0025] In an exemplary embodiment, the node compensation subcircuit includes: a first capacitor, a second transistor, and a fourth capacitor;

[0026] One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the first electrode of the second transistor;

[0027] One end of the fourth capacitor is electrically connected to the second node, and the other end of the fourth capacitor is electrically connected to the second electrode of the second transistor;

[0028] The control electrode of the second transistor is electrically connected to the second scan signal terminal.

[0029] In an exemplary embodiment, the first scanning signal terminal and the second scanning signal terminal are different signal terminals, or are the same signal terminal.

[0030] In an exemplary embodiment, when the write signal terminal is a data signal terminal in at least part of the time period and a reference signal terminal in at least part of the time period, the at least one scan signal terminal includes: a fourth scan signal terminal, and the second node control sub-circuit is electrically connected to the fourth scan signal terminal, the second node, the voltage stabilization signal terminal and the write signal terminal, respectively.

[0031] In an exemplary embodiment, the second node control subcircuit includes: a second capacitor, a third capacitor, and a fourth transistor;

[0032] One end of the second capacitor is electrically connected to the voltage-stabilized signal terminal, and the other end of the second capacitor is electrically connected to the second node;

[0033] One end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the fifth node;

[0034] The control electrode of the fourth transistor is electrically connected to the fourth scan signal terminal, the first electrode of the fourth transistor is electrically connected to the write signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

[0035] In an exemplary embodiment, the third scan signal terminal and the fourth scan signal terminal are different signal terminals, or are the same signal terminal.

[0036] In an exemplary embodiment, when the write signal terminal includes: a data signal terminal and a reference signal terminal, the at least one scan signal terminal includes: a fourth scan signal terminal and a fifth scan signal terminal, and the second node control sub-circuit is electrically connected to the fourth scan signal terminal, the fifth scan signal terminal, the second node, the voltage stabilization signal terminal, the reference signal terminal and the data signal terminal, respectively.

[0037] In an exemplary embodiment, the second node control subcircuit includes: a second capacitor, a third capacitor, a fourth transistor, and an eighth transistor;

[0038] One end of the second capacitor is electrically connected to the voltage-stabilized signal terminal, and the other end of the second capacitor is electrically connected to the second node;

[0039] One end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the fifth node;

[0040] The control electrode of the fourth transistor is electrically connected to the fourth scan signal terminal, the first electrode of the fourth transistor is electrically connected to the reference signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node;

[0041] The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the data signal terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node.

[0042] In an exemplary embodiment, the third scan signal terminal, the fourth scan signal terminal, and the fifth scan signal terminal are different signal terminals.

[0043] In an exemplary embodiment, the driving subcircuit includes: a third transistor, the light emitting control subcircuit includes: a fifth transistor and a sixth transistor, and the anode reset subcircuit includes: a seventh transistor;

[0044] The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the second node;

[0045] The control electrode of the fifth transistor is electrically connected to the first light-emitting signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the third node;

[0046] The control electrode of the sixth transistor is electrically connected to the second light emitting signal terminal, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fourth node;

[0047] The control electrode of the seventh transistor is electrically connected to the third scan signal terminal, the first electrode of the seventh transistor is electrically connected to the second initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

[0048] In an exemplary embodiment, the pixel driving circuit includes a plurality of transistors, and at least one transistor in the pixel driving circuit is an N-type transistor.

[0049] In a second aspect, the present disclosure further provides a display device, comprising: the above-mentioned pixel driving circuit.

[0050] In an exemplary embodiment, the present invention further includes: a scan driving circuit, the scan driving circuit being electrically connected to the first scan signal terminal, the second scan signal terminal, the third scan signal terminal, the first light-emitting signal terminal, and the second light-emitting signal terminal, to which the pixel driving circuit is electrically connected, and being configured to provide a valid level signal to the second light-emitting signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal, and provide an invalid level signal to the first light-emitting signal terminal in a first time period; provide a valid level signal to the first light-emitting signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal, and provide an invalid level signal to the second light-emitting signal terminal in a second time period; provide a valid level signal to the third scan signal terminal, and provide an invalid level signal to the first light-emitting signal terminal, the second light-emitting signal terminal, the first scan signal terminal, and the second scan signal terminal in a third time period; and provide a valid level signal to the first light-emitting signal terminal and the second light-emitting signal terminal, and provide an invalid level signal to the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal in a fourth time period;

[0051] The first time period to the fourth time period occur sequentially, and at least two time periods from the first time period to the fourth time period do not overlap.

[0052] In an exemplary embodiment, the end time of the first time period is the start time of the second time period, the end time of the second time period is the start time of the third time period, and the end time of the third time period is the start time of the fourth time period.

[0053] In an exemplary embodiment, the scan driving circuit is also electrically connected to a fourth scan signal terminal to which the pixel driving circuit is electrically connected, and is configured to provide a valid level signal to the fourth scan signal terminal from the first time period to the third time period, and to provide an invalid level signal to the fourth scan signal terminal in the fourth time period.

[0054] In an exemplary embodiment, the scan driving circuit is also electrically connected to the fourth scan signal terminal and the fifth scan signal terminal to which the pixel driving circuit is electrically connected, and is configured to provide a valid level signal to the fourth scan signal terminal in a first time period and a second time period, and provide an invalid level signal to the fifth scan signal terminal, provide a valid level signal to the fifth scan signal terminal in a third time period, provide an invalid level signal to the fourth scan signal terminal, and provide an invalid level signal to the fourth scan signal terminal and the fifth scan signal terminal in a fourth time period.

[0055] In an exemplary embodiment, when the first scan signal terminal and the second scan signal terminal electrically connected to the pixel driving circuit are different signal terminals, the scan driving circuit includes: a first scan driving sub-circuit and a second scan driving sub-circuit;

[0056] The first scan driving sub-circuit is electrically connected to the first scan signal terminal, and the second scan driving sub-circuit is electrically connected to the second scan signal terminal.

[0057] In an exemplary embodiment, when the first scan signal terminal and the second scan signal terminal electrically connected to the pixel driving circuit are the same signal terminal, the scan driving circuit includes: a first scan driving sub-circuit;

[0058] The first scan driving sub-circuit is electrically connected to the first scan signal terminal and the second scan signal terminal respectively.

[0059] In an exemplary embodiment, when the at least one scan signal terminal electrically connected to the second node control subcircuit is a fourth scan signal terminal, and the third scan signal terminal and the fourth scan signal terminal electrically connected to the pixel driving circuit are different signal terminals, the scan driving circuit includes: a third scan driving subcircuit and a fourth scan driving subcircuit;

[0060] The third scan driving sub-circuit is electrically connected to the third scan signal terminal, and the fourth scan driving sub-circuit is electrically connected to the fourth scan signal terminal.

[0061] In an exemplary embodiment, when the at least one scan signal terminal electrically connected to the second node control subcircuit is a fourth scan signal terminal, and the third scan signal terminal and the fourth scan signal terminal electrically connected to the pixel driving circuit are the same signal terminal, the scan driving circuit includes: a third scan driving subcircuit;

[0062] The third scan driving sub-circuit is electrically connected to the third scan signal terminal and the fourth scan signal terminal respectively.

[0063] In an exemplary embodiment, when the at least one scan signal terminal electrically connected to the second node control sub-circuit is a fourth scan signal terminal and a fifth scan signal terminal, the scan driving circuit includes: a third scan driving sub-circuit, a fourth scan driving sub-circuit, and a fifth scan driving sub-circuit;

[0064] The third scan driving sub-circuit is electrically connected to the third scan signal terminal, the fourth scan driving sub-circuit is electrically connected to the fourth scan signal terminal, and the fifth scan driving sub-circuit is electrically connected to the fifth scan signal terminal.

[0065] In a third aspect, the present disclosure further provides a driving method for a pixel driving circuit, configured to drive the above-mentioned pixel driving circuit, the method comprising:

[0066] The first node control subcircuit provides the signal of the first initial signal terminal to the first node under the control of the signals of the first scan signal terminal and the second scan signal terminal, and drives the signal of the first node through the signal of the second node;

[0067] The second node control sub-circuit drives the signal of the second node through the signal of the write signal terminal under the control of the signal of at least one scan signal terminal;

[0068] The driving sub-circuit provides a driving signal to the second node under the control of the signals at the first node and the third node.

[0069] In an exemplary embodiment, further comprising:

[0070] The anode reset subcircuit provides the signal of the second initial signal terminal to the fourth node under the control of the signal of the third scan signal terminal;

[0071] Under the control of the signals at the first light-emitting signal terminal and the second light-emitting signal terminal, the light-emitting control subcircuit provides the signal at the first power supply terminal to the third node and provides the signal at the second node to the fourth node.

[0072] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0073] Summary of the Figures

[0074] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0075] FIG1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0076] FIG2 is a schematic structural diagram of a pixel driving circuit provided in an exemplary manner;

[0077] FIG3 is an equivalent circuit diagram of a node reset subcircuit;

[0078] FIG4A is an equivalent circuit diagram 1 of the node compensation subcircuit;

[0079] FIG4B is a second equivalent circuit diagram of the node compensation subcircuit;

[0080] FIG4C is a third equivalent circuit diagram of the node compensation subcircuit;

[0081] FIG5A is an equivalent circuit diagram 1 of the second node control sub-circuit;

[0082] FIG5B is a second equivalent circuit diagram of the second node control sub-circuit;

[0083] FIG6 is a partial equivalent circuit diagram of a pixel driving circuit;

[0084] FIG7 is an equivalent circuit diagram 1 of a pixel driving circuit;

[0085] FIG8 is a second equivalent circuit diagram of a pixel driving circuit;

[0086] FIG9 is a third equivalent circuit diagram of a pixel driving circuit;

[0087] FIG10 is a fourth equivalent circuit diagram of a pixel driving circuit;

[0088] FIG11 is a fifth equivalent circuit diagram of a pixel driving circuit;

[0089] FIG12 is an equivalent circuit diagram of a pixel driving circuit;

[0090] FIG13 is an operation timing diagram of the pixel driving circuit provided in FIG7 to FIG9;

[0091] FIG14 is an operation timing diagram of the pixel driving circuit provided in FIG10 to FIG12;

[0092] FIG15 is a schematic structural diagram of a display device;

[0093] FIG16 is a structural diagram of a scan drive circuit 1;

[0094] FIG17 is a second structural diagram of a scan drive circuit;

[0095] FIG18 is a third structural diagram of a scan drive circuit;

[0096] FIG19 is a fourth structural diagram of a scan drive circuit;

[0097] FIG20 is a fifth structural diagram of a scan drive circuit;

[0098] FIG21 is a sixth structural diagram of the scan drive circuit.

[0099] Details

[0100] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0101] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0102] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0103] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0104] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0105] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0106] In this specification, "connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0107] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0108] With the development of OLED display technology, oxide processes are often used in OLED display products due to their high uniformity. However, the internal compensation accuracy of pixel driver circuits made with oxide processes is not high, resulting in low stability of the pixel driver circuits.

[0109] FIG1 is a schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG1 , the pixel driving circuit provided by an embodiment of the present disclosure may include: a first node control subcircuit, a second node control subcircuit, and a driving subcircuit. The driving subcircuit is connected to a first node N1, a second node N2, and a third node N3, respectively, and is configured to provide a driving signal to the second node N2 under the control of signals from the first node N1 and the third node N3. The first node control subcircuit is connected to a first scan signal terminal Gate1, a second scan signal terminal Gate2, a first initial signal terminal Vinit1, the first node N1, and the second node N2, respectively, and is configured to provide a signal from the first initial signal terminal Vinit1 to the first node N1 under the control of signals from the first scan signal terminal Gate1 and the second scan signal terminal Gate2, and drive the signal from the first node N1 via the signal from the second node N2. The second node control subcircuit is connected to at least one scan signal terminal Gate, the second node N2, a voltage stabilization signal terminal V, and a write signal terminal WS, respectively, and is configured to drive the signal from the second node N2 via the signal from the write signal terminal WS under the control of signals from at least one scan signal terminal Gate and the voltage stabilization signal terminal V. The write signal terminal WS includes: a data signal terminal and a reference signal terminal, or the write signal terminal WS is a data signal terminal in at least a part of the time period and is a reference signal terminal in at least a part of the time period.

[0110] The first node control subcircuit in the present disclosure includes: at least one capacitor, and the second node control subcircuit includes: at least two capacitors and at least one transistor. The at least one capacitor in the first node control subcircuit is connected to the at least one transistor in the second node control subcircuit through the at least one capacitor in the second node control subcircuit, that is, the at least one capacitor in the second node control subcircuit separates the at least one capacitor in the first node control subcircuit from the at least one transistor in the second node control subcircuit.

[0111] In an exemplary embodiment, the driving sub-circuit may include a driving transistor.

[0112] In an exemplary embodiment, at least one transistor in the second node control sub-circuit may be configured to write a signal to a data signal terminal or to write a signal to a reference signal terminal.

[0113] In an exemplary embodiment, the voltage-stabilized signal terminal V may continuously provide a high-level signal or a low-level signal.

[0114] In an exemplary embodiment, the first initial signal terminal Vinit1 continuously provides a low-level signal, and the signal of the first initial signal terminal Vinit1 may be a DC signal.

[0115] In an exemplary embodiment, the reference signal terminal continuously provides a low-level signal. The signal at the reference signal terminal may be a DC signal. Exemplarily, the voltage of the signal at the reference signal terminal may be 0V.

[0116] The present disclosure can control the signal written to the second node by allocating at least two capacitors in the second node control subcircuit, and then can control the signal of the first node by the first node control subcircuit, thereby achieving compensation for the threshold voltage of the driving transistor in the driving subcircuit, which can improve the stability of the pixel driving circuit.

[0117] In an exemplary embodiment, as shown in FIG1 , the pixel driving circuit may further include: an anode reset subcircuit and a light emission control subcircuit. The anode reset subcircuit is electrically connected to the third scan signal terminal Gate3, the second initial signal terminal Vinit2, and the fourth node N4, respectively, and is configured to provide the signal of the second initial signal terminal Vinit2 to the fourth node N4 under the control of the signal of the third scan signal terminal Gate3. The light emission control subcircuit is electrically connected to the first light emission signal terminal EM1, the second light emission signal terminal EM2, the first power supply terminal VDD, the second node N2, the third node N3, and the fourth node N4, respectively, and is configured to provide the signal of the first power supply terminal VDD to the third node N3 and the signal of the second node N2 to the fourth node N4 under the control of the signals of the first light emission signal terminal EM1 and the second light emission signal terminal EM2.

[0118] In an exemplary embodiment, the pixel driving circuit is configured to drive the light emitting device L to emit light. As shown in FIG. 1 , the light emitting device L is electrically connected to the fourth node N4 and the second power supply terminal VSS, respectively.

[0119] In an exemplary embodiment, the first power supply terminal VDD continuously provides a high-level signal, and the signal of the first power supply terminal VDD is a DC signal.

[0120] In an exemplary embodiment, the second power supply terminal VSS continuously provides a low-level signal, and the signal of the second power supply terminal VSS is a DC signal.

[0121] In an exemplary embodiment, the voltage value of the signal at the second initial signal terminal Vinit2 may be lower than the voltage value of the signal at the second power supply terminal VSS, thereby preventing the light emitting device L from emitting light inadvertently and improving the reliability of the pixel driving circuit.

[0122] In an exemplary embodiment, the light emitting device L may include a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode). Exemplarily, the anode of the light emitting device L is electrically connected to the fourth node N4, and the cathode of the light emitting device L is electrically connected to the second power supply terminal VSS.

[0123] In an exemplary embodiment, the light-emitting device L may include a current-driven device, and may be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), an organic light-emitting diode (OLED), or a quantum dot light-emitting diode (QLED). A typical size (e.g., length) of a Micro LED may be less than 100 μm, for example, 10 μm to 50 μm. A typical size (e.g., length) of a Mini LED may be approximately 100 μm to 300 μm, for example, 120 μm to 260 μm.

[0124] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0125] FIG2 is a schematic diagram of the structure of a pixel driving circuit provided in an exemplary manner. As shown in FIG2 , in an exemplary embodiment, the first node control subcircuit may include: a node reset subcircuit and a node compensation subcircuit. The node reset subcircuit is electrically connected to the first scan signal terminal Gate1, the first initial signal terminal Vinit1, and the first node N1, respectively, and is configured to provide the signal of the first initial signal terminal Vinit1 to the first node N1 under the control of the signal of the first scan signal terminal Gate1; the node compensation subcircuit is electrically connected to the first node N1, the second node N2, and the second scan signal terminal Gate2, respectively, and is configured to drive the signal of the first node N1 through the signal of the second node N2 under the control of the signal of the second scan signal terminal Gate2.

[0126] In an exemplary embodiment, FIG3 is an equivalent circuit diagram of a node reset subcircuit. As shown in FIG3 , the node reset subcircuit may include a first transistor T1. A control electrode of the first transistor T1 is electrically connected to a first scan signal terminal Gate1, a first electrode of the first transistor T1 is electrically connected to a first initial signal terminal Vinit1, and a second electrode of the first transistor T1 is electrically connected to a first node N1.

[0127] FIG3 only shows an exemplary structure of the node reset subcircuit. Those skilled in the art will readily appreciate that the implementation of the node reset subcircuit is not limited thereto.

[0128] Figure 4A is an equivalent circuit diagram of a node compensation subcircuit. As shown in Figure 4A , in an exemplary embodiment, the node compensation subcircuit may include a first capacitor C1 and a second transistor T2. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, and the second electrode of the second transistor T2 is electrically connected to the second node N2.

[0129] Figure 4B is a second equivalent circuit diagram of the node compensation subcircuit. As shown in Figure 4B , in an exemplary embodiment, the node compensation subcircuit may include: a first capacitor C1 and a second transistor T2. One end of the first capacitor C1 is electrically connected to the second node N2, and the other end of the first capacitor C1 is electrically connected to the second electrode of the second transistor T2. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, and the first electrode of the second transistor T2 is electrically connected to the first node N1.

[0130] Figure 4C is a third equivalent circuit diagram of the node compensation subcircuit. As shown in Figure 4C , in an exemplary embodiment, the node compensation subcircuit includes: a first capacitor C1, a second transistor T2, and a fourth capacitor C4. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2; one end of the fourth capacitor C4 is electrically connected to the second node N2, and the other end of the fourth capacitor C4 is electrically connected to the second electrode of the second transistor T2; and the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2.

[0131] In an exemplary embodiment, a time when the signal at the first scan signal terminal Gate1 to which the pixel driving circuit is electrically connected is an active level signal and a time when the signal at the second scan signal terminal Gate2 is an active level signal at least partially overlap.

[0132] In an exemplary embodiment, the time when the signal of the first scanning signal terminal Gate1 to which the pixel driving circuit is electrically connected is the active level signal coincides with the time when the signal of the second scanning signal terminal Gate2 is the active level signal.

[0133] In an exemplary embodiment, the first scan signal terminal Gate1 and the second scan signal terminal Gate2 may be different signal terminals, or may be the same signal terminal.

[0134] FIG. 4A to FIG. 4C only show three exemplary structures of the node compensation sub-circuit. Those skilled in the art will readily appreciate that the implementation of the node compensation sub-circuit is not limited thereto.

[0135] Figure 5A is an equivalent circuit diagram 1 of the second node control subcircuit. As shown in Figure 5A, in an exemplary embodiment, when the write signal terminal WS functions as a data signal terminal during at least a portion of a time period and as a reference signal terminal during at least a portion of a time period, the at least one scan signal terminal may include a fourth scan signal terminal Gate4. The second node control subcircuit is electrically connected to the fourth scan signal terminal Gate4, the second node N2, the voltage stabilization signal terminal V, and the write signal terminal WS. The time periods when the write signal terminal WS functions as a data signal terminal and the time periods when the write signal terminal WS functions as a reference signal terminal do not overlap.

[0136] In an exemplary embodiment, as shown in FIG5A , the second node control subcircuit may include: a second capacitor C2, a third capacitor C3, and a fourth transistor T4. One end of the second capacitor C2 is electrically connected to the voltage stabilization signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2; one end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5; a control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the write signal terminal WS, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5.

[0137] In an exemplary embodiment, a time when the signal of the third scan signal terminal Gate3 to which the pixel driving circuit is electrically connected is an active level signal at least partially overlaps a time when the signal of the fourth scan signal terminal Gate4 is an active level signal.

[0138] In an exemplary embodiment, the time when the signal of the third scan signal terminal Gate3 to which the pixel driving circuit is electrically connected is the active level signal coincides with the time when the signal of the fourth scan signal terminal Gate4 is the active level signal.

[0139] In an exemplary embodiment, the time when the signal of the first scanning signal terminal Gate1 electrically connected to the pixel driving circuit is a valid level signal at least partially overlaps with the time when the signal of the third scanning signal terminal Gate3 is a valid level signal, and the time when the signal of the first scanning signal terminal Gate1 electrically connected to the pixel driving circuit is a valid level signal is within the time when the signal of the third scanning signal terminal Gate3 is a valid level signal.

[0140] In an exemplary embodiment, the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 may be different signal terminals, or may be the same signal terminal.

[0141] Figure 5B is a second equivalent circuit diagram of the second node control subcircuit. As shown in Figure 5B , in an exemplary embodiment, when the write signal terminal includes a data signal terminal Data and a reference signal terminal REF, the at least one scan signal terminal may include a fourth scan signal terminal Gate4 and a fifth scan signal terminal Gate5. The second node control subcircuit is electrically connected to the fourth scan signal terminal Gate4, the fifth scan signal terminal Gate5, the second node N2, the voltage stabilization signal terminal V, the reference signal terminal REF, and the data signal terminal Data, respectively.

[0142] In an exemplary embodiment, as shown in FIG5B , the second node control subcircuit may include: a second capacitor C2, a third capacitor C3, a fourth transistor T4, and an eighth transistor T8. One end of the second capacitor C2 is electrically connected to the voltage stabilization signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2; one end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5; a control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the reference signal terminal REF, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5; a control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the data signal terminal Data, and a second electrode of the eighth transistor T8 is electrically connected to the fifth node N5.

[0143] In an exemplary embodiment, the third scan signal terminal Gate3 , the fourth scan signal terminal Gate4 , and the fifth scan signal terminal Gate5 are different signal terminals.

[0144] In an exemplary embodiment, the time when the signal of the third scan signal terminal Gate3 electrically connected to the pixel driving circuit is a valid level signal at least partially overlaps with the time when the signal of the fourth scan signal terminal Gate4 is a valid level signal and the time when the signal of the fifth scan signal terminal Gate5 is a valid level signal, and the time when the signal of the fourth scan signal terminal Gate4 electrically connected to the pixel driving circuit is a valid level signal does not overlap with the time when the signal of the fifth scan signal terminal Gate5 is a valid level signal.

[0145] In an exemplary embodiment, the time when the signal of the fourth scanning signal terminal Gate4 electrically connected to the pixel driving circuit is a valid level signal is within the time when the signal of the third scanning signal terminal Gate3 electrically connected to the pixel driving circuit is a valid level signal, and the time when the signal of the fifth scanning signal terminal Gate5 electrically connected to the pixel driving circuit is a valid level signal is within the time when the signal of the third scanning signal terminal Gate3 electrically connected to the pixel driving circuit is a valid level signal.

[0146] In an exemplary embodiment, the start time when the signal of the third scan signal terminal Gate3 to which the pixel driving circuit is electrically connected is the start time when the signal of the fourth scan signal terminal Gate4 is the start time when the signal of the fourth scan signal terminal Gate4 is the start time when the signal of the fifth scan signal terminal Gate5 is the start time when the signal of the fifth scan signal terminal Gate5 is the start time when the signal of the third scan signal terminal Gate3 is the end time when the signal of the fifth scan signal terminal Gate5 is the end ... fourth scan signal terminal Gate4 is the end time when the signal of the fourth scan signal terminal Gate4 is the end time

[0147] In an exemplary embodiment, the time when the signal of the first scanning signal terminal Gate1 electrically connected to the pixel driving circuit is a valid level signal at least partially overlaps with the time when the signal of the third scanning signal terminal Gate3 is a valid level signal, and the time when the signal of the first scanning signal terminal Gate1 electrically connected to the pixel driving circuit is a valid level signal is within the time when the signal of the third scanning signal terminal Gate3 is a valid level signal.

[0148] In an exemplary embodiment, a time when the signal of the first scan signal terminal Gate1 to which the pixel driving circuit is electrically connected is an active level signal and a time when the signal of the fourth scan signal terminal Gate4 is an active level signal at least partially overlap.

[0149] In an exemplary embodiment, the time when the signal at the first scanning signal terminal Gate1 to which the pixel driving circuit is electrically connected is the time when the signal at the fourth scanning signal terminal Gate4 is the effective level signal coincides with the time when the signal at the first scanning signal terminal Gate1 to which the pixel driving circuit is electrically connected is the effective level signal.

[0150] FIG5A and FIG5B only show two exemplary structures of the second node control sub-circuit. Those skilled in the art will readily appreciate that the implementation of the second node control sub-circuit is not limited thereto.

[0151] Figure 6 is a partial equivalent circuit diagram of a pixel driving circuit. As shown in Figure 6 , in an exemplary embodiment, the driving subcircuit may include a third transistor T3. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The third transistor T3 serves as a driving transistor.

[0152] FIG6 only shows an exemplary structure of the driving sub-circuit. Those skilled in the art will readily appreciate that the implementation of the driving sub-circuit is not limited thereto.

[0153] As shown in FIG6 , in an exemplary embodiment, the light emission control subcircuit may include a fifth transistor T5 and a sixth transistor T6. The control electrode of the fifth transistor T5 is electrically connected to the first light emission signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the second light emission signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0154] In an exemplary embodiment, the signals at the first and second emission signal terminals EM1 and EM2 electrically connected to the pixel driving circuit are both active level signals in at least a portion of the time period and are inverted signals in at least a portion of the time period.

[0155] FIG6 only shows an exemplary structure of the light emitting control subcircuit. Those skilled in the art will readily appreciate that the implementation of the light emitting control subcircuit is not limited thereto.

[0156] As shown in FIG6 , in an exemplary embodiment, the anode reset subcircuit may include a seventh transistor T7 , wherein a control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3 , a first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2 , and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4 .

[0157] FIG6 only shows an exemplary structure of the anode reset sub-circuit. Those skilled in the art will readily appreciate that the implementation of the anode reset sub-circuit is not limited thereto.

[0158] Figure 7 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 7, in an exemplary embodiment, the first node control subcircuit includes a first transistor T1, a second transistor T2, and a first capacitor C1; the second node control subcircuit includes a fourth transistor T4, a second capacitor C2, and a third capacitor C3; the driving subcircuit includes a third transistor T3; the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6; and the anode reset subcircuit includes a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. A control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the write signal terminal WS, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. A control electrode of the fifth transistor T5 is electrically connected to the first emission signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3. A control electrode of the sixth transistor T6 is electrically connected to the second emission signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected to the second node N2, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. A control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2. One end of the second capacitor C2 is electrically connected to the voltage stabilization signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2; one end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5.

[0159] Figure 8 is a second equivalent circuit diagram of a pixel driving circuit. As shown in Figure 8 , in an exemplary embodiment, the first node control subcircuit includes a first transistor T1, a second transistor T2, and a first capacitor C1; the second node control subcircuit includes a fourth transistor T4, a second capacitor C2, and a third capacitor C3; the driving subcircuit includes a third transistor T3; the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6; and the anode reset subcircuit includes a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, and the first electrode of the second transistor T2 is electrically connected to the first node N1. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. A control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the write signal terminal WS, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. A control electrode of the fifth transistor T5 is electrically connected to the first emission signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3. A control electrode of the sixth transistor T6 is electrically connected to the second emission signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected to the second node N2, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. A control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. One end of the first capacitor C1 is electrically connected to the second node N2, and the other end of the first capacitor C1 is electrically connected to the second electrode of the second transistor T2. One end of the second capacitor C2 is electrically connected to the voltage stabilization signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2; one end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5.

[0160] Figure 9 is a third equivalent circuit diagram of a pixel driving circuit. As shown in Figure 9 , in an exemplary embodiment, the first node control subcircuit includes a first transistor T1, a second transistor T2, a first capacitor C1, and a fourth capacitor C4; the second node control subcircuit includes a fourth transistor T4, a second capacitor C2, and a third capacitor C3; the driving subcircuit includes a third transistor T3; the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6; and the anode reset subcircuit includes a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. The control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, the first electrode of the fourth transistor T4 is electrically connected to the write signal terminal WS, and the second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. The control electrode of the fifth transistor T5 is electrically connected to the first emission signal terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the third node N3. The control electrode of the sixth transistor T6 is electrically connected to the second emission signal terminal EM2, the first electrode of the sixth transistor T6 is electrically connected to the second node N2, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal terminal Vinit2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2. One end of the second capacitor C2 is electrically connected to the voltage stabilization signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2. One end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5. One end of the fourth capacitor C4 is electrically connected to the second node N2, and the other end of the fourth capacitor C4 is electrically connected to the second electrode of the second transistor T2.

[0161] In an exemplary embodiment, in the pixel driving circuits provided in FIG. 7 to FIG. 9 , the first scan signal terminal Gate1 and the second scan signal terminal Gate2 may be the same signal terminal, and the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 may be the same signal terminal.

[0162] FIG10 is a fourth equivalent circuit diagram of a pixel driving circuit. As shown in FIG10 , in an exemplary embodiment, the first node control subcircuit includes a first transistor T1, a second transistor T2, and a first capacitor C1; the second node control subcircuit includes a fourth transistor T4, an eighth transistor T8, a second capacitor C2, and a third capacitor C3; the driving subcircuit includes a third transistor T3; the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6; and the anode reset subcircuit includes a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, and the second electrode of the second transistor T2 is electrically connected to the second node N2. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. A control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the reference signal terminal REF, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. A control electrode of the fifth transistor T5 is electrically connected to the first emission signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3. A control electrode of the sixth transistor T6 is electrically connected to the second emission signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected to the second node N2, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. A control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. A control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the data signal terminal Data, and a second electrode of the eighth transistor T8 is electrically connected to the fifth node N5. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2. One end of the second capacitor C2 is electrically connected to the regulated voltage signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2. One end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5.

[0163] Figure 11 is a fifth equivalent circuit diagram of a pixel driving circuit. As shown in Figure 11 , in an exemplary embodiment, the first node control subcircuit includes a first transistor T1, a second transistor T2, and a first capacitor C1; the second node control subcircuit includes a fourth transistor T4, an eighth transistor T8, a second capacitor C2, and a third capacitor C3; the driving subcircuit includes a third transistor T3; the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6; and the anode reset subcircuit includes a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initialization signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2, and the first electrode of the second transistor T2 is electrically connected to the first node N1. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. A control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the reference signal terminal REF, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. A control electrode of the fifth transistor T5 is electrically connected to the first emission signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3. A control electrode of the sixth transistor T6 is electrically connected to the second emission signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected to the second node N2, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. A control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. A control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the data signal terminal Data, and a second electrode of the eighth transistor T8 is electrically connected to the fifth node N5. One end of the first capacitor C1 is electrically connected to the second node N2, and the other end of the first capacitor C1 is electrically connected to the second electrode of the second transistor T2. One end of the second capacitor C2 is electrically connected to the regulated voltage signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2. One end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5.

[0164] Figure 12 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 12, in an exemplary embodiment, the first node control subcircuit includes a first transistor T1, a second transistor T2, a first capacitor C1, and a fourth capacitor C4; the second node control subcircuit includes a fourth transistor T4, an eighth transistor T8, a second capacitor C2, and a third capacitor C3; the driving subcircuit includes a third transistor T3; the light emission control subcircuit includes a fifth transistor T5 and a sixth transistor T6; and the anode reset subcircuit includes a seventh transistor T7. The control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal terminal Vinit1, and the second electrode of the first transistor T1 is electrically connected to the first node N1. The control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate2. The control electrode of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the third node N3, and the second electrode of the third transistor T3 is electrically connected to the second node N2. A control electrode of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Gate4, a first electrode of the fourth transistor T4 is electrically connected to the reference signal terminal REF, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5. A control electrode of the fifth transistor T5 is electrically connected to the first emission signal terminal EM1, a first electrode of the fifth transistor T5 is electrically connected to the first power supply terminal VDD, and a second electrode of the fifth transistor T5 is electrically connected to the third node N3. A control electrode of the sixth transistor T6 is electrically connected to the second emission signal terminal EM2, a first electrode of the sixth transistor T6 is electrically connected to the second node N2, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. A control electrode of the seventh transistor T7 is electrically connected to the third scan signal terminal Gate3, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. A control electrode of the eighth transistor T8 is electrically connected to the fifth scan signal terminal Gate5, a first electrode of the eighth transistor T8 is electrically connected to the data signal terminal Data, and a second electrode of the eighth transistor T8 is electrically connected to the fifth node N5. One end of the first capacitor C1 is electrically connected to the first node N1, and the other end of the first capacitor C1 is electrically connected to the first electrode of the second transistor T2. One end of the second capacitor C2 is electrically connected to the voltage-stabilized signal terminal V, and the other end of the second capacitor C2 is electrically connected to the second node N2. One end of the third capacitor C3 is electrically connected to the second node N2, and the other end of the third capacitor C3 is electrically connected to the fifth node N5. One end of the fourth capacitor C4 is electrically connected to the second node N2, and the other end of the fourth capacitor C4 is electrically connected to the second electrode of the second transistor T2.

[0165] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0166] In an exemplary embodiment, the N-type transistor may be an oxide thin film transistor. The active layer of the oxide thin film transistor uses an oxide semiconductor (Oxide). The oxide thin film transistor has advantages such as low leakage current.

[0167] In an exemplary embodiment, the pixel driving circuit includes a plurality of transistors, and at least one transistor in the pixel driving circuit is an N-type transistor.

[0168] In an exemplary embodiment, in the pixel driving circuits provided in FIG. 7 to FIG. 9 , the first to seventh transistors T1 to T7 may be N-type transistors.

[0169] The pixel driving circuit is arranged in the display substrate, and the content displayed by the display substrate includes a plurality of display frames.

[0170] In an exemplary embodiment, Figure 13 is an operation timing diagram of the pixel driving circuit provided in Figures 7 to 9. As shown in Figure 13, within at least one display frame, the pixel driving circuit operates from a first time period t1 to a fourth time period t4.

[0171] As shown in FIG13 , in the first time period t1 , the signals of the second light-emitting signal terminal EM2 , the first scan signal terminal Gate1 , the second scan signal terminal Gate2 , the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 are valid level signals, and the signal of the first light-emitting signal terminal EM1 is an invalid level signal.

[0172] As shown in FIG13 , in the second time period t2 , the signals of the first light-emitting signal terminal EM1 , the first scan signal terminal Gate1 , the second scan signal terminal Gate2 , the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 are valid level signals, and the signal of the second light-emitting signal terminal EM2 is an invalid level signal.

[0173] As shown in Figure 13, in the third time period t3, the signals of the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 are valid level signals, and the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are invalid level signals.

[0174] As shown in FIG13 , in the fourth time period t4 , the signals of the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are valid level signals, and the signals of the first scan signal terminal Gate1 , the second scan signal terminal Gate2 , the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 are invalid level signals.

[0175] In an exemplary embodiment, the write signal terminal WS is a reference signal terminal in the first time period t1 , the second time period t2 , and the fourth time period t4 .

[0176] In an exemplary embodiment, the write signal terminal WS is a data signal terminal in the third period t3.

[0177] In an exemplary embodiment, in the pixel driving circuits provided in FIG. 10 to FIG. 12 , the first to eighth transistors T1 to T8 may be N-type transistors.

[0178] In an exemplary embodiment, Figure 14 is an operation timing diagram of the pixel driving circuit provided in Figures 10 to 12. As shown in Figure 14, within at least one display frame, the pixel driving circuit operates from a first time period t1 to a fourth time period t4.

[0179] As shown in Figure 14, in the first time period t1, the signals of the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 are valid level signals, and the signals of the first light-emitting signal terminal EM1 and the fifth scan signal terminal Gate5 are invalid level signals.

[0180] As shown in FIG14 , in the second time period t2 , the first light emitting signal terminal EM1 , the first scan signal terminal Gate1 , the second scan signal terminal Gate2 and the third scan signal terminal Gate3 are valid level signals, and the signals of the second light emitting signal terminal EM2 and the fifth scan signal terminal Gate5 are invalid level signals.

[0181] As shown in Figure 14, in the third time period t3, the signals of the third scan signal terminal Gate3 and the fifth scan signal terminal Gate5 are valid level signals, and the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are invalid level signals.

[0182] As shown in Figure 14, in the fourth time period t4, the signals of the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are valid level signals, and the signals of the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4 and the fifth scan signal terminal Gate5 are invalid level signals.

[0183] As shown in FIG13 and FIG14 , the stage where the first time period t1 is located is the first stage P1, the stage where the second time period t2 is located is the second stage P2, the stage where the third time period t3 is located is the third stage P3, and the stage where the fourth time period t4 is located is the fourth stage P4.

[0184] The following illustrates an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in Figures 7 to 9. The pixel driving circuit in Figures 7 to 9 includes 7 transistors (first transistor T1 to seventh transistor T7), Figures 7 and 8 include three capacitors (first capacitor C1 to third capacitor C3), and Figure 9 includes four capacitors (first capacitor C1 to fourth capacitor C4). All 7 transistors are N-type transistors.

[0185] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 7 to FIG. 9 may include:

[0186] In the first phase P1, or initialization phase, the signals at the second light-emitting signal terminal EM2, the first scanning signal terminal Gate1, the second scanning signal terminal Gate2, the third scanning signal terminal Gate3, and the fourth scanning signal terminal Gate4 are high-level signals, while the signal at the first light-emitting signal terminal EM1 is low-level. During this phase, the write signal terminal WS serves as the reference signal terminal. The signal at the first scanning signal terminal Gate1 is high-level, the first transistor T1 is turned on, and the signal at the first initial signal terminal Vinit1 is written to the first node N1, initializing (resetting) the signal at the first node N1 and clearing the existing charge in the first node N1. The voltage value V1 of the signal at the first node N1 is Vini1, where Vini1 is the voltage value of the signal at the first initial signal terminal Vinit1. Because the voltage values ​​of the signals at the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on during this phase. The signal at the third scan signal terminal Gate3 is high, the seventh transistor T7 is turned on, and the signal at the second initial signal terminal Vinit2 is written to the fourth node N4, initializing (resetting) the signal at the fourth node N4 and clearing the existing charge in the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vini2, where Vini2 is the voltage value of the signal at the second initial signal terminal Vinit2. The signals at the second scan signal terminal Gate2 and the second emission signal terminal EM2 are high, the second transistor T2 and the sixth transistor T6 are turned on. In this stage, the third transistor T3 is turned on, and the signal at the second initial signal terminal Vinit2 is written to the second node N2 and the third node N3, initializing (resetting) the signals at the second node N2 and the third node N3 and clearing the existing charge in the second node N2 and the third node N3. The voltage value of the signal at the second node N2 is V2 = Vini2, and the voltage value of the signal at the third node N3 is V3 = Vini2. The signal at the fourth scanning signal terminal Gate4 is high, the fourth transistor T4 is turned on, and the signal at the reference signal terminal is written to the fifth node N5, initializing (resetting) the signal at the fifth node N5 and clearing the existing charge in the fifth node N5. The voltage value V5 of the signal at the fifth node N5 is equal to Vref, where Vref is the voltage value of the signal at the reference signal terminal. The signal at the first light-emitting signal terminal EM1 is low, and the fifth transistor T5 is turned off. At this stage, the light-emitting device L does not emit light.

[0187] In the second phase P2, i.e., the threshold compensation phase, the signals at the first emission signal terminal EM1, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are high-level signals, while the signal at the second emission signal terminal EM2 is low-level. During this phase, the write signal terminal WS serves as the reference signal terminal. The signal at the first scan signal terminal Gate1 remains high-level, the first transistor T1 remains on, and the signal at the first initial signal terminal Vinit1 is continuously written to the first node N1, initializing (resetting) the signal at the first node N1 and clearing the existing charge in the first node N1. The voltage value of the signal at the first node N1 is V1 = Vini1. The signal at the third scan signal terminal Gate3 remains high-level, the seventh transistor T7 remains on, and the signal at the second initial signal terminal Vinit2 is continuously written to the fourth node N4, initializing (resetting) the signal at the fourth node N4 and clearing the existing charge in the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vini2, where Vini2 is the voltage value of the signal at the second initial signal terminal Vinit2. The signals at the second scanning signal terminal Gate2 and the first light-emitting signal terminal EM1 are high. The second transistor T2 and the fifth transistor T5 are turned on. The signal at the first power supply terminal VDD is written to the other end of the first capacitor C1 and the second node N2 through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on second transistor T2, until the voltage V2 of the signal at the second node N2 reaches Vini1 - Vth. The voltage V3 of the signal at the third node N3 reaches Vdd, where Vdd is the voltage of the first power supply terminal VDD. At this point, the first capacitor C1 stores the voltage difference Vth between the signals at the first node N1 and the second node N2. The signal at the fourth scanning signal terminal Gate4 remains high, the fourth transistor T4 remains on, and the signal at the reference signal terminal is continuously written to the fifth node N5, initializing (resetting) the signal at the fifth node N5 and clearing the existing charge in the fifth node N5. The voltage V5 of the signal at the fifth node N5 reaches Vref. The signal at the second light-emitting signal terminal EM2 is low, and the sixth transistor T6 is turned off. During this phase, the light-emitting device L does not emit light.

[0188] In the third phase P3, the data writing phase, the signals at the third scan signal terminal Gate3 and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. During this phase, the write signal terminal WS serves as the data signal terminal, which outputs a data voltage. The signal at the third scan signal terminal Gate3 remains high-level, the seventh transistor T7 remains on, and the signal at the second initial signal terminal Vinit2 is continuously written to the fourth node N4, initializing (resetting) the signal at the fourth node N4 and clearing the existing charge in the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vini2. The signal at the fourth scan signal terminal Gate4 is high, the fourth transistor T4 is turned on, and the data voltage at the data signal terminal Data is written to the fifth node N5. At this time, the voltage value V5 of the fifth node N5 is equal to Vdata, where Vdata is the data voltage. The signal at the fifth node N5 jumps from the voltage value Vdata of the current stage to the voltage value Vref of the previous stage. Therefore, under the coupling effect of the second capacitor C2 and the third capacitor C3, the signal at the second node N2 also jumps. At this time, the voltage value V2 of the signal at the second node N2 is equal to Vini1-Vth+(Vdata-Vref)*(C3 / (C2+C3)), where C2 is the capacitance value of the second capacitor C2, and C3 is the capacitance value of the third capacitor C3. The signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the first emission signal terminal EM1, and the second emission signal terminal EM2 are low, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are turned off. The first node N1 maintains the signal of the previous stage, and the third node N3 maintains the signal of the previous stage. In this stage, the light emitting device L does not emit light.

[0189] In the fourth phase P4, i.e., the light-emitting phase, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are low-level signals. During this phase, the write signal terminal WS serves as the reference signal terminal. The signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals. The fifth transistor T5 and the sixth transistor T6 are turned on. The power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light-emitting device L to emit light. The signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are low-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are turned off. The first node N1 maintains the signal from the previous phase. During this phase, the light-emitting device L emits light.

[0190] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the second node N2). Since the voltage value V1 of the signal at the first node N1 = Vini1, and the voltage value V2 of the signal at the second node N2 = Vini1-Vth+(Vdata-Vref)*(C3 / (C2+C3)), the voltage difference Vgs between the control electrode and the second electrode of the third transistor T3 satisfies: Vgs=V1-V2=Vth+(Vref-Vdata)*(C3 / (C2+C3)).

[0191] Therefore, the driving current I of the third transistor T3 satisfies: I=K*(Vgs-Vth) 2 =K*[(C3 / (C2+C3))*(Vref-Vdata)] 2 .

[0192] The driving current flowing through the third transistor T3 is also the driving current for driving the light emitting device L, and K is a constant.

[0193] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0194] The following illustrates an exemplary embodiment of the present disclosure through the working process of the pixel driving circuit illustrated in Figures 10 to 12. The pixel driving circuit in Figures 10 to 12 includes 8 transistors (first transistor T1 to eighth transistor T8), Figures 10 and 11 include three capacitors (first capacitor C1 to third capacitor C3), and Figure 12 includes four capacitors (first capacitor C1 to fourth capacitor C4). All 8 transistors are N-type transistors.

[0195] In an exemplary embodiment, the operation process of the pixel driving circuit provided in FIG. 10 to FIG. 12 may include:

[0196] In the first phase P1, i.e., the initialization phase, the signals at the second light-emitting signal terminal EM2, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the first light-emitting signal terminal EM1 and the fifth scan signal terminal Gate5 are low-level signals. The signal at the first scan signal terminal Gate1 is high-level, the first transistor T1 is turned on, and the signal at the first initial signal terminal Vinit1 is written to the first node N1, initializing (resetting) the signal at the first node N1 and clearing the existing charge in the first node N1. The voltage value V1 of the signal at the first node N1 is Vini1, where Vini1 is the voltage value of the signal at the first initial signal terminal Vinit1. Because the voltage values ​​of the signals at the first node N1 and the third node N3 are greater than the threshold voltage of the third transistor T3, the third transistor T3 is turned on during this phase. The signal at the third scanning signal terminal Gate3 is high, the seventh transistor T7 is turned on, and the signal at the second initial signal terminal Vinit2 is written to the fourth node N4, initializing (resetting) the signal at the fourth node N4 and clearing the existing charge in the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vini2, where Vini2 is the voltage value of the signal at the second initial signal terminal Vinit2. The signals at the second scanning signal terminal Gate2 and the second emission signal terminal EM2 are high, the second transistor T2 and the sixth transistor T6 are turned on. In this stage, the third transistor T3 is turned on, and the signal at the second initial signal terminal Vinit2 is written to the second node N2 and the third node N3, initializing (resetting) the signals at the second node N2 and the third node N3 and clearing the existing charge in the second node N2 and the third node N3. The voltage value of the signal at the second node N2 is V2 = Vini2, and the voltage value of the signal at the third node N3 is V3 = Vini2. The signal at the fourth scanning signal terminal Gate4 is high, the fourth transistor T4 is turned on, and the signal at the reference signal terminal REF is written to the fifth node N5, initializing (resetting) the signal at the fifth node N5 and clearing the existing charge in the fifth node N5. The voltage value V5 of the signal at the fifth node N5 is equal to Vref, where Vref is the voltage value of the signal at the reference signal terminal REF. The signals at the first light-emitting signal terminal EM1 and the fifth scanning signal terminal Gate5 are low, and the fifth transistor T5 and the eighth transistor T8 are turned off. During this stage, the light-emitting device L does not emit light.

[0197] In the second phase P2, i.e., the threshold compensation phase, the signals at the first emission signal terminal EM1, the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, and the fourth scan signal terminal Gate4 are high-level signals, while the signals at the second emission signal terminal EM2 and the fifth scan signal terminal Gate5 are low-level signals. The signal at the first scan signal terminal Gate1 remains high-level, the first transistor T1 remains on, and the signal at the first initial signal terminal Vinit1 is continuously written to the first node N1, initializing (resetting) the signal at the first node N1 and clearing the existing charge in the first node N1. The voltage value of the signal at the first node N1 is V1 = Vini1. The signal at the third scan signal terminal Gate3 remains high-level, the seventh transistor T7 remains on, and the signal at the second initial signal terminal Vinit2 is continuously written to the fourth node N4, initializing (resetting) the signal at the fourth node N4 and clearing the existing charge in the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vini2, where Vini2 is the voltage value of the signal at the second initial signal terminal Vinit2. The signals at the second scanning signal terminal Gate2 and the first luminous signal terminal EM1 are high-level signals. The second transistor T2 and the fifth transistor T5 are turned on. The signal at the first power supply terminal VDD is written to the other end of the first capacitor C1 and the second node N2 through the turned-on fifth transistor T5, the turned-on third transistor T3, and the turned-on second transistor T2, until the voltage V2 of the signal at the second node N2 reaches Vini1 - Vth. The voltage value V3 of the signal at the third node N3 is Vdd, where Vdd is the voltage value of the first power supply terminal VDD. At this time, the first capacitor C1 stores the voltage difference Vth between the signals at the first node N1 and the second node N2. The signal at the fourth scanning signal terminal Gate4 remains high-level, the fourth transistor T4 remains turned on, and the signal at the reference signal terminal REF is continuously written to the fifth node N5, initializing (resetting) the signal at the fifth node N5 and clearing the existing charge in the fifth node N5. The voltage value V5 of the signal at the fifth node N5 reaches Vref. The signals of the second light emitting signal terminal EM2 and the fifth scanning signal terminal Gate5 are low level signals, and the sixth transistor T6 and the eighth transistor T8 are turned off. In this stage, the light emitting device L does not emit light.

[0198] In the third phase P3, i.e., the data writing phase, the signals at the third scan signal terminal Gate3 and the fifth scan signal terminal Gate5 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low-level signals. During this phase, the data signal terminal Data outputs a data voltage. The signal at the third scan signal terminal Gate3 remains high-level, the seventh transistor T7 remains on, and the signal at the second initial signal terminal Vinit2 is continuously written to the fourth node N4, initializing (resetting) the signal at the fourth node N4 and clearing the existing charge in the fourth node N4. The voltage value of the signal at the fourth node N4 is V4 = Vini2. The signal at the fifth scan signal terminal Gate5 is high, the eighth transistor T8 is turned on, and the data voltage at the data signal terminal Data is written to the fifth node N5. At this time, the voltage value V5 of the fifth node N5 is equal to Vdata, where Vdata is the data voltage. The signal at the fifth node N5 jumps from the voltage value Vdata of the current stage to the voltage value Vref of the previous stage. Therefore, under the coupling effect of the second capacitor C2 and the third capacitor C3, the signal at the second node N2 also jumps. At this time, the voltage value V2 of the signal at the second node N2 is equal to Vini1-Vth+(Vdata-Vref)*(C3 / (C2+C3)), where C2 is the capacitance value of the second capacitor C2, and C3 is the capacitance value of the third capacitor C3. The signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the fourth scan signal terminal Gate4, the first light-emitting signal terminal EM1, and the second light-emitting signal terminal EM2 are low, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The first node N1 maintains the signal of the previous stage, and the third node N3 maintains the signal of the previous stage. In this stage, the light emitting device L does not emit light.

[0199] In the fourth phase P4, i.e., the light-emitting phase, the signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, while the signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals. The signals at the first light-emitting signal terminal EM1 and the second light-emitting signal terminal EM2 are high-level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply terminal VDD provides a driving voltage to the first electrode of the light-emitting device L through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the light-emitting device L to emit light. The signals at the first scan signal terminal Gate1, the second scan signal terminal Gate2, the third scan signal terminal Gate3, the fourth scan signal terminal Gate4, and the fifth scan signal terminal Gate5 are low-level signals, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are turned off. The first node N1 maintains the signal from the previous phase, and in this phase, the light-emitting device L emits light.

[0200] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its control electrode (also the first node N1) and the second electrode (also the second node N2). Since the voltage value V1 of the signal at the first node N1 = Vini1, and the voltage value V2 of the signal at the second node N2 = Vini1-Vth+(Vdata-Vref)*(C3 / (C2+C3)), the voltage difference Vgs between the control electrode and the second electrode of the third transistor T3 satisfies: Vgs=V1-V2=Vth+(Vref-Vdata)*(C3 / (C2+C3)).

[0201] Therefore, the driving current I of the third transistor T3 satisfies: I=K*(Vgs-Vth) 2 =K*[(C3 / (C2+C3))*(Vref-Vdata)] 2 .

[0202] The driving current flowing through the third transistor T3 is also the driving current for driving the light emitting device L, and K is a constant.

[0203] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0204] According to the above analysis, the present disclosure sets a second capacitor C2 and a third capacitor C3 in the second node control subcircuit, and controls the signal of the second node N2 through the coupling effect of the second capacitor C2 and the third capacitor C3, so that the driving current satisfies: I = K*[(C3 / (C2+C3))*(Vref-Vdata)] 2 , ensuring the stability of the driving current of the pixel driving circuit.

[0205] The embodiments of the present disclosure further provide a driving method for a pixel driving circuit, which is configured to drive the pixel driving circuit provided by any of the aforementioned embodiments. The driving method for the pixel driving circuit may include the following steps:

[0206] Step 100: The first node control subcircuit provides a signal from a first initial signal terminal to a first node under the control of signals from a first scan signal terminal and a second scan signal terminal, and drives the signal from the first node through the signal from the second node.

[0207] Step 200: The second node control sub-circuit drives the signal of the second node through the signal of the write signal terminal under the control of the signal of at least one scan signal terminal;

[0208] Step 300: The driving sub-circuit provides a driving signal to the second node under the control of the signals of the first node and the third node.

[0209] In an exemplary embodiment, the driving method of the pixel driving circuit may further include the following steps:

[0210] Step 400: The anode reset sub-circuit provides the signal of the second initial signal terminal to the fourth node under the control of the signal of the third scan signal terminal;

[0211] Step 500: Under the control of the signals at the first light-emitting signal terminal and the second light-emitting signal terminal, the light-emitting control subcircuit provides the signal at the first power supply terminal to the third node and provides the signal at the second node to the fourth node.

[0212] FIG15 is a schematic diagram of the structure of a display device. As shown in FIG15 , the embodiment of the present disclosure further provides a display device having a display area, wherein a plurality of pixel driving circuits P are provided in the display area.

[0213] In an exemplary embodiment, as shown in FIG15 , a display device may include a timing controller, a data driver circuit, a scan driver circuit, and a pixel array. The timing controller is electrically connected to the data driver circuit and the scan driver circuit, respectively. The data driver circuit is electrically connected to a plurality of data signal lines D, respectively. The scan driver circuit is electrically connected to a plurality of scan signal lines G, respectively. The pixel array may include a plurality of sub-pixels, at least one of which may include a circuit unit and a light-emitting device electrically connected to the circuit unit. The circuit unit may include a pixel driver circuit, and the pixel driver circuit may be electrically connected to the scan signal lines and the data signal lines, respectively. The scan signal lines are electrically connected to at least one scan signal terminal and at least one light-emitting signal terminal electrically connected to the pixel driver circuit, respectively. The data signal points are electrically connected to the data signal terminal electrically connected to the pixel driver circuit.

[0214] In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driving circuit to the data driving circuit, can provide clock signals, scanning start signals, etc. suitable for the specifications of the scanning driving circuit to the scanning driving circuit, and can provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driving circuit to the light-emitting driving circuit.

[0215] In an exemplary embodiment, the data driving circuit may generate a data voltage to be supplied to the data signal line using a grayscale value and a control signal received from the timing controller. For example, the data driving circuit may sample the grayscale value using a clock signal and apply a data voltage corresponding to the grayscale value to the data signal line in units of pixel rows.

[0216] In an exemplary embodiment, the scan driver circuit may generate a scan signal to be provided to the scan signal line by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan driver circuit may sequentially provide a scan signal having an on-level pulse to the scan signal line. For example, the scan driver circuit may be configured in the form of a shift register and may generate the scan signal by sequentially transmitting the scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal.

[0217] In an exemplary embodiment, a display device may include a plurality of pixel units arranged in a matrix, at least one of the plurality of pixel units including a first subpixel that emits light of a first color, a second subpixel that emits light of a second color, and a third subpixel that emits light of a third color. The first, second, and third subpixels each include a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first, second, and third subpixels are electrically connected to a scan signal line and a data signal line, respectively. The pixel driving circuits are configured to receive a data voltage transmitted by the data signal line under the control of at least one scan signal line and output a corresponding current to the light-emitting device. The light-emitting devices in the first, second, and third subpixels are electrically connected to the pixel driving circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuits of their respective subpixels.

[0218] In exemplary embodiments, the shape of the sub-pixels may be rectangular, diamond, pentagonal, or hexagonal.

[0219] In an exemplary embodiment, the first subpixel may be a red subpixel (R) emitting red light, the second subpixel may be a blue subpixel (B) emitting blue light, and the third subpixel may be a green subpixel (G) emitting green light.

[0220] In an exemplary embodiment, a pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a triangular arrangement, which is not limited in the present disclosure.

[0221] In an exemplary embodiment, a pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in a horizontal parallel arrangement, a vertical parallel arrangement, or a square arrangement, etc., which is not limited in the present disclosure.

[0222] The display device may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on a side of the light-emitting structure layer away from the substrate. In some possible implementations, the display device may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0223] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate, wherein the rigid substrate may be, but is not limited to, one or more of glass and conductive foil; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0224] In an exemplary embodiment, the driving structure layer may include multiple transistors and storage capacitors that constitute a pixel driving circuit, and the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer and a cathode. The anode is electrically connected to the drain electrode of the transistor therein through a via, the organic light-emitting layer is electrically connected to the anode, and the cathode is electrically connected to the organic light-emitting layer. The organic light-emitting layer emits light of corresponding color under the drive of the anode and the cathode.

[0225] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0226] In an exemplary embodiment, the touch structure layer may include a first touch insulation layer arranged on the packaging structure layer, a first touch metal layer arranged on the first touch insulation layer, a second touch insulation layer covering the first touch metal layer, a second touch metal layer arranged on the second touch insulation layer, and a touch protection layer covering the second touch metal layer. The first touch metal layer may include a plurality of bridging electrodes, the second touch metal layer may include a plurality of first touch electrodes and second touch electrodes, and the first touch electrode or the second touch electrode may be electrically connected to the bridging electrode through a via.

[0227] In an exemplary embodiment, the scan driving circuit is electrically connected to a first scan signal terminal, a second scan signal terminal, a third scan signal terminal, a first light-emitting signal terminal, and a second light-emitting signal terminal, to which the pixel driving circuit is electrically connected, and is configured to provide a valid level signal to the second light-emitting signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal, and provide a invalid level signal to the first light-emitting signal terminal during a first time period; provide a valid level signal to the first light-emitting signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal, and provide a invalid level signal to the second light-emitting signal terminal during a second time period; provide a valid level signal to the third scan signal terminal, and provide an invalid level signal to the first light-emitting signal terminal, the second light-emitting signal terminal, the first scan signal terminal, and the second scan signal terminal during a third time period; and provide a valid level signal to the first light-emitting signal terminal and the second light-emitting signal terminal, and provide an invalid level signal to the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal during a fourth time period. The first to fourth time periods occur sequentially, and at least two of the first to fourth time periods do not overlap.

[0228] In an exemplary embodiment, the end time of the first time period is the start time of the second time period, the end time of the second time period is the start time of the third time period, and the end time of the third time period is the start time of the fourth time period.

[0229] In an exemplary embodiment, the scan driving circuit is also electrically connected to the fourth scan signal terminal to which the pixel driving circuit is electrically connected, and is configured to provide a valid level signal to the fourth scan signal terminal from the first time period to the third time period, and to provide an invalid level signal to the fourth scan signal terminal in the fourth time period.

[0230] In an exemplary embodiment, the scan driving circuit is also electrically connected to the fourth scan signal terminal and the fifth scan signal terminal to which the pixel driving circuit is electrically connected, and is configured to provide a valid level signal to the fourth scan signal terminal in a first time period and a second time period, and provide an invalid level signal to the fifth scan signal terminal, provide a valid level signal to the fifth scan signal terminal in a third time period, provide an invalid level signal to the fourth scan signal terminal, and provide an invalid level signal to the fourth scan signal terminal and the fifth scan signal terminal in a fourth time period.

[0231] In an exemplary embodiment, FIG16 is a first schematic structural diagram of a scan driving circuit, FIG17 is a second schematic structural diagram of a scan driving circuit, FIG18 is a third schematic structural diagram of a scan driving circuit, FIG19 is a fourth schematic structural diagram of a scan driving circuit, FIG20 is a fifth schematic structural diagram of a scan driving circuit, and FIG21 is a sixth schematic structural diagram of a scan driving circuit. The scan driving circuit includes at least one scan driving sub-circuit.

[0232] In an exemplary embodiment, as shown in Figures 16, 18, and 20, when the first scan signal terminal and the second scan signal terminal electrically connected to the pixel driving circuit are different signal terminals, the scan driving circuit may include a first scan driving sub-circuit 11 and a second scan driving sub-circuit 12. The first scan driving sub-circuit 11 is electrically connected to the first scan signal terminal, and the second scan driving sub-circuit 12 is electrically connected to the second scan signal terminal.

[0233] In an exemplary embodiment, as shown in FIG17 , FIG19 , and FIG21 , when the first scan signal terminal and the second scan signal terminal electrically connected to the pixel driving circuit are the same signal terminal, the scan driving circuit includes a first scan driving sub-circuit 11. The first scan driving sub-circuit 11 is electrically connected to the first scan signal terminal and the second scan signal terminal, respectively.

[0234] In an exemplary embodiment, as shown in Figures 16 and 17 , when the at least one scan signal terminal electrically connected to the second node control sub-circuit is a fourth scan signal terminal, and the third scan signal terminal and the fourth scan signal terminal electrically connected to the pixel driving circuit are different signal terminals, the scan driving circuit includes a third scan driving sub-circuit 13 and a fourth scan driving sub-circuit 14. The third scan driving sub-circuit 13 is electrically connected to the third scan signal terminal, and the fourth scan driving sub-circuit 14 is electrically connected to the fourth scan signal terminal.

[0235] In an exemplary embodiment, as shown in FIG18 and FIG19 , when the at least one scan signal terminal electrically connected to the second node control subcircuit is a fourth scan signal terminal, and the third scan signal terminal and the fourth scan signal terminal electrically connected to the pixel driving circuit are the same signal terminal, the scan driving circuit includes a third scan driving subcircuit 13. The third scan driving subcircuit 13 is electrically connected to the third scan signal terminal and the fourth scan signal terminal, respectively.

[0236] In an exemplary embodiment, as shown in Figures 20 and 21, when the at least one scan signal terminal electrically connected to the second node control sub-circuit is the fourth scan signal terminal and the fifth scan signal terminal, the scan driving circuit includes: a third scan driving sub-circuit 13, a fourth scan driving sub-circuit 14, and a fifth scan driving sub-circuit 15. The third scan driving sub-circuit 13 is electrically connected to the third scan signal terminal, the fourth scan driving sub-circuit 14 is electrically connected to the fourth scan signal terminal, and the fifth scan driving sub-circuit 15 is electrically connected to the fifth scan signal terminal.

[0237] In an exemplary embodiment, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0238] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0239] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0240] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit, comprising: The first node control sub - circuit, the second node control sub - circuit, and the driving sub - circuit; The driving sub - circuit is electrically connected to the first node, the second node, and the third node respectively, and is configured to provide a driving signal to the second node under the control of the signals of the first node and the third node; The first node control sub - circuit is electrically connected to the first scan signal terminal, the second scan signal terminal, the first initial signal terminal, the first node, and the second node respectively, and is configured to provide the signal of the first initial signal terminal to the first node under the control of the signals of the first scan signal terminal and the second scan signal terminal, and drive the signal of the first node through the signal of the second node; The second node control sub - circuit is electrically connected to at least one scan signal terminal, the second node, the voltage - stabilizing signal terminal, and the write signal terminal respectively, and is configured to drive the signal of the second node through the signal of the write signal terminal under the control of the signals of the at least one scan signal terminal and the voltage - stabilizing signal terminal; The write signal terminal includes: a data signal terminal and a reference signal terminal, or the write signal terminal is a data signal terminal in at least part of the time period and a reference signal terminal in at least part of the time period; The first node control sub - circuit includes: at least one capacitor, the second node control sub - circuit includes: at least two capacitors and at least one transistor, and at least one capacitor in the first node control sub - circuit is electrically connected to at least one transistor in the second node control sub - circuit through at least one capacitor in the second node control sub - circuit; 2. The pixel driving circuit according to claim 1, further comprising: The anode reset sub - circuit and the light - emitting control sub - circuit; The anode reset sub - circuit is electrically connected to the third scan signal terminal, the second initial signal terminal, and the fourth node respectively, and is configured to provide the signal of the second initial signal terminal to the fourth node under the control of the signal of the third scan signal terminal; The light - emitting control sub - circuit is electrically connected to the first light - emitting signal terminal, the second light - emitting signal terminal, the first power supply terminal, the second node, the third node, and the fourth node respectively, and is configured to provide the signal of the first power supply terminal to the third node and the signal of the second node to the fourth node under the control of the signals of the first light - emitting signal terminal and the second light - emitting signal terminal; 3. The pixel driving circuit according to claim 1 or 2, wherein, The first node control sub - circuit includes: a node reset sub - circuit and a node compensation sub - circuit; The node reset sub - circuit is electrically connected to the first scan signal terminal, the first initial signal terminal, and the first node respectively, and is configured to provide the signal of the first initial signal terminal to the first node under the control of the signal of the first scan signal terminal; The node compensation sub - circuit is electrically connected to the first node, the second node, and the second scan signal terminal respectively, and is configured to drive the signal of the first node through the signal of the second node under the control of the signal of the second scan signal terminal; 4. The pixel driving circuit according to claim 3, wherein, The node reset sub - circuit includes: a first transistor; The control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode of the first transistor is electrically connected to the first initial signal terminal, and the second electrode of the first transistor is electrically connected to the first node.

5. The pixel driving circuit according to claim 3, wherein, The node compensation sub-circuit includes: a first capacitor and a second transistor; One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the first electrode of the second transistor; The control electrode of the second transistor is electrically connected to the second scan signal terminal, and the second electrode of the second transistor is electrically connected to the second node.

6. The pixel driving circuit according to claim 3, wherein, The node compensation sub-circuit includes: a first capacitor and a second transistor; One end of the first capacitor is electrically connected to the second node, and the other end of the first capacitor is electrically connected to the second electrode of the second transistor; The control electrode of the second transistor is electrically connected to the second scan signal terminal, and the first electrode of the second transistor is electrically connected to the first node.

7. The pixel driving circuit according to claim 3, wherein, The node compensation sub-circuit includes: a first capacitor, a second transistor, and a fourth capacitor; One end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the first electrode of the second transistor; One end of the fourth capacitor is electrically connected to the second node, and the other end of the fourth capacitor is electrically connected to the second electrode of the second transistor; The control electrode of the second transistor is electrically connected to the second scan signal terminal.

8. The pixel driving circuit according to any one of claims 3 to 7, wherein, The first scan signal terminal and the second scan signal terminal are different signal terminals or the same signal terminal.

9. The pixel driving circuit according to claim 1, any one of claims 3 to 7, wherein, When the write signal terminal is a data signal terminal in at least a partial time period and a reference signal terminal in at least a partial time period, the at least one scan signal terminal includes: a fourth scan signal terminal, and the second node control sub-circuit is respectively connected to the fourth scan signal terminal, the second node, the voltage stabilizing signal terminal, and the write signal terminal.

10. The pixel driving circuit according to claim 9, wherein, The second node control sub-circuit includes: a second capacitor, a third capacitor, and a fourth transistor; One end of the second capacitor is electrically connected to the voltage stabilizing signal terminal, and the other end of the second capacitor is electrically connected to the second node; One end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the fifth node; The control electrode of the fourth transistor is electrically connected to the fourth scan signal terminal, the first electrode of the fourth transistor is electrically connected to the write signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node.

11. The pixel driving circuit according to claim 9, wherein, The third scan signal terminal and the fourth scan signal terminal are different signal terminals or the same signal terminal.

12. The pixel driving circuit according to any one of claims 1, 3 to 7, wherein, When the write signal terminal includes a data signal terminal and a reference signal terminal, the at least one scan signal terminal includes: a fourth scan signal terminal and a fifth scan signal terminal, and the second node control sub-circuit is respectively electrically connected to the fourth scan signal terminal, the fifth scan signal terminal, the second node, the voltage stabilizing signal terminal, the reference signal terminal, and the data signal terminal.

13. The pixel driving circuit according to claim 12, wherein, The second node control sub-circuit includes: a second capacitor, a third capacitor, a fourth transistor, and an eighth transistor; One end of the second capacitor is electrically connected to the regulated voltage signal terminal, and the other end of the second capacitor is electrically connected to the second node; One end of the third capacitor is electrically connected to the second node, and the other end of the third capacitor is electrically connected to the fifth node; The control electrode of the fourth transistor is electrically connected to the fourth scan signal terminal, the first electrode of the fourth transistor is electrically connected to the reference signal terminal, and the second electrode of the fourth transistor is electrically connected to the fifth node; The control electrode of the eighth transistor is electrically connected to the fifth scan signal terminal, the first electrode of the eighth transistor is electrically connected to the data signal terminal, and the second electrode of the eighth transistor is electrically connected to the fifth node.

14. The pixel driving circuit according to claim 13, wherein, The third scan signal terminal, the fourth scan signal terminal, and the fifth scan signal terminal are different signal terminals.

15. The pixel driving circuit according to any one of claims 2, 10 and 13, wherein, The driving sub-circuit includes: a third transistor, the light emission control sub-circuit includes: a fifth transistor and a sixth transistor, and the anode reset sub-circuit includes: a seventh transistor; The control electrode of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the second node; The control electrode of the fifth transistor is electrically connected to the first light emission signal terminal, the first electrode of the fifth transistor is electrically connected to the first power supply terminal, and the second electrode of the fifth transistor is electrically connected to the third node; The control electrode of the sixth transistor is electrically connected to the second light emission signal terminal, the first electrode of the sixth transistor is electrically connected to the second node, and the second electrode of the sixth transistor is electrically connected to the fourth node; The control electrode of the seventh transistor is electrically connected to the third scan signal terminal, the first electrode of the seventh transistor is electrically connected to the second initial signal terminal, and the second electrode of the seventh transistor is electrically connected to the fourth node.

16. The pixel driving circuit according to claim 1, wherein, The pixel driving circuit includes a plurality of transistors, and at least one transistor in the pixel driving circuit is an N-type transistor.

17. A display device, comprising: The pixel driving circuit according to any one of claims 1 to 16.

18. The display device according to claim 17, further comprising: A scan driving circuit, the scan driving circuit is respectively electrically connected to the first scan signal terminal, the second scan signal terminal, the third scan signal terminal, the first light emission signal terminal, and the second light emission signal terminal electrically connected to the pixel driving circuit, and is configured to provide an effective level signal to the second light emission signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal in a first time period, provide an invalid level signal to the first light emission signal terminal, provide an effective level signal to the first light emission signal terminal, the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal in a second time period, provide an invalid level signal to the second light emission signal terminal, in a third time period, provide an effective level signal to the third scan signal terminal, provide an invalid level signal to the first light emission signal terminal, the second light emission signal terminal, the first scan signal terminal, and the second scan signal terminal, and in a fourth time period, provide an effective level signal to the first light emission signal terminal and the second light emission signal terminal, and provide an invalid level signal to the first scan signal terminal, the second scan signal terminal, and the third scan signal terminal; Among them, the first time period to the fourth time period occur in sequence, and at least two of the first time period to the fourth time period do not overlap.

19. The display device according to claim 18, wherein, The end time of the first time period is the start time of the second time period, the end time of the second time period is the start time of the third time period, and the end time of the third time period is the start time of the fourth time period.

20. The display device according to claim 18, wherein, The scan driving circuit is also electrically connected to a fourth scan signal terminal electrically connected to the pixel driving circuit, and is configured to provide an effective level signal to the fourth scan signal terminal in the first time period to the third time period, and provide an invalid level signal to the fourth scan signal terminal in the fourth time period.

21. The display device according to claim 18, wherein, The scan driving circuit is also electrically connected to a fourth scan signal terminal and a fifth scan signal terminal electrically connected to the pixel driving circuit respectively, and is configured to provide an effective level signal to the fourth scan signal terminal and an invalid level signal to the fifth scan signal terminal in the first time period and the second time period, provide an effective level signal to the fifth scan signal terminal and an invalid level signal to the fourth scan signal terminal in the third time period, and provide invalid level signals to the fourth scan signal terminal and the fifth scan signal terminal in the fourth time period.

22. The display device according to claim 18, wherein, When the first scan signal terminal and the second scan signal terminal electrically connected to the pixel driving circuit are different signal terminals, the scan driving circuit includes: a first scan driving sub-circuit and a second scan driving sub-circuit; The first scan driving sub-circuit is electrically connected to the first scan signal terminal, and the second scan driving sub-circuit is electrically connected to the second scan signal terminal.

23. The display device according to claim 18, wherein, When the first scan signal terminal and the second scan signal terminal electrically connected to the pixel driving circuit are the same signal terminal, the scan driving circuit includes: a first scan driving sub-circuit; The first scan driving sub-circuit is electrically connected to the first scan signal terminal and the second scan signal terminal respectively.

24. The display device according to claim 22 or 23, wherein, When at least one scan signal terminal electrically connected to the second node control sub-circuit is a fourth scan signal terminal, and the third scan signal terminal and the fourth scan signal terminal electrically connected to the pixel driving circuit are different signal terminals, the scan driving circuit includes: a third scan driving sub-circuit and a fourth scan driving sub-circuit; The third scan driving sub-circuit is electrically connected to the third scan signal terminal, and the fourth scan driving sub-circuit is electrically connected to the fourth scan signal terminal.

25. The display device according to claim 22 or 23, wherein, When at least one scan signal terminal electrically connected to the second node control sub-circuit is a fourth scan signal terminal, and the third scan signal terminal and the fourth scan signal terminal electrically connected to the pixel driving circuit are the same signal terminal, the scan driving circuit includes: a third scan driving sub-circuit; The third scan driving sub-circuit is electrically connected to the third scan signal terminal and the fourth scan signal terminal respectively.

26. The display device according to claim 22 or 23, wherein, When at least one scan signal terminal electrically connected to the second node control sub-circuit is a fourth scan signal terminal and a fifth scan signal terminal, the scan driving circuit includes: a third scan driving sub-circuit, a fourth scan driving sub-circuit and a fifth scan driving sub-circuit; The third scan driving sub-circuit is electrically connected to the third scan signal terminal, the fourth scan driving sub-circuit is electrically connected to the fourth scan signal terminal, and the fifth scan driving sub-circuit is electrically connected to the fifth scan signal terminal.

27. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 16, the method comprising: Under the control of the signals of the first scan signal terminal and the second scan signal terminal, the first node control sub-circuit provides the signal of the first initial signal terminal to the first node, and drives the signal of the first node through the signal of the second node; Under the control of the signal of at least one scan signal terminal, the second node control sub-circuit drives the signal of the second node through the signal of the write signal terminal; Under the control of the signals of the first node and the third node, the driving sub-circuit provides a driving signal to the second node.

28. The method according to claim 27, further comprising: Under the control of the signal of the third scan signal terminal, the anode reset sub-circuit provides the signal of the second initial signal terminal to the fourth node; Under the control of the signals of the first light-emitting signal terminal and the second light-emitting signal terminal, the light-emitting control sub-circuit provides the signal of the first power supply terminal to the third node and provides the signal of the second node to the fourth node.

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