Silicon oxide filled GST phase change shallow trench pixel level electrically controlled metasurface structure and processing method thereof

Abstract

The present application relates to a kind of silicon oxide filled GST phase transition shallow trench pixel-level electrically controlled metasurface structure and its processing method, the metasurface structure includes silicon substrate from bottom to top, silicon oxide layer and top layer ITO electrode;The shallow trench is equipped in the silicon oxide layer, and bottom layer ITO electrode and GST nanocolumn are deposited in the shallow trench from bottom to top;The GST nanocolumn is made of GST phase transition material, and is connected with bottom layer ITO electrode and top layer ITO electrode;Bottom layer ITO electrode and top layer ITO electrode are arranged orthogonally.The method of the present application optimizes the damage problem of phase transition structure caused in high-temperature deposition, plasma etching process, while optimizing process complexity and process stability, reduces the processing cost of metasurface.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of micro-nano photonics, and particularly relates to a silicon oxide filled GST (Ge2Sb2Te5) phase change shallow trench pixel-level electrically controlled metasurface structure and a processing method thereof. BACKGROUND

[0002] With the development of optoelectronic chips towards high density and multifunction, the near-infrared dynamic optical modulation technology puts forward higher requirements for the process compatibility, modulation precision and reliability of the metasurface device.

[0003] In the prior art, the electrically controlled metasurface process mainly includes the following links:

[0004] 1. Processing technology of phase change material: sputtering GST film at high substrate temperature, etching GST layer by fluorine-based or chlorine-based plasma to form isolation grooves. On the one hand, high-temperature sputtering may directly damage the pre-integrated CMOS circuit on the silicon substrate, which brings difficulties to the process compatibility of the metasurface device. On the other hand, fluorine / chlorine-based plasma etching easily leads to chemical damage of GST sidewall (such as Te element volatilization), forming amorphous-crystal mixed phase, reducing the optical response consistency, and at the same time, etching leads to reduction of the surface flatness of GST column, forming interface defects between ITO (indium tin oxide (In2O3: SnO2=9:1)) electrode and GST material, which will significantly increase the optical loss.

[0005] 2. Processing technology of interval filling layer: filling the isolation groove by chemical vapor deposition (CVD) and planarizing by chemical mechanical polishing (CMP). On the one hand, high-temperature deposition causes GST and silicon oxide interface stress mismatch, which will significantly reduce the reliability of the metasurface. On the other hand, it is difficult to achieve accurate regulation of nanoscale scale through CMP process, and the yield is low.

[0006] 3. Processing technology of electrode: traditional electrode design is mostly in global driving mode, which adopts full-area sputtering electrode process. This leads to that all GST units share the same electrical signal, and cannot realize pixel-level independent regulation. At the same time, the continuous layer introduces parasitic capacitance, causing electrical signal coupling between adjacent units.

[0007] Therefore, there is currently no suitable low-cost, low-optical-loss and high-stability pixel-level electrically controlled metasurface structure process method to solve the problems that the existing electrically controlled metasurface process lacks comprehensive consideration, ignores the chemical damage of structure sidewall caused by etching process; high-temperature deposition filling causes interface stress mismatch; multiple exposure, etching and polishing processes increase process complexity; and full-area sputtering electrode limits the degree of freedom of dynamic regulation. SUMMARY

[0008] The technical problem to be solved by the present application is to provide a silicon oxide filled GST phase change shallow trench pixel level electrically controlled metasurface structure and a processing method thereof, so as to reduce the process damage of the metasurface, reduce the processing cost of the metasurface, and realize pixel level electrical control.

[0009] The present application provides a silicon oxide filled GST phase change shallow trench pixel level electrically controlled metasurface structure, which comprises a silicon substrate, a silicon oxide layer and a top layer ITO electrode from bottom to top; a shallow trench is arranged in the silicon oxide layer, and a bottom layer ITO electrode and a GST nanocolumn are deposited in the shallow trench from bottom to top; the GST nanocolumn is made of GST phase change material and is connected with the bottom layer ITO electrode and the top layer ITO electrode; and the bottom layer ITO electrode and the top layer ITO electrode are arranged in orthogonality.

[0010] The present application also provides a processing method of the above-mentioned silicon oxide filled GST phase change shallow trench pixel level electrically controlled metasurface structure, which comprises the following steps:

[0011] S1. Processing of the silicon oxide layer

[0012] A silicon oxide layer is deposited on the surface of the silicon substrate by chemical vapor deposition (CVD), and the interface bonding strength is optimized by in-situ plasma activation technology; then a positive photoresist is spin-coated on the surface of the silicon oxide layer, and a patterned treatment is performed by using an electron beam exposure system to form a bottom layer hole array structure by exposure; then a shallow trench is etched by a reactive ion etching (RIE) process, so as to complete the processing of the silicon oxide layer;

[0013] S2. Processing of the bottom layer ITO electrode

[0014] An ITO thin film is deposited on the surface of the silicon substrate by using a magnetron sputtering process; then the silicon substrate is immersed in a de-bonding solution, and the redundant ITO thin film outside the shallow trench is peeled off by an ultrasonic assisted lift-off process to realize electrode patterning, so as to complete the processing of the bottom layer ITO electrode;

[0015] S3. Processing of the GST nanocolumn

[0016] The silicon oxide layer is deposited on the surface of the silicon substrate by the same process as step S1, a positive photoresist is spin-coated on the surface of the silicon oxide layer, a top layer hole array structure is formed by overexposure, and a shallow trench is etched; then a low-damage magnetron sputtering process is used to deposit a GST phase change material into the shallow trench, and the redundant GST phase change material outside the shallow trench is peeled off by lift-off, so as to complete the processing of the GST nanocolumn;

[0017] S4. Processing of the top layer ITO electrode

[0018] Repeat the processing procedure of the ITO electrode in step S2 to prepare the top layer ITO electrode arranged orthogonally on the surface of the silicon substrate, thereby obtaining the silicon oxide filled GST phase change shallow trench pixel-level electrically controlled metasurface structure.

[0019] Preferably, the silicon substrate is subjected to a patterned processing pretreatment by electron beam exposure-reactive plasma etching in step S1.

[0020] Preferably, the thickness of the silicon oxide layer in step S1 is 40-60 nm.

[0021] Preferably, the interface bonding strength is optimized by in-situ plasma activation technology in step S1, that is, the silicon substrate with the deposited silicon oxide layer is subjected to an oxygen plasma treatment process, high-energy oxygen plasma generated by glow discharge physically and chemically reacts with the surface of the substrate to generate high-density hydroxyl groups in-situ on the surface. This hydrophilic modification process effectively reduces the surface free energy, significantly reduces the contact angle between the photoresist and the substrate, thereby enhancing the wettability and spreadability of the photoresist on the substrate surface, and ensuring the thickness uniformity and surface flatness of the photoresist film during the spin coating process.

[0022] Preferably, the thickness of the positive photoresist in step S1 is 150-200 nm.

[0023] Preferably, the acceleration voltage of the electron beam exposure system in step S1 is 50-150 KV.

[0024] Preferably, the diameter of the circular holes in the bottom layer circular hole array in step S1 is 200-1000 nm, and the array period error is ≤±5 nm.

[0025] Preferably, the depth of the shallow trench in step S1 is 40-60 nm.

[0026] Preferably, the chamber temperature of the magnetron sputtering process in step S2 is <150°C, and the sputtering power is 5-20 W.

[0027] Preferably, the thickness of the ITO thin film in step S2 is 40-60 nm.

[0028] Preferably, the photoresist stripping solution in step S2 includes but is not limited to N-methyl pyrrolidone (NMP) based photoresist stripping solution.

[0029] Preferably, the overlaying accuracy of the top layer circular hole array in step S3 and the bottom layer circular hole array in step S1 is ≤10 nm.

[0030] Preferably, the chamber temperature of the low-damage magnetron sputtering process in step S3 is <150°C, and the sputtering power is 5-10 W.

[0031] Preferably, the GST phase change material in step S3 is Ge2Sb2Te5 phase change material.

[0032] Preferably, the thickness tolerance of the GST phase change material deposited in the shallow trench in step S3 is ±1 nm.

[0033] Preferably, the top layer ITO electrode in step S4 is perpendicular to the bottom layer ITO electrode in step S2, and the cross point spacing error is ≤20 nm.

[0034] In the present application, the super surface structure is composed of a periodic Si-ITO-GST nanocolumn-ITO array on a silicon substrate, and the gap between the array is filled with silicon oxide to realize a non-isolation groove design. Compared with conventional super surface structures, the super surface structure in the present application can realize independent addressing of pixel-level electrically controlled units, significantly improving the dynamic control ability of near-infrared light field. Through a low-temperature deposition-peeling process, the process complexity is reduced and the introduction of interface defects is avoided, significantly reducing the preparation cost and optical loss of the super surface structure. The super surface structure can be applied to the field of near-infrared dynamic imaging, and provides technical support for the integration and function reconstruction of optoelectronic chips.

[0035] Advantages

[0036] The present application provides a pixel-level electrically controlled super surface structure and a processing method thereof, which optimizes the damage of phase change structure caused by high-temperature deposition and plasma etching process, and optimizes the process complexity and process stability, thereby reducing the processing cost of the super surface. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 It is a perspective view and sectional view of the super surface structure of the present application.

[0038] Figure 2 It is a flow chart of the processing method of the super surface structure of the present application.

[0039] Figure 3 It is an SEM image of the silicon oxide layer after processing in the embodiment.

[0040] Figure 4 It is an SEM image of the GST nanocolumn after processing in the embodiment.

[0041] Figure 5 It is an SEM image of the top layer ITO electrode after processing in the embodiment.

[0042] Reference signs: 1-silicon substrate, 2-silicon oxide layer, 3-bottom layer ITO electrode, 4-GST nanocolumn, 5-top layer ITO electrode, 6-positive photoresist. DETAILED DESCRIPTION

[0043] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0044] Example

[0045] This embodiment provides a silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure, its three-dimensional and cross-sectional views are as follows: Figure 1 As shown, the metasurface structure includes a silicon substrate 1, a silicon oxide layer 2, and a top ITO electrode 5 from bottom to top. Shallow trenches are provided in the silicon oxide layer 2, and bottom ITO electrodes 3 and GST nanopillars 4 are deposited in the shallow trenches from bottom to top. The GST nanopillars 4 are made of GST phase change material and are connected to the bottom ITO electrode 3 and the top ITO electrode 5. The bottom ITO electrode 3 and the top ITO electrode 5 are orthogonally arranged.

[0046] The flowchart of the above metasurface structure fabrication method is as follows: Figure 2 As shown, the specific steps include:

[0047] S1. Processing of silicon oxide layer 2

[0048] (1) Provide a silicon substrate 1 and perform patterning pretreatment on the silicon substrate 1 by electron beam exposure-reactive plasma etching;

[0049] (2) A silicon oxide layer 2 with a thickness of 40-60 nm was deposited on the surface of silicon substrate 1 using CVD process, and the interface bonding strength was optimized by in-situ plasma activation technology;

[0050] (3) A positive photoresist 6 with a thickness of 150-200 nm is spin-coated onto the surface of silicon oxide layer 2; then, patterning is performed using an electron beam exposure system (accelerating voltage 100 kV) to expose and form a bottom circular hole array structure with a diameter of 200-1000 nm (period error ≤ ±5 nm); and shallow trenches with a depth of 40-60 nm are created by RIE process to complete the processing of silicon oxide layer 2. The bottom surface roughness of the resulting shallow trenches is <1 nm (AFM detection), and the sidewall perpendicularity is >88°. Its morphology is as follows. Figure 3 As shown, there are no burr defects at the edges;

[0051] S2. Fabrication of the bottom ITO electrode 3

[0052] (4) An ITO thin film with a thickness of 40-60 nm was deposited on the surface of silicon substrate 1 using a magnetron sputtering process with a chamber temperature of <150℃;

[0053] (5) Then the silicon substrate 1 is immersed in an N-methyl pyrrolidone-based adhesive solution, and the shallow trench outer redundant ITO film is peeled off by an ultrasonic-assisted lift-off process to realize electrode patterning, thereby completing the bottom ITO electrode 3 processing, and the appearance is as shown in Figure 4

[0054] S3. Processing of GST nanocolumn 4

[0055] (6) The same as step (2), a 40-60 nm thick silicon oxide layer 2 is deposited on the surface of the silicon substrate 1 by a CVD process;

[0056] (7) The same as step (3), a 150-200 nm thick positive photoresist 6 is spin-coated on the surface of the silicon oxide layer 2, a top layer circular hole array structure is formed by overlay exposure, the overlay accuracy with the bottom circular hole array is ≤10 nm, and a 40-60 nm deep shallow trench is formed by RIE etching;

[0057] (8) A low-damage magnetron sputtering process (chamber temperature <150℃, sputtering power 5-10 W) is used to deposit GST phase change material (thickness tolerance ±1 nm) into the shallow trench;

[0058] (9) The same as step (3), the lift-off process is performed to peel off the redundant GST phase change material outside the shallow trench, thereby completing the processing of the GST nanocolumn 4, and the appearance after peeling off is as shown in Figure 5

[0059] S4. Processing of top ITO electrode 5

[0060] (10) The ITO electrode processing process of steps (4)-(5) is repeated to prepare the top ITO electrode 5 (perpendicular to the bottom ITO electrode 3, intersection point spacing error ≤20 nm) orthogonally arranged on the surface of the silicon substrate 1, thereby obtaining a silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure.

[0061] The processing method of the silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure in the application can provide a stable independent electrically controlled environment for the phase change material structure without damaging the phase change material structure. The lift-off process for preparing the metasurface phase change unit and electrode material can reduce the complexity of the process while optimizing the optical loss caused by defects between the stacked materials.​​

Claims

1. A silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure, characterized in that, The metasurface structure comprises, from bottom to top, a silicon substrate, a silicon oxide layer, and a top ITO electrode. Shallow trenches are formed within the silicon oxide layer by etching the bottom and top circular aperture arrays created through overlay exposure. Bottom ITO electrodes and GST nanopillars are deposited within the shallow trenches from bottom to top. The GST nanopillars are fabricated using GST phase change material and are connected to the bottom and top ITO electrodes. The bottom and top ITO electrodes are orthogonally arranged. The metasurface structure consists of a periodic Si-ITO-GST nanopillar-ITO array on the silicon substrate, with the gaps between the arrays filled with silicon oxide to achieve a trenchless design.

2. A method for fabricating a silicon oxide-filled GST phase-change shallow trench pixel-level electrically controlled metasurface structure, characterized in that, Includes the following steps: S1. Processing of silicon oxide layer A silicon oxide layer was deposited on the surface of a silicon substrate using chemical vapor deposition, and the interface bonding strength was optimized by in-situ plasma activation technology. Subsequently, positive photoresist was spin-coated on the surface of the silicon oxide layer, and patterning was performed using an electron beam exposure system to expose and form the underlying circular hole array structure. Then, shallow trenches are formed by reactive ion etching, thereby completing the processing of the silicon oxide layer; S2. Fabrication of the underlying ITO electrode An ITO thin film is deposited on the surface of a silicon substrate using magnetron sputtering. The silicon substrate is then immersed in a resist remover solution, and the redundant ITO film outside the shallow trench is peeled off by an ultrasonic-assisted lift-off process to achieve electrode patterning, thereby completing the processing of the bottom ITO electrode. Fabrication of S3.GST nanopillars The same process as in step S1 is used to deposit a silicon oxide layer on the surface of the silicon substrate, spin-coat a positive photoresist on the surface of the silicon oxide layer, overlay exposure to form a top-level circular hole array structure, and then etch to form shallow trenches; subsequently, a low-damage magnetron sputtering process is used to deposit GST phase change material into the shallow trenches, and a lift-off is performed to remove redundant GST phase change material outside the shallow trenches, thereby completing the fabrication of GST nanopillars; S4. Fabrication of the top ITO electrode Repeat the processing technology of the bottom ITO electrode described in step S2 to prepare the top ITO electrode arranged orthogonally on the surface of the silicon substrate, thereby obtaining a silicon oxide-filled GST phase change shallow trench pixel-level electrically controlled metasurface structure.

3. The processing method according to claim 2, characterized in that, In step S1, the silicon substrate is pre-processed by patterning using electron beam exposure-reactive plasma etching.

4. The processing method according to claim 2, characterized in that, The thickness of the silicon oxide layer in step S1 is 40-60 nm.

5. The processing method according to claim 2, characterized in that, The thickness of the positive photoresist in step S1 is 150-200 nm; the accelerating voltage of the electron beam exposure system is 50-150 KV.

6. The processing method according to claim 2, characterized in that, The diameter of the circular holes in the bottom circular hole array described in step S1 is 200-1000nm, and the array period error is ≤±5nm; the depth of the shallow trench described in step S1 is 40-60nm.

7. The processing method according to claim 2, characterized in that, The chamber temperature of the magnetron sputtering process in step S2 is <150℃, and the sputtering power is 5-20W; the thickness of the ITO thin film is 40-60nm.

8. The processing method according to claim 2, characterized in that, The overlap accuracy between the top circular aperture array in step S3 and the bottom circular aperture array in step S1 is ≤10nm.

9. The processing method according to claim 2, characterized in that, The chamber temperature of the low-damage magnetron sputtering process described in step S3 is <150℃, and the sputtering power is 5-10W; the thickness tolerance of the GST phase change material deposited in the shallow trench in step S3 is ±1nm.

10. The processing method according to claim 2, characterized in that, The top ITO electrode in step S4 is perpendicular to the bottom ITO electrode in step S2, and the spacing error between the intersection points is ≤20nm.

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