An infrared detector

Abstract

This application provides an infrared detector, including: a signal processing integrated circuit and a storage integrated circuit; the signal processing integrated circuit and the storage integrated circuit are communicatively connected; the signal processing integrated circuit includes a readout module and a correction module; the readout module is used to acquire the analog electrical signal converted from external infrared radiation, convert the analog electrical signal into a raw digital image signal, and output the raw digital image signal to the correction module; the correction module is used to correct the raw digital image signal based on correction configuration data to obtain a corrected digital image signal; the storage integrated circuit is used to store the correction configuration data. By fabricating the correction module in the signal processing integrated circuit and then integrating the signal processing integrated circuit and the storage integrated circuit, the space occupied by the infrared sensing system can be reduced.

Description

Technical Field

[0001] This application relates to the field of infrared sensing technology, and in particular to an infrared detector. Background Technology

[0002] In existing uncooled infrared focal plane array (FLAS) sensing technologies, the non-uniformity correction circuit is characterized by numerous modules, complex structure, long computation time, and large storage space requirements. It primarily relies on an external image processor and external memory to complete the correction work. Specifically, the uncooled infrared FLAS sensor transmits the image signal to the non-uniformity correction circuit (which includes the external image processor) via a high-speed signal interface. Simultaneously, it relies on a large-capacity external memory to perform complex correction operations. The correction configuration data stored in the external memory is sent to the external image processor via another high-speed signal interface. The external image processor converts the correction configuration data and outputs it to the sensor. Based on the acquired image signal and the correction configuration data, the non-uniformity correction circuit calculates the corrected image signal and outputs it through an image output interface. This results in a separate architecture for the uncooled infrared FLAS sensor, image processor, and memory, leading to low integration and a large footprint for the infrared sensing system.

[0003] To address these issues, related technologies typically employ a stacked approach for integration. However, since the communication connection point and photosensitive surface of an uncooled infrared focal plane array sensor are on the same side, and the sensor and correction circuit have vastly different dimensions, it is difficult to integrate the uncooled infrared focal plane array sensor and the correction circuit using a stacked approach, or the cost of stacked integration is high. Summary of the Invention

[0004] The purpose of this application is to provide an infrared detector to reduce the space occupied by an infrared sensing system. The specific technical solution is as follows:

[0005] In a first aspect, embodiments of this application provide an infrared detector, the infrared detector comprising:

[0006] Signal processing integrated circuit and memory integrated circuit; the signal processing integrated circuit and the memory integrated circuit are communicatively connected.

[0007] The signal processing integrated circuit includes a readout module and a correction module; the readout module is used to acquire the analog electrical signal after conversion of external infrared radiation, convert the analog electrical signal into an original digital image signal, and output the original digital image signal to the correction module; the correction module is used to correct the original digital image signal based on correction configuration data to obtain a corrected digital image signal; the storage integrated circuit is used to store the correction configuration data.

[0008] In one possible implementation, the signal processing integrated circuit further includes a control module, a storage control module, and a clock reset control module;

[0009] The control module, the readout module, the storage control module, the correction module, and the clock reset control module are all communicatively connected to the first bus of the signal processing integrated circuit, and the readout module, the correction module, and the storage control module are all communicatively connected to the second bus of the signal processing integrated circuit.

[0010] The control module is used to control each module in the signal processing integrated circuit;

[0011] The storage control module is used to perform read and write operations on the correction configuration data in the correction module and the storage integrated circuit.

[0012] The clock reset control module is used to provide a timing reference for the signal processing integrated circuit.

[0013] In one possible implementation, the correction module is specifically configured to: receive the original digital image signal output by the readout module and the correction configuration data read by the storage control module; calculate a corrected digital image signal based on the original digital image signal and the correction configuration data through its own correction submodules; encode and output the corrected digital image signal through its own encoding output submodule; and obtain updated correction configuration data based on the corrected digital image signal and the original digital image signal.

[0014] In one possible implementation, the correction module includes an encoding output submodule and N correction submodules; where N is an integer not less than 1.

[0015] The i-th correction submodule is communicatively connected to the (i-1)-th correction submodule, and the N-th correction submodule is communicatively connected to the encoding output submodule; where i ∈ N, and i is an integer not less than 2;

[0016] The (i-1)th correction submodule outputs its processed correction result to the ith correction submodule with minimal delay.

[0017] In one possible implementation, the N correction submodules include a multiplicative correction submodule, an additive correction submodule, and a time-domain filtering submodule;

[0018] The multiplicative correction submodule is communicatively connected to the additive correction submodule, the additive correction submodule is communicatively connected to the time-domain filtering submodule, and the time-domain filtering submodule is communicatively connected to the encoding output submodule.

[0019] The multiplicative correction submodule outputs its processed correction result to the additive correction submodule with minimal delay, and the additive correction submodule outputs its processed correction result to the time-domain filtering submodule with minimal delay.

[0020] In one possible implementation, the infrared detector further includes a substrate;

[0021] The signal processing integrated circuit is disposed on the substrate, and the storage integrated circuit is disposed on the side of the signal processing integrated circuit away from the substrate;

[0022] or,

[0023] Both the signal processing integrated circuit and the storage integrated circuit are disposed on the substrate, and there is a first preset distance between the orthographic projection of the storage integrated circuit on the substrate and the orthographic projection of the signal processing integrated circuit on the substrate.

[0024] In one possible implementation, the storage integrated circuit is provided with a first communication connection point, and the signal processing integrated circuit is provided with a second communication connection point on the side away from the substrate, and the first communication connection point is connected to the second communication connection point.

[0025] In one possible implementation, the infrared detector further includes a MEMS pixel array;

[0026] The MEMS pixel array and the second communication connection point are located on the same side of the signal processing integrated circuit;

[0027] The MEMS pixel array is communicatively connected to the readout module of the signal processing integrated circuit;

[0028] The MEMS pixel array is used to convert external infrared radiation into analog electrical signals.

[0029] In one possible implementation, the orthographic projection of the MEMS pixel array and the memory integrated circuit on the substrate do not overlap, and there is a second preset distance between the orthographic projection of the memory integrated circuit on the substrate and the orthographic projection of the MEMS pixel array on the substrate.

[0030] In one possible implementation, the infrared detector further includes a cover plate structure;

[0031] The cover plate structure is disposed on the substrate, and a cavity is formed between the cover plate structure and the substrate. The signal processing integrated circuit, the MEMS pixel array and the storage integrated circuit are located in the cavity.

[0032] The cover plate structure includes an infrared light-transmitting surface and an annular protrusion, and the annular protrusion of the cover plate structure is connected to the substrate.

[0033] or,

[0034] The cover plate structure is disposed on the side of the signal processing integrated circuit away from the substrate, and a cavity is formed between the cover plate structure and the signal processing integrated circuit, and the MEMS pixel array is located in the cavity;

[0035] The cover plate structure includes an infrared-transmitting surface and an annular protrusion, and the annular protrusion of the cover plate structure is connected to the signal processing integrated circuit.

[0036] In one possible implementation, the second preset distance is not less than 1.5 times the thickness of the memory integrated circuit.

[0037] In one possible implementation, when the storage integrated circuit is disposed on the side of the signal processing integrated circuit away from the substrate, the side of the signal processing integrated circuit away from the substrate has a thermally conductive material deposition area.

[0038] Wherein, the orthographic projections of the MEMS pixel array and the thermally conductive material deposition area on the substrate do not overlap, and the orthographic projection of the storage integrated circuit on the substrate is included in the orthographic projection of the thermally conductive material deposition area on the substrate.

[0039] Beneficial effects of the embodiments in this application:

[0040] This application provides an infrared detector, comprising: a signal processing integrated circuit and a storage integrated circuit; the signal processing integrated circuit and the storage integrated circuit are communicatively connected; the signal processing integrated circuit includes a readout module and a correction module; the readout module is used to acquire the analog electrical signal converted from external infrared radiation, convert the analog electrical signal into a raw digital image signal, and output the raw digital image signal to the correction module; the correction module is used to correct the raw digital image signal based on correction configuration data to obtain a corrected digital image signal; the storage integrated circuit is used to store the correction configuration data. By fabricating the correction module in the signal processing integrated circuit and then integrating the signal processing integrated circuit and the storage integrated circuit, the space occupied by the infrared sensing system can be reduced.

[0041] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0043] Figure 1 This is a schematic diagram of a first structure of an infrared detector provided in an embodiment of this application;

[0044] Figure 2 A top view schematic diagram of the signal processing integrated circuit of the infrared detector provided in an embodiment of this application;

[0045] Figure 3 This is a schematic diagram of a second structure of the infrared detector provided in an embodiment of this application;

[0046] Figure 4 This is a schematic diagram of a business segment table and its corresponding priority table.

[0047] Figure 5 A schematic diagram illustrating the working process of the signal processing integrated circuit for the infrared detector provided in this application embodiment;

[0048] Figure 6 A schematic diagram of the arbitration logic of the read / write instruction arbitration unit;

[0049] Figure 7 A schematic diagram of a third structure (stacked structure) of the infrared detector provided in an embodiment of this application.

[0050] Figure 8 A schematic diagram of a fourth structure (stacked structure) of the infrared detector provided in an embodiment of this application.

[0051] Figure 9 A schematic diagram of the fifth structure (stacked structure) of the infrared detector provided in the embodiments of this application.

[0052] Figure 10 This is a schematic diagram of the sixth structure (stacked structure) of the infrared detector provided in the embodiments of this application. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0054] In existing uncooled infrared focal plane array (FLAS) sensing technologies, the non-uniformity correction circuit is characterized by numerous modules, complex structure, long computation time, and large storage space requirements. It primarily relies on an external image processor and external memory to complete the correction work. Specifically, the uncooled infrared FLAS sensor transmits the image signal to the non-uniformity correction circuit (which includes the external image processor) via a high-speed signal interface. Simultaneously, it relies on a large-capacity external memory to perform complex correction operations. The correction configuration data stored in the external memory is sent to the external image processor via another high-speed signal interface. The external image processor converts the correction configuration data and outputs it to the sensor. Based on the acquired image signal and the correction configuration data, the non-uniformity correction circuit calculates the corrected image signal and outputs it through an image output interface. This results in a separate architecture for the uncooled infrared FLAS sensor, image processor, and memory, leading to low integration and a large footprint for the infrared sensing system.

[0055] To address these issues, related technologies typically employ a stacked approach for integration. However, since the communication connection point and photosensitive surface of an uncooled infrared focal plane array sensor are on the same side, and the sensor and correction circuit have vastly different dimensions, it is difficult to integrate the uncooled infrared focal plane array sensor and the correction circuit using a stacked approach, or the cost of stacked integration is high.

[0056] To improve at least one of the above problems, embodiments of this application provide an infrared detector.

[0057] First, the technical terms that may be used in the embodiments of this application will be explained:

[0058] Uncooled infrared focal plane array (IFA) sensitive pixels, also known as sensitive microbolometers, absorb external infrared radiation, causing the pixel itself to heat up and thus changing the resistance of the heat-sensitive material inside the pixel. Given these characteristics, the output signal (usually the output voltage) of the sensitive pixel is read. Then, by analyzing the relationship between the output signal and the change in the resistance of the heat-sensitive material, the change in resistance of the material within the sensitive pixel is calculated. Finally, by analyzing the relationship between the change in resistance and the amount of absorbed external infrared radiation, the amount of external infrared radiation absorbed by the sensitive pixel is obtained. Uncooled IFA sensitive pixels commonly employ a cantilever beam microbridge structure fabricated using micromachining technology. The bridge surface is deposited with a layer of heat-sensitive material with a high temperature coefficient of resistance. The bridge surface is supported by two legs with good mechanical properties and coated with conductive material. The contact points between the legs and the substrate are called piers, which are electrically connected to the readout circuit. Through the legs and piers, the heat-sensitive material is connected to the electrical path of the readout circuit, forming a temperature-sensitive pixel unit connected to the readout circuit.

[0059] Uncooled infrared focal plane array: includes multiple uncooled infrared focal plane sensitive pixels arranged orthogonally in rows and columns, and the bias circuit corresponding to each sensitive pixel.

[0060] Uncooled infrared focal plane array readout circuit: Used to extract, integrate, sample / hold, and convert the weak electrical signal generated by the uncooled infrared focal plane pixel array to digital output. Its typical structure includes: bias circuit, current mirror circuit, column integrator amplifier circuit, sample-and-hold circuit, multiplexer switch, timing control circuit, and analog-to-digital converter circuit. The signal current generated by infrared thermal radiation is very small, so noise control of the circuit itself is crucial. Input stage zero-point offset, analog-to-digital conversion nonlinearity, and differences in charge transfer efficiency all contribute to the non-uniformity of the readout circuit.

[0061] Non-uniformity in uncooled infrared focal plane arrays refers to the phenomenon where the output response of each pixel in the array is inconsistent under uniform infrared radiation input, manifesting as fixed pattern noise (FPN). Its main causes include factors such as detector materials, manufacturing process quality, readout circuit non-uniformity, ambient temperature variations, and the infrared optical system. Specific forms of non-uniformity include stripe or grid noise, multiplicative and additive noise, and temperature-dependent noise. Non-uniformity poses significant challenges to image quality, radiometric measurement errors, and system stability.

[0062] Next, the infrared detector 1 provided in the embodiments of this application will be described in detail. (See also: [link to relevant documentation]). Figure 1 The infrared detector 1 includes:

[0063] Signal processing integrated circuit 11 and storage integrated circuit 12; the signal processing integrated circuit 11 and the storage integrated circuit 12 are communicatively connected;

[0064] The signal processing integrated circuit 11 includes a readout module 111 and a correction module 112. The readout module 111 is used to acquire the analog electrical signal after conversion from external infrared radiation, convert the analog electrical signal into an original digital image signal, and output the original digital image signal to the correction module 112. The correction module 112 is used to correct the original digital image signal based on correction configuration data to obtain a corrected digital image signal. The storage integrated circuit 12 is used to store the correction configuration data.

[0065] The readout module 111 is used to output the original digital image signal to the correction module 112. The storage control module 114 of the signal processing integrated circuit 11 is used to read the correction configuration data stored in the storage integrated circuit 12 to the correction module 112. Based on the acquired original digital image signal and the correction configuration data, the correction module 112 calculates the corrected digital image signal and outputs the corrected digital image signal to the outside of the infrared detector 1 through its own image output interface, so that it can be used directly by the user.

[0066] In this embodiment, by fabricating the correction module 112 in the signal processing integrated circuit 11 (non-stacked integration), and then integrating the signal processing integrated circuit 11 with the storage integrated circuit 12, the integration of infrared sensing, correction calculation and storage is realized, which improves the integration of the infrared sensing system, reduces the space occupied by the infrared sensing system, and reduces the complexity of circuit design and the cost of circuit design on the basis of realizing the integration of sensing, calculation and storage.

[0067] In one possible implementation, see [link to relevant documentation]. Figure 1 and Figure 2 The signal processing integrated circuit 11 further includes a control module 113, a storage control module 114, and a clock reset control module 115;

[0068] The control module 113, the readout module 111, the storage control module 114, the correction module 112, and the clock reset control module 115 are all communicatively connected to the first bus of the signal processing integrated circuit 11, and the readout module 111, the correction module 112, and the storage control module 114 are all communicatively connected to the second bus of the signal processing integrated circuit 11.

[0069] The control module 113 is used to control each module in the signal processing integrated circuit 11;

[0070] The storage control module 114 is used to perform read and write operations on the correction configuration data in the correction module 112 and the storage integrated circuit 12.

[0071] The clock reset control module 115 is used to provide a timing reference for the signal processing integrated circuit 11.

[0072] The bias circuit and multiplexer circuit inside the readout module 111 are controlled by the control module 113 via the first bus.

[0073] The storage control module 114 is controlled by the control module 113 via the first bus.

[0074] The clock reset control module 115 is used to generate the operating frequency and reset release control of each circuit of the infrared detector 1. The clock reset control module 115 is controlled by the control module 113 through the first bus.

[0075] The correction module 112 is used to correct the non-uniformity of the original digital image signal and encode the corrected digital image signal into BT1120 (a video coding standard for digital interfaces of high-definition television studio signals), BT656 (a parallel hardware interface standard mainly used for transmitting standard-definition digital video streams), MIPI (Mobile Industry Processor Interface, a low-voltage differential signal interface for high-speed, interference-resistant video data transmission), or DVP (Digital Video Port, a parallel transmission interface designed as a low-speed bus) image format. This image is then output to the outside of the infrared detector 1 via a third bus for direct user use. The non-uniformity correction may include: resistance correction, bias correction, two-point correction and temperature drift suppression, baffle-less correction, horizontal stripe removal, vertical stripe removal, dead pixel removal, dish removal, temporal filtering noise reduction, motion compensation, boundary enhancement, wide dynamic range mapping, and image data encoding, etc. The above-mentioned correction processes can be interconnected step by step to achieve successive correction. According to the needs of the scenario, the correction cascade sequence (flowing series sequence) can be adjusted in real time to a suitable cascade sequence for different causes and types of nonuniformity through the parameter configuration of the first bus controlled by the control module 113.

[0076] The control module 113 is the core control module. On one hand, it interacts with external components of the infrared detector 1 via the fourth bus to exchange commands and data. On the other hand, relying on its internal central control unit, it controls the various modules in the signal processing integrated circuit 11 and their coordination and linkage through the first bus to achieve overall control of the infrared detector 1. The control module 113 is the scheduling core of the entire infrared detector 1. During the calibration phase (the calibration phase is a process of collecting response data under known conditions, generating compensation parameters, and storing them through a preset standardized process), the control module 113 controls the various modules in the signal processing integrated circuit 11 to cooperate in completing the calibration according to the calibration process, and stores the calibrated template data (correction configuration data) in the storage integrated circuit 12. During the normal operation phase, the control module 113 schedules the various modules in the signal processing integrated circuit 11 according to the actual configuration and actual working scenario, and completes timing control and other tasks to ensure that the readout timing and the calculated digital image signal meet the design requirements. In addition, the control module 113 also needs to monitor internal and external interruptions or other abnormal events in real time during the entire operation of the infrared detector 1, and handle these events to ensure that the working state of the infrared detector 1 meets expectations.

[0077] The storage control module 114 drives and reads / writes the storage integrated circuit 12 via the fifth bus according to the interface timing of the storage integrated circuit 12, and provides sufficient storage bandwidth for the infrared detector 1 via the second bus. Specifically, the storage integrated circuit 12 needs to be selected appropriately based on the required storage capacity and bandwidth, and the bus interface of the fifth bus needs to be designed according to the type of storage integrated circuit 12 and its interface protocol timing.

[0078] The second bus can be an AHB (Advanced High-performance Bus) or an AXI (Advanced extensible Interface) bus, or other similar custom buses.

[0079] The fourth bus can be an SPI (Serial Peripheral Interface) or USB (Universal Serial Bus) bus, or other similar custom buses.

[0080] The first bus can be an APB (Advanced Peripheral Bus) or an AHB bus, or other similar custom buses.

[0081] The third bus can be a BT656, MIPI, or DVP bus, or other similar custom buses.

[0082] It is understandable that the first bus and the second bus are internal buses of the signal processing integrated circuit 11, the third bus and the fourth bus are external buses, and the fifth bus is the bus between the signal processing integrated circuit 11 and the memory integrated circuit 12.

[0083] By employing a dual-bus design (first bus and second bus) inside the signal processing integrated circuit 11, the first bus is used to transmit control signals and the second bus is used to transmit data signals (the data signals mainly include the original digital image signals transmitted from the readout module 111 to the correction module 112 and the correction configuration data transmitted between the correction module 112 and the storage control module 114), the control flow and data flow are isolated, which can effectively improve the bandwidth congestion problem.

[0084] The storage control module 114 dynamically schedules the fifth bus and the second bus to match real-time storage requirements.

[0085] The storage control module 114 allocates storage bandwidth as needed. During the calibration phase, the control module 113 writes the correction configuration data to the storage integrated circuit 12. During the working phase, the correction module 112 processes the original digital image signal in real time according to the configured pipeline sequence.

[0086] To better understand the solution of this application, an embodiment of this application provides a simple illustration of the positional arrangement of each module in the signal processing integrated circuit 11. (See attached diagram.) Figure 2 (Top view illustration), of course Figure 2 The positions shown in the diagram are for illustrative purposes only and do not represent the actual layout in a real application. In actual design, the positions of each module need to be arranged reasonably according to different resolutions and the power consumption and heat generation of each module, so as not to affect the temperature uniformity of the signal processing integrated circuit 11.

[0087] Understandable, Figure 2 The diagram also illustrates the position of the MEMS (Micro-Electro-Mechanical System) pixel array 15 disposed on the signal processing integrated circuit 11.

[0088] In this embodiment, by employing a dual-bus design within the signal processing integrated circuit 11, with the first bus used for transmitting control signals and the second bus used for transmitting data signals, the control flow and data flow are isolated, effectively improving bandwidth congestion. Compared to data interaction between different integrated circuits in related technologies, data exchange via the second bus reduces power consumption by approximately 70%. For different causes and types of non-uniformity, the control module 113 dynamically adjusts the correction cascade sequence (pipeline serial sequence) to adapt to various scenarios and enhance system configurability. For unnecessary correction types, the control module 113 can bypass them, ensuring system flexibility and further reducing power consumption.

[0089] In one possible implementation, see Figure 3 The control module 113 includes a central control unit 11131, a readout control unit 11132, a correction control unit 11133, and a memory control unit 11134;

[0090] The central control unit 11131 is communicatively connected to the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134, respectively. The readout control unit 11132 is communicatively connected to the readout module 111. The correction control unit 11133 is communicatively connected to the correction module 112. The memory control unit 11134 is communicatively connected to the readout module 111, the correction module 112, and the storage control module 114, respectively.

[0091] The central control unit 11131 is used to acquire the target operating mode of the infrared detector 1, and to start its own pixel counter and row counter based on the target operating mode; the row counter counts the number of pixel rows in a frame image, and the pixel counter counts the number of pixels in a row of pixels in a frame image; it generates a synchronization pulse, and uses the synchronization pulse to align the actions of the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134;

[0092] The readout control unit 11132 is used to generate line period timing and frame period timing for the readout module 111 based on the synchronization pulse and the target working mode.

[0093] The correction control unit 11133 is used to determine the sequential order of each correction submodule 1122 in the correction module 112 based on the synchronization pulse and the target working mode, and to control each correction submodule 1122 to start working.

[0094] The memory control unit 11134 is used to generate a service slice table and a priority table for the read module 111, the correction module 112, and the storage control module 114 based on the synchronization pulse and the target working mode; wherein, the service slice table is the service requirements determined based on the pipelined sequence of the correction control unit 11133, and the priority table is the priority corresponding to each service slice in the service slice table.

[0095] The central control unit 11131, as the core unit of the control module 113, acts as the brain. After power-on initialization, the central control unit 11131 adaptively adjusts its working mode by sensing the working environment (such as temperature, posture, external environment, etc.). Based on the working mode, the central control unit 11131 sets the maximum value and counting mode of the pixel counter and row counter, and then starts counting. Simultaneously, the linkage and coordination circuit within the central control unit 11131 generates synchronization pulses to align the actions of the readout control unit 11132, the correction control unit 11133, and the memory control unit 11134. These synchronization pulses can achieve pixel-level alignment, achieving efficient coordination.

[0096] In one example, the operating mode can be HDR (High Dynamic Range) mode. In another example, the operating mode can be real-time single-frame mode.

[0097] Based on the synchronization pulse and the working mode, the readout control unit 11132 starts its own timing generation circuit to generate line period timing and frame period timing for the readout module 111, guides the operation of each circuit in the readout module 111, and applies different biases to each sensitive pixel line by line and point by point.

[0098] The correction control unit 11133 adjusts the serial sequence of N correction sub-modules 1122 based on the synchronization pulse and operating mode, and starts each correction sub-module 1122 to start working. For different operating modes, the correction control unit 11133 can adjust the serial sequence of each row with fine granularity.

[0099] The memory control unit 11134 generates a service slice table and a variable priority table for the read module 111 and the correction module 112 based on synchronization pulses and operating modes. This table guides the operation of the read / write instruction channel and read / write data channel of the storage control module 114. The memory control unit 11134 can finely adjust the service slices and priorities of read / write services in each row. This dynamic scheduling mechanism ensures optimal memory requirements under different operating modes. The service slices are divided into read services R1, R2...Rn and write services W1, W2...Wn. The service slice table is based on the pipelined sequence of the correction control unit 11133, which determines the service requirements. For example, if the pipelined sequence is {second correction submodule, third correction submodule, first correction submodule}, where the second correction submodule requires two writes, the third correction submodule requires one write and one read, and the first correction submodule requires one write, then the generated service slices are {R3, W2, W2, W3, W1}. The priority table represents the priority of each service slice in the service slice table, with 1 being the highest and 5 being the lowest. A schematic diagram is shown below. Figure 4 As shown, the service slice table can be R3, W2, W2, W3, W1, and the corresponding priority table can be 1, 3, 3, 4, 4.

[0100] In this embodiment of the application, the read control unit 11132, the correction control unit 11133, and the memory control unit 11134 in the control module 113 tightly integrate the originally independent read module 111, correction module 112, and storage control module 114 into a unified management system, so that each module can achieve pixel-level alignment based on the working mode, thereby reducing the management difficulty and time complexity of each module.

[0101] To better understand the solution of this application, a brief description of the workflow of the signal processing integrated circuit 11 is provided. (See also...) Figure 5 This includes the following steps:

[0102] Step 1: Signal processing integrated circuit 11 initializes; Step 2: Central control unit 11131 acquires operating mode; Step 3: Central control unit 11131 starts pixel counter and line counter, and generates synchronization pulse; Step 4: Readout control unit 11132 starts timing generation, generating line period timing and frame period timing; Step 5: Correction control unit 11133 determines the pipelined sequence of each correction submodule 1122 in correction module 112, and controls each correction submodule 1122 to start operating; Step 6: Memory control unit 11134 generates service slice table and priority table; Step 7: Readout module 111 outputs the raw digital image signal of one sensitive pixel; Step 8: Storage control module 114 reads the... Step 9: The correction configuration data of the sensitive pixel should be obtained; Step 10: The encoding output submodule 1121 of the correction module 112 outputs the corrected digital image signal; Step 11: The storage control module 114 writes the updated correction configuration data into the storage integrated circuit 12; Step 12: Check if the pixel counter has reached the number of pixels in one row. If not, return to steps 7 and 8. If yes, execute step 13: Check if the line counter has reached the number of lines in one frame. If not, return to steps 4, 5, and 6. If yes, execute step 14: One frame processing is completed.

[0103] In one possible implementation, see Figure 3 The storage control module 114 includes a read / write data transceiver unit 11141, a read / write data arbitration unit 11142, a read / write instruction generation unit 11143, a read / write instruction arbitration unit 11144, and a particle control unit 11145.

[0104] The read / write data transceiver unit 11141 is communicatively connected to the read / write data arbitration unit 11142, and the read / write data arbitration unit 11142 is communicatively connected to the particle control unit 11145; the read / write instruction generation unit 11143 is communicatively connected to the read / write instruction arbitration unit 11144, and the read / write instruction arbitration unit 11144 is communicatively connected to both the read / write data arbitration unit 11142 and the particle control unit 11145; the particle control unit 11145 is communicatively connected to the memory integrated circuit 12.

[0105] The read / write instruction generation unit 11143 is used to generate corresponding read / write instructions based on the service slice table of the control module 113;

[0106] The read / write instruction arbitration unit 11144 is used to sort the read / write instructions based on the priority table of the control module 113;

[0107] The read / write data transceiver unit 11141 is used to read the correction configuration data in the storage integrated circuit 12 to the correction module 112, or to write the correction configuration data in the correction module 112 to the storage integrated circuit 12.

[0108] The read / write data arbitration unit 11142 is used to control the transmission timing of the correction configuration data;

[0109] The particle control unit 11145 is used to convert the read / write instructions and correction configuration data into signals that are recognized by the storage integrated circuit 12.

[0110] The read / write instruction generation unit 11143 of the storage control module 114 is used to generate corresponding read / write instructions according to the service chip table; the read / write instruction arbitration unit 11144 is used to arbitrate the read / write instructions sent by the read / write instruction generation unit 11143 according to the priority; the granular control unit 11145 is used to convert the read / write instructions and correction configuration data into the external bus timing of the storage integrated circuit 12 interface to complete the corresponding read / write work.

[0111] The read / write instruction arbitration unit 11144 is the core unit of the storage control module 114. Its main task is to ensure that all services corresponding to the service slice table are completed within one synchronization pulse cycle. Its core mechanism is to rearrange the read / write instructions according to the priority table, obtain the arbitration result, and send them out one by one. The arbitration logic of the read / write instruction arbitration unit 11144 can be found in [reference needed]. Figure 6 The read / write instructions can be C1, C2, C3, C4, C5, and C6, with priorities of 1, 3, 3, 2, 2, and 2 respectively. The arbitration result is then C1, C4, C5, C2, C6, and C3.

[0112] In one possible implementation, the correction module 112 is specifically configured to: receive the original digital image signal output by the readout module 111 and the correction configuration data read by the storage control module 114; calculate a corrected digital image signal based on the original digital image signal and the correction configuration data through its own correction submodules 1122; encode and output the corrected digital image signal through its own encoding output submodule 1121; obtain updated correction configuration data based on the corrected digital image signal and the original digital image signal; and write the updated correction configuration data into the storage integrated circuit 12 through the storage control module 114.

[0113] The cascading order of each correction submodule 1122 is controlled by the correction control unit 11133, which can adjust the cascading order in real time according to the working mode to adapt to various working scenarios. After the cascading order is determined, each correction submodule 1122 will input the correction result of the upper-level correction submodule to the next correction submodule in a pipeline manner with minimal delay, so as to achieve minimal delay (microsecond level) and improve the calculation speed.

[0114] The updated correction configuration data is obtained based on the corrected digital image signal and the original digital image signal in order to ensure continuous optimization of image processing effect and meet dynamically changing processing needs (during image processing, conditions may change in real time, and the correction configuration data needs to be dynamically adjusted to adapt to new situations. In addition, multi-step processing may accumulate errors, and updating the correction configuration data can eliminate these errors and improve accuracy).

[0115] In one possible implementation, see Figure 3 The correction module 112 includes an encoding output submodule 1121 and N correction submodules 1122; where N is an integer not less than 1.

[0116] The i-th correction submodule 1122 is communicatively connected to the (i-1)-th correction submodule 1122, and the N-th correction submodule 1122 is communicatively connected to the encoding output submodule 1121; where i ∈ N, and i is an integer not less than 2;

[0117] The (i-1)th correction submodule 1122 outputs its processed correction result to the ith correction submodule 1122 with minimal delay.

[0118] In this embodiment, the (i-1)th correction submodule 1122 outputs its processed correction result to the ith correction submodule 1122 with minimal delay, thereby achieving minimal delay and improving computation speed.

[0119] In one possible implementation, the N correction submodules include a multiplicative correction submodule, an additive correction submodule, and a time-domain filtering submodule;

[0120] The multiplicative correction submodule is communicatively connected to the additive correction submodule, the additive correction submodule is communicatively connected to the time-domain filtering submodule, and the time-domain filtering submodule is communicatively connected to the encoding output submodule 1121.

[0121] The multiplicative correction submodule outputs its processed correction result to the additive correction submodule with minimal delay, and the additive correction submodule outputs its processed correction result to the time-domain filtering submodule with minimal delay, thereby achieving minimal delay and improving computation speed.

[0122] The multiplicative correction submodule, additive correction submodule, and time-domain filtering submodule all have built-in parameter caches (stored in the storage integrated circuit 12) to support parallel processing.

[0123] In one possible implementation, the infrared detector 1 further includes a substrate 13;

[0124] See also Figure 7 and Figure 8 The signal processing integrated circuit 11 is disposed on the substrate 13, and the storage integrated circuit 12 is disposed on the side of the signal processing integrated circuit 11 away from the substrate 13;

[0125] or,

[0126] See also Figure 9 and Figure 10 The signal processing integrated circuit 11 and the storage integrated circuit 12 are both disposed on the substrate 13, and there is a first preset distance between the orthographic projection of the storage integrated circuit 12 on the substrate 13 and the orthographic projection of the signal processing integrated circuit 11 on the substrate 13.

[0127] In one possible implementation, the storage integrated circuit 12 is provided with a first communication connection point, and the signal processing integrated circuit 11 is provided with a second communication connection point on the side away from the substrate 13. The first communication connection point and the second communication connection point are connected. The storage integrated circuit 12 achieves communication connection with the signal processing integrated circuit 11 through the first communication connection point and the second communication connection point.

[0128] The first communication connection point can be located on the side of the memory integrated circuit 12 away from the substrate 13, or on the side of the memory integrated circuit 12 close to the substrate 13, or at other locations on the memory integrated circuit 12. This application does not specifically limit this.

[0129] A third communication connection point is also provided on the substrate 13, which is connected to the second communication connection point. The signal processing integrated circuit 11 and the storage integrated circuit 12 communicate with external signals through the substrate 13.

[0130] In one possible implementation, see [link to relevant documentation]. Figure 7 , Figure 8 , Figure 9 and Figure 10 The infrared detector 1 also includes a MEMS pixel array 15;

[0131] The MEMS pixel array 15 is disposed on the side of the signal processing integrated circuit 11 away from the substrate 13 (the MEMS pixel array 15 and the second communication connection point are disposed on the same side of the signal processing integrated circuit 11).

[0132] The MEMS pixel array 15 is communicatively connected to the readout module 111 of the signal processing integrated circuit 11;

[0133] The MEMS pixel array 15 is used to convert external infrared radiation into analog electrical signals.

[0134] MEMS pixel array 15 can be a bridge-shaped pixel array, including a bridge surface and two edge support legs. The edge support legs can be communicatively connected to the readout module 111 of the signal processing integrated circuit 11. MEMS pixel array 15 can also be a pixel array with other structures. This application does not specifically limit it.

[0135] The bias circuits corresponding to each sensitive pixel in the MEMS pixel array 15 can be controlled by the control module 113 of the signal processing integrated circuit 11 via the first bus.

[0136] Understandable, Figure 7 , Figure 8 , Figure 9 and Figure 10 The diagram only illustrates the MEMS pixel array 15 and does not represent its actual structure.

[0137] In one possible implementation, the orthographic projections of the MEMS pixel array 15 and the storage integrated circuit 12 on the substrate 13 do not overlap, and there is a second preset distance between the orthographic projection of the storage integrated circuit 12 on the substrate 13 and the orthographic projection of the MEMS pixel array 15 on the substrate 13.

[0138] In one possible implementation, the second preset distance is not less than 1.5 times the thickness of the memory integrated circuit 12.

[0139] See Figure 7 When the cover structure 14 is disposed on the substrate 13 and the memory integrated circuit 12 is disposed on the side of the signal processing integrated circuit 11 away from the substrate 13, the orthographic projections of the MEMS pixel array 15 and the memory integrated circuit 12 on the substrate 13 do not overlap, and there is a second preset distance between the orthographic projection of the memory integrated circuit 12 on the substrate 13 and the orthographic projection of the MEMS pixel array 15 on the substrate 13. This ensures that the projection of the memory integrated circuit 12 avoids the MEMS pixel array 15 and does not obstruct the optical path. In one example, in a 640×512 array with an 8-micron pixel pitch, zero obstruction can be achieved when the thickness of the memory integrated circuit 12 is ≤200 microns.

[0140] In one possible implementation, the infrared detector 1 further includes a cover structure 14, which can be seen in [reference needed]. Figure 7 and Figure 10The cover plate structure 14 is disposed on the substrate 13, and a cavity is formed between the cover plate structure 14 and the substrate 13. The signal processing integrated circuit 11, the MEMS pixel array 15 and the storage integrated circuit 12 are located in the cavity.

[0141] The cover plate structure 14 includes an infrared light-transmitting surface 141 and an annular protrusion 142, and the annular protrusion 142 of the cover plate structure 14 is connected to the substrate 13.

[0142] Alternatively, you can refer to Figure 8 and Figure 9 The cover plate structure 14 is disposed on the side of the signal processing integrated circuit 11 away from the substrate 13, and a cavity is formed between the cover plate structure 14 and the signal processing integrated circuit 11, and the MEMS pixel array 15 is located in the cavity;

[0143] The cover plate structure 14 includes an infrared light-transmitting surface 141 and an annular protrusion 142, and the annular protrusion 142 of the cover plate structure 14 is connected to the signal processing integrated circuit 11.

[0144] The storage integrated circuit 12 is one or more volatile or non-volatile memory chips used to store calibration data, calibration calculations, and the central control unit 11131. The power consumption of the storage integrated circuit 12 must be appropriate to avoid temperature non-uniformity. The storage integrated circuit 12 is communicatively connected to the storage control module 114 of the signal processing integrated circuit 11 via the fifth bus to complete the data storage and retrieval functions.

[0145] The signal processing integrated circuit 11 and the memory integrated circuit 12 are packaged together in the same package using advanced packaging technology. The signal processing integrated circuit 11 and the memory integrated circuit 12 are connected internally via wires and communicate with external signals via a substrate 13. The memory integrated circuit 12 can be stacked on top of the signal processing integrated circuit 11, such as... Figure 7 and Figure 8 As shown, Figure 7 The storage integrated circuit 12 is positioned at an appropriate distance from the MEMS pixel array 15 to avoid obstructing the optical path. If the side of the signal processing integrated circuit 11 furthest from the substrate 13 is insufficient to stack the storage integrated circuit 12, the storage integrated circuit 12 can be placed directly on the substrate 13. Figure 9 and Figure 10 As shown. The cover structure 14 includes an infrared light-transmitting surface 141 and an annular protrusion 142, which makes the infrared detector 1 form a vacuum cavity, thereby forming an infrared detector 1 that integrates sensing, computing and storage.

[0146] The annular protrusion 142 can be either an annular light-shielding protrusion or an annular light-transmitting protrusion; this application does not specifically limit its application in this regard. When the annular protrusion 142 is an annular light-shielding protrusion, the material of the light-shielding protrusion can be metal, ceramic, or wafer-level. The light-shielding protrusion can serve the following functions: physically protect the brittle infrared light-transmitting surface 141, isolate the integrated circuit from environmental dust and moisture corrosion, and prevent side light leakage that could lead to signal crosstalk.

[0147] Figure 7 and Figure 10 The cavity formed by the infrared detector 1 shown can protect the exposed solder pads at the wire connections, improving the reliability and safety of the infrared detector. Compared to Figure 7 and Figure 10 The infrared detector 1 shown is... Figure 8 Zhongyu Figure 9 The infrared detector 1 shown is lighter, which can achieve weight reduction.

[0148] By adopting a dual-integrated circuit co-package architecture, that is, the signal processing integrated circuit 11 and the memory integrated circuit 12 are integrated into the same package through advanced packaging technology, and the bus inside the same integrated circuit replaces the high-speed communication between different circuits, the high-speed communication between different circuits is eliminated compared with the traditional discrete architecture, reducing the risk of EMI (Electromagnetic Interference), simplifying PCB (Printed Circuit Board) design, and the size of the co-packaged circuit is reduced by about 50% compared with the discrete architecture. Furthermore, through vacuum packaging and module layout optimization, thermal crosstalk is reduced and thermal stability is improved.

[0149] In one possible implementation, Figure 7 and Figure 8 In the infrared detector 1 shown, when the storage integrated circuit 12 is disposed on the side of the signal processing integrated circuit 11 away from the substrate 13, the side of the signal processing integrated circuit 11 away from the substrate 13 has a thermally conductive material deposition area.

[0150] Wherein, the orthographic projection of the MEMS pixel array 15 and the thermally conductive material deposition area on the substrate 13 does not overlap, and the orthographic projection of the storage integrated circuit 12 on the substrate 13 is included in the orthographic projection of the thermally conductive material deposition area on the substrate 13.

[0151] By depositing a thermally conductive material on the side of the signal processing integrated circuit 11 away from the substrate 13, the heat generated during the operation of the memory integrated circuit 12 is rapidly conducted through the signal processing integrated circuit 11 to the substrate 13, thereby increasing the allowable power consumption of the memory integrated circuit 12 to 50mW. In one example, the thermally conductive material can be aluminum nitride (AlN).

[0152] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0153] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0154] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. An infrared detector, characterized in that, The infrared detector includes: Signal processing integrated circuit and memory integrated circuit; the signal processing integrated circuit and the memory integrated circuit are communicatively connected. The signal processing integrated circuit includes a readout module, a correction module, a control module, a storage control module, and a clock reset control module. The readout module acquires the analog electrical signal converted from external infrared radiation, converts the analog electrical signal into a raw digital image signal, and outputs the raw digital image signal to the correction module. The correction module performs non-uniformity correction on the raw digital image signal based on correction configuration data to obtain a corrected digital image signal. The storage integrated circuit stores the correction configuration data. The control module, the readout module, the storage control module, the correction module, and the clock reset control module are all communicatively connected to the first bus of the signal processing integrated circuit, and the readout module, the correction module, and the storage control module are all communicatively connected to the second bus of the signal processing integrated circuit; the first bus is used to transmit control signals, and the second bus is used to transmit data signals; The control module is used to control each module in the signal processing integrated circuit; the storage control module is used to perform read and write operations on the correction module and the correction configuration data in the storage integrated circuit; the clock reset control module is used to provide a timing reference for the signal processing integrated circuit. The storage integrated circuit has a first communication connection point, and the signal processing integrated circuit has a second communication connection point on the side away from the substrate. The first communication connection point and the second communication connection point are connected. The infrared detector also includes a MEMS pixel array. The MEMS pixel array and the second communication connection point are located on the same side of the signal processing integrated circuit. The MEMS pixel array is communicatively connected to the readout module of the signal processing integrated circuit. The MEMS pixel array is used to convert external infrared radiation into analog electrical signals. The orthographic projection of the MEMS pixel array and the storage integrated circuit on the substrate has no overlapping portion, and there is a second preset distance between the orthographic projection of the storage integrated circuit on the substrate and the orthographic projection of the MEMS pixel array on the substrate. The second preset distance is not less than 1.5 times the thickness of the storage integrated circuit.

2. The infrared detector according to claim 1, characterized in that, The correction module is specifically used to receive the original digital image signal output by the readout module and the correction configuration data read by the storage control module; based on the original digital image signal and the correction configuration data, calculate a corrected digital image signal through its own correction sub-modules; encode the corrected digital image signal and output it through its own encoding output sub-module; and obtain updated correction configuration data based on the corrected digital image signal and the original digital image signal.

3. The infrared detector according to claim 2, characterized in that, The correction module includes an encoding output submodule and N correction submodules; where N is an integer not less than 1. The i-th correction submodule is communicatively connected to the (i-1)-th correction submodule, and the N-th correction submodule is communicatively connected to the encoding output submodule; where i ∈ N, and i is an integer not less than 2; The (i-1)th correction submodule outputs its processed correction result to the ith correction submodule with minimal delay.

4. The infrared detector according to claim 3, characterized in that, The N correction submodules include a multiplicative correction submodule, an additive correction submodule, and a time-domain filtering submodule; The multiplicative correction submodule is communicatively connected to the additive correction submodule, the additive correction submodule is communicatively connected to the time-domain filtering submodule, and the time-domain filtering submodule is communicatively connected to the encoding output submodule. The multiplicative correction submodule outputs its processed correction result to the additive correction submodule with minimal delay, and the additive correction submodule outputs its processed correction result to the time-domain filtering submodule with minimal delay.

5. The infrared detector according to claim 1, characterized in that, The infrared detector also includes a substrate; The signal processing integrated circuit is disposed on the substrate, and the storage integrated circuit is disposed on the side of the signal processing integrated circuit away from the substrate; or, Both the signal processing integrated circuit and the storage integrated circuit are disposed on the substrate, and there is a first preset distance between the orthographic projection of the storage integrated circuit on the substrate and the orthographic projection of the signal processing integrated circuit on the substrate.

6. The infrared detector according to claim 5, characterized in that, The infrared detector also includes a cover plate structure; The cover plate structure is disposed on the substrate, and a cavity is formed between the cover plate structure and the substrate. The signal processing integrated circuit, the MEMS pixel array and the storage integrated circuit are located in the cavity. The cover plate structure includes an infrared light-transmitting surface and an annular protrusion, and the annular protrusion of the cover plate structure is connected to the substrate. or, The cover plate structure is disposed on the side of the signal processing integrated circuit away from the substrate, and a cavity is formed between the cover plate structure and the signal processing integrated circuit, and the MEMS pixel array is located in the cavity; The cover plate structure includes an infrared-transmitting surface and an annular protrusion, and the annular protrusion of the cover plate structure is connected to the signal processing integrated circuit.

7. The infrared detector according to claim 5, characterized in that, When the storage integrated circuit is disposed on the side of the signal processing integrated circuit away from the substrate, the side of the signal processing integrated circuit away from the substrate has a thermally conductive material deposition area; Wherein, the orthographic projections of the MEMS pixel array and the thermally conductive material deposition area on the substrate do not overlap, and the orthographic projection of the storage integrated circuit on the substrate is included in the orthographic projection of the thermally conductive material deposition area on the substrate.

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