Pixel array substrate and reflective display panel

Abstract

The invention provides a pixel array substrate and a reflective display panel. The pixel array substrate comprises a first reflective electrode, a second reflective electrode and a third reflective electrode. The first reflection electrode and the second reflection electrode are adjacently arranged along the first direction and are spaced by a first gap. The first reflection electrode and the third reflection electrode are adjacently arranged along the second direction and are spaced by a second gap. The first gap has a first edge portion adjacent to the third reflective electrode and a first central portion located at one side of the first edge portion away from the third reflective electrode. In the first direction, a width of the first edge portion is greater than a width of the first central portion. The second gap has a second edge portion adjacent to the second reflective electrode and a second central portion located at one side of the second edge portion away from the second reflective electrode. In the second direction, a width of the second edge portion is greater than a width of the second central portion.

Description

Technical Field

[0001] The present invention relates to a substrate and a display panel, and in particular to a pixel array substrate and a reflective display panel. Background Art

[0002] Reflective display panels use reflective electrodes to reflect ambient light to achieve their display effects. Their display brightness depends on the overall reflectivity. The reflective electrode's area ratio to the display area is a key factor in determining the reflectivity of a reflective display panel. However, while maximizing the reflective electrode's area ratio can maximize the reflectivity of a reflective display panel, it also minimizes the spacing between the reflective electrodes. When the spacing is too small, the reflective electrode etching process can easily result in incomplete etching in areas adjacent to multiple reflective electrodes, impacting the process yield of these reflective electrodes. Summary of the Invention

[0003] The present invention is directed to a pixel array substrate and a reflective display panel, which have a better manufacturing process yield.

[0004] According to an embodiment of the present invention, a pixel array substrate includes a substrate and a plurality of pixel structures. The plurality of pixel structures are disposed on the substrate. Each of the plurality of pixel structures includes a reflective electrode. The reflective electrodes include a first reflective electrode, a second reflective electrode, and a third reflective electrode. The first reflective electrode and the second reflective electrode are adjacently arranged along a first direction and separated by a first gap. The first reflective electrode and the third reflective electrode are adjacently arranged along a second direction and separated by a second gap. The first direction intersects the second direction. The first gap includes a first edge portion and a first central portion that are interconnected. The first edge portion is proximate to the third reflective electrode. The first central portion is located on a side of the first edge portion away from the third reflective electrode. The width of the first edge portion along the first direction is greater than the width of the first central portion along the first direction. The second gap includes a second edge portion and a second central portion that are interconnected. The second edge portion is proximate to the second reflective electrode. The second central portion is located on a side of the second edge portion away from the second reflective electrode. The width of the second edge portion along the second direction is greater than the width of the second central portion along the second direction.

[0005] According to an embodiment of the present invention, a reflective display panel includes a pixel array substrate, an opposing substrate, and a liquid crystal layer. The pixel array substrate includes a substrate and a plurality of pixel structures. The plurality of pixel structures are disposed on the substrate. Each of the plurality of pixel structures includes a reflective electrode. The reflective electrodes include a first reflective electrode, a second reflective electrode, and a third reflective electrode. The first reflective electrode and the second reflective electrode are adjacently arranged along a first direction and separated by a first gap. The first reflective electrode and the third reflective electrode are adjacently arranged along a second direction and separated by a second gap. The first direction intersects the second direction. The first gap includes a first edge portion and a first central portion that are interconnected. The first edge portion is proximate to the third reflective electrode. The first central portion is located on a side of the first edge portion away from the third reflective electrode. The width of the first edge portion along the first direction is greater than the width of the first central portion along the first direction. The second gap includes a second edge portion and a second central portion that are interconnected. The second edge portion is proximate to the second reflective electrode. The second central portion is located on a side of the second edge portion away from the second reflective electrode. The width of the second edge portion along the second direction is greater than the width of the second central portion along the second direction. The opposing substrate overlaps the pixel array substrate. The liquid crystal layer is disposed between the pixel array substrate and the opposing substrate.

[0006] Based on the foregoing, in a reflective display panel according to one embodiment of the present invention, the gap between any reflective electrode and its adjacent reflective electrode on the pixel array substrate includes an edge portion proximate to the adjacent reflective electrode and a central portion distal to the adjacent reflective electrode. By having the width of the edge portion be greater than the width of the central portion in the alignment direction of the reflective electrode and the adjacent reflective electrode, the reflective electrodes are electrically isolated from each other after the etching process, thereby improving the production yield of the reflective display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a reflective display panel according to a first embodiment of the present invention;

[0008] Figure 2 yes Figure 1 A front view schematic diagram of a pixel array substrate;

[0009] Figure 3 yes Figure 2 An enlarged schematic diagram of a local area of a pixel array substrate;

[0010] Figure 4 is a front view schematic diagram of a pixel array substrate according to a second embodiment of the present invention;

[0011] Figure 5 is a schematic front view of a pixel array substrate according to a third embodiment of the present invention;

[0012] Figure 6 is a schematic front view of a pixel array substrate according to a fourth embodiment of the present invention;

[0013] Figure 7 is a schematic front view of a pixel array substrate according to a fifth embodiment of the present invention;

[0014] Figure 8 FIG. 4 is a schematic front view of a pixel array substrate according to a sixth embodiment of the present invention.

[0015] Description of Reference Numerals

[0016] 10: reflective display panel;

[0017] 100, 100A, 100B, 100C, 100D, 100E: pixel array substrates;

[0018] 101, 201: substrate;

[0019] 101s: substrate surface;

[0020] 110: gate insulating layer;

[0021] 120, 130: insulation layer;

[0022] 200: opposite substrate;

[0023] 210: coating layer;

[0024] CE: common electrode;

[0025] CEL: common electrode layer;

[0026] CPE: capacitive electrode;

[0027] D1, D2, D3: direction;

[0028] DE: drain;

[0029] DL: data line;

[0030] FP: filter pattern;

[0031] GE: gate;

[0032] GL: scan line;

[0033] LCL: liquid crystal layer;

[0034] OP: Opening;

[0035] PX: pixel structure;

[0036] RE: reflective electrode;

[0037] RE1~RE4: first reflective electrode to fourth reflective electrode;

[0038] SC: semiconductor pattern;

[0039] SE: source;

[0040] SLT1, SLT1-A, SLT1-B, SLT1-C, SLT1-D, SLT1-E: first gap;

[0041] SLT1cp: first central part;

[0042] SLT1ep, SLT1ep-A, SLT1ep-B, SLT1ep-C, SLT1ep-D, SLT1ep-E: first marginal segment;

[0043] SLT2, SLT2-A, SLT2-B, SLT2-C, SLT2-D, SLT2-E: Second gap;

[0044] SLT2cp: second central part;

[0045] SLT2ep, SLT2ep-A, SLT2ep-B, SLT2ep-C, SLT2ep-D, SLT2ep-E: second marginal portion;

[0046] SLT3, SLT3-A, SLT3-B, SLT3-C, SLT3-D, SLT3-E: third gap;

[0047] SLT3cp: third central section;

[0048] SLT3ep, SLT3ep-A, SLT3ep-B, SLT3ep-C, SLT3ep-D, SLT3ep-E: third marginal segment;

[0049] SLT4, SLT4-A, SLT4-B, SLT4-C, SLT4-D, SLT4-E: fourth gap;

[0050] SLT4cp: fourth central section;

[0051] SLT4ep, SLT4ep-A, SLT4ep-B, SLT4ep-C, SLT4ep-D, SLT4ep-E: fourth marginal segment;

[0052] T: active element;

[0053] TH: contact hole;

[0054] W1c, W1e, W2c, W2e, W3c, W3e, W4c, W4e: width;

[0055] A-A': section line. DETAILED DESCRIPTION

[0056] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0057] The foregoing and other technical aspects, features, and benefits of the present invention will be more clearly understood in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are merely references to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0058] Figure 1 FIG. 1 is a schematic cross-sectional view of a reflective display panel according to a first embodiment of the present invention. Figure 2 yes Figure 1 A front view schematic diagram of a pixel array substrate. Figure 3 yes Figure 2 An enlarged schematic diagram of a local area of a pixel array substrate. Figure 1 Corresponding to Figure 2 For clarity, Figure 2 and Figure 3 Only shown Figure 1 Part of the film layer of the pixel array substrate 100.

[0059] Please refer to Figure 1 and Figure 2 The reflective display panel 10 includes a pixel array substrate 100, an opposing substrate 200, and a liquid crystal layer LCL. The pixel array substrate 100 and the opposing substrate 200 are arranged to overlap, for example, along direction D3. The liquid crystal layer LCL is disposed between the pixel array substrate 100 and the opposing substrate 200. It should be noted that unless otherwise specified below, the overlapping relationship between the two components is defined along direction D3, and the overlapping direction will not be further described.

[0060] The pixel array substrate 100 includes a substrate 101 and a plurality of scan lines GL, a plurality of data lines DL, and a plurality of pixel structures PX disposed on the substrate 101. In this embodiment, the plurality of data lines DL may be arranged along a direction D1 and extend in a direction D2, while the plurality of scan lines GL may be arranged along a direction D2 and extend in a direction D1. The direction D1 intersects with (e.g., is perpendicular to) the direction D2. The plurality of pixel structures PX may be arranged in a plurality of rows and a plurality of columns along the directions D1 and D2, respectively. That is, the pixel structures PX may be arranged in an array on the substrate 101 and each electrically connected to a scan line GL and a data line DL, but the present invention is not limited thereto.

[0061] The pixel structure PX may include an active device T and a reflective electrode RE electrically connected to each other. In this embodiment, a method for forming the active device T may include the following steps: sequentially forming a gate electrode GE, a gate insulating layer 110, a semiconductor pattern SC, a source electrode SE, and a drain electrode DE on a substrate 101. The semiconductor pattern SC is arranged to overlap the gate electrode GE. The source electrode SE and the drain electrode DE overlap the semiconductor pattern SC and are in electrical contact with two different regions of the semiconductor pattern SC. In this embodiment, the gate electrode GE of the active device T may optionally be disposed below the semiconductor pattern SC to form a bottom-gate thin-film transistor (TFT), but the present invention is not limited thereto. In other embodiments, the gate electrode of the active device may also be optionally disposed above the semiconductor pattern to form a top-gate thin-film transistor (TFT).

[0062] Furthermore, the active device T may be sequentially covered with an insulating layer 120 and an insulating layer 130. In this embodiment, the insulating layer 120 is, for example, a passivation layer, and the insulating layer 130 is, for example, a planarization layer. It should be noted that the gate GE, the source SE, the drain DE, the semiconductor pattern SC, the gate insulating layer 110, the passivation layer (i.e., the insulating layer 120), and the planarization layer (i.e., the insulating layer 130) may be implemented by any gate, any source, any drain, any semiconductor pattern, any gate insulating layer, any passivation layer, and any planarization layer used in a reflective display panel, as known to those skilled in the art. Furthermore, the gate GE, the source SE, the drain DE, the semiconductor pattern SC, the gate insulating layer 110, the passivation layer, and the planarization layer may be formed by any method known to those skilled in the art, and therefore will not be described in detail herein. In this embodiment, the material of the reflective electrode RE includes, for example, metal, alloy, metal nitride, metal oxide, metal oxynitride, or other suitable materials, or a stacked layer of metal and other conductive materials.

[0063] In this embodiment, the pixel structure PX may further include a common electrode CE, a capacitor electrode CPE, and a conductive pattern CP that overlap with each other, but is not limited to this. The common electrode CE is arranged between the substrate 101 and the gate insulating layer 110. The capacitor electrode CPE is arranged between the gate insulating layer 110 and the insulating layer 120. Therefore, the capacitor electrode CPE, the common electrode CE, and the gate insulating layer 110 sandwiched therebetween may form a storage capacitor. In other embodiments, the pixel structure PX may not include the common electrode CE and the capacitor electrode CPE that overlap with each other. The conductive pattern CP is arranged between the insulating layer 120 and the insulating layer 130. The insulating layer 130 has an opening OP, and this opening OP exposes a portion of the surface of the conductive pattern CP. The reflective electrode RE of the pixel structure PX is arranged on the surface of the insulating layer 130 and is electrically connected to the conductive pattern CP through the opening OP of the insulating layer 130. The conductive pattern CP is electrically connected to the capacitor electrode CPE via the contact hole TH of the insulating layer 120, and the capacitor electrode CPE may extend from the drain DE of the active device T (i.e., the drain DE and the capacitor electrode CPE are coupled to each other), but the present invention is not limited thereto. In this embodiment, the opening OP does not overlap with the contact hole TH in the direction D3, but the present invention is not limited thereto. In other embodiments, the opening OP may overlap with the contact hole TH in the direction D3. In particular, for clarity, Figure 2 and Figure 3 The conductive pattern CP is omitted from illustration. In some embodiments, the conductive pattern CP may overlap the capacitor electrode CPE, the opening OP, and the contact hole TH in direction D3. The front-view shape of the conductive pattern CP may be substantially the same as the front-view shape of the capacitor electrode CPE, but the front-view shape of the conductive pattern CP is not limited to this. In other embodiments, the pixel structure PX may not include the conductive pattern CP, and the reflective electrode RE may be electrically connected to the drain DE of the active device T via a through-hole penetrating the insulating layer 130 and the insulating layer 120.

[0064] On the other hand, the counter substrate 200 may include a substrate 201 and a plurality of filter patterns FP disposed on the substrate 201. These filter patterns FP may overlap the plurality of reflective electrodes RE of the plurality of pixel structures PX and have at least three filter colors. For example, each of the filter patterns FP may be adapted to pass red light, green light, blue light, or white light, but this is not limited thereto. In other embodiments, the counter substrate 200 may not include the filter patterns FP.

[0065] In this embodiment, a common electrode layer CEL and a covering layer 210 may also be provided on the substrate 201, but the present invention is not limited thereto. The covering layer 210 covers a plurality of filter patterns FP, and the common electrode layer CEL is provided on the covering layer 210. In other embodiments, a common electrode layer CEL may be provided on the substrate 101 (i.e., the common electrode layer CEL is located between the substrate 101 and the liquid crystal layer LCL). The electric field generated between the common electrode layer CEL and the reflective electrode RE is suitable for driving the plurality of liquid crystal molecules (not shown) of the liquid crystal layer LCL to rotate and form an arrangement state corresponding to the direction and intensity of the electric field. By changing the arrangement state of these liquid crystal molecules, the polarization state of the light passing through the liquid crystal layer LCL is changed to form a light output brightness corresponding to the arrangement state.

[0066] Please refer to Figures 1 to 3 First, to prevent electrical short circuits between at least three reflective electrodes RE caused by etched metal residues formed during the etching process due to a loading effect in areas adjacent to these reflective electrodes RE, the distance between any two adjacent reflective electrodes RE in these areas is greater than the distance between any two adjacent reflective electrodes RE in areas farther away from these areas. This ensures that the reflective electrodes RE formed after the etching process are electrically independent of each other.

[0067] For example, in this embodiment, each of the plurality of pixel structures PX on the pixel array substrate 100 includes a reflective electrode RE, and the plurality of reflective electrodes RE include, for example, a first reflective electrode RE1, a second reflective electrode RE2, a third reflective electrode RE3, and a fourth reflective electrode RE4. The first reflective electrode RE1 and the second reflective electrode RE2 are adjacently arranged along a direction D1 and separated by a first slit SLT1. The first reflective electrode RE1 and the third reflective electrode RE3 are adjacently arranged along a direction D2 and separated by a second slit SLT2. The second reflective electrode RE2 and the fourth reflective electrode RE4 are adjacently arranged along a direction D2 and separated by a third slit SLT3. The third reflective electrode RE3 and the fourth reflective electrode RE4 are adjacently arranged along a direction D1 and separated by a fourth slit SLT4. The first slit SLT1 and the fourth slit SLT4 may extend in the direction D2 and be aligned with each other, while the second slit SLT2 and the third slit SLT3 may extend in the direction D1 and be aligned with each other, but the present invention is not limited thereto.

[0068] In detail, the first slit SLT1 includes a first central portion SLT1cp and a first edge portion SLT1ep, both communicating with each other. The first edge portion SLT1ep is adjacent to the third reflective electrode RE3 and the fourth reflective electrode RE4. The first central portion SLT1cp is located on the side of the first edge portion SLT1ep that is away from the third reflective electrode RE3 and the fourth reflective electrode RE4. The second slit SLT2 includes a second central portion SLT2cp and a second edge portion SLT2ep, both communicating with each other. The second edge portion SLT2ep is adjacent to the second reflective electrode RE2 and the fourth reflective electrode RE4. The second central portion SLT2cp is located on the side of the second edge portion SLT2ep that is away from the second reflective electrode RE2 and the fourth reflective electrode RE4. The third slit SLT3 includes a third central portion SLT3cp and a third edge portion SLT3ep, both communicating with each other. The third edge portion SLT3ep is adjacent to the first reflective electrode RE1 and the third reflective electrode RE3. The third central portion SLT3cp is located on the side of the third edge portion SLT3ep that is away from the first reflective electrode RE1 and the third reflective electrode RE3. The fourth slit SLT4 includes a fourth central portion SLT4cp and a fourth edge portion SLT4ep that are connected to each other. The fourth edge portion SLT4ep is adjacent to the first reflective electrode RE1 and the second reflective electrode RE2. The fourth central portion SLT4cp is located on the side of the fourth edge portion SLT4ep that is remote from the first reflective electrode RE1 and the second reflective electrode RE2. From another perspective, the first edge portion SLT1ep of the first slit SLT1 is adjacent to the second slit SLT2, the third slit SLT3, and the fourth slit SLT4, and the first central portion SLT1cp is located on the side of the first edge portion SLT1ep that is remote from the second slit SLT2, the third slit SLT3, and the fourth slit SLT4. The second edge portion SLT2ep of the second slit SLT2 is adjacent to the first slit SLT1, the third slit SLT3, and the fourth slit SLT4, and the second central portion SLT2cp is located on the side of the second edge portion SLT2ep that is remote from the first slit SLT1, the third slit SLT3, and the fourth slit SLT4. The third edge portion SLT3ep of the third slit SLT3 is adjacent to the first slit SLT1, the second slit SLT2, and the fourth slit SLT4, and the third central portion SLT3cp is located on a side of the third edge portion SLT3ep away from the first slit SLT1, the second slit SLT2, and the fourth slit SLT4. The fourth edge portion SLT4ep of the fourth slit SLT4 is adjacent to the first slit SLT1, the second slit SLT2, and the third slit SLT3, and the fourth central portion SLT4cp is located on a side of the fourth edge portion SLT4ep away from the first slit SLT1, the second slit SLT2, and the third slit SLT3.

[0069] In this embodiment, the first edge portion SLT1ep, the second edge portion SLT2ep, the third edge portion SLT3ep, and the fourth edge portion SLT4ep are interconnected, and their orthographic projection on the substrate surface 101s of the substrate 101 forms a cross, but this is not limiting. It should be noted that the width W1e of the first edge portion SLT1ep along direction D1 is greater than the width W1c of the first central portion SLT1cp along direction D1. The width W2e of the second edge portion SLT2ep along direction D2 is greater than the width W2c of the second central portion SLT2cp along direction D2. The width W3e of the third edge portion SLT3ep along direction D2 is greater than the width W2c of the third central portion SLT3cp along direction D2. The width W4e of the fourth edge portion SLT4ep along direction D1 is greater than the width W4c of the fourth central portion SLT4cp along direction D1.

[0070] For example, when the width W1c of the first central portion SLT1cp, the width W2c of the second central portion SLT2cp, the width W3c of the third central portion SLT3cp, and the width W4c of the fourth central portion SLT4cp are less than or equal to 3 microns, the width W1e of the first edge portion SLT1ep, the width W2e of the second edge portion SLT2ep, the width W3e of the third edge portion SLT3ep, and the width W4e of the fourth edge portion SLT4ep are designed to be larger than the widths of the aforementioned central portions (for example, larger than 3 microns), thereby ensuring that the reflective electrodes RE1 to RE4 formed after the etching process are electrically independent of each other.

[0071] From another perspective, the width of the areas immediately adjacent to the four reflective electrodes (i.e., the four edges of the four slits) is greater along both directions D1 and D2 than the width of the slits further away from these areas (i.e., the central portions). Therefore, even if metal residue remains in these areas due to the greater loading effect during the etching process, the four reflective electrodes remain electrically isolated after etching.

[0072] Since the reflective electrode RE of the pixel structure PX of the reflective display panel 10 is used to reflect ambient light or light from the frontlight module to display the corresponding image, the planar area of the reflective electrode RE of the pixel structure PX (i.e., the area of the reflective electrode RE in the plane formed by directions D1 and D2) corresponds to the display area of the pixel structure PX. In this embodiment, by designing the gap between two adjacent reflective electrodes RE to have a narrower central portion and a wider edge portion, this not only prevents short circuits between adjacent reflective electrodes RE caused by a loading effect, but also maintains a larger reflective electrode RE area to prevent a significant decrease in the reflectivity of the pixel structure PX, which could affect the display quality of the reflective display panel 10. Furthermore, the design of the gap between two adjacent reflective electrodes RE having a narrower central portion and a wider edge portion in this embodiment is applicable not only to the aforementioned pixel structure PX but also to the design of reflective electrodes in the pixel structures of reflective display panels of various embodiments, thereby preventing short circuits between adjacent reflective electrodes and a significant decrease in the reflectivity of the pixel structure.

[0073] It is particularly noted that in order to achieve the aforementioned relationship between the width of the gap between any two adjacent reflective electrodes in the central portion and the edge portion, the width of the exposure (or shading) area corresponding to the formation of each of the aforementioned edge portions of the mask used in the lithography process is also larger than the width of the exposure (or shading) area corresponding to the formation of each of the aforementioned central portions.

[0074] Some other embodiments will be listed below to illustrate the present disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the aforementioned embodiments and will not be repeated below.

[0075] Figure 4 : is a front view schematic diagram of a pixel array substrate according to a second embodiment of the present invention. Figure 4 The pixel array substrate 100A of this embodiment is Figure 3 The difference between the pixel array substrate 100 and the pixel array substrate 101 lies in the configuration of the edge portions of the slits. Specifically, in this embodiment, the orthographic projection outlines of the first edge portion SLT1ep-A of the first slit SLT1-A, the second edge portion SLT2ep-A of the second slit SLT2-A, the third edge portion SLT3ep-A of the third slit SLT3-A, and the fourth edge portion SLT4ep-A of the fourth slit SLT4-A on the substrate surface of the substrate 101 are rhombus-shaped, with the four corners of the rhombus facing the first slit SLT1-A, the second slit SLT2-A, the third slit SLT3-A, and the fourth slit SLT4-A, respectively.

[0076] From another point of view, the width W1e of the first edge portion SLT1ep-A along the direction D1 increases as it approaches the fourth edge portion SLT4ep-A, the width W2e of the second edge portion SLT2ep-A along the direction D2 increases as it approaches the third edge portion SLT3ep-A, the width W3e of the third edge portion SLT3ep-A along the direction D2 increases as it approaches the second edge portion SLT2ep-A, and the width W4e of the fourth edge portion SLT4ep-A along the direction D1 increases as it approaches the first edge portion SLT1ep-A.

[0077] By ensuring that the width of each slit's edge is greater than that of its center and that the width gradually increases as it moves away from the center, electrical shorts between the four reflective electrodes caused by etched metal residues formed during the etching process due to a loading effect can be avoided. In other words, the electrical independence of the multiple reflective electrodes formed during the etching process is ensured, thereby improving the production yield of the pixel array substrate 100A.

[0078] Figure 5 FIG is a front view schematic diagram of a pixel array substrate according to a third embodiment of the present invention. Figure 5 The pixel array substrate 100B of this embodiment is Figure 3 The difference between the pixel array substrate 100 and the pixel array substrate 100 is that the configuration of the edge portions of the slits is different. Specifically, in this embodiment, the orthographic projection outlines of the first edge portion SLT1ep-B of the first slit SLT1-B, the second edge portion SLT2ep-B of the second slit SLT2-B, the third edge portion SLT3ep-B of the third slit SLT3-B, and the fourth edge portion SLT4ep-B of the fourth slit SLT4-B on the substrate surface of the substrate 101 are circular.

[0079] From another point of view, the width W1e of the first edge portion SLT1ep-B along the direction D1 increases as it approaches the fourth edge portion SLT4ep-B, the width W2e of the second edge portion SLT2ep-B along the direction D2 increases as it approaches the third edge portion SLT3ep-B, the width W3e of the third edge portion SLT3ep-B along the direction D2 increases as it approaches the second edge portion SLT2ep-B, and the width W4e of the fourth edge portion SLT4ep-B along the direction D1 increases as it approaches the first edge portion SLT1ep-B.

[0080] By ensuring that the width of each slit's edge is greater than that of its center and that the width gradually increases as it moves away from the center, electrical shorts between the four reflective electrodes caused by etched metal residues formed during the etching process due to a loading effect can be avoided. In other words, the electrical independence of the multiple reflective electrodes formed during the etching process is ensured, thereby improving the production yield of the pixel array substrate 100B.

[0081] Figure 6 FIG is a front view schematic diagram of a pixel array substrate according to a fourth embodiment of the present invention. Figure 6 The pixel array substrate 100C of this embodiment is Figure 3 The difference between the pixel array substrate 100 and the pixel array substrate 100 is that the configuration of the edge portions of the slits is different. Specifically, in this embodiment, the orthographic projection outlines of the first edge portion SLT1ep-C of the first slit SLT1-C, the second edge portion SLT2ep-C of the second slit SLT2-C, the third edge portion SLT3ep-C of the third slit SLT3-C, and the fourth edge portion SLT4ep-C of the fourth slit SLT4-C on the substrate surface of the substrate 101 are rectangular.

[0082] From another perspective, the width W1e of the first edge portion SLT1ep-C along direction D1 remains constant as it approaches the fourth edge portion SLT4ep-C, the width W2e of the second edge portion SLT2ep-C along direction D2 remains constant as it approaches the third edge portion SLT3ep-C, the width W3e of the third edge portion SLT3ep-C along direction D2 remains constant as it approaches the second edge portion SLT2ep-C, and the width W4e of the fourth edge portion SLT4ep-C along direction D1 remains constant as it approaches the first edge portion SLT1ep-C. In this embodiment, widths W1e, W2e, W3e, and W4e may be equal, meaning that the orthographic projections of the four edge portions on the substrate surface may be square, but this is not limited to this.

[0083] By making the edge width of each slit greater than the center width, electrical short circuits between the four reflective electrodes caused by etched metal residues formed in areas adjacent to the four reflective electrodes during the etching process due to a loading effect can be avoided. In other words, the electrical independence of the multiple reflective electrodes formed during the etching process is ensured, thereby improving the production yield of the pixel array substrate 100C.

[0084] Figure 7 FIG is a front view of a pixel array substrate according to a fifth embodiment of the present invention. Figure 7 The pixel array substrate 100D of this embodiment is Figure 3The difference between the pixel array substrate 100 and the pixel array substrate 100 is that the configuration of the edge portions of the slits is different. Specifically, in this embodiment, the width W1e of the first edge portion SLT1ep-D of the first slit SLT1-D along the direction D1 increases as it approaches the fourth edge portion SLT4ep-D, the width W2e of the second edge portion SLT2ep-D of the second slit SLT2-D along the direction D2 increases as it approaches the third edge portion SLT3ep-D, the width W3e of the third edge portion SLT3ep-D of the third slit SLT3-D along the direction D2 increases as it approaches the second edge portion SLT2ep-D, and the width W4e of the fourth edge portion SLT4ep-D of the fourth slit SLT4-D along the direction D1 increases as it approaches the first edge portion SLT1ep-D.

[0085] It is particularly noteworthy that, in this embodiment, the rate of change in the width of the edge portion of each slit increases as it moves away from its central portion. That is, in this embodiment, the orthographic projection of the four edge portions onto the surface of substrate 101 generally forms a four-pointed star with four inwardly concave sides.

[0086] By ensuring that the width of each slit's edge is greater than that of its center and that the width gradually increases as it moves away from the center, electrical shorts between the four reflective electrodes caused by etched metal residues formed during the etching process due to a loading effect can be avoided. In other words, the electrical independence of the multiple reflective electrodes formed during the etching process is ensured, thereby improving the production yield of the pixel array substrate 100D.

[0087] Figure 8 : is a front view schematic diagram of a pixel array substrate according to a sixth embodiment of the present invention. Figure 8 The pixel array substrate 100E of this embodiment is Figure 3 The difference between the pixel array substrate 100 and the pixel array substrate 101 lies in the configuration of the slit edge portions. Specifically, in this embodiment, the orthographic projection outlines of the first edge portion SLT1ep-E of the first slit SLT1-E, the second edge portion SLT2ep-E of the second slit SLT2-E, the third edge portion SLT3ep-E of the third slit SLT3-E, and the fourth edge portion SLT4ep-E of the fourth slit SLT4-E on the substrate surface of the substrate 101 are star-shaped.

[0088] From another point of view, the width W1e of the first edge portion SLT1ep-E along the direction D1 increases as it approaches the fourth edge portion SLT4ep-E, the width W2e of the second edge portion SLT2ep-E along the direction D2 increases as it approaches the third edge portion SLT3ep-E, the width W3e of the third edge portion SLT3ep-E along the direction D2 increases as it approaches the second edge portion SLT2ep-E, and the width W4e of the fourth edge portion SLT4ep-E along the direction D1 increases as it approaches the first edge portion SLT1ep-E.

[0089] By ensuring that the width of each slit's edge is greater than that of its center and that the width gradually increases as it moves away from the center, electrical shorts between the four reflective electrodes caused by etched metal residues formed during the etching process due to a loading effect can be avoided. In other words, the electrical independence of the multiple reflective electrodes formed during the etching process is ensured, thereby improving the production yield of the pixel array substrate 100E.

[0090] In each of the above embodiments, the reflective electrode RE defines a reflective region of the reflective display panel 10. It should be noted that the reflective display panel 10 of the present invention may be a fully reflective display panel having only a reflective region, or a transflective display panel having both a reflective region and a transmissive region (not shown).

[0091] In summary, in a reflective display panel according to one embodiment of the present invention, the gap between any reflective electrode and its adjacent reflective electrode on the pixel array substrate includes an edge portion proximate to the adjacent reflective electrode and a central portion distal to the adjacent reflective electrode. By having the width of the edge portion be greater than the width of the central portion in the alignment direction of the reflective electrode and the adjacent reflective electrode, the reflective electrodes are electrically isolated from each other after the etching process, thereby improving the production yield of the reflective display panel.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pixel array substrate, characterized in that: include: substrate; as well as A plurality of pixel structures are provided on the substrate, each of the plurality of pixel structures includes a reflective electrode, the plurality of reflective electrodes in the plurality of pixel structures include a first reflective electrode, a second reflective electrode, and a third reflective electrode, the first reflective electrode and the second reflective electrode are adjacently arranged along a first direction and separated by a first gap, the first reflective electrode and the third reflective electrode are adjacently arranged along a second direction and separated by a second gap, the first direction intersecting the second direction, The first slit has a first edge portion and a first central portion that are connected to each other, the first edge portion is adjacent to the third reflective electrode, the first central portion is located on a side of the first edge portion away from the third reflective electrode, and a width of the first edge portion along the first direction is greater than a width of the first central portion along the first direction. The second slit has a second edge portion and a second central portion that are connected to each other, the second edge portion is adjacent to the second reflective electrode, the second central portion is located on a side of the second edge portion away from the second reflective electrode, and the width of the second edge portion along the second direction is greater than the width of the second central portion along the second direction.

2. The pixel array substrate according to claim 1, wherein: The multiple reflective electrodes further include a fourth reflective electrode, the second reflective electrode and the fourth reflective electrode are adjacently arranged along the second direction and separated by a third gap, the third reflective electrode and the fourth reflective electrode are adjacently arranged along the first direction and separated by a fourth gap, the third gap having a third edge portion and a third central portion that are connected to each other, the third edge portion being closely adjacent to the first reflective electrode, the third central portion being located on a side of the third edge portion away from the first reflective electrode, and a width of the third edge portion along the second direction being greater than a width of the third central portion along the second direction, and the fourth gap having a fourth edge portion and a fourth central portion that are connected to each other, the fourth edge portion being closely adjacent to the second reflective electrode, the fourth central portion being located on a side of the fourth edge portion away from the second reflective electrode, and a width of the fourth edge portion along the first direction being greater than a width of the fourth central portion along the first direction.

3. The pixel array substrate according to claim 2, wherein: The first edge portion, the second edge portion, the third edge portion, and the fourth edge portion are connected to each other, and their orthographic projection contours on the substrate surface of the substrate are in a cross, diamond, circle, rectangle, or star shape.

4. The pixel array substrate according to claim 2, wherein: The width of the first edge portion increases as it approaches the fourth edge portion, the width of the second edge portion increases as it approaches the third edge portion, the width of the third edge portion increases as it approaches the second edge portion, and the width of the fourth edge portion increases as it approaches the first edge portion.

5. The pixel array substrate according to claim 2, wherein: The width of the first central portion, the width of the second central portion, the width of the third central portion, and the width of the fourth central portion are less than or equal to 3 micrometers.

6. A reflective display panel, characterized in that: include: A pixel array substrate, comprising: substrate; and a plurality of pixel structures disposed on the substrate, each of the plurality of pixel structures including a reflective electrode, the plurality of reflective electrodes in the plurality of pixel structures including a first reflective electrode, a second reflective electrode, and a third reflective electrode, the first reflective electrode and the second reflective electrode being adjacently arranged along a first direction and separated by a first gap, the first reflective electrode and the third reflective electrode being adjacently arranged along a second direction and separated by a second gap, the first direction intersecting the second direction, wherein the first gap has a first edge portion and a first central portion that are connected to each other, the first edge portion being proximate to the third reflective electrode, the first central portion being located on a side of the first edge portion away from the third reflective electrode, and a width of the first edge portion along the first direction being greater than a width of the first central portion along the first direction, the second gap having a second edge portion and a second central portion that are connected to each other, the second edge portion being proximate to the second reflective electrode, the second central portion being located on a side of the second edge portion away from the second reflective electrode, and a width of the second edge portion along the second direction being greater than a width of the second central portion along the second direction; an opposite substrate, arranged to overlap the pixel array substrate; and The liquid crystal layer is arranged between the pixel array substrate and the opposite substrate.

7. The reflective display panel according to claim 6, wherein: The multiple reflective electrodes further include a fourth reflective electrode, the second reflective electrode and the fourth reflective electrode are adjacently arranged along the second direction and separated by a third gap, the third reflective electrode and the fourth reflective electrode are adjacently arranged along the first direction and separated by a fourth gap, the third gap having a third edge portion and a third central portion that are connected to each other, the third edge portion being closely adjacent to the first reflective electrode, the third central portion being located on a side of the third edge portion away from the first reflective electrode, and a width of the third edge portion along the second direction being greater than a width of the third central portion along the second direction, and the fourth gap having a fourth edge portion and a fourth central portion that are connected to each other, the fourth edge portion being closely adjacent to the second reflective electrode, the fourth central portion being located on a side of the fourth edge portion away from the second reflective electrode, and a width of the fourth edge portion along the first direction being greater than a width of the fourth central portion along the first direction.

8. The reflective display panel according to claim 7, wherein: The first edge portion, the second edge portion, the third edge portion, and the fourth edge portion are connected to each other, and their orthographic projection contours on the substrate surface of the substrate are in a cross, diamond, circle, rectangle, or star shape.

9. The reflective display panel according to claim 7, wherein: The width of the first edge portion increases as it approaches the fourth edge portion, the width of the second edge portion increases as it approaches the third edge portion, the width of the third edge portion increases as it approaches the second edge portion, and the width of the fourth edge portion increases as it approaches the first edge portion.

10. The reflective display panel according to claim 7, wherein: The width of the first central portion, the width of the second central portion, the width of the third central portion, and the width of the fourth central portion are less than or equal to 3 micrometers.

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