Method for dynamically adjusting first-in first-out buffer operation mechanism and transmission system thereof

Abstract

The embodiment of the invention relates to a method for dynamically adjusting a first-in first-out buffer operation mechanism and a transmission system using the same. The method comprises the following steps: inspecting the type of the processor according to system information; when the type of the processor is a first type, calculating a packet difference value between the number of packets input to the first-in first-out buffer and the number of packets output to the processor until an error occurs; and adjusting the size of the first-in first-out buffer according to the packet difference value. When the type of the processor is a second type, calculating the time length of the processor from the sleep state to the reading of the first-in first-out buffer; and according to the time duration, determining how many interrupt instructions need to be triggered when the first-in first-out buffer is stored.

Description

Technical Field

[0001] The present invention relates to a first-in-first-out transmission technology, and more particularly to a method for dynamically adjusting a first-in-first-out buffer operation mechanism and a transmission system using the same. Background Art

[0002] The First In, First Out (FIFO) buffer is a widely used buffering mechanism in serial communication systems, such as Universal Asynchronous Receiver / Transmitter (UART). However, while it plays an important role in improving system performance and data flow, it also faces some challenges, especially in scenarios involving processor performance.

[0003] A common problem is that when processor performance is low, the FIFO buffer system may not be able to process the received data in a timely manner, resulting in a data overrun error. This is because when the system cannot read and process the data in the FIFO buffer in a timely manner, the new data will overwrite the old unprocessed data, causing an error.

[0004] On the other hand, similar issues can occur even with high-performance processors. In high-performance systems, the processor may read data from a first-in-first-out buffer at a rapid rate and then enter sleep or hibernation mode to save energy. However, if an interrupt fails to wake the processor in time, new data may arrive before the processor enters sleep mode, resulting in the same data overwrite error. Summary of the Invention

[0005] The present invention provides a method for dynamically adjusting a FIFO buffer operation mechanism and a transmission system using the same, for selecting the best FIFO buffer adjustment or interruption strategy according to different processor types to avoid subsequent errors.

[0006] An embodiment of the present invention provides a method for dynamically adjusting a first-in-first-out (FIFO) buffer operation mechanism, applicable to a universal asynchronous receiver / transmitter (UART). The method comprises: inspecting a processor type based on system information; when the processor type is a first type, performing operation A: calculating the packet difference between the number of packets input to the FIFO buffer and the number of packets output from the processor until an error occurs; and adjusting the size of the FIFO buffer based on the packet difference; and when the processor type is a second type, performing operation B: calculating the time it takes for the processor to read the FIFO buffer from a sleep state; and determining, based on the time and the current transmission rate of the UART, the number of packets stored in the FIFO buffer required to trigger an interrupt instruction to wake the processor when the processor is in sleep mode.

[0007] An embodiment of the present invention further provides a first-in-first-out transmission system, which includes a processor, a first-in-first-out buffer, a receiving circuit, a counting circuit, and a decision control circuit. The receiving circuit is coupled to the first-in-first-out buffer to receive packets and sequentially temporarily store them in the first-in-first-out buffer. The counting circuit is used to calculate the difference between the packets received by the receiving circuit and the packets sent by the first-in-first-out buffer until an error occurs, thereby generating a packet difference. The decision control circuit is coupled to the processor and the counting circuit to check the processor type based on system information. When the processor type is the first type, the counting circuit is controlled to calculate the difference until an error occurs and adjust the size of the first-in-first-out buffer based on the difference. When the processor type is the second type, the time length for the processor to reach a state of reading the first-in-first-out buffer from a sleep state is calculated, and based on the time length and the transmission rate used at the time, the number of packets stored in the first-in-first-out buffer is determined to trigger an interrupt instruction to wake up the processor.

[0008] According to a preferred embodiment of the present invention, the method for dynamically adjusting a FIFO buffering mechanism and a transmission system utilizing the same further include a BIOS circuit, wherein the decision control circuit detects the processor's status via the BIOS circuit. In another preferred embodiment, the FIFO transmission system further includes a bus, wherein the decision control circuit communicates with the BIOS circuit via the bus.

[0009] According to a preferred embodiment of the present invention, the method for dynamically adjusting a FIFO buffering mechanism and the transmission system utilizing the same, when the processor is in the first mode, the decision control circuit increases the original FIFO buffer capacity by the difference based on the difference. In another preferred embodiment, if the decision control circuit detects that the processor enters the sleep state before an error occurs, the decision control circuit sets the processor mode to the second mode.

[0010] In summary, embodiments of the present invention categorize processors into two types based on their characteristics. The first type of processor calculates the packet difference between input and output packets. When a data overrun error occurs, the size of the FIFO buffer is expanded based on this difference. The second type of processor calculates the time required for the processor to wake up from sleep mode. Based on the current transmission rate, the FIFO buffer capacity is adjusted to the level at which an immediate interrupt instruction is required to wake the processor. These different strategies can effectively prevent data overrun errors.

[0011] To further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, which may provide a thorough and specific understanding of the purposes, features and concepts of the present invention. However, the following detailed description and accompanying drawings are intended only to provide a reference and illustration of the implementation of the present invention and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are provided to help those skilled in the art to which the present invention pertains to further understanding of the present invention and are incorporated into and constitute a part of the specification of the present invention. The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the specification of the present invention, are used to explain the principles of the present invention.

[0013] Figure 1 FIG. 1 is a system block diagram of a first-in-first-out transmission system according to a preferred embodiment of the present invention.

[0014] Figure 2 FIG2 is a flow chart illustrating a method for dynamically adjusting a first-in-first-out buffer operation mechanism according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0015] Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used in the drawings and the description to refer to the same or similar parts. The exemplary embodiments are merely one way to implement the design concepts of the present invention, and the following examples are not intended to limit the present invention.

[0016] Figure 1The diagram shows a system block diagram of a first-in-first-out transmission system according to a preferred embodiment of the present invention. Figure 1 This FIFO transmission system includes a processor 101, a FIFO buffer 102, a receiving circuit 103, a counting circuit 104, a decision control circuit 105, a flat cable 106, and a basic input / output system circuit 107. The coupling relationship is shown in the figure. This embodiment uses a general personal computer system as an example, so the FIFO transmission system is exemplified by a universal asynchronous receiver / transmitter (UART).

[0017] In this embodiment, the decision control circuit 105 first detects the type of the processor 101 through system information. In this embodiment, the processor 101 can be divided into a slow processor type and a fast processor type. In addition, in this embodiment, there are two solutions for the slow processor type and the fast processor type, respectively referred to as operation A and operation B. When the processor 101 is a slow processor type, a larger size of the first-in-first-out buffer 102 is generally required. However, the system does not allow unlimited configuration of the first-in-first-out buffer 102. To simply explain the present invention, it is first assumed that it is determined that the processor is a slow processor type. In addition, it is assumed that in the initial setting, the size of the first-in-first-out buffer 102 can store 10 packets.

[0018] At the start of transmission, receiving circuit 103 begins receiving packets from an external device and sends them to FIFO buffer 102. Counter circuit 104 counts the number of packets received. Processor 101 also sequentially removes packets from FIFO buffer 102. Counter circuit 104 also counts the number of packets received by processor 101.

[0019] In this embodiment, processor 101 is assumed to be a slow processor. Suppose, for example, that processor 101 receives packets too slowly, resulting in a data overrun error. In this case, counting circuit 104 stops counting when a data overrun error occurs. This provides the total number of packets received and the total number of packets removed at the time of the data overrun error. Subtracting these two numbers yields the number of packets overrun, or the packet difference. In this embodiment, assuming the packet difference is 4, decision control circuit 105 adaptively adjusts the size of FIFO buffer 102 from 10 to 14, thereby preventing a recurrence of the data overrun error.

[0020] The above embodiment describes an example of operation A. The following describes an embodiment of operation B.

[0021] Similarly, assume that processor 101 is a fast processor. Processor 101 is very fast and can receive all the packets stored in FIFO buffer 102 at once. However, in order to save power, processor 101 will enter sleep mode immediately after completing the reading of FIFO buffer 102 and there is no more data to read. At this time, receiving circuit 103 will continue to receive packets and store them in FIFO buffer 102. Decision control circuit 105 will detect the current remaining capacity of FIFO buffer 102. When the remaining capacity of FIFO buffer 102 is 2, that is, when 8 packets have been stored, an interrupt instruction will be triggered to processor 101 to wake up processor 101 and inform processor 101 to start receiving packets from FIFO buffer 102.

[0022] At this time, the decision control circuit 105 also detects the time required to wake up the processor 101. When a data overrun error occurs, it means that data was continuously being received between the time the interrupt instruction was triggered and the time the processor 101 was awakened, resulting in a data overrun error. The decision control circuit 105 then determines when to trigger the interrupt instruction for the next transmission based on the time it takes for the processor 101 to be triggered and awakened, as well as the transmission rate. Here, a simple mathematical formula illustrates this:

[0023]

[0024] The Interrupt Trigger Level indicates the time at which the interrupt instruction is triggered, that is, the buffer capacity required to trigger an interrupt; the FIFO depth indicates the size of the FIFO buffer; the Round indicates the number of times the buffer is stored; the Trvcore indicates the time required for the processor to wake up; and the Baudtime indicates the transmission rate used at the time, using the transmission time required for one packet as an example. For example, if a packet is overwritten during the time between when the processor 101 is triggered and when it wakes up to read the FIFO 102, the decision control circuit 105 will determine, based on the relationship between the transmission rate and the interrupt, whether to trigger an interrupt instruction to the processor 101 the next time the remaining capacity of the FIFO 102 equals the calculated trigger level, for example, when Round = 4, that is, when the Interrupt Trigger Level equals 6 packets.

[0025] From the above embodiments, it can be seen that the present invention adopts two different means to select the best FIFO buffer size adjustment or change the interrupt strategy for different types of processors to avoid subsequent errors.

[0026] In the above embodiment, the type of processor 101 can be determined from system information, for example. For example, the decision control circuit 105 can obtain information about the processor 101 from the flat cable 106 via the basic input / output system circuit 107. This allows a determination to be made as to whether operation A or operation B is to be used as a strategy for preventing data overwrite errors. In another preferred embodiment, the type of processor can be determined based on the time required for the processor 101 to transition from a sleep state to a wake-up state. Furthermore, in another preferred embodiment, the type of processor can be determined based on the power ramp time of the processor 101. Furthermore, in another preferred embodiment, assuming that the processor 101 had already entered a sleep state before the data overwrite error occurred, in this case, it can also be directly determined that the processor 101 is a fast processor type.

[0027] The above embodiments can be summarized into a method for dynamically adjusting the FIFO buffer operation mechanism. Figure 2 FIG2 is a flow chart illustrating a method for dynamically adjusting a first-in-first-out buffer operation mechanism according to a preferred embodiment of the present invention.

[0028] Please refer to Figure 2 The method for dynamically adjusting the first-in-first-out buffer operation mechanism includes the following steps:

[0029] Step S201: Start.

[0030] Step S202: Determine the processor type. For example, the processor type can be determined based on the time required to transition from sleep to wakeup, the power ramp-up time, and whether the processor 101 has previously entered a sleep state before the data overwrite error occurs. If the processor type is determined to be a slow processor, the process proceeds to step S203. If the processor type is determined to be a fast processor, the process proceeds to step S205.

[0031] Step S203: Calculate a packet difference between the number of packets input to the FIFO buffer and the number of packets output to the processor until an error occurs.

[0032] Step S204: Adjust the size of the FIFO buffer according to the packet difference.

[0033] Step S205: Calculate the time length for the processor to read the FIFO buffer from a sleep state.

[0034] Step S206: Based on the aforementioned time duration and the current UART transmission rate, a determination is made as to how many packets are stored in the FIFO buffer when the processor is dormant, requiring an interrupt instruction to be triggered to wake up the processor. As described in the above embodiment, the ratio of Trvcore to Baudtime is used to determine the interrupt triggering time to wake up the processor.

[0035] In summary, embodiments of the present invention categorize processors into two types based on their characteristics. The first type of processor calculates the packet difference between input and output packets. When a data overrun error occurs, the size of the FIFO buffer is expanded based on this difference. The second type of processor calculates the time required for the processor to wake up from sleep mode and adjusts the FIFO buffer storage level to the level at which an immediate interrupt instruction is required to wake the processor. These different strategies can effectively prevent data overrun errors.

[0036] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to those skilled in the art and are to be included within the spirit and purview of this application and the scope of the appended claims.

Claims

1. A method for dynamically adjusting a first-in-first-out buffer operation mechanism, applicable to a universal asynchronous receiver / transmitter (UART), wherein the method comprises: include: Determine the type of processor; When the type of the processor is the first type, perform operation A: calculating a packet difference between a number of packets input to a first-in-first-out buffer and a number of packets output to the processor until an error occurs; as well as adjusting the size of the first-in-first-out buffer according to the packet difference; When the type of the processor is the second type, perform operation B: Calculating the time length of the processor from the sleep state to the read state of the first-in-first-out buffer; as well as According to the time length and the transmission rate of the UART currently used, it is determined that when the processor is in sleep mode, an interrupt instruction needs to be triggered when the number of packets stored in the FIFO buffer is reached to wake up the processor.

2. The method for dynamically adjusting the first-in-first-out buffer operation mechanism according to claim 1, wherein: The step of adjusting the size of the first-in-first-out buffer according to the packet difference comprises: The original packet capacity of the FIFO buffer is increased by the packet difference.

3. The method for dynamically adjusting the first-in-first-out buffer operation mechanism according to claim 1, wherein: The step of determining the type of the processor comprises: The type of the processor is determined according to the time required for the processor to change from the sleep state to an awake state.

4. The method for dynamically adjusting the first-in-first-out buffer operation mechanism according to claim 1, wherein: The step of determining the type of the processor comprises: The type of the processor is determined according to the power ramp-up time of the processor.

5. The method for dynamically adjusting the first-in-first-out buffer operation mechanism according to claim 1, wherein: The step of determining the type of the processor comprises: Determining whether the processor enters the sleep state before the error occurs; and If the processor has entered the sleep state before the error occurs, the mode of the processor is set to the second mode.

6. A first-in-first-out transmission system, characterized in that: include: processor; First-in-first-out buffer; A receiving circuit coupled to the FIFO buffer receives packets and temporarily stores them in the FIFO buffer in sequence; a counting circuit for calculating a difference between packets received by the receiving circuit and packets sent by the FIFO buffer until an error occurs, thereby generating a packet difference; as well as A decision control circuit is coupled to the processor and the counting circuit, and is used to check the type of the processor according to system information. wherein, when the type of the processor is the first type, controlling the counting circuit to calculate the packet difference until an error occurs, and adjusting the size of the first-in-first-out buffer according to the packet difference; When the processor is in the second mode, the time length for the processor to read the FIFO buffer from a sleep state is calculated, and based on the time length and the transmission rate used at the time, the number of packets stored in the FIFO buffer is determined to trigger an interrupt instruction to wake up the processor.

7. The first-in-first-out transmission system according to claim 6, characterized in that: include: A basic input-output system circuit, wherein the decision control circuit checks the type of the processor through the basic input-output system circuit.

8. The first-in-first-out transmission system according to claim 7, characterized in that: include: A bus, wherein the decision control circuit communicates with the basic input and output system circuit through the bus.

9. The first-in-first-out transmission system according to claim 6, characterized in that: When the processor is in the first type, the decision control circuit increases the original packet capacity of the FIFO buffer by the packet difference.

10. The first-in-first-out transmission system according to claim 6, characterized in that: include: When the decision control circuit detects that the processor has entered the sleep state before an error occurs, the decision control circuit sets the mode of the processor to the second mode.

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