Debugging interface conversion device and server

Abstract

The invention discloses a debugging interface conversion device and a server. The debugging interface conversion device comprises a debugging bus controller, a debugging signal end of the debugging bus controller is connected with a debugging interface bus of the at least one extended function chip, and the debugging bus controller is used for receiving a debugging signal sent by the extended function chip through the debugging interface bus through the debugging signal end and converting the debugging signal into a network protocol signal; and the network interface is connected with the network protocol signal output end of the debugging bus controller and is used for sending a network protocol signal output by the debugging bus controller through the network protocol signal output end to remote equipment. According to the debugging interface conversion device, a worker can access the debugging interface bus of the extended function chip through the network interface, the remote debugging function of the extended function chip is achieved, and the condition that a tool is connected to a debugging interface on a board card after the whole server is powered off and a case cover is opened is not needed.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a debugging interface conversion device and a server. Background Art

[0002] With the rapid development of cloud computing, big data, and artificial intelligence technologies, the current trend of informationization and intelligentization in society is accelerating. As the core equipment of information systems, servers have become increasingly complex in internal architecture to meet the ever-increasing computing power and performance requirements. For example, multiple complex components such as PCIe Switch (Peripheral Component Interconnect Express Switch, a high-speed serial computer expansion bus standard switch) chips, RAID (disk array) chips, and Expander chips are required to complete system design.

[0003] During server system development, design, and maintenance, debugging and logging are essential. Debug interfaces are required on certain chip-related boards within the system. This requires powering off the server and opening the chassis on-site. Tools are then connected to the debug interface on the board before powering it on. This current design is difficult to use and can cause corruption after powering it back on. Summary of the Invention

[0004] The present application provides a debugging interface conversion device and server, which converts the debugging signals of each extended function chip into network protocol signals through a debugging bus controller and outputs them to a network interface. Engineers can remotely access the debugging interface bus of each extended function chip through the network interface, read the debugging data of each extended function chip, realize remote debugging, and facilitate operation and maintenance.

[0005] In a first aspect, the present application provides a debugging interface conversion device, comprising:

[0006] A debug bus controller, wherein a debug signal terminal of the debug bus controller is connected to a debug interface bus of at least one extended function chip, and is configured to receive a debug signal sent by the extended function chip via the debug interface bus through the debug signal terminal, and convert the debug signal into a network protocol signal;

[0007] The network interface is connected to the network protocol signal output terminal of the debug bus controller and is used to send the network protocol signal output by the debug bus controller through the network protocol signal output terminal to the remote device.

[0008] In a second aspect, the present application further provides a server, comprising the debugging interface conversion device as in the first aspect.

[0009] The debug interface conversion device of the present application includes a debug bus controller and a network interface, and connects the debug signal end of the debug bus controller to the debug interface bus of at least one extended function chip, and is used to receive the debug signal sent by the extended function chip through the debug interface bus through the debug signal end, and convert the debug signal into a network protocol signal. Since the network interface is connected to the network protocol signal output end of the debug bus controller, the network interface can send the network protocol signal output by the debug bus controller through the network protocol signal output end to the remote device, and the staff can access the debug interface bus of the extended function chip through the network interface to realize the remote debugging function of the extended function chip. There is no need to power off the entire server and open the chassis cover and then connect the tool to the debug interface on the board as in the prior art, so it is convenient for operation and maintenance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0011] Figure 1 This is a schematic diagram of a debug interface conversion device provided in an embodiment of the present application;

[0012] Figure 2 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application;

[0015] Figure 5 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application;

[0016] Figure 6 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application;

[0017] Figure 7 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application;

[0018] Figure 8 A schematic diagram of another debugging interface conversion device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0021] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0022] With the rapid development of cloud computing, big data, and artificial intelligence technologies, the current trend of informatization and intelligentization in society is accelerating. As the core equipment of information systems, servers have become increasingly complex in their internal architecture to meet the ever-increasing computing power and performance requirements. In addition to basic key components such as the CPU (Central Processing Unit), PCH (Platform Controller Hub), BMC (Baseboard Management Controller), and CPLD (Complex Programmable Logic Device), they also require the use of multiple complex components such as PCIe Switch (Peripheral Component Interconnect Express Switch, a high-speed serial computer expansion bus standard switch) chips, RAID (disk array) chips, and Expander chips to complete the system design.

[0023] During the development, design, operation, and maintenance of server system products, in order to implement system debugging and log output functions, it is necessary to reserve debugging interfaces on some chip-related boards within the system to facilitate engineers to quickly locate problems.

[0024] Currently, internal servers, such as complex chips, have UART (Universal Asynchronous Receiver-Transmitter) buses that are simply reserved for debugging on the relevant boards. This reserved debugging interface requires on-site personnel to first power off the entire server and open the chassis cover, then connect the tool to the debug interface on the board before restarting the server for debugging. This current design is cumbersome and requires a power cycle, which can damage the system.

[0025] Based on the above problems, an embodiment of the present application provides a debugging interface conversion device. By setting a debugging bus controller and a network interface, the debugging signal of each extended function chip is converted into a network protocol signal through the debugging bus controller and output to the network interface. Engineers can remotely access the debugging interface bus of each extended function chip through the network interface, read the debugging data of each extended function chip, realize remote debugging, and facilitate operation and maintenance.

[0026] Figure 1 Schematic diagram of a debugging interface conversion device provided by an embodiment of the present application. Figure 1 As shown, the debug interface conversion device provided in the embodiment of the present application includes a debug bus controller 10 and a network interface 20 .

[0027] The debug signal terminal of the debug bus controller 10 is connected to the debug interface bus of at least one extended function chip 30 , and is used to receive debug signals sent by the extended function chip 30 through the debug interface bus and convert the debug signals into network protocol signals. Figure 1 In the example, three extended function chips 30 are set up. The extended function chip 30 and its corresponding debug interface 31 are connected through a debug interface bus. The extended function chip 30 is connected to the debug interface 31 through the debug interface bus and can be used for local debugging. In addition, in the application embodiment, the debug signal end of the debug bus controller 10 is connected to the debug interface bus of the extended function chip 30, and the debug bus controller 10 can convert the debug signal of the extended function chip 30 into a network protocol signal. The network protocol signal output end of the debug bus controller 10 is also connected to the network interface 20, and the network interface 20 is used to send the network protocol signal output by the debug bus controller 10 through the network protocol signal output end to the remote device. Therefore, engineers can remotely access the debug interface bus of the extended function chip 30 through the network interface 20, read the data of the debug interface bus, and perform remote debugging.

[0028] The debugging interface conversion device provided in the embodiment of the present application can convert the debugging signals of each extended function chip into a network protocol signal through a debugging bus controller and output it to the network interface. Therefore, there is no need to power off the entire server and open the chassis cover to connect the tool to the debugging interface on the board as in the prior art. Compared with the debugging method of the prior art, the embodiment of the present application improves the convenience of debugging operations on the one hand. On the other hand, re-powering on may cause the problem phenomenon to disappear. For example, some faults only appear in a specific operating state and cannot be reproduced after power off, affecting the debugging efficiency. The embodiment of the present application does not require the server to be powered off and restarted, and data can be directly accessed through the network interface. Therefore, the disadvantage of destroying the problem phenomenon after re-powering on can also be avoided.

[0029] In some optional implementations, the debug interface conversion device provided in the embodiments of the present application may further include a network switching chip and a baseboard management controller.

[0030] The network protocol signal output end of the baseboard management controller and the network protocol signal output end of the debug bus controller are both connected to the same network interface through the network switching chip.

[0031] Figure 2 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 2 As shown, the debug interface conversion device may further include a network switch chip 40 and a baseboard management controller 50 .

[0032] The baseboard management controller 50 is a management chip independent of the CPU and typically has a corresponding network interface. This network interface enables remote access, firmware updates, hardware monitoring, power management, security management, and more. It also allows remote access to baseboard management controller logs and system serial port logs, helping debuggers analyze faults.

[0033] In the embodiment of the present application, the baseboard management controller 50 and the debug bus controller use the same network interface 20 through the network switching chip 40. Figure 2 As shown, the network protocol signal output terminal of the baseboard management controller 50 and the network protocol signal output terminal of the debug bus controller 10 are both connected to the network interface 20 through the network switching chip 40 .

[0034] The debug signal of the extended function chip inside the system is converted into a network protocol signal by the debug bus controller 10 and connected to the network switching chip 40. The network protocol signal of the baseboard management controller 50 is also connected to the network switching chip 40. The baseboard management controller 50 and the debug bus controller 10 can be accessed simultaneously through the network interface 20.

[0035] This embodiment of the present application enables remote debugging of extended function chips within the system while retaining the network interface and functionality corresponding to the baseboard management controller. The debug bus controller and baseboard management controller reuse the same network interface, eliminating the need to modify the chassis structure. The corresponding network switching chip only needs to support three ports, resulting in a simple structure and low cost.

[0036] In some optional implementations, the debug interface conversion device provided in the embodiments of the present application may further include a processor, a baseboard management controller, a serial port selection switching module, and an output serial port.

[0037] The processor is connected to the baseboard management controller (BMC) via a data bus, exchanging control commands and data signals with the BMC via the data bus. The BMC is connected to the serial port selection switching module via the system serial bus and the BMC serial bus, respectively. The BMC exchanges system serial port information with the serial port selection switching module via the system serial bus. The BMC exchanges serial port signals with the selection switching module via the BMC serial bus. The serial port selection switching module selects data on the system serial bus or the BMC serial bus for output via the output serial port.

[0038] Figure 3 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 3 As shown, the debug interface conversion device includes a processor 60 , a baseboard management controller 50 , a serial port selection switching module 70 and an output serial port 80 .

[0039] The processor 60 may be, for example, a central processing unit (CPU) or a platform control center (PCH). The processor 60 is connected to the baseboard management control via a data bus. The data bus may be, for example, an LPC (Low Pin Count Bus) or an ESPI (Enhanced Serial Peripheral Interface) bus.

[0040] The processor 60 and the baseboard management controller 50 interact through the data bus to exchange status information (temperature, voltage, sensor data), control commands (reset, power management), firmware related information (BIOS update, firmware image), diagnostic data (POST code, error log), and security related information.

[0041] The BMC 50 is connected to the serial port switching module 70 via the system serial bus SYS UART and the BMC serial bus BMC UART. The serial port switching module 70 is used to select the data on the system serial bus or the BMC serial bus to be output through the output serial port 80.

[0042] Serial port data from processor 60 is transmitted to baseboard management controller 50 via the ESPI bus or LPC bus. Baseboard management controller 50 outputs two buses, one for the system serial port and the other for its own BMC serial port, to gating switch module 70. For example, gating switch module 70 includes a gating circuit. After gating by the gating circuit within gating switch module 70, one bus is output to output serial port 80. Engineers can access both the system serial port and the BMC serial port through output serial port 80.

[0043] In the embodiment of the present application, an output serial port is provided for the baseboard management controller. When a remote communication failure occurs, the baseboard management controller and the system can be debugged on-site through the output serial port.

[0044] In some optional embodiments, the debug interface conversion device provided in the embodiments of the present application may further include a mainboard. The debug bus controller and the network interface are disposed on the mainboard. The extended function chip is connected to the signal interface of the mainboard via a signal interface. The debug interface bus of the extended function chip is connected to the signal interface of the extended function chip. The debug signal terminal of the debug bus controller is connected to the signal interface of the mainboard.

[0045] Figure 4 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 4 As shown, the debug interface conversion device includes a mainboard 100. A debug bus controller 10 and a network interface 20 are disposed on the mainboard.

[0046] The extended function chip 30 is connected to the signal interface of the mainboard 100 via a signal interface. The debug interface bus of the extended function chip 30 is connected to the signal interface of the extended function chip 30. The debug signal terminal of the debug bus controller 10 is connected to the signal interface of the mainboard.

[0047] In the embodiment of the present application, the extended function chip 30, debug interface 31, and signal interface are provided on a board, and are connected to the signal interface on the mainboard 100 via the signal interface on the board. Accordingly, to enable the debug bus controller 10 to obtain the signals transmitted by the debug interface bus of each extended function chip 30, a debug interface bus for the extended function chip 30 is provided on the board and connected to the signal interface of the extended function chip 30. After the signal interface on the mainboard 100 obtains the debug signal of the extended function chip 30, it transmits it to the debug bus controller 10. The debug bus controller 10 converts the debug signal of the extended function chip into a network protocol signal, which is then output through the network interface 20, thereby achieving remote debugging.

[0048] The embodiments of the present application are applicable to the case where the extended function chip is connected through the board signal interface, that is, the external board type. This method can select extended function chips of different specifications according to actual needs (such as supporting different numbers of channels, rate levels or protocol versions) without modifying the mainboard design. It is also possible to select a board connected to the signal interface of the mainboard according to debugging requirements. When the needs change, it is only necessary to replace or add a new board without replacing the mainboard, which can reduce the upgrade cost. The board can be adapted to different mainboards as an independent module, which is suitable for general-purpose equipment and improves the hardware reuse rate.

[0049] On this basis, if Figure 4 As shown, a network switch chip 40 can be added to the mainboard 100. The debug signals of the extended function chips 30 within the system are converted into network protocol signals by the debug bus controller 10 and connected to the network switch chip 40. The network protocol signals of the baseboard management controller 50 are also connected to the network switch chip 40. The baseboard management controller 50 and the debug bus controller 10 can be accessed simultaneously through the network interface 20. The embodiment of the present application can realize the remote debugging function of key components within the system while retaining the original network interface and functions on the mainboard, which facilitates operation and maintenance, has simple software and hardware design, and is low in implementation cost.

[0050] In some optional implementations, the debug interface conversion device provided in the embodiments of the present application may further include a mainboard. The extended function chip, the debug bus controller, and the network interface are disposed on the mainboard. The debug interface bus of the extended function chip is connected to the debug signal terminal of the debug bus controller.

[0051] Figure 5 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 5 As shown, the debugging interface conversion device provided in the embodiment of the present application may further include a mainboard 100 .

[0052] See also Figure 5The extended function chip 30, the debug bus controller 10, and the network interface 20 are disposed on the mainboard 100. The debug interface bus of the extended function chip 30 is connected to the debug signal terminal of the debug bus controller 10.

[0053] In the embodiment of the present application, the extended function chip 30, the debug bus controller 10, and the network interface 20 are all provided on the mainboard 100, and the extended function chip 30 no longer needs to be connected to the mainboard through the signal interface on the board. In the embodiment of the present application, since the extended function chip 30 is integrated on the mainboard 100, the debug interface bus of the extended function chip 30 is connected to the debug signal terminal of the debug bus controller 10 on the mainboard, thereby enabling the debug bus controller 10 to obtain the signal transmitted by the debug interface bus of each extended function chip 30. After the debug bus controller 10 obtains the signal transmitted by the debug interface bus of each extended function chip 30, it converts the debug signal of the extended function chip into a network protocol signal, and then outputs it through the network interface 20, thereby achieving remote debugging.

[0054] The embodiment of the present application provides another layout of the debug interface conversion device, compared to Figure 4 The layout shown in the figure can shorten the signal transmission path, eliminating the connector (such as a PCIe slot) and cable between the card and the motherboard. This shortens the high-speed signal transmission path, reduces impedance mismatch, electromagnetic interference (EMI), and signal attenuation, and is particularly effective for high-frequency protocols. Because there is no need to reserve a slot or installation space for the card, the debug interface conversion device provided by the embodiment of the application is suitable for compact equipment.

[0055] In some optional implementations, the debug interface conversion device provided in the embodiments of the present application may further include a storage module. The storage module is connected to the debug bus controller and is used to store historical data acquired by the debug bus controller.

[0056] Figure 6 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 6 As shown, the debugging interface conversion device provided in the embodiment of the present application may further include a storage module 90 .

[0057] See also Figure 6 The storage module 90 is connected to the debug bus controller 10 and is used to store historical data acquired by the debug bus controller.

[0058] The historical data obtained by debugging the bus controller may include, for example, device status, error logs, and performance indicators. By collecting this data, the operation of the core components of the system can be fully monitored to ensure the stability of the entire system.

[0059] In an embodiment of the present application, a storage module 90 is provided on the mainboard, and the storage module 90 is connected to the debug bus controller 10 to store the historical data obtained by the debug bus controller. The historical data stored in the storage module 90 records the complete state of the device before and after the failure (such as register values, error counts, protocol interaction logs), which can avoid the loss of key information due to system restart or state reset. For example, when the PCIe link is suddenly disconnected, the UART log can accurately capture the signal quality parameters before the disconnection and directly locate whether it is a poor hardware contact or electromagnetic interference problem. For occasional failures, historical data can be associated with multiple component logs through timestamps to quickly lock the trigger conditions. The anomaly of a single component may be indirectly caused by upstream or downstream devices. Historical data provides a full-link timing log, which can be cross-compared through timelines to accurately locate the source of the fault and avoid blind troubleshooting.

[0060] The storage module in the embodiment of the present application can be, for example, a Flash chip. Flash chips are non-volatile storage devices, so data will not be lost even if the system is powered off, ensuring that fault data will not be lost. Moreover, Flash generally has high durability and reliability, making it suitable for long-term storage of historical data.

[0061] Non-volatile storage such as Flash ensures that historical data can be recovered even after system power outages and hardware failures. Compared to temporary logs that rely on DRAM, this avoids log loss due to logs not being written to disk in time when a failure occurs. For edge nodes with unstable networks (such as base stations in remote areas and industrial field equipment), local Flash storage can temporarily store data. Once the network is restored, the data can be transferred in batches through the network interface, ensuring data loss and reducing bandwidth pressure for real-time transmission.

[0062] In some optional implementations, the debug interface conversion device provided in the embodiments of the present application may further include a baseboard management controller connected to the debug bus controller, and configured to trigger the debug bus controller to collect data in response to fault information.

[0063] Figure 7 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 7 As shown, the debugging interface conversion device provided in the embodiment of the present application may further include a baseboard management controller 50 .

[0064] See also Figure 7 The baseboard management controller 50 is connected to the debug bus controller 10 , and the baseboard management controller 50 is used to trigger the debug bus controller 10 to collect data in response to fault information.

[0065] In the embodiment of the present application, the baseboard management controller 50 can trigger the debug bus controller 10 to automatically collect data based on the fault information when a fault is detected, and can collect valid data in a timely manner to facilitate rapid location of the fault problem.

[0066] Because hardware or system failures (such as firmware anomalies and hardware compatibility issues) can be sporadic or transient, manual data collection can result in the loss of critical information due to response delays. The automatic triggering mechanism of the present embodiment can capture serial port logs (such as startup errors, hardware initialization anomalies, driver loading failures, etc.) as soon as a failure occurs, preserving the original state of the failure scene.

[0067] This embodiment of the application eliminates the need for manual device login or command execution, which, particularly in large-scale data center environments, can avoid the inefficient operation of troubleshooting each device one by one and shorten fault location time. It allows operations and maintenance personnel to complete preliminary diagnosis without physically touching the device, making it particularly suitable for remote data centers or embedded device scenarios.

[0068] In some optional implementations, the debug bus controller in the debug interface conversion device provided in the embodiments of the present application may also be configured to collect data based on a preset period.

[0069] In the embodiment of the present application, the debug bus controller can be configured to collect data based on a preset period. The preset period can be set based on actual needs. By collecting UART data (such as sensor readings, device operating parameters, communication instruction receipts) at a fixed frequency (such as every second, every minute), the device operating status can be tracked in real time to avoid being missed due to occasional or periodic failures (such as intermittent communication interruptions, parameter drift). Periodic collection ensures that data is recorded continuously in chronological order to form a complete operation log (such as parameter changes during device startup, signal quality fluctuations of the communication link), which is convenient for identifying periodic failures through timing analysis. Different periods are set according to device performance and data importance (such as high frequency collection of key sensor data, low frequency collection of secondary status information), while ensuring data validity, reducing CPU, memory and storage resource consumption, especially suitable for embedded devices with limited computing power (such as Internet of Things terminals, industrial controllers). Collecting data at a preset period balances real-time monitoring needs and resource consumption. It is suitable for scenarios that require long-term status tracking and can also provide complete timing evidence for intermittent fault diagnosis.

[0070] In some optional implementations, the operation and maintenance personnel may also trigger the debug bus controller to collect data by sending instructions through a network interface.

[0071] In some optional embodiments, the debug bus controller may include at least one sub-debug bus controller. The debug signal terminals of different sub-debug bus controllers are connected to debug interface buses with different communication protocols. The network protocol signal output terminals of each sub-debug bus controller are connected to a network interface.

[0072] Figure 8 A schematic diagram of another debug interface conversion device provided in an embodiment of the present application is shown as follows: Figure 8 As shown, the debug bus controller 10 in the debug interface conversion device provided in the embodiment of the present application includes at least one sub-debug bus controller. Figure 8 The exemplary debug bus controller 10 includes two sub-debug bus controllers, namely sub-debug bus controller 11 and sub-debug bus controller 12. The debug signal terminals of the different sub-debug bus controllers are connected to debug interface buses with different communication protocols. The network protocol signal output terminals of each sub-debug bus controller are connected to a network interface.

[0073] The embodiment of the present application sets corresponding sub-debugging bus controllers for debug interface buses of different communication protocols, which can realize modular design. When debugging debug interfaces of different communication protocols, the corresponding sub-debugging bus controllers can be directly connected, so the flexibility is high.

[0074] It should be noted that the embodiments of the present application do not limit the type of extended function chip, for example, it can be a PCIeSwitch chip, a Raid chip, an Expander chip, etc. Corresponding to the extended function chip integrated on the board, a board can also have multiple extended function chips at the same time. For example, two or more PCIeSwitch chips are set on a PCIe Switch board. The debug interface bus of the extended function chip can be, for example, a UART bus. In some optional implementations, the corresponding debug interface is selected according to the type of the extended function chip, such as I2C (Inter-Integrated Circuit) bus, SPI (Serial Peripheral Interface) bus, JTAG (Joint Test Action Group) bus, SWD (Serial Wire Debug).

[0075] The present application also provides a server, comprising the debugging interface conversion device in any of the above embodiments.

[0076] For an introduction to the server provided by this application, please refer to the embodiment of the debug interface conversion device described above. In the server provided by the embodiment of this application, since the debug interface conversion device is provided with a debug bus controller and a network interface, the debug signal end of the debug bus controller is connected to the debug interface bus of at least one extended function chip, which is used to convert the debug signal of the extended function chip into a network protocol signal. Since the network interface is connected to the network protocol signal output end of the debug bus controller, the network interface can output the network protocol signal converted by the debug bus controller, and the staff can access the debug interface bus of the extended function chip through the network interface to realize the remote debugging function of the extended function chip. There is no need to power off the entire server and open the chassis cover to connect the tool to the debug interface on the board as in the prior art, so it is convenient for operation and maintenance.

[0077] Professionals may further appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0078] The above is a detailed introduction to the production management method provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A debugging interface conversion device, characterized in that: include: a debug bus controller, wherein a debug signal terminal of the debug bus controller is connected to a debug interface bus of at least one extended function chip, and is configured to receive a debug signal sent by the extended function chip via the debug interface bus through the debug signal terminal, and convert the debug signal into a network protocol signal; A network interface is connected to the network protocol signal output terminal of the debug bus controller and is used to send the network protocol signal output by the debug bus controller through the network protocol signal output terminal to a remote device.

2. The debugging interface conversion device according to claim 1, wherein: Also includes: Network switch chips and baseboard management controllers; The network protocol signal output end of the baseboard management controller and the network protocol signal output end of the debug bus controller are both connected to the same network interface through the network switching chip.

3. The debugging interface conversion device according to claim 2, wherein: It also includes a processor, a baseboard management controller, a serial port selection switching module and an output serial port; The processor is connected to the baseboard management controller via a data bus, and the processor interacts with the baseboard management controller via the data bus to perform control instructions and data signals; The baseboard management controller is connected to the serial port strobe switching module via the system serial port bus and the baseboard management controller serial port bus respectively; the baseboard management controller interacts with the serial port strobe switching module via the system serial port bus to perform system serial port information exchange; The baseboard management controller interacts with the selection switching module via the baseboard management controller serial port bus to perform serial port signal exchanges of the baseboard management controller; the serial port selection switching module is used to select the data on the system serial port bus or the baseboard management controller serial port bus to be output through the output serial port.

4. The debugging interface conversion device according to claim 1, wherein: It also includes a mainboard; the debug bus controller and the network interface are arranged on the mainboard; the extended function chip is connected to the signal interface of the mainboard via a signal interface; The debug interface bus of the extended function chip is connected to the signal interface of the extended function chip; The debugging signal terminal of the debugging bus controller is connected to the signal interface of the mainboard.

5. The debugging interface conversion device according to claim 1, wherein: It also includes a mainboard; the extended function chip, the debug bus controller and the network interface are arranged on the mainboard; the debug interface bus of the extended function chip is connected to the debug signal terminal of the debug bus controller.

6. The debugging interface conversion device according to claim 1, wherein: It also includes a storage module, which is connected to the debug bus controller and is used to store historical data acquired by the debug bus controller.

7. The debugging interface conversion device according to claim 1, wherein: The system further comprises a baseboard management controller connected to the debug bus controller. The baseboard management controller is configured to trigger the debug bus controller to collect data in response to fault information.

8. The debugging interface conversion device according to claim 1, wherein: The debug bus controller is configured to collect data based on a preset period.

9. The debugging interface conversion device according to claim 1, wherein: The debug bus controller includes at least one sub-debug bus controller; debug signal terminals of different sub-debug bus controllers are connected to debug interface buses with different communication protocols; and the network protocol signal output terminals of each sub-debug bus controller are connected to the network interface.

10. A server, characterized in that: The debug interface conversion device comprises the debug interface conversion device according to any one of claims 1 to 9.

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