PLC based on MLVDS communication, PLC control system and communication method

Abstract

The invention relates to the field of PLCs, in particular to a PLC based on MLVDS communication, a PLC control system and a communication method, and a PLC internal module comprises a PLC controller and a plurality of control modules; the PLC comprises a central processing unit, a first FPGA and first MLVDS transceivers, one end of the first FPGA is connected with the central processing unit through a high-speed bus, and the other end of the first FPGA is connected with the first MLVDS transceivers; the control module comprises a local processor, a second FPGA and a plurality of second MLVDS transceivers, one end of the second FPGA is connected with the local processor through an SPI, and the other end of the second FPGA is connected with the plurality of second MLVDS transceivers; a plurality of MLVDS channels are connected in parallel between the PLC and the control module, one end of each MLVDS channel is connected with the first MLVDS transceiver, and the other end of each MLVDS channel is connected with the second MLVDS transceiver; the first MLVDS transceiver and the second MLVDS transceiver are both used for mutual conversion of multi-point low-voltage differential signals and single-point TTL level signals. According to the invention, multi-channel MLVDS parallel connection is adopted, so that localization of communication between modules in the PLC can be realized, communication delay between the modules is reduced, and communication bandwidth is improved.

Description

Technical Field

[0001] The present invention relates to the field of PLC technology, and in particular to a PLC based on MLVDS communication, a PLC control system and a communication method. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Traditional PLC (Programmable Logic Controller) internal inter-module communication mainly relies on EtherCAT communication. However, this technology has the following problems: (1) Unable to achieve localization: EtherCAT technology relies on foreign technical support, which limits the independent development of domestic PLC technology.

[0004] (2) High communication delay: Traditional communication methods have a certain delay in data transmission between modules, which affects the system response speed.

[0005] (3) Insufficient bandwidth: In high-volume data transmission scenarios, the communication bandwidth of existing technologies is difficult to meet the demand.

[0006] In view of the above-mentioned defects, the present invention has made improvements. Summary of the Invention

[0007] In order to overcome the shortcomings of the background technology, the present invention provides a PLC, a PLC control system and a communication method based on MLVDS communication. By utilizing the high-bandwidth characteristics of MLVDS and adopting a multi-channel MLVDS parallel mode, the localization of communication between modules within the PLC can be achieved, the communication delay between modules is reduced, and the communication bandwidth is increased to meet the needs of high data volume transmission.

[0008] To achieve the above object, the present invention provides the following technical solutions: In a first aspect, a PLC based on MLVDS communication is provided, wherein the internal modules of the PLC include a PLC controller and several control modules; The PLC controller includes a central processing unit, a first FPGA and a first MLVDS transceiver, wherein one end of the first FPGA is connected to the central processing unit via a high-speed bus, and the other end is connected to a plurality of the first MLVDS transceivers; The control module includes a local processor, a second FPGA and a second MLVDS transceiver, wherein one end of the second FPGA is connected to the local processor via SPI, and the other end is connected to a plurality of the second MLVDS transceivers; A plurality of MLVDS channels are connected in parallel between the PLC controller and the control module, one end of the MLVDS channel is connected to the first MLVDS transceiver, and the other end is connected to the second MLVDS transceiver; The first MLVDS transceiver and the second MLVDS transceiver are both used for mutual conversion between multi-point low voltage differential signals and single-point TTL level signals.

[0009] Further, The plurality of MLVDS channels connected in parallel between the PLC controller and the control module include an MLVDS data transmission channel and an MLVDS control channel for sending control instructions; There are two MLVDS control channels, and the remaining MLVDS channels are all MLVDS data transmission channels. The MLVDS data transmission channels are bidirectional channels, and the MLVDS control channels are unidirectional channels.

[0010] Further, The PLC controller is provided with two first MLVDS transceivers for sending control instructions, and each control module is respectively provided with two second MLVDS transceivers for receiving control instructions. The two first MLVDS transceivers of the PLC controller are respectively connected to the two second MLVDS transceivers of each control module, forming two MLVDS control channels from the PLC controller to the control modules.

[0011] Further, One end of the first FPGA is connected to the high-speed bus via a high-speed parallel interface, and the high-speed bus adopts a high-speed parallel data bus. The other end of the first FPGA is connected to a plurality of the first MLVDS transceivers via a high-speed parallel interface. The first FPGA is used to realize the mutual conversion of data in the parallel communication interface of the central processing unit and data between the multi-channel MLVDS parallel processing interface; One end of the second FPGA is connected to the local processor via an SPI interface, and the other end of the second FPGA is connected to several second MLVDS transceivers via a high-speed parallel interface. The second FPGA is used to realize the mutual conversion of data on the local processor serial interface and data between the multi-channel MLVDS parallel processing interface.

[0012] In a second aspect, a PLC control system is also provided, which includes a host computer and the PLC based on MLVDS communication as described above, and the host computer and the PLC controller are communicatively connected.

[0013] In a third aspect, a communication method is provided, which is applied to the PLC control system as described above, and the method includes: After power-on initialization, the PLC controller discovers all local control modules by traversing the device and caches the traversal information configured for the control modules; After establishing communication with the PLC controller, the host computer sends the initial information of the control module configuration to the PLC controller; The PLC controller performs configuration verification by comparing the traversal information of the control module configuration with the initial information of the control module configuration; If the configuration verification passes, the PLC controller waits for the next instruction; After receiving the configuration instructions from the host computer, the PLC controller configures the control module according to the configuration instructions; If the control module is configured successfully, the PLC controller communicates with the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; If the data verification passes, the data communication is successful, otherwise the data communication is repeated.

[0014] Furthermore, the method further comprises: If the configuration verification fails, the host computer will be returned to update the initial information of the control module configuration; If configuration of the control module fails, the PLC controller will re-traverse the device to confirm whether the control module to be configured is normal; If the control module to be configured is confirmed to be normal, it returns to the PLC controller and waits for the next instruction; If it is confirmed that the control module to be configured is abnormal, it returns to the host computer to update the initial information of the control module configuration.

[0015] Further, After the control module is successfully configured, the PLC controller transmits data to the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; If the data verification passes, the data transmission is successful, and the PLC controller sends an update data instruction to the control module; After receiving the data update instruction from the PLC controller, the control module uses the received new data to overwrite the local original data; If the data verification fails, the PLC controller retransmits the data to the control module.

[0016] Further, The data communication between the PLC controller and the control module adopts a custom communication protocol frame; The frame structure of the custom communication protocol frame includes several bytes, among which Byte0 and Byte1 are the frame header, Byte2 is the device address, Byte3 is the device type, Byte4 is the frame type, Byte5 and Byte6 are the frame length, Byte7 and Byte8 are the operation data address, Byte N0~Nx are data packets, Byte9 and Byte10 are CRC check codes, Byte11 is the MLVDS channel number, and Byte12 and Byte13 are the frame tail.

[0017] Further, The data packet includes a device identification code for uniquely identifying the device.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. High bandwidth: Multi-channel MLVDS in parallel greatly improves communication bandwidth to meet high data volume requirements; 2. High reliability: Customized communication protocols and error correction mechanisms ensure the accuracy and integrity of data transmission; 3. Localization: Break through the limitations of EtherCAT technology and achieve autonomy in PLC internal communication; 4. Low latency: Optimize the communication mechanism, significantly reduce the delay between modules, and improve the system response speed; 5. Efficiency: The introduction of device identification code avoids communication conflicts and improves point-to-point communication efficiency.

[0019] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings.

[0020] The present invention will be further described below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a schematic diagram of the architecture of a PLC based on MLVDS communication according to an embodiment of the present invention; Figure 2 This is a schematic structural diagram of a PLC control system according to an embodiment of the present invention; Figure 3A flow chart of a communication method according to an embodiment of the present invention; Figure 4 A schematic diagram of the overall flow of a communication method according to an embodiment of the present invention; Figure 5 The figure is a schematic diagram of the frame structure of a customized communication protocol frame according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] like Figure 1 As shown, the first embodiment of the present invention provides a PLC based on MLVDS communication, wherein the internal modules of the PLC include a PLC controller and several control modules; the PLC controller includes a central processing unit, a first FPGA and a first MLVDS transceiver, wherein one end of the first FPGA is connected to the central processing unit via a high-speed bus, and the other end is connected to several of the first MLVDS transceivers; the control module includes a local processor, a second FPGA and a second MLVDS transceiver, wherein one end of the second FPGA is connected to the local processor via SPI, and the other end is connected to several of the second MLVDS transceivers; Several MLVDS channels are connected in parallel between the PLC controller and the control module, one end of the MLVDS channel is connected to the first MLVDS transceiver, and the other end is connected to the second MLVDS transceiver; the first MLVDS transceiver and the second MLVDS transceiver are both used for mutual conversion between multi-point low voltage differential signals and single-point TTL level signals.

[0025] The above technical solution gives the internal structure of the PLC controller and control module, both of which use FPGA and MLVDS transceivers, and gives the communication connection method between the PLC controller and other control modules, which adopts a multi-channel MLVDS parallel structure. The above solution fully utilizes the high-bandwidth characteristics of MLVDS and adopts a multi-channel MLVDS parallel method. It can realize the localization of communication between PLC internal modules, get rid of dependence on foreign technology, reduce communication delays between modules, improve the real-time performance and response speed of the PLC system, increase communication bandwidth, and meet the needs of high data volume transmission.

[0026] MLVDS (Multipoint Low-Voltage Differential Signaling) features high bandwidth and strong anti-interference capabilities. This embodiment of the present invention establishes an efficient and stable communication infrastructure by adapting MLVDS signals to the communication interfaces of PLC internal modules. This is achieved through an MLVDS transceiver, which converts multi-point low-voltage differential signals to internal, standard single-point TTL-level signals and vice versa. The communication interface formed by the MLVDS transceiver in this embodiment is a multi-channel, high-speed serial MLVDS interface. This communication interface significantly reduces communication response time and meets the requirements of high-data-volume, low-latency PLC controller applications. The MLVDS communication transmission method employed in this embodiment effectively resists interference in complex electromagnetic environments, ensuring stable and accurate data transmission and providing technical support for high-speed communication. The local processor configured in the control module of this embodiment refers to a module that loads configuration information according to the default state upon power-up, placing the module in a default operating state.

[0027] This embodiment significantly increases the communication bandwidth between the PLC controller and other control modules by connecting multiple MLVDS channels in parallel. Each channel transmits data independently, and the parallel operation of multiple channels is like multiple data highways running in parallel, effectively increasing communication capabilities. This embodiment of the present invention overcomes the bandwidth limitations of a single channel by connecting multiple MLVDS channels in parallel, meeting the needs for fast transmission of high data volumes in complex industrial scenarios.

[0028] Taking the control module sending data to the PLC controller as an example, the signal data on the MLVDS bus is converted into a single-point TTL level signal after passing through the MLVDS transceiver and input into the FPGA. The FPGA integrates the data of multiple MLVDS channels into internal high-speed serial data according to its own protocol and transmits it to the central processing unit.

[0029] In specific implementation, the above-mentioned control modules include but are not limited to digital input / output, analog input / output, thermal resistor / thermocouple acquisition, frequency generation / measurement and other modules.

[0030] It should be noted that Figure 1 Although the technical solution adopted by the present invention is described by taking a modular PLC as an example, the technical solution of the present invention can actually also be applied to a fixed PLC.

[0031] As a preferred technical solution, the several MLVDS channels connected in parallel between the PLC controller and the control module include an MLVDS data transmission channel and an MLVDS control channel for sending control instructions; wherein, two MLVDS control channels are set, and the remaining MLVDS channels are all MLVDS data transmission channels, the MLVDS data transmission channel is a bidirectional channel, and the MLVDS control channel is a unidirectional channel.

[0032] In this embodiment, two MLVDS control channels are set separately, which can not affect the transmission of control instructions when large amounts of data are transmitted. If the MLVDS control channel is not set separately, the control instructions cannot be transmitted when transmitting data. In this embodiment, the two MLVDS control channels are set as redundant settings, which can better ensure the correctness of the control instruction transmission. The MLVDS data transmission channel is a bidirectional channel, that is, data can be transmitted bidirectionally between the PLC controller and the control module. The MLVDS control channel is a unidirectional channel, that is, the control instruction is sent from the PLC controller to the control module.

[0033] Figure 1 Two control modules are set up in the system. Four MLVDS data transmission channels and two MLVDS control channels are set up between the PLC controller and the control modules. In this embodiment, four MLVDS data transmission channels are used as a group for data transmission, and are divided into odd and even slots. Since FPGA uses a parallel processing mode, the parity slots can be divided into even and odd slots so that data can be transmitted on odd slots while also being transmitted on even slots, thereby improving transmission efficiency. In specific implementation, the data is evenly divided onto the four MLVDS data transmission channels after unpacking, similar to the packet length / 4, and the remainder is placed on the MLVDS data transmission channel of the same number. The transmission effect of this embodiment is based on the CRC check code in the data packet; the four MLVDS data transmission channels set here are only the actual number used in this embodiment. In specific implementation, the number of MLVDS data transmission channels can be expanded or reduced according to actual needs.

[0034] As a preferred technical solution, the PLC controller is provided with two first MLVDS transceivers for sending control instructions, and each control module is respectively provided with two second MLVDS transceivers for receiving control instructions. The two first MLVDS transceivers of the PLC controller are respectively connected to the two second MLVDS transceivers of each control module, forming two MLVDS control channels from the PLC controller to the control modules.

[0035] In this embodiment, the PLC controller is provided with two first MLVDS transceivers specifically for sending control instructions, and each control module is provided with two second MLVDS transceivers specifically for receiving control instructions, wherein the above-mentioned two second MLVDS transceivers of the control module are respectively connected to the above-mentioned two first MLVDS transceivers of the PLC controller, forming two MLVDS control channels from the PLC controller to the control module.

[0036] As a preferred technical solution, one end of the first FPGA is connected to the high-speed bus through a high-speed parallel interface, and the high-speed bus adopts a high-speed parallel data bus. The other end of the first FPGA is connected to several of the first MLVDS transceivers through a high-speed parallel interface. The first FPGA is used to realize the mutual conversion of data in the parallel communication interface of the central processing unit and data between the multi-channel MLVDS parallel processing interface; one end of the second FPGA is connected to the local processor through an SPI interface, and the other end of the second FPGA is connected to several of the second MLVDS transceivers through a high-speed parallel interface. The second FPGA is used to realize the mutual conversion of data on the local processor serial interface and data between the multi-channel MLVDS parallel processing interface.

[0037] In this embodiment, the first FPGA and the second FPGA are both parallel processing functional devices, wherein the first FPGA is used to realize the mutual conversion of data in the parallel communication interface of the central processing unit and the data between the multi-channel MLVDS parallel processing interface, and the second FPGA is used to realize the mutual conversion of data on the serial interface of the local processor and the data between the multi-channel MLVDS parallel processing interface.

[0038] In specific implementation, the high-speed bus adopts a high-speed parallel data bus with a data width of 16 bits and a maximum support of 100 MHz.

[0039] like Figure 2 As shown, the second embodiment of the present invention further provides a PLC control system, which includes a host computer and the PLC based on MLVDS communication as described above, and the host computer and the PLC controller are communicatively connected.

[0040] In this embodiment, the host computer and the PLC controller communicate via Ethernet, and the PLC controller and each control module communicate data using the aforementioned multiple parallel MLVDS channels.

[0041] The PLC based on MLVDS communication in the above embodiment has been described in detail in the aforementioned PLC embodiment and will not be elaborated on here.

[0042] like Figure 3As shown, the third embodiment of the present invention further provides a communication method, which is applied to the PLC control system as described above, and the method includes: After power-on initialization, the PLC controller discovers all local control modules by traversing the device and caches the traversal information configured for the control modules; After establishing communication with the PLC controller, the host computer sends the initial information of the control module configuration to the PLC controller; The PLC controller performs configuration verification by comparing the traversal information of the control module configuration with the initial information of the control module configuration; If the configuration verification passes, the PLC controller waits for the next instruction; After receiving the configuration instructions from the host computer, the PLC controller configures the control module according to the configuration instructions; If the control module is configured successfully, the PLC controller communicates with the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; If the data verification passes, the data communication is successful, otherwise the data communication is repeated.

[0043] The above technical solution mainly includes establishing communication between the host computer and the PLC controller and establishing communication between the PLC controller and the control module. Configuration verification is used to check whether the control module configuration in the host computer corresponds to the physical module (that is, all the control modules that actually exist locally discovered by traversing the device). Data verification is used to check whether the data transmitted by data communication is accurate and complete. This method can better realize the internal communication of the PLC control system.

[0044] The following will be combined Figure 4 The above method is further described, wherein: Figure 4 The middle part corresponds to the execution of the PLC controller, Figure 4 The left part corresponds to the execution of the host computer. Figure 4 The right part corresponds to the execution of the control module.

[0045] The communication methods specifically include: After power-on initialization, the PLC controller discovers all the control modules that exist locally by traversing the device and caches the traversal information configured for the control modules; this step corresponds to Figure 4 The middle part is power-on-initialization-traversal device-slave device mapping cache, where the cache is the traversal information configured by the control module, namely the slave device mapping cache. The control module in this embodiment is also written as a slave device, the same below.

[0046] After the host computer establishes communication with the PLC controller, it sends the initial information of the control module configuration to the PLC controller; this step corresponds to Figure 4The host computer on the left is connected to the CPU (that is, connected to the PLC controller) and configures the mapping cache.

[0047] The PLC controller performs configuration verification by comparing the traversal information of the control module configuration with the initial information of the control module configuration; this step corresponds to Figure 4 Configuration verification in .

[0048] If the configuration verification fails, the host computer will be returned to update the initial information of the control module configuration; this step corresponds to Figure 4 Configure the failure action above the verification.

[0049] If the configuration check passes, the PLC controller waits for the next instruction; in this step, the PLC controller waits for the next instruction and enters the idle mode. This embodiment also adds a pre-operation after the PLC enters the idle mode. The pre-operation can be used to pre-process the data, such as taking some local data from the local memory to facilitate the next step of sending it to the slave device.

[0050] After receiving the configuration instructions from the host computer, the PLC controller configures the control module according to the configuration instructions; this step corresponds to Figure 4 The configuration slave device in the configuration (its purpose is to update the configuration of the slave device), that is, to configure the control module.

[0051] If the configuration of the control module fails, the PLC controller will re-traverse the device to confirm whether the control module to be configured is normal; this step corresponds to Figure 4 Configure the failed operation on the right side of the slave device.

[0052] If the control module to be configured is confirmed to be normal, it returns to the PLC controller to wait for the next instruction (i.e. enters idle mode); If the control module to be configured is confirmed to be abnormal, the host computer will be returned to update the initial information of the control module configuration; this step also corresponds to Figure 4 Configure the failure action above the verification.

[0053] If the control module is configured successfully (which can be understood as the successful establishment of communication between the PLC controller and the slave device), the PLC controller communicates with the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; this step corresponds to Figure 4 The transmission data and data verification in .

[0054] If the data verification passes, data communication is successful; otherwise, data communication is re-established. In this embodiment, data verification is performed during data transmission. If any data outside the data packet in the frame format is found to be non-compliant with the format, an error code is returned to the device sending the data, and the device sending the data re-sends the data. In this step, if the data verification fails, data communication must be re-established. This re-establishment of data communication in this embodiment includes re-establishing data communication between the host computer and the PLC controller, as well as re-establishing data communication between the PLC controller and the control module, because the data from the PLC controller essentially originates from the host computer.

[0055] The above method covers the operating steps of the sending and receiving ends, and introduces error detection (mainly including configuration verification, configuration verification of slave devices, and data verification) and correction mechanisms (mainly including the processing of various verification errors). Through the above method, the internal communication of the PLC control system can be well realized, that is, the communication between the host computer and the PLC controller and the communication between the internal modules of the PLC (that is, the communication between the PLC controller and the control module).

[0056] exist Figure 4 When the PLC controller traverses the devices, it sends instructions to the control module to check whether the slave device exists in a certain slot. The control module returns the configuration to the PLC controller, which returns the slot and type of the slave device. During the execution of the control module, updating the local configuration cache means updating the hardware configuration information such as its own address (slot). The data cache can be understood as readable and writable.

[0057] Generally speaking, control modules are mainly divided into input-type control modules and output-type control modules. Among them, the input-type control module is used to receive external data and transmit the data to the PLC controller, and the output-type control module is used to receive data from the PLC controller and output it to the outside.

[0058] As an optimal technical solution, after the control module is successfully configured, the PLC controller transmits data to the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; if the data verification passes, the data transmission is successful, and the PLC controller sends an update data instruction to the control module; after receiving the update data instruction from the PLC controller, the control module uses the received new data to overwrite the local original data; if the data verification fails, the PLC controller retransmits the data to the control module.

[0059] In this embodiment, when the PLC controller transmits data to the control module, it also sends an update data instruction to ensure that the local data of the control module will not be overwritten by error. The update data instruction will only be sent to the control module when the data verification passes, thereby ensuring that the local data of the control module will not be lost, making data transmission more efficient.

[0060] As a preferred technical solution, the data communication between the PLC controller and the control module adopts a custom communication protocol frame; the frame structure of the custom communication protocol frame includes several bytes, among which Byte0 and Byte1 are the frame header, Byte2 is the device address, Byte3 is the device type, Byte4 is the frame type, Byte5 and Byte6 are the frame length, Byte7 and Byte8 are the operation data address, Byte N0~Nx are data packets, Byte9 and Byte10 are CRC check codes, Byte11 is the MLVDS channel number, and Byte12 and Byte13 are the frame tail.

[0061] To ensure data transmission reliability under high bandwidth, the embodiment of the present invention designs a set of custom protocols (i.e., adopts the above-mentioned custom communication protocol frame), and the data encoding rules of the custom communication protocol frame (see the table below for details) Figure 5 ) Use a specific encoding method to make data easy to identify and analyze. Specifically, this encoding method can easily identify the type, location, quantity, etc. of each control module to facilitate the analysis of the data content in the data packet (data frame structure); Customize the frame structure design of the communication protocol frame (see the table below and Figure 5 ) includes a frame header, data segment (i.e., data packet), checksum, frame tail, etc., which ensures the orderliness of data transmission; the above-mentioned custom communication protocol frame forms an effective error correction mechanism by integrating technologies such as checksum and cyclic redundancy check (CRC), which can facilitate timely detection and correction of transmission errors and ensure the accuracy and integrity of data.

[0062] The definition and meaning of each byte in the frame structure of the custom communication protocol frame of this embodiment are shown in the following table:

[0063] As a preferred technical solution, the data packet includes a device identification code for uniquely identifying the device.

[0064] Traditional PLCs (Programmable Logic Controllers) rely primarily on EtherCAT for inter-module communication, but this technology also suffers from signal conflicts: the lack of an effective device differentiation mechanism in bus communication can easily lead to communication conflicts and data loss. This embodiment introduces a device identification code into the bus communication protocol, assigning a unique identifier to each device (including the PLC controller and individual control modules). This effectively avoids communication conflicts, thereby resolving the bus signal communication conflict issue and improving the efficiency of point-to-point communication. Specifically, the sending end appends the device identification code to the data packet of the custom communication protocol frame. The receiving end uses the device identification code to determine the data source, improving the efficiency and reliability of point-to-point communication.

[0065] Here is a simple example to illustrate the above process. After power-on, the PLC controller sends a broadcast message 0xFFFFFFFF01XXXXXX01DDDD to all MLVDS buses to inquire whether there is a control module in slot 1. If there is a control module in the slot, the control module replies 0xFFFF010000XXXXXX01DDDD on the corresponding MLVDS channel (there is a type 00 control module in slot 1 on MLVDS channel 01).

[0066] In this embodiment, each type of control module has an independent identification code associated with type, slot, operation, etc., so that the module has a unique identification code in a system controlled by a PLC controller.

[0067] In summary, the present invention abandons the traditional EtherCAT communication method and adopts MLVDS technology combined with multi-channel parallel and custom protocol, which not only realizes the localization of communication, but also significantly improves the bandwidth and response speed, and solves many shortcomings of the existing technology.

[0068] It should be noted that for the aforementioned method embodiments, for ease of description, they are all expressed as a series of action combinations. However, those skilled in the art should be aware that the present invention is not limited by the order of the actions described, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0069] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0070] Parts not involved in the above embodiments are the same as the existing technology or can be implemented by using the existing technology, and will not be further explained here.

[0071] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A PLC based on MLVDS communication, characterized in that: The internal modules of the PLC include a PLC controller and several control modules; The PLC controller includes a central processing unit, a first FPGA and a first MLVDS transceiver, wherein one end of the first FPGA is connected to the central processing unit via a high-speed bus, and the other end is connected to a plurality of the first MLVDS transceivers; The control module includes a local processor, a second FPGA and a second MLVDS transceiver, wherein one end of the second FPGA is connected to the local processor via SPI, and the other end is connected to a plurality of the second MLVDS transceivers; A plurality of MLVDS channels are connected in parallel between the PLC controller and the control module, one end of the MLVDS channel is connected to the first MLVDS transceiver, and the other end is connected to the second MLVDS transceiver; The first MLVDS transceiver and the second MLVDS transceiver are both used for mutual conversion between multi-point low voltage differential signals and single-point TTL level signals.

2. A PLC based on MLVDS communication according to claim 1, characterized in that: The plurality of MLVDS channels connected in parallel between the PLC controller and the control module include an MLVDS data transmission channel and an MLVDS control channel for sending control instructions; There are two MLVDS control channels, and the remaining MLVDS channels are all MLVDS data transmission channels. The MLVDS data transmission channels are bidirectional channels, and the MLVDS control channels are unidirectional channels.

3. A PLC based on MLVDS communication according to claim 2, characterized in that: The PLC controller is provided with two first MLVDS transceivers for sending control instructions, and each control module is respectively provided with two second MLVDS transceivers for receiving control instructions. The two first MLVDS transceivers of the PLC controller are respectively connected to the two second MLVDS transceivers of each control module, forming two MLVDS control channels from the PLC controller to the control modules.

4. The PLC based on MLVDS communication according to claim 1, characterized in that: One end of the first FPGA is connected to the high-speed bus via a high-speed parallel interface, and the high-speed bus adopts a high-speed parallel data bus. The other end of the first FPGA is connected to a plurality of the first MLVDS transceivers via a high-speed parallel interface. The first FPGA is used to realize the mutual conversion of data in the parallel communication interface of the central processing unit and data between the multi-channel MLVDS parallel processing interface; One end of the second FPGA is connected to the local processor via an SPI interface, and the other end of the second FPGA is connected to several second MLVDS transceivers via a high-speed parallel interface. The second FPGA is used to realize the mutual conversion of data on the local processor serial interface and data between the multi-channel MLVDS parallel processing interface.

5. A PLC control system, characterized in that: The PLC control system includes a host computer and the PLC based on MLVDS communication according to any one of claims 1 to 4, and the host computer and the PLC controller are communicatively connected.

6. A communication method, applied to the PLC control system according to claim 5, characterized in that: The method comprises: After power-on initialization, the PLC controller discovers all local control modules by traversing the device and caches the traversal information configured for the control modules; After establishing communication with the PLC controller, the host computer sends the initial information of the control module configuration to the PLC controller; The PLC controller performs configuration verification by comparing the traversal information of the control module configuration with the initial information of the control module configuration; If the configuration verification passes, the PLC controller waits for the next instruction; After receiving the configuration instructions from the host computer, the PLC controller configures the control module according to the configuration instructions; If the control module is configured successfully, the PLC controller communicates with the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; If the data verification passes, the data communication is successful, otherwise the data communication is repeated.

7. A communication method according to claim 6, characterized in that: The method further comprises: If the configuration verification fails, the host computer will be returned to update the initial information of the control module configuration; If configuration of the control module fails, the PLC controller will re-traverse the device to confirm whether the control module to be configured is normal; If the control module to be configured is confirmed to be normal, it returns to the PLC controller and waits for the next instruction; If it is confirmed that the control module to be configured is abnormal, it returns to the host computer to update the initial information of the control module configuration.

8. A communication method according to claim 6, characterized in that: After the control module is successfully configured, the PLC controller transmits data to the control module through several MLVDS channels connected in parallel between the PLC controller and the control module, and performs data verification; If the data verification passes, the data transmission is successful, and the PLC controller sends an update data instruction to the control module; After receiving the data update instruction from the PLC controller, the control module uses the received new data to overwrite the local original data; If the data verification fails, the PLC controller retransmits the data to the control module.

9. A communication method according to claim 6, characterized in that: The data communication between the PLC controller and the control module adopts a custom communication protocol frame; The frame structure of the custom communication protocol frame includes several bytes, among which Byte0 and Byte1 are the frame header, Byte2 is the device address, Byte3 is the device type, Byte4 is the frame type, Byte5 and Byte6 are the frame length, Byte7 and Byte8 are the operation data address, Byte N0~Nx are data packets, Byte9 and Byte10 are CRC check codes, Byte11 is the MLVDS channel number, and Byte12 and Byte13 are the frame tail.

10. A communication method according to claim 9, characterized in that: The data packet includes a device identification code for uniquely identifying the device.

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