A method and device for CPU simulation synchronization between simulators based on FPGA and CPU

Abstract

The application discloses a kind of between FPGA and CPU's method and device of CPU simulation synchronization based on simulator, the method includes: CPU real-time synchronization device is issued CPU operation instruction to multiple real-time simulators by optical fiber, each equipment FPGA receives instruction and uploads to communication core, is distributed to all simulation cores by inter-core shared memory;Each simulation core generates CPU state signal before period cut-off and feeds back to communication core, communication core carries out the operation of "and" to each simulation core CPU state signal, and generates the device level synchronization confirmation signal and is issued to FPGA, FPGA sends signal to CPU real-time synchronization device by optical fiber;Device receives the synchronization confirmation signal of each equipment and carries out the synchronization state summary and determination of each equipment in current period, and whether the operation instruction of each CPU in next period is generated according to determination result;Compared with prior art, the application realizes the parallel simulation of CPU strict and accurate synchronization between multiple real-time simulation devices, guarantees the accurate simulation synchronization result of large-scale electrical system CPU.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of real-time simulation, in particular to a method and device for CPU simulation synchronization between simulators based on FPGA and CPU. BACKGROUND

[0002] With the rapid development of power systems, new energy stations and industrial control fields, the system scale and complexity grow exponentially. The mathematical model of large-scale power grids, new energy stations or complex mechanical and electrical systems needs to be solved with high precision. Single-core CPU cannot meet the real-time requirements, and traditional single-core or single-device simulation faces the bottleneck of insufficient computing power. New energy station applications require multiple device controllers to be tested simultaneously in a hardware-in-the-loop, that is, synchronous parallel simulation of multiple cores and devices.

[0003] However, in synchronous parallel simulation applications with multiple CPUs and devices, due to unbalanced computing task loads or communication delays, a CPU may not complete the current cycle operation, resulting in data synchronization errors or even system instability. Therefore, a method and device for CPU simulation synchronization between simulators based on FPGA and CPU are provided. SUMMARY

[0004] The present application aims to solve the problem of data synchronization errors or even system instability caused by the lack of strict synchronization of multiple CPUs and devices in parallel simulation applications. A method and device for CPU simulation synchronization between simulators based on FPGA and CPU are provided, which can achieve strict and accurate synchronization of multiple real-time simulation devices and ensure accurate simulation results for large-scale electrical systems.

[0005] To achieve the above-mentioned purpose, the present application provides the following technical solutions: a method for CPU simulation synchronization between simulators based on FPGA and CPU, comprising the following steps:

[0006] Step 1: At the beginning of each simulation cycle, the CPU real-time synchronization device sends the running instruction CPU_REQ of each simulator device CPU simulation core through optical fiber.

[0007] The CPU real-time synchronization device transmits the CPU running instruction CPU_REQ to each real-time simulator device through the optical fiber port, supports a maximum of 16 devices, and the instruction format is encapsulated using a custom protocol, containing the following fields:

[0008] Frame header (2 bytes): 55aa55aa55aa55aa;

[0009] Run instruction (1 byte): CPU run instruction CPU_REQ;

[0010] Frame tail (2 bytes): 1000000000000000;

[0011] Step 2: Each real-time simulator device FPGA receives the CPU run instruction, and uploads the instruction to the CPU communication core 0 in the device, and the communication core receives the run instruction CPU_REQ uploaded by the FPGA and issues the instruction to other simulation cores core1-i in the simulator;

[0012] If the real-time simulator device contains i+1 CPU cores, wherein core 0 is a dedicated communication core responsible for communication and data interaction with FPGA and other simulation cores, core 1~i is a simulation core for performing simulation calculation tasks, including the following steps:

[0013] Step 201: Each device's FPGA receives the run instruction CPU_REQ through an optical fiber, and parses and verifies the instruction;

[0014] Step 202: After the instruction is parsed, the FPGA transmits the instruction to the CPU communication core core 0 through the PCIE bus;

[0015] Step 203: After the CPU communication core receives the CPU run instruction CPU_REQ, it issues the instruction to other simulation cores core1-i in the simulator through the inter-core shared memory, which is a high-speed cache area accessible between multiple simulation cores in the CPU, supporting low-latency and high-efficiency data sharing and fast communication;

[0016] Step 3: After each CPU simulation core receives the CPU run instruction, it can start the current cycle model operation; each simulation core will generate the corresponding CPU state signal S i before the current cycle is over, and send the state signal to the communication core through the inter-core shared memory;

[0017] Step 301: After each CPU simulation core receives the CPU run instruction CPU_REQ, it can start the current cycle calculation task;

[0018] Step 302: Each simulation core core1-i will generate a CPU state signal S i before the current CPU calculation cycle is over, wherein:

[0019] ;

[0020] Each simulation core has a built-in hardware timer, and if the calculation is completed within the cycle, a signal = 1, if the calculation is not completed before the cycle is cut off, it is automatically marked = 0;

[0021] Step 303: Each simulation core sends the CPU state signal S to the communication core core 0 through the inter-core shared memory i :

[0022] Step 4: The communication core receives the state signal S of all simulation cores i , and performs a global logical AND operation on the signal to generate a device-level synchronization confirmation signal CPU_ACK, and sends this signal to the device FPGA;

[0023] Step 401: The communication core receives the CPU state signal S of all simulation cores i and stores the signal in the state register. Before the cycle is cut off, the communication core performs a global logical AND operation on the CPU state signal to generate a device-level synchronization confirmation signal CPU_ACK, wherein:

[0024] ;

[0025] Step 402: The communication core sends the CPU_ACK signal to the FPGA through the high-speed PCIE bus;

[0026] Step 5: The FPGA sends the synchronization confirmation signal CPU_ACK to the CPU real-time synchronization device through the optical fiber;

[0027] Step 6: The CPU real-time synchronization device waits for each real-time simulator to return the synchronization confirmation signal CPU_ACK, and ends the current simulation cycle after receiving the synchronization confirmation signal CPU_ACK of all devices;

[0028] Step 601: The CPU real-time synchronization device receives the synchronization confirmation signal CPU_ACK sent by each simulator device through the high-speed optical fiber interface;

[0029] Step 602: The CPU real-time synchronization device performs synchronization state summary, stores the received synchronization confirmation signal CPU_ACK in the synchronization state table, and marks the corresponding device as a completion state;

[0030] Step 603: The CPU real-time synchronization device traverses the synchronization state table before the current cycle is cut off, and performs an AND operation on the synchronization confirmation signal CPU_ACK of each device to generate a global synchronization state flag Global_Sync. If the total number of devices is M, then:

[0031] Global_Sync =

[0032] Step 604: the CPU real-time synchronization device determines whether to generate the running instruction of each CPU in the next cycle according to the global synchronization state flag bit Global_Sync:

[0033] If Global_Sync=1, that is, the CPU emulation core in all devices in the current cycle has completed the calculation, the device will perform the following operations:

[0034] (a) the CPU real-time synchronization device generates the running instruction CPU_REQ of each CPU in the next cycle;

[0035] (b) the device empties the synchronization state table in the current cycle, ends the simulation cycle, and prepares to receive the synchronization confirmation signal of each device in the next cycle;

[0036] If Global_Sync=0, that is, the CPU emulation core in the current cycle in the device has not completed the calculation, the device will perform the following operations:

[0037] (a) the device system enters a delay waiting stage, and suspends the issuance of the CPU running instruction in the next cycle;

[0038] (b) the current synchronization state table is not reset, and the missing synchronization confirmation signal is continuously monitored until the CPU_ACK of all emulators is received.

[0039] A device for CPU emulation synchronization between simulators based on FPGA and CPU, which is used for implementing the method for CPU emulation synchronization between simulators based on FPGA and CPU.

[0040] Compared with the prior art, the device has the beneficial effects that:

[0041] The CPU real-time synchronization device is adopted to ensure the strict synchronization emulation of four CPU emulation cores of two simulators, the high-speed interaction of simulation data between the two simulators is realized through the optical fiber, and the clock synchronization of each device is realized through the clock line connected with the CPU real-time synchronization device, so that the strict and accurate synchronization parallel emulation of four CPU emulation cores between the two real-time simulation devices is realized, and the synchronization result of the CPU emulation of the main network IEEE118 node electrical system is ensured to be accurate. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 It is a flow chart of the method for CPU emulation synchronization between simulators based on FPGA and CPU;

[0043] Figure 2 It is a schematic diagram of the device for CPU emulation synchronization between simulators based on FPGA and CPU;

[0044] Figure 3The signal schematic diagram of the CPU real-time synchronization device of the application;

[0045] Figure 4 The main network IEEE118 node multi-device multi-CPU core synchronization parallel simulation real-time result waveform of the application. DETAILED DESCRIPTION

[0046] The preferred embodiments of the application are described in detail below with reference to the accompanying drawings, so that the advantages and features of the application can be more easily understood by those skilled in the art, and the protection scope of the application can be more clearly defined.

[0047] Embodiment 1: A method for CPU simulation synchronization between simulators based on FPGA and CPU, comprising the following steps:

[0048] Step 1: At the beginning of each simulation cycle, the CPU real-time synchronization device transmits the running instruction CPU_REQ of the CPU simulation core of each simulator device through the optical fiber;

[0049] In step 1, as shown in the figure, Figure 1 the CPU real-time synchronization device transmits the CPU running instruction CPU_REQ to each real-time simulator device through the optical fiber, supports a maximum of 16 devices, the instruction format is packaged by a self-defined protocol, and contains the following fields:

[0050] Frame header (2 bytes): 55aa55aa55aa55aa;

[0051] Running instruction (1 byte): CPU running instruction CPU_REQ;

[0052] Frame tail (2 bytes): 1000000000000000;

[0053] Step 2: Each real-time simulator device FPGA receives the CPU running instruction and uploads the instruction to the CPU communication core 0 in the device, and the communication core receives the running instruction CPU_REQ uploaded by the FPGA and transmits the instruction to other simulation cores core1-i in the simulator;

[0054] In step 2, as shown in the figure, Figure 2 if the real-time simulator device contains i+1 CPU cores, core 0 is a dedicated communication core, responsible for communication and data interaction with FPGA and other simulation cores, and cores 1~i are simulation cores, used for performing simulation calculation tasks, comprising the following steps:

[0055] Step 201: The FPGA of each device receives the running instruction CPU_REQ through the optical fiber, and parses and verifies the instruction;

[0056] Step 202: After the instruction is parsed, the FPGA transmits the instruction to the CPU communication core core 0 through the PCIE bus;

[0057] Step 203: After the CPU communication core receives the CPU running instruction CPU_REQ, the instruction is issued to other simulation cores core1-i in the simulator through the inter-core shared memory. The inter-core shared memory is a cache area that can be directly accessed between the multiple simulation cores in the CPU, supporting low-latency and high-efficiency data sharing and fast communication;

[0058] Step 3: After each CPU simulation core receives the CPU running instruction, it can start the current cycle model operation; each simulation core generates the corresponding CPU state signal S i before the current cycle ends, and sends the state signal to the communication core through the CPU inter-core shared memory;

[0059] Step 3 includes the following steps:

[0060] Step 301: After each CPU simulation core receives the CPU running instruction CPU_REQ, it starts the simulation calculation task of the current cycle;

[0061] Step 302: Each simulation core core1-i generates a CPU state signal S i before the current CPU calculation cycle ends, wherein:

[0062] ;

[0063] Each simulation core has a built-in hardware timer. If the calculation is completed within the cycle, the signal = 1 is generated, and if the calculation is not completed before the cycle ends, the signal = 0 is automatically marked;

[0064] Step 33: Each simulation core sends the CPU state signal S i to the communication core core 0 through the inter-core shared memory;

[0065] Step 4: The communication core receives the state signal S i of all simulation cores, and performs a global logical AND operation on the signal to generate a device-level synchronization confirmation signal CPU_ACK, and issues this signal to the device FPGA;

[0066] Step 4 includes the following steps:

[0067] Step 401: The communication core receives the CPU state signal Si of all simulation cores and stores the signal in the state register. Before the cycle ends, the communication core performs a global logical AND operation on the CPU state signal to generate a device-level synchronization confirmation signal CPU_ACK, wherein:

[0068] ;

[0069] Step 402: The communication core sends the CPU_ACK signal to the FPGA through the high-speed PCIE bus;

[0070] Step 5: The FPGA sends the synchronization confirmation signal CPU_ACK to the CPU real-time synchronization device through the optical fiber;

[0071] Step 6: The CPU real-time synchronization device waits for the synchronization confirmation signal CPU_ACK returned by each real-time simulator, and ends the current simulation cycle after receiving the synchronization confirmation signal CPU_ACK of all devices;

[0072] As shown in Figure 3 . Step 6 includes the following steps:

[0073] Step 601: The CPU real-time synchronization device receives the synchronization confirmation signal CPU_ACK sent by each simulator device through the high-speed optical fiber interface;

[0074] Step 602: The CPU real-time synchronization device performs synchronization state summary, stores the received synchronization confirmation signal CPU_ACK of each device into the synchronization state table, and marks the corresponding device as completed state;

[0075] Step 603: The CPU real-time synchronization device traverses the synchronization state table before the current cycle ends, performs "AND" operation on the synchronization confirmation signal CPU_ACK of each device to generate the global synchronization state flag Global_Sync, and if the total number of devices is M, then:

[0076] Global_Sync =

[0077] Step 604: The CPU real-time synchronization device decides whether to generate the running instruction of each CPU in the next cycle according to the global synchronization state flag Global_Sync:

[0078] If Global_Sync = 1, that is, all CPU simulation cores in the current cycle have completed the calculation, the device will perform the following operations:

[0079] (a) The CPU real-time synchronization device generates the running instruction CPU_REQ of each CPU in the next cycle;

[0080] (b) The device clears the synchronization state table of the current cycle, ends the current simulation cycle, and prepares to receive the synchronization confirmation signal of each device in the next cycle;

[0081] If Global_Sync = 0, that is, the current cycle exists in the device CPU simulation core unfinished calculation, the device will perform the following operations:

[0082] (a), the device system enters the delay waiting stage, suspends the next cycle of CPU running instruction;

[0083] (b), the current synchronization state table is not reset, and the missing synchronization confirmation signal is continuously monitored until all the CPU_ACK of the simulator is received;

[0084] In the above system, the data interaction between each device is carried out through optical fiber, and the clock signal is sent to each real-time simulator by the CPU real-time synchronization device to ensure the clock synchronization of all devices.

[0085] Example 2: Analysis of real-time simulation results of IEEE118 node multi-core model parallel simulation of main network

[0086] Take the IEEE118 node model of the main network as an example to verify the performance of strict synchronization real-time parallel simulation of multiple CPUs and multiple devices. The IEEE118 node model is a standard test system widely used in power system analysis, which has complex structure and rich parameters, and is suitable for studying the dynamic characteristics, economic optimization and multi-energy collaborative scheduling of power grid, and is an important tool for power system algorithm verification and smart grid research.

[0087] The grid frame has 118 three-phase nodes, including 177 lines, 54 synchronous machines, 83 loads, and 9 transformers. There are three voltage levels of 20kV, 138kV and 345kV, and the total power of all generators is 4377.4MW.

[0088] The grid model is divided into 4 cores and runs on two real-time simulators, with two cores running on each real-time simulator. The calculation step of each CPU simulation core is 50us. Among them, there are 40 three-phase nodes in the core 1 of the simulator A, including 3 transformers, 16 synchronous machines, 58 lines and 29 loads; there are 19 three-phase nodes in the core 2 of the simulator A, including 1 transformer, 11 synchronous machines, 31 lines and 14 loads; there are 24 three-phase nodes in the core 1 of the simulator B, including 2 transformers, 12 synchronous machines, 34 lines and 17 loads; there are 35 three-phase nodes in the core 2 of the simulator B, including 3 transformers, 15 synchronous machines, 45 lines and 23 loads; the modules contained in each core and the actual running time of each CPU are shown in Table 1.

[0089] Table 1. Modules contained in each core of IEEE118 node and actual running time

[0090] The application provides a method and device for CPU simulation synchronization between simulators based on FPGA and CPU, which adopts a CPU real-time synchronization device to ensure strict synchronization simulation of four CPU simulation cores of two simulators, high-speed interaction of simulation data between the two simulators through optical fibers, and synchronization of clocks of each device through a clock line connected between the CPU real-time synchronization device and the device, so as to realize strict and accurate synchronization of the four CPU simulation cores of the two real-time simulation devices, and ensure accuracy of the CPU simulation synchronization result of the main network IEEE118 node electrical system.

[0091] Figure 4 The (a), (b), (c) and (d) in the figure respectively represent current and voltage waveforms at the 138kV node of the simulator A core 1 and the simulator B core 1, the sine of the voltage and current is good, the waveforms are smooth, the main network model is in stable operation, and the method for CPU simulation synchronization can realize strict and synchronized parallel real-time simulation hardware-in-the-loop test of multiple CPUs and multiple real-time simulation devices.

[0092] The above examples only express the embodiments of the application, and the description is relatively specific and detailed, but it cannot be understood as a limitation on the scope of the patent application. It should be pointed out that, for those skilled in the art, without departing from the concept of the application, a number of modifications and improvements can be made, which are all within the protection scope of the application.

Claims

1. A method for CPU simulation synchronization between FPGA and CPU based emulators, the method comprising: Specifically comprising the following steps: Step 1: At the beginning of each simulation cycle, the CPU real-time synchronization device sends the running instruction CPU_REQ of each simulator device CPU simulation core through the optical fiber; Step 2: Each real-time simulator FPGA receives the CPU running instruction and uploads the instruction to the device CPU communication core core 0, and the communication core receives the running instruction CPU_REQ uploaded by the FPGA and sends the instruction to other simulation cores core1-i in the simulator; Step 3: Each CPU simulation core receives the CPU operation instruction and can start the current cycle model operation; each simulation core will generate the corresponding CPU state signal S before the current cycle ends i and send the state signal to the communication core through the shared memory between CPU cores; Step 3 comprises the following steps: Step 301: After each CPU simulation core receives the CPU running instruction CPU_REQ, the calculation task of the current cycle can be started; Step 302: Each simulation core 1 ~ i generates a CPU status signal S before the current CPU computation cycle ends i , wherein: Step 303: Each simulation core sends a CPU state signal S to the communication core core 0 through the inter-core shared memory i ; Step 4: the communication core receives the state signals S of all simulation cores i And performs a global logical "and" operation on the signals, generates a device-level synchronization confirmation signal CPU_ACK, and issues this signal to the device FPGA; Step 5: Each real-time simulator FPGA sends the synchronization confirmation signal CPU_ACK to the CPU real-time synchronization device through the optical fiber; Step 6: The CPU real-time synchronization device waits for the synchronization confirmation signal CPU_ACK returned by each real-time simulator, and ends the simulation cycle after receiving the synchronization confirmation signal CPU_ACK of all devices; Step 6 comprises the following steps: Step 601: The CPU real-time synchronization device receives the synchronization confirmation signal CPU_ACK sent by each simulator device through the high-speed optical fiber interface; Step 602: The CPU real-time synchronization device performs synchronization state summary, stores the received synchronization confirmation signal CPU_ACK in the synchronization state table, and marks the corresponding device as a completed state; Step 603: The CPU real-time synchronization device traverses the synchronization state table before the end of the current cycle, performs the "and" operation on the synchronization confirmation signal CPU_ACK of each device, generates a global synchronization state flag Global_Sync, and if the total number of devices is M, then: Global_Sync = 0x00000001 Step 604: The CPU real-time synchronization device decides whether to generate the running instruction of each CPU in the next cycle according to the global synchronization state flag Global_Sync: If Global_Sync=1, that is, the CPU simulation core in all devices in the current cycle has completed the calculation, the device will perform the following operations: (a) The CPU real-time synchronization device generates the running instruction CPU_REQ of each CPU in the next cycle; (b) The device clears the synchronization state table of the current cycle, ends the simulation cycle, and prepares to receive the synchronization confirmation signal of each device in the next cycle; If Global_Sync=0, that is, there is a device in which the CPU simulation core has not completed the calculation in the current cycle, the device will perform the following operations: (a) The device system enters a delay waiting stage and pauses the running instruction of the next cycle; (b) The current synchronization state table is not reset, and the missing synchronization confirmation signal is continuously monitored until the CPU_ACK of all simulators is received.

2. The method for FPGA and CPU based inter-simulator CPU emulation synchronization of claim 1, wherein: Step 2 comprises the following steps: Step 201: Each device FPGA receives the running instruction CPU_REQ through the optical fiber, and parses and verifies the instruction; Step 202: After the instruction parsing, the FPGA transmits the instruction to the CPU communication core core 0 through the PCIE bus; Step 203: After the CPU communication core receives the CPU running instruction CPU_REQ, the instruction is sent to other simulation cores core1-i in the emulator through the inter-core shared memory, which is a cache area directly accessible between the multiple simulation cores in the CPU, supporting low-latency, high-efficiency data sharing and fast communication.

3. The FPGA and CPU-based inter-emulator CPU simulation synchronization method according to claim 1, characterized in that: Step 4 comprises the following steps: Step 401: The communication core receives the CPU state signals S of all simulation cores i and performs a global logical AND operation on the signals, generating a device-level synchronization acknowledgement signal CPU_ACK, wherein: ； Step 402: The communication core sends the CPU_ACK signal to the FPGA through the high-speed PCIE bus.

4. The method for FPGA and CPU based inter-simulator CPU emulation synchronization of claim 1, wherein: In step 2, each real-time emulator device FPGA is used to connect the optical fiber for high-speed interaction of simulation data.

5. The method for FPGA and CPU based inter-simulator CPU emulation synchronization of claim 1, wherein: The CPU real-time synchronization device in step 5 ensures the synchronization of the clocks of each device through the connection of the clock synchronization line between each real-time emulator.

6. An apparatus for CPU simulation synchronization between FPGA and CPU based emulators, the apparatus comprising: A FPGA and CPU-based inter-emulator CPU simulation synchronization method according to any one of claims 1-5.

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