A solid state disk rapid hard destruction method, device, system and storage medium

Abstract

The application provides a solid state disk rapid hard destruction method, device, system and storage medium, and belongs to the technical field of data processing; the solid state disk rapid hard destruction method specifically comprises the following steps: receiving a destruction voltage signal input from outside, generating a periodic square wave control signal through a single-chip microcomputer, the high and low level duty cycles of the square wave signal are determined by the charging and discharging time of a capacitor charging and discharging circuit, and a MOS tube switching circuit is used to switch the on-off of a normal power supply circuit and a destruction circuit; a pulse voltage is generated through the capacitor charging and discharging circuit, the pulse voltage is applied to the Flash chip power supply pin of the solid state disk, so that the storage chip is burned out, and the purpose of destroying data is achieved. The application adopts the form of capacitor charging and discharging to form a pulse voltage for destruction, reduces the pressure of the power supply circuit, ensures that each Flash chip is fully burned out, and there is no risk of data recovery.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of solid state disk data processing, in particular to a solid state disk rapid hard destruction method, device, system and computer readable storage medium. BACKGROUND

[0002] With the development of computer technology, higher requirements are put forward for the security and confidentiality of solid state disks storing data. The solid state disk hard destruction technology can realize rapid destruction of data and burn the Flash chip to achieve the purpose of permanently destroying data. At present, solid state disks are widely used in military and civilian fields, and store a large amount of confidential data such as electronic maps and guidance video information, which need to be destroyed under certain conditions to prevent information leakage. Therefore, the application scenarios of solid state disks with hard destruction technology are more extensive.

[0003] The utility model patent with publication number CN204719761U (hereinafter referred to as: prior art 1) discloses an intelligent destruction solid state disk, which comprises a single-chip microcomputer and a Flash chip. The single-chip microcomputer is connected with a key security device, an inductor, a power conversion chip, a password cracking detector, a signal transceiver and a destruction circuit. The key security device is connected with the password cracking detector. The Flash chip is connected with the key security device and the destruction circuit. The password cracking detector is connected with a data interface. The power conversion chip is connected with a backup power supply. The utility model has the advantages that the destruction speed of the solid state disk is effectively improved through the destruction circuit, the password cracking detector and the inductor. The operation is convenient and the intelligent degree is high. Therefore, the intelligent destruction solid state disk has a wider development space.

[0004] The invention patent with publication number CN117037880A (hereinafter referred to as: prior art 2) discloses an optimization design circuit of a hardware destruction circuit of a solid state disk, which comprises a power supply selection circuit and an energy storage capacitor. The power supply selection circuit is used for receiving an external hardware destruction instruction and switching the supply power of the Flash chip to the energy storage capacitor according to the hardware destruction instruction. The high voltage of the energy storage capacitor destroys the internal data of the Flash chip to destroy the data. The present scheme uses the original energy storage capacitor (high voltage) of the solid state disk as the impact voltage for destroying the Flash chip, which can be realized only by a simple control and conversion circuit. The original destruction power supply boost circuit is simplified, the high-voltage boost circuit is removed, the hardware cost is saved, and the circuit board layout space is simplified.

[0005] The prior art 1 relies on a password cracking detector and an inductor trigger to trigger the destruction, has a risk of false triggering and an unadjustable destruction voltage, and is insufficient in adaptability; the prior art 2 mainly releases high voltage directly through a fixed 35V energy storage capacitor, and cannot adapt to different power supply environments, resulting in complex design; and the prior art 1 adopts continuous high voltage burning, needs high-power front-end power supply, and is prone to incomplete destruction due to insufficient power supply.

[0006] In actual use, the following deficiencies exist:

[0007] Firstly, the destruction voltage amplitude is unadjustable: the destruction voltage of the existing hard destruction technology is obtained by converting 3.3V to 8V, and is output to the Flash chip by using the normal power supply circuit of the Flash, so that the destruction voltage cannot be controlled.

[0008] Secondly, the power supply circuit requirement is too high: the original hard destruction technology is to burn the Flash chip by converting 3.3V to 8V for a period of time, and all Flash chips are burned at the same time, so that the front-end has sufficient power supply capacity, otherwise the destruction process will be insufficient due to insufficient power supply, and the destruction will not be thorough.

[0009] Thirdly, the secondary use is poor: the original normal power supply circuit is used to input the destruction voltage, which will burn the original other devices and circuits, and even cause the entire solid state disk to be burned and other devices to be burned, so that the safety has a great risk, and there is no special destruction of the Flash chip for storing data, so that the hard-destroyed solid state disk cannot be used twice, and the cost is high. SUMMARY

[0010] The purpose of the present application is to provide a solid state disk fast hard destruction method, device, system and storage medium, which adopts the form of capacitor charging and discharging to form pulse voltage for destruction, reduces the pressure of the power supply circuit, ensures sufficient burning of each Flash chip, and has no risk of data recovery.

[0011] To solve the above technical problems, the technical solution adopted by the present application is:

[0012] In a first aspect, the present application provides a solid state disk fast hard destruction method, which specifically comprises the following steps:

[0013] Receiving an externally input destruction voltage signal, the amplitude range of the destruction voltage signal being 16V-32V;

[0014] Generating a periodic square wave control signal by a single-chip microcomputer, the high and low level duty cycle of the square wave control signal being determined by the charging and discharging time of the capacitor charging and discharging circuit; it is suggested that the low level duration is 0.8-1.5ms, and the high level duration is 9-20ms;

[0015] Based on the square wave control signal, MOS switch circuit is controlled to switch the on-off of normal power supply circuit and destruction circuit.

[0016] The pulse voltage generated by the capacitor charging and discharging circuit is applied to the Flash chip power supply pin of the solid state disk to burn the storage chip, so as to achieve the purpose of destroying data.

[0017] Further, the amplitude of the destruction voltage signal is inputted externally, the input voltage range is 16V-32V, and the input lasts more than 1 second.

[0018] Further, the pulse voltage duration is not more than 0.8-1.5ms, and the pulse interval is 10-30ms, and the specific time is adjusted by the capacitor charging and discharging circuit.

[0019] Further, after the destruction is completed, the method further comprises the steps of:

[0020] Detecting the burning state of the Flash chip, if the burning is not complete, automatically triggering the destruction process again.

[0021] In the second aspect, the application provides a solid state disk fast hard destruction device, comprising:

[0022] A signal receiving module is configured to receive an externally inputted destruction voltage signal.

[0023] A single-chip microcomputer control module is connected with the signal receiving module and configured to generate a periodic square wave control signal.

[0024] A MOS switch module is connected with the single-chip microcomputer control module and configured to switch the normal power supply circuit and the destruction circuit according to the square wave control signal.

[0025] A capacitor charging and discharging module is connected with the MOS switch module and configured to generate a pulse voltage and output the pulse voltage to the Flash chip.

[0026] Further, the capacitor charging and discharging module comprises a plurality of energy storage capacitors connected in parallel, each capacitor has a capacity of 0.1-10μF and a rated voltage of 63-100V, is designed with a 50% derating, and the total capacity is not less than 100μF.

[0027] Further, the MOS switch module comprises a combination circuit composed of an NMOS tube and a PMOS tube, and is configured to completely isolate the connection between the normal power supply circuit and the Flash chip in the destruction state.

[0028] In the third aspect, the application provides a solid state disk fast hard destruction system, comprising the solid state disk fast hard destruction device.

[0029] A power management unit is configured to provide an adjustable voltage input for the destruction device, and the voltage range is 16V to 32V.

[0030] A monitoring module is configured to detect voltage fluctuation and Flash chip state in real time during the destruction process, and feed back an abnormal signal to the single-chip microcomputer control module.

[0031] A communication interface is configured to support remote triggering of a destruction instruction or receiving of destruction state information.

[0032] The communication interface supports a wireless communication protocol, including Wi-Fi, Bluetooth or 5G, and is configured to interact with a cloud server or a mobile terminal.

[0033] In a fourth aspect, the application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer program instructions, and the program is executed by a processor to implement the solid-state disk rapid hard destruction method.

[0034] Compared with the prior art, the application has the following beneficial effects:

[0035] The application uses a single-chip microcomputer control circuit, a MOS switch circuit and a capacitor charging and discharging circuit to burn the Flash chip. The application uses capacitor charging and discharging to form a pulse voltage to destroy the Flash chip, thereby reducing the power supply circuit pressure, ensuring that each Flash chip is fully burned, and reducing the risk of data recovery. The application has an adjustable voltage, is suitable for different power supply capabilities, and reduces the design difficulty. The application uses a pulse destruction method to reduce the front-end power supply pressure and ensure the completeness of the destruction. More importantly, the application uses an independent circuit design, is only used for the Flash chip, can be used again after replacement, and reduces the cost. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the application, and therefore should not be regarded as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0037] Figure 1 It is a logic composition block diagram of the hard destruction technology.

[0038] Figure 2 It is a circuit principle diagram of the single-chip microcomputer control circuit.

[0039] Figure 3 It is a MOS switch circuit principle diagram.

[0040] Figure 4 It is a capacitor charging and discharging circuit principle diagram.

[0041] Figure 5 Input 20V destruction voltage effect diagram for the present application.

[0042] Figure 6 Input 25V destruction voltage effect diagram for the present application.

[0043] Figure 7 Input 28V destruction voltage effect diagram for the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. Figure 1 -Appendix Figure 7 The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. EMBODIMENT

[0045] The present embodiment provides a solid state disk fast hard destruction method, which specifically comprises the following steps:

[0046] Receiving an externally input destruction voltage signal, the amplitude range of the destruction voltage signal is 16V-32V; in the present embodiment, the voltage is 28V;

[0047] Wherein, receiving an externally input destruction voltage signal specifically refers to generating a destruction voltage signal after receiving an external trigger instruction;

[0048] Generating a periodic square wave control signal by a single-chip microcomputer, the high and low level duty cycle of the square wave control signal is determined by the charging and discharging time of the capacitor charging and discharging circuit, wherein the low level duration is 0.8-1.5ms, and the high level duration is 9-20ms.

[0049] In the present embodiment, the high and low level duty cycle of the square wave control signal is determined by the charging and discharging time of the capacitor charging and discharging circuit, wherein the low level duration is 1ms, and the high level duration is 15ms.

[0050] Based on the square wave control signal, the MOS tube switching circuit is controlled to switch the on-off of the normal power supply circuit and the destruction circuit;

[0051] Generating a pulse voltage by a capacitor charging and discharging circuit, the pulse voltage is applied to the Flash chip power supply pin of the solid state disk to burn the storage chip, so as to achieve the purpose of destroying data.

[0052] Further, the amplitude of the destruction voltage signal is inputted by external input, the input voltage range is 16V-32V, and the input lasts more than 1 second. In the present embodiment, the input voltage is 28V, and the input lasts 1 second.

[0053] Further, through experiments, it is verified that when the peak value of the pulse voltage is set to 28V, the duration of a single pulse is not more than 10ms, and the pulse interval is 100ms, the flash chip can be effectively burned out and the circuit overload can be avoided.

[0054] Further, after the destruction is completed, the method further comprises the steps of:

[0055] Detecting the burning state of the flash chip, and if the burning is not complete, triggering the destruction process again.

[0056] Specifically, the power pin current value of the flash chip is detected by the monitoring module, and if the current value is lower than a preset threshold, it is determined that the burning is complete; otherwise, the destruction process is triggered again.

[0057] It should be noted that the application periodically releases the stored energy in the energy storage capacitor through the capacitor charging and discharging circuit to generate a pulse voltage, thereby avoiding the dependence on the continuous high voltage of the power supply circuit. Embodiment

[0058] The embodiment provides a solid-state disk rapid hard destruction device, which comprises:

[0059] A signal receiving module is configured to receive an externally input destruction voltage signal.

[0060] A single-chip microcomputer control module is connected with the signal receiving module and configured to generate a periodic square wave control signal.

[0061] A MOS tube switch module is connected with the single-chip microcomputer control module and configured to switch the normal power supply circuit and the destruction circuit according to the square wave control signal.

[0062] A capacitor charging and discharging module is connected with the MOS tube switch module and configured to generate a pulse voltage and output the pulse voltage to the flash chip.

[0063] Further, the capacitor charging and discharging module comprises a plurality of energy storage capacitors connected in parallel, the capacity of a single capacitor is 0.1-10μF, the rated voltage is 63-100V, the design is according to 50% derating, and the total capacity is not less than 100μF.

[0064] In the embodiment, the capacity of a single capacitor is 8μF, the rated voltage is 68V, and the total capacity is 200μF.

[0065] Further, the MOS tube switch module comprises a combined circuit composed of an NMOS tube and a PMOS tube, and is configured to completely isolate the connection between the normal power supply circuit and the flash chip in the destruction state. Embodiment

[0066] The application provides a solid-state disk rapid hard destruction system, comprising a solid-state disk rapid hard destruction device as described in embodiment 1.

[0067] A power management unit is configured to provide an adjustable voltage input for the destruction device, and the voltage range is 16V to 32V.

[0068] A monitoring module is configured to detect voltage fluctuation and Flash chip state in real time during the destruction process, and feed back an abnormal signal to the single-chip microcomputer control module.

[0069] A communication interface is configured to support remote triggering of a destruction instruction or receiving of destruction state information.

[0070] The communication interface supports a wireless communication protocol, including Wi-Fi, Bluetooth or 5G, and is configured to interact with a cloud server or a mobile terminal.

[0071] The embodiment further discloses a computer readable storage medium, wherein the readable storage medium stores computer program instructions, and the program is executed by a processor to implement the solid-state disk rapid hard destruction method of embodiment 1. Embodiment

[0072] The embodiment further discloses another multi-stage data destruction method based on single-chip microcomputer control, which is mainly based on the solid-state disk rapid hard destruction device of embodiment 2, and specifically comprises the following steps.

[0073] A signal receiving module is used to receive a destruction instruction, and a MOS tube switch module and a capacitor charging and discharging module are controlled by a single-chip microcomputer.

[0074] A temperature sensor is used to monitor the surface temperature of a Flash chip, and a current detection circuit is used to feed back a real-time current value of a Flash power pin.

[0075] A multi-stage state machine is embedded in a single-chip microcomputer firmware, and a destruction parameter is dynamically adjusted according to the collected temperature and current value, wherein the destruction parameter includes voltage, pulse duty ratio and stage duration.

[0076] The multi-stage state machine controls multi-stage destruction, including a preheating and pre-destruction stage, a main destruction stage, a reinforced destruction stage and a cooling and resetting stage.

[0077] In the preheating and pre-destruction stage, a low-voltage pulse is used to gradually damage the internal structure of the Flash chip, in the main destruction stage, standard parameters are used to ensure physical damage of a core data area, in the reinforced destruction stage, higher energy is applied to stubborn areas when the current value is higher than a threshold value after the main destruction stage, and in the cooling and resetting stage, pulse output is stopped and a system self-check is performed to generate a destruction report.

[0078] Further, the dynamic adjustment of the destruction parameter is specifically:

[0079] In the preheating and pre-destruction stage, the voltage is 20V and can be dynamically adjusted by external input in 2V steps, the square wave duty cycle is 1:5, the pulse number is 5, and the interval is 100ms;

[0080] In the main destruction stage, the voltage is 28V, the square wave duty cycle is 1:10, and the pulse continues until the current detection value is lower than 10mA;

[0081] In the strengthening destruction stage, the voltage is 32V, the square wave duty cycle is 1:15, and the pulse number is 3, with an interval of 50ms.

[0082] Further, the multi-stage destruction method reuses the original monitoring module to realize temperature and current data acquisition function, based on the original detection of burnout state and triggering of the mechanism for re-destruction, and is expanded to trigger the strengthening destruction stage according to the current threshold, and the destruction voltage amplitude is dynamically adjusted by external input, and the duty cycle dynamic switching function is added based on the original square wave generation logic.

[0083] In actual use, the multi-stage destruction mechanism is based on the cooperative operation of hardware and software to realize complete data destruction in a phased and dynamically adjusted parameter manner, and the specific principle process is as follows:

[0084] After the signal receiving module obtains the destruction instruction, the whole system starts. The original capacitor charging and discharging module starts to work to provide the energy basis for destruction. The newly added temperature sensor is closely attached to the surface of the Flash chip to monitor the chip temperature in real time. Once the temperature is too high, it may affect the destruction effect and even damage the equipment, so it plays a key role in temperature early warning. The current detection circuit accurately collects the real-time current value of the Flash power pin through the sampling resistor and the operational amplifier circuit, which can intuitively reflect the working state and destruction degree of the chip inside.

[0085] The multi-stage state machine embedded in the single-chip microcomputer intelligently analyzes and decides according to the data feedback by the temperature sensor and the current detection circuit. The state machine dynamically adjusts the key parameters in the destruction process according to the preset logical rules, such as voltage size, pulse duty cycle and duration of each stage, to ensure that the destruction process can completely destroy the data and avoid various problems caused by improper parameters.

[0086] In the preheating stage, the single-chip microcomputer controls the power management unit to output a 20V voltage, and the capacitor group is charged to this voltage. The single-chip microcomputer outputs a square wave control signal with a duty ratio of 1:5, controls the MOS tube to switch the on-off of the destruction circuit, and releases 5 pulses to the Flash chip at a rhythm of 2ms low level and 10ms high level, with a pulse interval of 100ms each time. The low-voltage pulse gradually damages the internal structure of the chip. This progressive destruction method can evenly affect each part of the chip, preventing incomplete burning caused by local overheating due to instantaneous high voltage.

[0087] After the preheating is completed, the voltage is raised to the standard parameter of 28V. The duty ratio of the square wave is adjusted to 1:10, i.e. 1ms low level and 10ms high level. The pulse is continuously output until the current detection value is lower than the set threshold (such as 10mA), indicating that the core data area has been physically damaged. During this process, if the temperature sensor detects that the chip temperature exceeds 80℃, the single-chip microcomputer automatically inserts a 100ms cooling interval to prevent high temperature from affecting the destruction effect and equipment safety.

[0088] After the main destruction stage is completed, if the current value is still higher than the threshold, it means that there are stubborn area data that have not been completely destroyed, at which time the enhanced destruction is automatically triggered. The voltage is further raised to 32V, close to the safe upper limit of the rated voltage 35V of the capacitor. The duty ratio of the square wave is changed to 1:15, and a pulse with a low level of 0.5ms and a high level of 7.5ms is continuously sent 3 times with an interval of 50ms each time, to apply higher energy to the stubborn area to ensure that the data cannot be recovered. After the destruction is completed, the single-chip microcomputer controls the MOS tube to switch to the normal power supply circuit and stop pulse output. If the device is integrated with a cooling fan, the fan is started to accelerate heat dissipation; if there is no fan, the chip is naturally cooled. After the cooling process is completed, the system performs self-checking to check the working state of each module and generates a destruction report, uploads the log through the communication interface (Wi-Fi / 5G), and records whether the destruction is successful, the peak voltage, the total time consumption and other key information.

[0089] This method realizes efficient, complete and safe data destruction through multi-stage destruction mechanism, real-time hardware monitoring and software intelligent control.

[0090] In order to facilitate further understanding of the present application by those skilled in the art, the present application is further described.

[0091] The existing hard destruction technology destroys the voltage by 3.3V to 8V, and adopts the normal power supply circuit output to the flash chip, and cannot control the destruction voltage. The original hard destruction technology is 3.3V to 8V voltage burning the flash chip for a period of time, and all flash chips are burned at the same time, and the front end needs sufficient power supply capacity, otherwise it will cause insufficient power supply during the destruction process, and the destruction is not thorough enough; using the original normal power supply circuit input destruction voltage will burn the original other devices and circuits, and even cause the entire solid state disk to burn and other equipment to burn, the safety risk is large, there is no special destruction of the flash chip for storing data, so that the hard destruction solid state disk cannot be used twice, and the cost is high.

[0092] In view of the above-mentioned defects, the hard destruction in the application mainly comprises four parts of input destruction voltage as a starting signal, single-chip microcomputer control burning time, MOS switch circuit for preventing burning other devices, and capacitor charging and discharging circuit for burning flash chip, and the main components are as shown in Figure 1 .

[0093] The single-chip microcomputer control circuit, the MOS tube switch circuit and the capacitor charging and discharging circuit are included.

[0094] The single-chip microcomputer control circuit takes whether the destruction voltage is input from the outside as a starting signal, mainly for controlling the switching of normal power supply and hard destruction voltage, total destruction time and capacitor charging and discharging time, and the circuit principle diagram of the single-chip microcomputer control circuit is as shown in Figure 2 .

[0095] VDD is connected to the power supply VCC to supply power for the chip, and GND is grounded to provide a reference potential.

[0096] RST: reset pin;

[0097] PA0-PA5: general input / output pin;

[0098] VCC_EN_N: power supply enable pin, low level effective;

[0099] DES_EN0: may be a specific function enable pin.

[0100] Normal state: PA0 is high, VCC_EN_N is low, and DES_EN0 is low;

[0101] Destruction state: PA0 is low, VCC_EN_N is high, and DES_EN0 outputs a periodic square wave, and the waveform is 1ms low and 10ms high.

[0102] The MOS switch circuit is controlled by a 10:1 periodic waveform output by a single-chip microcomputer, a normal power supply and a hard-destroying voltage switching signal, and mainly controls the release and closing of the destroying voltage in the capacitor charging and discharging circuit; the MOS switch circuit is also controlled by a switching signal to ensure safety; the principle of the MOS switch circuit is as shown in Figure 3

[0103] The MOS switch circuit comprises a combined circuit composed of NMOS tubes and PMOS tubes, and comprises Q1, Q2, Q3, Q5, Q6 and a resistor R7.

[0104] Among them,

[0105] The gate of Q1 is connected to a signal VCC_EN_N, the source is grounded, and the drain is connected to the gate of Q2,

[0106] The source of Q2 is grounded, and the drain is connected to the gate of Q3.

[0107] The drain of Q3 is connected to VCC_R, and the source outputs PWR_NAND.

[0108] The signal VCC_EN is connected to a node between Q1 and Q2.

[0109] One end of R7 is connected to VCC_R, and the other end is connected to the gate of Q6; the source of Q6 is grounded, and the drain outputs DES_EN0. The drain of Q5 is connected to VCC_NAND, and the gate cooperates with other nodes to switch the power supply path.

[0110] Normal state: In the normal working state, PWR_NAND is directly delivered to VCC_NAND to supply power to the Flash.

[0111] Destroying state: In the destroying state, PWR_NAND is cut off to deliver VCC_NAND, and a destroying voltage is used for destruction. The circuit realizes the switching of the power supply path in the normal power supply and the destroying state through the conduction and cutoff of the transistor.

[0112] Among them, the capacitor charging and discharging circuit is controlled by the MOS switch circuit, and mainly outputs a pulse voltage to burn the Flash chip; a circuit diagram of the capacitor charging and discharging circuit is as shown in Figure 4

[0113] The capacitor charging and discharging circuit comprises an input power supply 28V_IN, a switch, an energy storage capacitor C1, an output node VCC_R and a ground end GND. The 28V_IN is connected to one end of the switch, the other end of the switch is connected to VCC_R, VCC_R is connected to one end of the energy storage capacitor C1, and the other end of C1 is grounded (GND).

[0114] ​​Wherein, the switch is a MOS tube or a relay. In the embodiment, the switch is a MOS tube. Normal state: 28V_IN is not input, the switch is off, and there is no destroy voltage.

[0115] Destroy state: 28V_IN is input, the switch is closed, 28V is applied to the capacitor, and then the Flash is destroyed.

[0116] The destroy voltage of the application supports 16V-32V (typical value 28V), and the destroy voltage amplitude can be modified according to actual conditions. The hard destroy voltage is input externally, and when the hard destroy voltage is input externally, it represents that the hard destroy starts to start. In actual conditions, the destroy voltage supply circuit also needs to balance the power supply capacity, safety, and implementation difficulty of itself, and the destroy voltage amplitude can be adjusted and controlled, which greatly reduces the difficulty of actual circuit implementation.

[0117] In order to solve the problem of insufficient front-end power supply caused by the destroy voltage for a period of time, the destroy voltage is not directly delivered to the Flash chip, but the capacitor charging and discharging mode is adopted to periodically destroy. In the destruction process, the capacitor releases the voltage to deliver the hard destroy voltage to the Flash chip under the control of the single-chip microcomputer, so as to ensure that the hard destroy is more thorough.

[0118] In actual use, the hard destroy circuit is separated from the normal power supply circuit: the hard destroy circuit is separated, the risk of hard destroy mis-triggering is reduced, and other devices and circuits except the Flash chip are also protected. After the hard destroy is executed, the normal Flash chip is replaced, and the solid state disk can be used again, thereby saving the cost.

[0119] In order to ensure the safety of data, the hard destroy technology provides a relatively simple and efficient data destroy method, and the specific method is that when the destroy voltage input by the external input is received, the destroy voltage is output to the Flash chip through the single-chip microcomputer and the MOS tube switch circuit control, and the whole solid state disk is not damaged, and the Flash chip can be used again after being replaced, so that the application scene is wider.

[0120] The hard destroy test is carried out, and the following is the effect diagram of the Flash chip destruction under different destroy voltage inputs Figure 5 、 Figure 6 and Figure 7 , which correspond to 20V, 25V and 28V destroy voltage respectively; under the destroy voltage of 20V, 25V and 28V, the Flash chip is destroyed, so that each Flash chip is fully destroyed, and there is no risk of data recovery.

[0121] It should be noted that the processor in the present application can be an integrated circuit chip with signal processing capability. The processor can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; or can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. It can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor can be a microprocessor or the processor can also be any conventional processor or the like.

[0122] The above merely provides the embodiments of the present application but does not serve to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings.

Claims

1. A device for rapid hard disk destruction of a solid-state drive, characterized in that, include: The signal receiving module is used to receive the externally input destruction voltage signal; A microcontroller control module, connected to the signal receiving module, is used to generate periodic square wave control signals; The MOS transistor switching module is connected to the microcontroller control module and is used to switch between the normal power supply circuit and the destruction circuit according to the square wave control signal. A capacitor charging and discharging module is connected to the MOS transistor switching module and is used to generate pulse voltage and output it to the Flash chip; the MOS transistor switching module includes a combination circuit composed of NMOS transistors and PMOS transistors, which is used to completely isolate the connection between the normal power supply circuit and the Flash chip in the destruction state. The capacitor charging and discharging module includes multiple energy storage capacitors connected in parallel. The capacitance of a single capacitor is 0.1-10μF, the rated voltage is 63-100V, it is designed with a 50% derating, and the total capacitance is not less than 100μF. Specifically, the steps include the following: The signal receiving module receives the destruction command, and the microcontroller controls the MOS transistor switching module and the capacitor charging and discharging module. The surface temperature of the Flash chip monitored by the temperature sensor and the real-time current value of the Flash power supply pin fed back by the current detection circuit are collected in real time. The microcontroller firmware embeds a multi-level state machine that dynamically adjusts the destruction parameters based on the collected temperature and current values. The destruction parameters include voltage, pulse duty cycle, and stage duration. The multi-level state machine control performs multi-level destruction, including a preheating and pre-damage stage, a main destruction stage, an enhanced destruction stage, and a cooling and reset stage; The preheating and pre-damage stages use low-voltage pulses to gradually damage the internal structure of the Flash chip. The main destruction stage uses standard parameters to ensure the physical destruction of the core data area. The enhanced destruction stage is automatically triggered when the current value is higher than the threshold after the main destruction stage, applying higher energy to stubborn areas. The cooling and reset stage stops pulse output and performs system self-test to generate a destruction report. Furthermore, the dynamic adjustment of the destruction parameters specifically refers to: During the preheating and pre-damage phase, the voltage is 20V and can be dynamically adjusted in 2V steps via external input. The square wave duty cycle is 1:5, the number of pulses is 5, and the interval is 100ms. During the main destruction phase, the voltage is 28V, the square wave duty cycle is 1:10, and the pulse continues until the current detection value is below 10mA. During the enhanced destruction phase, the voltage is 32V, the square wave duty cycle is 1:15, the number of pulses is 3, and the interval is 50ms.

2. A system for rapid hard disk destruction of a solid-state drive, characterized in that, include: The solid-state drive rapid hard disk destruction device as described in claim 1; A power management unit is used to provide an adjustable voltage input to the destruction device, with a voltage range of 16V-32V. The monitoring module is used to detect voltage fluctuations and Flash chip status in real time during the destruction process, and to feed back abnormal signals to the microcontroller control module. The communication interface supports remotely triggering destruction commands or receiving destruction status information.

3. The solid-state drive rapid hard disk destruction system according to claims 2, characterized in that: The communication interface supports wireless communication protocols, including Wi-Fi, Bluetooth, or 5G, for data interaction with cloud servers or mobile terminals.

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