Thermal resistance network model construction method for multi-heat source package junction temperature prediction

Abstract

The present invention discloses a method for constructing a thermal resistance network model for predicting the junction temperature of a multi-heat source package, which belongs to the field of chip packaging technology. The method includes: defining the highest temperature node of the contact surface between the th heat source and the TSV adapter plate as the th node, defining the highest temperature node of the contact surface between the th heat source and the metal cover as the th node, and defining the ambient temperature node as the th node; constructing a system thermal conductivity matrix of dimensions, and setting the initial value of each element to 0; calculating the thermal resistance of each heat source, and updating the system thermal conductivity matrix for the first time; calculating the diffusion coupling thermal conductivity matrix of the heat source, and updating the system thermal conductivity matrix for the second time; calculating the diagonal elements of the system thermal conductivity matrix after the second update and updating the system thermal conductivity matrix, at which point the update of the system thermal conductivity matrix is ​​completed, that is, the construction of the thermal resistance network model is completed. This method improves the prediction accuracy of the junction temperature of a multi-heat source package.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package. Background Art

[0002] In recent years, with the scaling of integrated circuit (IC) process technology and increasing design complexity, the development of monolithic systems-on-chip (SoCs) has been unable to keep pace with the semiconductor scaling trend predicted by Moore's Law. To address the challenges of high integration and low power consumption in the era of artificial intelligence and high-performance computing, heterogeneous chiplet integration systems have emerged. These systems break down larger monolithic SoCs (System-on-Chip) into smaller chiplets and integrate them into a single system. This approach offers advantages such as intellectual property reuse, short production cycles, and reduced risk and cost. Advanced packaging such as CoWoS (Coupling on Wo-on-Solid) and InFO (Information on Form Factor) are promising examples. CoWoS is a multi-wafer, wafer-level integration system based on a through-silicon via (Through-Silicon Via) interposer. CoWoS packaging technology integrates multiple chiplets on a silicon interposer, achieving high scalability, low power consumption, and high performance. However, due to the increased system integration and thermal interactions between the chiplets, the package junction temperature rises dramatically, gradually approaching its tolerable limit. Excessively high temperatures can negatively impact system performance and reliability. Therefore, accurate simulation and prediction of the junction temperature of multi-heat source packages such as CoWoS is the key to ensuring system reliability and service life.

[0003] Traditional numerical methods for thermal analysis of complex packaging systems include the boundary element method, the finite element method, and the finite difference method. These methods generate a large number of unknown temperature nodes by meshing the system to determine the thermal distribution, resulting in high computational cost and low efficiency. For predicting the junction temperature of complex packaging systems, the traditional approach to constructing a thermal resistance network model is to simulate a dual-resistance model under a standard test environment. This model, defined in the JESD15-3 standard document, has only one internal temperature node and is no longer suitable for predicting the junction temperature of packages with multiple heat sources, such as CoWoS. Summary of the Invention

[0004] In order to solve the problems in the prior art, the present invention provides a method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package.

[0005] The technical solutions of the present invention are as follows:

[0006] The present invention discloses a method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package. The multi-heat source package includes an organic carrier board, solder ball bumps and a filling layer, a TSV adapter board, a heat source group, a metal cover, a thermal interface material of a heat sink, and a heat sink plate, which are arranged in sequence from bottom to top. The heat source group includes multiple heat sources arranged horizontally on the upper surface of the TSV adapter board. The heat dissipation path of the multi-heat source package includes a first path in which the heat source is conducted in a vertical downward direction, and a second path in which the heat source is conducted in a vertical upward direction. The method includes the following steps:

[0007] S1: Define The highest temperature node on the contact surface between the heat source and the TSV adapter board is Node, define the The highest temperature node of the contact surface between the heat source and the metal cover is Node, define the ambient temperature node as the Node, where is the number of heat sources in the heat source group;

[0008] S2: Build dimensional system thermal conductivity matrix, and set the initial value of each element of the system thermal conductivity matrix to 0;

[0009] S3: Calculate the thermal resistance of each heat source and update the system thermal conductivity matrix;

[0010] S4: Calculate the diffusion-coupled thermal conductivity matrix of the heat source in the first path direction and the diffusion-coupled thermal conductivity matrix of the heat source in the second path direction, and then update the system thermal conductivity matrix updated in S3;

[0011] S5: Calculate the diagonal elements of the system thermal conductivity matrix updated in S4, and update the system thermal conductivity matrix again. At this time, the update of the system thermal conductivity matrix is ​​completed, that is, the construction of the thermal resistance network model is completed.

[0012] Compared with the prior art, the present invention has the following beneficial effects:

[0013] (1) The thermal resistance network model for multi-heat source package junction temperature prediction of the present invention fully considers the thermal diffusion effect of the heat source and the thermal interaction between the heat sources, and abstracts these thermal effects into specific thermal resistances with clear physical meanings during the calculation process, thereby improving the accuracy of junction temperature prediction;

[0014] (2) For composite components such as TSV adapters, micro-bumps and filling layers, solder ball bumps and filling layers, and organic substrates, orthotropic equivalent thermal conductivity calculations were performed, and the anisotropy of material heat transfer was considered in the construction of the thermal resistance network model of multi-heat source packaging;

[0015] (3) In the process of constructing the thermal resistance network model for multi-heat source package junction temperature prediction, the inverse relationship between the heat source diffusion coupling thermal conductivity matrix and the heat source thermal effect matrix is ​​used to obtain the target thermal resistance value with very little calculation amount, and the obtained thermal resistance value is independent of power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 2 is a front view of the CoWoS package according to this embodiment;

[0017] Figure 2 2. FIG. 1 is a top view of the CoWoS package of this embodiment;

[0018] Figure 3 1 is a top view of the TSV array in the TSV adapter board in this embodiment;

[0019] Figure 4 1 is a front view of the TSV array in the TSV adapter board in this embodiment;

[0020] Figure 5 Graphs showing the temperature distribution when power consumption of 100W and 20W is applied to the two core particles in this embodiment respectively.

[0021] Figure numerals: 1. Radiator plate, 2. Thermal interface material of radiator, 3. Metal cover, 4. Thermal interface material of core one, 5. Silicon-based bare chip of core one, 6. Micro-bumps and filling layer of core one, 7. Thermal interface material of core two, 8. Silicon-based bare chip of core two, 9. Micro-bumps and filling layer of core two, 10. TSV adapter board, 11. Solder ball bumps and filling layer, 12. Organic carrier board, 13. TSV unit. DETAILED DESCRIPTION

[0022] The present invention will be further described and illustrated below in conjunction with specific embodiments. The embodiments are merely illustrative of the present disclosure and do not limit its scope. The technical features of the various embodiments of the present invention may be combined accordingly, provided that there is no conflict between them.

[0023] The present invention provides a method for constructing a thermal resistance network model for predicting the junction temperature of a multi-heat source package. The method considers the thermal diffusion effect of the heat source and the thermal interaction between multiple heat sources, and abstracts these thermal effects into thermal resistances with clear physical meanings, thereby improving the accuracy of junction temperature prediction.

[0024] Any package containing multiple heat sources within the same system falls within the scope of multi-heat source packaging. The heat sources within the package refer to all heat-generating components, including but not limited to active heat-generating devices such as bare chips and passive heat-generating devices such as resistors, capacitors, and inductors.

[0025] In one embodiment of the present invention, the multi-heat source package in the thermal resistance network model construction method for multi-heat source package junction temperature prediction provided by the present invention is a CoWoS package, and the heat source is a heat-generating core particle. The CoWoS package includes multiple core particles and two main heat dissipation paths; each core particle is composed of three thin layers of micro-bumps and filling layers, silicon-based bare chips and core particle thermal interface materials stacked in sequence from bottom to top; the first heat dissipation path is composed of three thin layers of TSV adapter plate, solder ball bumps and filling layers, and organic carrier board stacked in sequence from top to bottom; the second heat dissipation path is composed of three thin layers of radiator plate, radiator thermal interface material and metal cover stacked in sequence from top to bottom, and the TSV adapter plate is composed of silicon and copper through-holes covered by a silicon dioxide insulating layer. The thermal resistance network model construction method includes the following steps:

[0026] 1) Define temperature nodes and core particles The node with the highest temperature on the contact surface of the first heat dissipation path is recorded as node , defining core particles The node with the highest temperature on the contact surface of the second heat dissipation path is recorded as node , define the ambient temperature node as ,in is the number of core particles.

[0027] 2) Build dimensional system thermal conductivity matrix , system thermal conductivity matrix The initial value of each element of is set to 0. Representation node With node Thermal conductivity between, thermal conductivity is the reciprocal of thermal resistance; .

[0028] 3) Obtain the thickness of each core component in the heat flow path direction, the length and width of the component in the heat flow path cross section, and the thermal conductivity of the component's constituent materials; wherein the core components include the microbumps and filler layer, the silicon-based bare die, and the thermal interface material of the core.

[0029] 4) Calculate the thermal resistance of the three thin layers of the micro-bump and the filling layer, silicon-based bare chip, and thermal interface material of each core particle according to the one-dimensional thermal conduction resistance calculation formula, and add them together using the thermal resistance series formula to get the thermal resistance of each core particle, take the reciprocal to get the thermal conductivity of each core particle, and divide the core particles into Take the inverse of the thermal conductivity and write it into the system thermal conductivity matrix of and middle.

[0030] The calculation formula for one-dimensional heat conduction thermal resistance is shown as follows:

[0031] ;

[0032] in, represents the one-dimensional thermal conductivity resistance of the core component, Indicates the thickness of the component in the direction of heat flow path, represents the thermal conductivity of the component's constituent materials, Indicates the cross-sectional area of ​​the heat flow path of the component in the heat flow path section.

[0033] 5) Obtain the thickness of the heat sink plate, the heat sink's thermal interface material, and the metal cover in the direction of the second heat dissipation path, the length and width of the second heat dissipation path cross section, and the thermal conductivity of the constituent materials. Then, obtain the thickness of the TSV adapter plate, the solder ball bump and filler layer, and the organic substrate in the direction of the first heat dissipation path, as well as the length and width of the first heat dissipation path cross section. Calculate the thermal conductivity of the constituent materials of the TSV adapter plate, the solder ball bump and filler layer, and the organic substrate. The calculation formula for calculating the thermal conductivity of the constituent materials of the TSV adapter plate, the solder ball bump and filler layer, and the organic substrate is:

[0034] ;

[0035] ;

[0036] in, Indicates the thermal conductivity of the TSV adapter board, solder ball bumps and filling layer or organic substrate along the first heat dissipation path; Indicates the thermal conductivity of the TSV adapter board, solder ball bump and filling layer or organic substrate in the direction perpendicular to the first heat dissipation path; Thermal conductivity of the composite filling material of the TSV adapter plate, solder ball bump and filling layer or organic carrier board; Thermal conductivity of the TSV adapter, solder ball bumps and filler layer or organic substrate via or bump material; It is the thermal conductivity of the insulating layer material attached to the outside of the TSV adapter board, the solder ball bump and the filling layer or the via of the organic carrier board; for example, in the TSV adapter board, the composite layer filling material, the via or bump material, and the insulating layer material attached to the outside of the via correspond to silicon, copper, and silicon dioxide, respectively; for example, in the solder ball bump and the filling layer, the composite layer filling material, the via or bump material correspond to U8410-302 material and solder, respectively, and there is no attached insulating layer; for example, in the organic carrier board, the composite layer filling material, the via or bump material correspond to BT resin and copper, respectively, and there is no attached insulating layer. The length of the TSV adapter board, solder ball bumps and filling layer or organic substrate in the first heat dissipation path section; The width of the TSV adapter board, solder ball bump and filling layer or organic substrate in the first heat dissipation path section; The diameter of the vias or bumps on the TSV adapter board, solder ball bumps and filler layer or organic substrate; The outer diameter of the insulating layer material attached to the outside of the via hole of the TSV adapter board, solder ball bump and filling layer or organic substrate. If the TSV adapter board, solder ball bump and filling layer or organic substrate does not have an insulating layer material, then ; The center distance between the TSV adapter board, solder ball bumps and the vias or bumps of the filling layer or organic substrate; The number of vias or bumps on the TSV adapter board, solder ball bumps, and filling layer or organic substrate.

[0037] 6) Calculate the self-heating coefficient of each core particle and the thermal interaction coefficient between core particles in the two heat dissipation paths according to the thermal diffusion effect calculation formula, and construct the core particle thermal effect matrix of the first heat dissipation path and the core particle thermal effect matrix of the second heat dissipation path.

[0038] Specifically, the calculation formula for the thermal diffusion effect is as follows:

[0039] ;

[0040] ;

[0041] in, The first heat dissipation path The self-heating coefficient of each core particle; 、 、 and Respectively The zeroth, first, second and third Fourier coefficients of the core particle self-heating coefficient and thermal interaction coefficient, 、 Integer index representing the Fourier series; represents the frequency of the first Fourier series term, , Indicates the length of the first path TSV adapter plate or the second path metal cover in the heat dissipation path section; For the The horizontal coordinate of the die on the plane of the first path TSV adapter plate or the second path metal cover; represents the frequency of the second Fourier series, , Indicates the width of the first path TSV adapter plate or the second path metal cover in the heat dissipation path cross section; For the The vertical coordinate of each die on the first path TSV adapter plate or the second path metal cover plane; The first heat dissipation path The core particle and the The thermal interaction coefficient of the core particles is ; For the The length of each chip in the heat dissipation path cross section; For the The horizontal coordinate of each die on the TSV adapter board or metal cover plane; For the The vertical coordinate of each die on the TSV adapter board or metal cover plane; Indicates the The width of a core particle in the cross section of the heat dissipation path.

[0042] The calculation formulas for each Fourier coefficient are shown below:

[0043] ;

[0044] ;

[0045] ;

[0046] ;

[0047] in, is the diffusion coefficient; For the The length of each chip in the heat dissipation path cross section; represents the frequency of the third Fourier series, ; Indicates the The width of a core particle in the cross section of the heat dissipation path.

[0048] When calculating the self-heating coefficient of each core particle and the thermal interaction coefficient between core particles in the first heat dissipation path, Indicates the length of the TSV adapter board in the first heat dissipation path section; Indicates the width of the TSV adapter board at the first heat dissipation path cross section; Indicates the length of the organic substrate in the first heat dissipation path section; Indicates the width of the organic substrate in the cross section of the first heat dissipation path; Indicates the thickness of the TSV adapter plate in the direction of the first heat dissipation path; Indicates the thickness of the solder ball bump and the filling layer in the direction of the first heat dissipation path; Indicates the thickness of the organic substrate in the direction of the first heat dissipation path; Indicates the thermal conductivity of the TSV adapter board along the first heat dissipation path; Indicates the thermal conductivity of the solder ball bump and the filling layer along the first heat dissipation path; Indicates the thermal conductivity of the organic substrate along the first heat dissipation path; Indicates the thermal conductivity of the TSV adapter plate in the direction perpendicular to the first heat dissipation path; Indicates the convective heat transfer coefficient on the organic carrier side. is the length of the first path TSV adapter plate in the heat dissipation path section, is the width of the first path TSV adapter plate in the heat dissipation path cross section.

[0049] When calculating the self-heating coefficient of each core particle and the thermal interaction coefficient between core particles in the second heat dissipation path, Indicates the length of the metal cover in the cross section of the second heat dissipation path; Indicates the width of the metal cover in the cross section of the second heat dissipation path; Indicates the length of the radiator plate in the second heat dissipation path section; Indicates the width of the radiator plate at the second heat dissipation path section; Indicates the thickness of the metal cover in the direction of the second heat dissipation path; Indicates the thickness of the thermal interface material of the heat sink in the direction of the second heat dissipation path; Indicates the thickness of the radiator plate in the direction of the second heat dissipation path; represents the thermal conductivity of the metal cover along the second heat dissipation path; Indicates the thermal conductivity of the heat sink's thermal interface material along the second heat dissipation path; Indicates the thermal conductivity of the radiator plate along the second heat dissipation path; Represents the thermal conductivity of the metal cover perpendicular to the second heat dissipation path, where ; Indicates the convection heat transfer coefficient on the radiator plate side. is the length of the second path metal cover in the heat dissipation path section, is the width of the second path metal cover in the heat dissipation path section.

[0050] The first heat dissipation path chip thermal effect matrix for:

[0051] ;

[0052] in, Chip in the first heat dissipation path Self-heating coefficient; Chip in the first heat dissipation path With core particles The thermal interaction coefficient is .

[0053] The second heat dissipation path chip thermal effect matrix for:

[0054] ;

[0055] in, The second heat dissipation path Self-heating coefficient; The second heat dissipation path With core particles The thermal interaction coefficient is .

[0056] Furthermore, the diffusion-coupled thermal conductivity matrix of the core particles of the first heat dissipation path for , the diffusion-coupled thermal conductivity matrix of the core particle of the second heat dissipation path for .

[0057] 7) is the diffusion-coupled thermal conductivity matrix Middle Row, No. Column element, its opposite That means core particle With core particles The coupling thermal conductivity between the first heat dissipation path will Write the system thermal conductivity matrix and Calculate the diffusion-coupled thermal conductivity matrix Middle The sum of all elements in the row is the sum of the elements in the The diffusion thermal conductivity value between the core particle and the ambient temperature node through the first path is negated and written into the system thermal conductivity matrix. and middle.

[0058] 8) is a matrix Middle Row, No. Column element, its opposite That is, core particles With core particles The coupling thermal conductivity of the second heat dissipation path between Write system thermal conductivity matrix of and Calculate the diffusion-coupled thermal conductivity matrix Middle The sum of all elements in the row is the sum of the elements in the The diffusion thermal conductivity value between the core particle and the ambient temperature node through the second path is negated and written into the system thermal conductivity matrix. and middle.

[0059] 9) Calculate the system thermal conductivity matrix The diagonal elements of the system thermal conductivity matrix No. Row diagonal elements For the The negative number of the sum of all other elements in the row, now the system thermal conductivity matrix is ​​completed The calculation of the thermal resistance network model is completed.

[0060] After completing the thermal resistance network model, the temperature of each node can be calculated according to the following formula;

[0061] ;

[0062] in, is the temperature vector, is the temperature vector No. Elements, representing nodes temperature, The value of is the ambient temperature; is the power consumption vector, is the power consumption vector No. Elements, representing nodes The heat dissipation, 、 The value of each core particle Half of the actual power consumption, The value of is 0; the temperature vector The maximum value of all elements in is the calculated package junction temperature.

[0063] like Figure 1 and Figure 2 The figure shows the structure of the CoWoS package in this embodiment. The CoWoS package structure includes a heat sink plate 1, a heat sink thermal interface material 2, a metal cover 3, a thermal interface material 4 for core 1, a silicon-based bare chip 5 for core 1, micro-bumps and a filling layer 6 for core 1, a thermal interface material 7 for core 2, a silicon-based bare chip 8 for core 2, micro-bumps and a filling layer 9 for core 2, a TSV adapter plate 10, solder ball bumps and a filling layer 11, and an organic carrier 12. The convective heat transfer coefficient of the side surface of the heat sink plate 1 is 150. The convective heat transfer coefficient of the organic carrier plate 12 side surface is 20 , and the other surface boundary conditions are set as adiabatic.

[0064] (1) Define the temperature nodes. The highest temperature node of the contact surface between chip 1 and TSV adapter board 10 is recorded as the first node, the highest temperature node of the contact surface between chip 2 and TSV adapter board 10 is recorded as the second node, the highest temperature node of the contact surface between chip 1 and metal cover 3 is recorded as the third node, the highest temperature node of the contact surface between chip 2 and metal cover 3 is recorded as the third node, and the ambient temperature node is recorded as the fourth node.

[0065] (2) Constructing a 5-dimensional system thermal conductivity matrix ,matrix The initial elements in are set to 0.

[0066] (3) The thickness of each component, the length and width of the heat flow path section, and the thermal conductivity of the constituent materials are obtained as shown in the following table:

[0067]

[0068] (4) Taking the TSV adapter plate 10 as an example, the equivalent thermal conductivity of the TSV adapter plate 10 is calculated according to the following formula:

[0069] ;

[0070] ;

[0071] =150.2, =150;

[0072] in, It represents the thermal conductivity of the heat flow path direction of the TSV adapter board 10, It represents the thermal conductivity of the TSV interposer 10 in the direction perpendicular to the heat flow path.

[0073] In this embodiment, =148W / (m·K), =401W / (m·K), =1.4W / (m·K), respectively, Figure 3 The thermal conductivity of the silicon-based filling, the copper via of the TSV unit 13, and the silicon dioxide insulating layer of the TSV unit 13 is shown; Figure 4 As shown, =0.035mm, =0.03511mm, =0.1mm, respectively represents the copper via diameter of TSV unit 13, the outer diameter of the silicon dioxide insulation layer of TSV unit 13, and the center distance of TSV unit 13; the number of TSV units 13 =5238.

[0074] Using the same method, calculate the equivalent thermal conductivity of the solder ball bump, the filling layer 11, and the organic carrier board 12:

[0075] =2.348, =0.6431;

[0076] =0.4028, =20.68;

[0077] in, Indicates the thermal conductivity of the solder ball bump and the filling layer 11 in the heat flow path direction, Indicates the thermal conductivity of the solder ball bump and the filling layer 11 in the direction perpendicular to the heat flow path; It represents the thermal conductivity of the organic substrate 12 in the heat flow path direction, It represents the thermal conductivity of the organic carrier 12 in the direction perpendicular to the heat flow path.

[0078] (5) The thermal resistance of the micro-bumps and the three thin layers of the filling layer, silicon-based bare chip, and thermal interface material in each core particle is calculated using the one-dimensional thermal conduction thermal resistance calculation formula shown below:

[0079] ;

[0080] ;

[0081] ;

[0082] ;

[0083] ;

[0084] ;

[0085] ;

[0086] in, 、 、 are the thermal resistances of the thermal interface material 4 of the core particle 1, the silicon-based bare chip 5 of the core particle 1, the micro-bumps of the core particle 1 and the filling layer 6, 、 、 They are the thermal resistances of the thermal interface material 7 of the second core, the silicon-based bare chip 8 of the second core, the micro-bumps of the second core and the filling layer 9.

[0087] The thermal conductivity of each core particle is obtained by adding the thermal resistance of each core particle assembly and taking the reciprocal:

[0088] ;

[0089] ;

[0090] in, is the thermal conductivity of core particle 1, is the thermal conductivity of core particle 2.

[0091] Will Write system thermal conductivity matrix of and In Write system thermal conductivity matrix of and middle.

[0092] (6) Calculate the self-heating coefficient of the first heat dissipation path core according to the thermal diffusion effect calculation formula 、 Thermal interaction coefficient between core particles 、 , and construct the first heat dissipation path core particle thermal effect matrix shown in the following formula :

[0093] ;

[0094] (7) Calculate the diffusion coupling thermal conductivity matrix of the first heat dissipation path core particle according to the following formula: :

[0095] ;

[0096] in, and represents the coupled thermal conductivity between chip 1 and chip 2 through the first heat dissipation path, and Write system thermal conductivity matrix of and In the matrix The value -0.0585 W / K obtained by taking the inverse of the sum of all elements in the first row is written into the system thermal conductivity matrix of and In the example, we will transform the matrix The value -0.0413 W / K obtained by taking the inverse sum of all elements in the second row is written into the system thermal conductivity matrix of and middle.

[0097] (8) According to the same method as in step (6) and step (7), the diffusion coupling thermal conductivity matrix of the second heat dissipation path core particle is obtained. :

[0098] ;

[0099] in, and represents the coupled thermal conductivity between chip 1 and chip 2 through the second heat dissipation path, and Write system thermal conductivity matrix of and In the matrix The value -0.4777 W / K obtained by taking the inverse of the sum of all elements in the first row is written into the system thermal conductivity matrix of and In the example, we will transform the matrix The value -0.3389W / K obtained by taking the inverse sum of all elements in the second row is written into the system thermal conductivity matrix of and middle.

[0100] (9) Calculate the system thermal conductivity matrix The diagonal elements of the system thermal conductivity matrix No. Row diagonal elements For the The negative number of the sum of all other elements in the row, the system thermal conductivity matrix , that is, the construction of the thermal resistance network model is completed.

[0101] ;

[0102] (10) Configure temperature vector :

[0103] ;

[0104] in 、 、 、 are the temperature values ​​of the first node, second node, third node, and fourth node respectively, and the ambient temperature is set to 293.15K.

[0105] Configuring Power Vectors :

[0106] ;

[0107] The temperature of each node is calculated according to the following formula:

[0108] ;

[0109] Calculated The maximum value among them, that is, the junction temperature of the package is calculated to be 429.19K.

[0110] After obtaining the predicted value of the junction temperature of the package, the predicted value needs to be verified to prove the rationality of the model. Figure 5 The following COMSOL simulation results show a power of 100W applied to core 1 and 20W applied to core 2. At this point, the maximum temperature of the package reached 429.386K. The relative error between the predicted and simulated values ​​is no more than 0.144%.

[0111] The present invention abstracts the thermal diffusion effect of each core particle and the thermal coupling effect between each core particle into a specific thermal resistance, thereby improving the prediction accuracy of the CoWoS package junction temperature. Compared with the finite element method, the error does not exceed 0.2%.

[0112] The above-described embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. Persons skilled in the art will readily appreciate that variations and modifications may be made without departing from the scope of the present invention, all of which fall within the scope of protection of the present invention.

Claims

1. A method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package, wherein the multi-heat source package comprises, arranged from bottom to top, an organic carrier board, a solder ball bump and filler layer, a TSV adapter board, a heat source group, a metal cover, a heat sink thermal interface material, and a heat sink plate. The heat source group comprises multiple heat sources arranged horizontally on the upper surface of the TSV adapter board. The heat dissipation path of the multi-heat source package comprises a first path in which the heat source is conducted vertically downward, and a second path in which the heat source is conducted vertically upward. The method is characterized in that: The method comprises the following steps: S1: Define The highest temperature node on the contact surface between the heat source and the TSV adapter board is Node, define the The highest temperature node of the contact surface between the heat source and the metal cover is Node, define the ambient temperature node as the Node, where is the number of heat sources in the heat source group; S2: Build dimensional system thermal conductivity matrix, and set the initial value of each element of the system thermal conductivity matrix to 0; S3: Calculate the thermal resistance of each heat source and update the system thermal conductivity matrix; S4: Calculate the diffusion-coupled thermal conductivity matrix of the heat source in the first path direction and the diffusion-coupled thermal conductivity matrix of the heat source in the second path direction, and then update the system thermal conductivity matrix updated in S3; S5: Calculate the diagonal elements of the system thermal conductivity matrix updated in S4, and update the system thermal conductivity matrix again. At this time, the update of the system thermal conductivity matrix is ​​completed, that is, the construction of the thermal resistance network model is completed; Thermal conductivity matrix of the system in S2 of Indicates the Node and The inverse of the thermal resistance between nodes, ; S4 includes: S41: Obtain the thickness of the heat sink plate, the heat sink thermal interface material, and the metal cover in the second path direction, the length and width in the second path cross section, and the thermal conductivity of the constituent materials; then obtain the thickness of the TSV adapter plate, the solder ball bump and the filling layer, and the organic carrier plate in the first path direction, and the length and width in the first path cross section; and calculate the thermal conductivity of the constituent materials of the TSV adapter plate, the solder ball bump and the filling layer, and the organic carrier plate; S42: Calculate the self-heating coefficient of each heat source in the heat dissipation path and the thermal interaction coefficient between the heat sources according to the heat diffusion effect calculation formula, and construct a thermal effect matrix of the heat sources in the first path and a thermal effect matrix of the heat sources in the second path; S43: Obtain the diffusion coupling thermal conductivity matrix of the heat source in the first path direction according to the thermal effect matrix of the heat source in the first path , according to the thermal effect matrix of the heat source in the second path, the diffusion coupling thermal conductivity matrix of the heat source in the second path direction is obtained ; S44: Write the system thermal conductivity matrix and Calculate the diffusion-coupled thermal conductivity matrix Middle The sum of all elements in the row is the sum of the elements in the The diffusion heat conductance value between the heat source and the ambient temperature node through the first path is taken as the inverse of the diffusion heat conductance value and written into the system thermal conductivity matrix. and middle; S45: Write the system thermal conductivity matrix and Calculate the diffusion-coupled thermal conductivity matrix Middle The sum of all elements in the row is the sum of the elements in the The diffusion heat conductance value between the heat source and the ambient temperature node through the second path is taken as the inverse of the diffusion heat conductance value and written into the system thermal conductivity matrix. and middle.

2. The method for constructing a thermal resistance network model for multi-heat source package junction temperature prediction according to claim 1, wherein S3 include: S31: Obtaining the thickness of each layer of material constituting each heat source in the direction of the heat dissipation path, the length and width of each layer of material in the cross section of the heat dissipation path, and the thermal conductivity of each layer of material; S32: Calculate the thermal resistance of each layer of material in each heat source according to the one-dimensional heat conduction thermal resistance calculation formula, and use the thermal resistance series formula to obtain the thermal resistance of each heat source, and then take the inverse of the thermal resistance to obtain the thermal conductivity of the heat source. Take the inverse of the thermal conductivity of each heat source and write it into the system thermal conductivity matrix and middle.

3. The method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package according to claim 2, characterized in that: The calculation formula for the one-dimensional heat conduction thermal resistance in S32 is: ； in, represents the one-dimensional thermal conduction resistance of the material constituting the heat source, Indicates the thickness of the material that makes up the heat source in the direction of the heat dissipation path. represents the thermal conductivity of the material that composes the heat source, It represents the cross-sectional area of ​​the material that makes up the heat source in the cross section of the heat dissipation path.

4. The method for constructing a thermal resistance network model for multi-heat source package junction temperature prediction according to claim 1, characterized in that: The formula for calculating the thermal conductivity of the constituent materials of the TSV adapter plate, solder ball bumps, filler layer, and organic carrier in S41 is: ； ； in, Indicates the thermal conductivity of the TSV adapter board, solder ball bumps and filling layer or organic substrate along the first path direction; Indicates the thermal conductivity of the TSV adapter, solder ball bump and filling layer or organic substrate in the first path direction perpendicular to the ground plane; Thermal conductivity of the composite filling material of the TSV adapter plate, solder ball bump and filling layer or organic carrier board; Thermal conductivity of the TSV adapter, solder ball bumps and filler layer or organic substrate via or bump material; Thermal conductivity of the insulating layer material attached to the outside of the TSV adapter board, solder ball bumps and filler layer or organic substrate vias; The length of the TSV adapter plate, solder ball bump and filling layer or organic carrier board in the first path section; The width of the TSV adapter, solder ball bump and filling layer or organic carrier in the first path cross section; The diameter of the vias or bumps on the TSV adapter board, solder ball bumps and filler layer or organic substrate; The outer diameter of the insulating layer material attached to the outside of the via hole of the TSV adapter board, solder ball bump and filling layer or organic substrate. If the TSV adapter board, solder ball bump and filling layer or organic substrate does not have an insulating layer material, then ; The center distance between the TSV adapter board, solder ball bumps and the vias or bumps of the filling layer or organic substrate; The number of vias or bumps on the TSV adapter board, solder ball bumps, and filling layer or organic substrate.

5. The method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package according to claim 1, wherein: The calculation formula for the thermal diffusion effect in S42 is: ； ； in, The first heat dissipation path The self-heating coefficient of each heat source; 、 、 and Respectively The heat comes from the zeroth, first, second and third Fourier coefficients of the heat generation coefficient and the thermal interaction coefficient, 、 Integer index representing the Fourier series; represents the frequency of the first Fourier series term, , Indicates the length of the first path TSV adapter plate or the second path metal cover in the heat dissipation path section; For the The horizontal coordinate of a heat source on the plane of the first path TSV adapter plate or the second path metal cover; represents the frequency of the second Fourier series, , Indicates the width of the first path TSV adapter plate or the second path metal cover in the heat dissipation path cross section; For the The vertical coordinate of a heat source on the plane of the first path TSV adapter plate or the second path metal cover; The first heat dissipation path The heat source and The thermal interaction coefficient of the heat source is ; For the The length of a heat source in the cross section of the heat dissipation path; For the The horizontal coordinate of the heat source on the TSV adapter plate or metal cover plane; For the The vertical coordinate of the heat source on the plane of the TSV adapter plate or metal cover; Indicates the The width of a heat source in the cross section of the heat dissipation path.

6. The method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package according to claim 5, characterized in that: The calculation formulas for Fourier coefficients are: ； ； ； ； in, is the diffusion coefficient; represents the frequency of the third Fourier series, ; For the The length of a heat source in the cross section of the heat dissipation path; Indicates the The width of a heat source in the cross section of the heat dissipation path; When calculating the self-heating coefficient of each heat source in the first path and the thermal interaction coefficient between heat sources, Indicates the length of the TSV adapter plate in the first path section; Indicates the width of the TSV adapter plate in the first path cross section; represents the length of the organic carrier plate in the first path section; represents the width of the organic carrier in the cross section of the first path; represents the thickness of the TSV adapter plate in the direction of the first path; Indicates the thickness of the solder ball bump and the filling layer in the first path direction; The thickness of the organic carrier plate in the direction of the first path is represented by ∠; represents the thermal conductivity of the TSV adapter plate along the first path direction; Indicates the thermal conductivity of the solder ball bump and the filling layer along the first path direction; represents the thermal conductivity of the organic substrate along the first path; represents the thermal conductivity of the TSV adapter plate in the direction perpendicular to the first path; Indicates the convective heat transfer coefficient on one side of the organic carrier; When calculating the heat generation coefficient of each heat source and the thermal interaction coefficient between heat sources in the second path, Indicates the length of the metal cover in the second path section; Indicates the width of the metal cover in the second path section; Indicates the length of the radiator plate in the second path section; Indicates the width of the radiator plate in the second path section; represents the thickness of the metal cover in the direction of the second path; represents the thickness of the thermal interface material of the heat sink in the second path direction; represents the thickness of the radiator plate in the direction of the second path; represents the thermal conductivity of the metal cover along the second path direction; represents the thermal conductivity of the thermal interface material of the heat sink along the second path direction; represents the thermal conductivity of the radiator plate along the second path direction; represents the thermal conductivity of the metal cover perpendicular to the second path, where ; Indicates the convection heat transfer coefficient on one side of the radiator plate.

7. The method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package according to claim 5, characterized in that: The first path heat source thermal effect matrix in S42 for: ； in, The first path The self-heating coefficient of each heat source; The first path The heat source and The thermal interaction coefficient of the heat source is ; The second path heat source thermal effect matrix in S42 for: ； in, For the second path The self-heating coefficient of each heat source; For the second path The heat source and The thermal interaction coefficient of the heat source is ; Diffusion coupled thermal conductivity matrix of the heat source in the first path direction in S42 for , the diffusion coupling thermal conductivity matrix of the heat source in the second path direction for .

8. The method for constructing a thermal resistance network model for predicting junction temperature of a multi-heat source package according to claim 1, characterized in that: In S5, the diagonal elements of the system thermal conductivity matrix updated in S4 are calculated, and the system thermal conductivity matrix is ​​updated again, including: The first Except the first Add up all the elements except the diagonal elements in the row, and the opposite of the sum is the The calculated diagonal elements are written into the system thermal conductivity matrix middle.

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