Superconducting quantum chip structure and superconducting quantum computer

Abstract

The invention relates to the technical field of superconducting quantum, and discloses a superconducting quantum chip structure and a superconducting quantum computer, the superconducting quantum chip structure comprises a superconducting quantum chip and a packaging sample box, a carrier plate of the packaging sample box is provided with a signal separation device, a first signal line and a second signal line; the signal separation device is used for receiving the combined control signal and separating the combined control signal to generate a first control signal and a second control signal; the first input end of the first signal line is electrically connected with the output end of the signal separation device, and the first output end of the first signal line is electrically connected with the superconducting quantum chip, so that a first control signal is transmitted to a first control line on the superconducting quantum chip; the second input end of the second signal line is electrically connected with the output end of the signal separation device, and the second output end of the second signal line is electrically connected with the superconducting quantum chip, so that a second control signal is transmitted to a second control line of the bit. The bit and the control line are in the same horizontal plane, so that the processing difficulty can be reduced, and the yield is improved.

Description

Technical Field

[0001] The present application relates to the field of superconducting quantum technology, and in particular to a superconducting quantum chip structure and a superconducting quantum computer. Background Art

[0002] Superconducting quantum chips are the core components of superconducting quantum computers, enabling the storage, manipulation, and access of quantum bits (qubits). As the number of bits on a superconducting quantum chip increases, the circuitry used in the dilution refrigerator gradually increases. Since the XY and Z control lines of a superconducting qubit have similar functions and paths, exploring ways to merge the XY and Z control lines of a superconducting qubit has important practical implications. Merging the XY and Z control lines of a superconducting qubit can significantly increase the number of bits that can be placed within the dilution refrigerator, reducing the cost of the superconducting quantum computer.

[0003] Currently, when merging the XY and Z control lines, the XY and Z control signals from the measurement and control system are combined into a single line (the XYZ signal). A high-frequency line inside the refrigerator transmits the signal to a corresponding line on a terminal on the sample box's carrier board. Once inside the sample box, a duplexer and bandpass filter are used to split the original signal into two. These duplexers and bandpass filters are typically built into the bit chip, which introduces noise and heat. To minimize the effects of heat generation, the combined XYZ control signal line is typically used in flip-chip superconducting quantum chips, placing the XYZ control line on the top plate and the bit chip on the bottom plate. This XYZ combined line solution requires significant modifications to the flat-pack chip structure. To ensure coupling strength, this places high demands on the distance between the top and bottom plates of the flip-chip chip and the height of the indium pillars, complicating chip fabrication and reducing chip yield.

[0004] Therefore, how to solve the above technical problems should be the focus of those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a superconducting quantum chip structure and a superconducting quantum computer to eliminate the deviation in the relative capacitance of the device caused by the uneven height of the indium pillar, reduce the difficulty of processing and manufacturing, and improve the yield; and can use a superconducting quantum chip in a planar package.

[0006] To solve the above technical problems, the present application provides a superconducting quantum chip structure, comprising:

[0007] A superconducting quantum chip and a packaged sample box, wherein the superconducting quantum chip is packaged inside the packaged sample box, and a signal separation device, a first signal circuit, and a second signal circuit are provided on a carrier board of the packaged sample box;

[0008] The signal separation device is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0009] The first input end of the first signal circuit is electrically connected to the output end of the signal separation device, and the first output end of the first signal circuit is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of the bit on the superconducting quantum chip;

[0010] The second input end of the second signal line is electrically connected to the output end of the signal separation device, and the second output end of the second signal line is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of the bit; the first signal line and the second signal line are at the same horizontal plane as the bit.

[0011] As an implementable embodiment, the signal separation device includes a first duplexer or a power splitter.

[0012] As an implementable embodiment, the first signal line includes a first filter and / or a first attenuator.

[0013] As an implementable embodiment, the second signal line includes a second filter and / or a second attenuator.

[0014] As an implementable embodiment, it also includes:

[0015] a third attenuator located between the signal separation device and the first input end of the first signal line; and / or,

[0016] a fourth attenuator located between the signal separation component and the second input end of the second signal line.

[0017] As an implementable embodiment, it also includes:

[0018] The measurement and control device is electrically connected to the input end of the signal separation device and is used to generate a combined control signal.

[0019] As an implementable embodiment, the measurement and control device includes:

[0020] a first digital-to-analog converter, configured to generate a DC signal and a low-frequency microwave signal;

[0021] a synthesizer connected to the first digital-to-analog converter, configured to receive the DC signal and the low-frequency microwave signal and synthesize the DC signal and the low-frequency microwave signal into a bit frequency adjustment signal;

[0022] a second digital-to-analog converter, configured to generate an in-phase component signal and a quadrature component signal;

[0023] a signal mixer connected to the second digital-to-analog converter, configured to receive the phase component signal and the quadrature component signal and generate a bit driving signal;

[0024] The second duplexer connected to the signal mixer and the synthesizer respectively is used to combine the bit frequency adjustment signal and the bit driving signal in a non-mixing and non-interfering manner to form the combined control signal.

[0025] As an implementable embodiment, it also includes:

[0026] a fifth attenuator, wherein a first end of the fifth attenuator is connected to the second duplexer, and a second end of the fifth attenuator is connected to the combiner.

[0027] As an implementation method, the first output end of the first signal line is connected to the pin of the superconducting quantum chip by wedge bonding; and / or,

[0028] The second output end of the second signal line is connected to a pin of the superconducting quantum chip through wedge bonding.

[0029] The present application also provides a superconducting quantum computer, comprising any of the above-mentioned superconducting quantum chip structures.

[0030] A superconducting quantum chip structure provided by the present application includes: a superconducting quantum chip and a packaged sample box, wherein the superconducting quantum chip is packaged inside the packaged sample box, and a signal separation device, a first signal line, and a second signal line are provided on a carrier board of the packaged sample box; the signal separation device is used to receive a combined control signal and separate the combined control signal to generate a first control signal and a second control signal; a first input end of the first signal line is electrically connected to an output end of the signal separation device, and a first output end of the first signal line is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to a first control line of a bit on the superconducting quantum chip; a second input end of the second signal line is electrically connected to the output end of the signal separation device, and a second output end of the second signal line is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of the bit; the first signal line and the second signal line are on the same horizontal plane as the bit.

[0031] It can be seen that the superconducting quantum chip structure in the present application includes a superconducting quantum chip and a packaging sample box for packaging the superconducting quantum chip, the packaging sample box includes a carrier, a signal separation device, a first signal line and a second signal line are provided on the carrier, and the signal separation device separates the combined control signal into a first control signal and a second control signal. The first control signal enters the first signal line from the first input end of the first signal line, and then enters the first control line of the bit on the superconducting quantum chip from the first output end of the first signal line. The second control signal enters the second signal line from the second input end of the second signal line, and then enters the second control line of the bit on the superconducting quantum chip from the second output end of the second signal line. Therefore, the present application realizes the separation of the first control signal and the second control signal on a carrier on a packaging sample box, without the need to modify the design scheme of the current mainstream planar packaging type superconducting quantum chip, and can be used on a planar packaged superconducting quantum chip. In addition, the bit of the superconducting quantum chip in the present application is on the same horizontal plane as the first signal line and the second signal line, which can eliminate the deviation of the relative capacitance of the device caused by the uneven height of the indium column, reduce the difficulty of processing and manufacturing, and improve the yield.

[0032] In addition, the present application also provides a superconducting quantum computer with the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 Schematic diagram of the structure of a superconducting quantum chip packaged by flip-chip soldering in the prior art;

[0035] Figure 2 A schematic diagram of a superconducting quantum chip structure provided in an embodiment of the present application Figure 1 ;

[0036] Figure 3 A schematic diagram of a superconducting quantum chip structure provided in an embodiment of the present application Figure 2 ;

[0037] Figure 4 A schematic diagram of a superconducting quantum chip structure provided in an embodiment of the present application Figure 3 ;

[0038] Figure 5 A schematic diagram of a superconducting quantum chip structure provided in an embodiment of the present application Figure 4 ;

[0039] Figure 6 A schematic diagram of a superconducting quantum chip structure provided in an embodiment of the present application Figure 5 ;

[0040] In the figure, 1, bottom film, 2, top film, 3, bit, 4, XYZ control line, 5, indium column, 6, signal separation device, 7, first signal line, 8, second signal line, 9, packaged sample box, 10, third attenuator, 11, fourth attenuator, 12, first digital-to-analog converter, 13, synthesizer, 14, second digital-to-analog converter, 15, signal mixer, 16, second duplexer, 17, fifth attenuator, 71, first filter, 72, first attenuator, 81, second filter, 82, second attenuator. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the embodiments described are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present application.

[0042] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0043] As mentioned in the background technology section, Figure 1 Currently, XYZ control signal merging is commonly used in flip-chip superconducting quantum chips, with the XYZ control lines 4 placed on the top plate 2 and the bits 3 on the bottom plate 1. This XYZ merging scheme requires significant modifications to the flat-package chip structure. Considering coupling strength, this places high demands on the distance between the top and bottom plates of the flip-chip chip and the height of the indium pillars 5, making the chip structure complex to manufacture and resulting in relatively low chip yield.

[0044] In view of this, this application provides a superconducting quantum chip structure, please refer to Figure 2 , which may include:

[0045] A superconducting quantum chip and a packaged sample box 9, wherein the superconducting quantum chip is packaged inside the packaged sample box 9, and a signal separation device 6, a first signal line 7, and a second signal line 8 are provided on a carrier board of the packaged sample box 9;

[0046] The signal separation device 6 is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0047] The first input end of the first signal line 7 is electrically connected to the output end of the signal separation device 6, and the first output end of the first signal line 7 is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of bit 3 on the superconducting quantum chip;

[0048] The second input end of the second signal line 8 is electrically connected to the output end of the signal separation device 6, and the second output end of the second signal line 8 is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of bit 3; the first signal line 7 and the second signal line 8 are at the same horizontal plane as bit 3.

[0049] The combined control signal may be an XYZ control signal. The first control signal may be an XY control signal, and the second control signal may be a Z control signal. Accordingly, the first control line is an XY control line, and the second control line is a Z control line.

[0050] The first signal line 7 and the second signal line 8 are on the same level as the bit 3 .

[0051] The XY control signal is typically a high-frequency signal, typically around 5 GHz, which falls within the microwave band. It acts on superconducting qubit 3 via capacitive coupling, primarily enabling rotation of qubit 3 and, in turn, various quantum logic gates. It is a key signal for implementing complex operations in quantum computing. For example, when performing operations such as flipping the state of qubit 3 or executing a quantum gate, precise control of the XY control signal's frequency, amplitude, and phase is required to ensure that qubit 3 evolves as expected.

[0052] The Z control signal is typically a low-frequency signal, primarily used to adjust the frequency of qubit 3. By inductively coupling to a superconducting quantum interference device (SQUID) in qubit 3, the SQUID's magnetic flux is biased, thereby changing the equivalent inductance of qubit 3 and ultimately adjusting the frequency of qubit 3. This frequency adjustment plays a crucial role in qubit 3's initialization, state reading, and interaction with other qubits 3. It helps precisely control the evolution of qubit 3, reduces crosstalk between qubits 3, and improves the accuracy and stability of quantum computing.

[0053] It should be noted that, in this embodiment, there is no limitation on the type of the signal separation device 6 , as long as it can separate the combined control signal into the first control signal and the second control line signal.

[0054] As an implementation method, the signal separation device 6 may include a first duplexer. The first duplexer has a filtering function and can suppress out-of-band interference signals.

[0055] A first duplexer is a device used for wireless communications and signal processing, primarily for simultaneously transmitting and receiving signals over the same transmission medium. Its function is to isolate the transmit and receive signals, ensuring both functions operate simultaneously and preventing the local transmitter's transmitted signal from reaching the receiver.

[0056] As another possible implementation, the signal separation device 6 may include a power divider.

[0057] A power divider, or power splitter, is a device that splits one input signal into two or more outputs of equal or unequal energy. A power divider typically consists of an input port, a distribution network, and multiple output ports.

[0058] The first signal line 7 and the second signal line 8 are two independent lines. The first signal line 7 and the second signal line 8 are split on the packaging sample box 9, which can save space for the superconducting quantum chip, simplify the design and processing complexity of the superconducting quantum chip, and reduce noise caused by heat.

[0059] The first output end of the first signal line 7 is electrically connected to the pin of the superconducting quantum chip. In this application, there is no limitation on the manner in which the first output end of the first signal line 7 is electrically connected to the pin of the superconducting quantum chip, as long as electrical connection can be achieved.

[0060] The second output end of the second signal line 8 is electrically connected to the pin of the superconducting quantum chip. In this application, there is no limitation on the manner in which the second output end of the second signal line 8 is electrically connected to the pin of the superconducting quantum chip, as long as electrical connection can be achieved.

[0061] There are two terminals on the carrier of the packaged sample box 9, which are called the first terminal and the second terminal respectively. The first terminal corresponds to the first signal line 7, and the second terminal corresponds to the second signal line 8. The signal separation device 6 is electrically connected to the two terminals respectively. The first control signal enters the first signal line 7 through the first terminal, and then is transmitted to the first control line of bit 3 on the superconducting quantum chip. The second control signal enters the second signal line 8 through the second terminal, and then is transmitted to the second control line of bit 3 on the superconducting quantum chip, thereby regulating bit 3.

[0062] In this embodiment, the first signal line 7, the second signal line 8, and the circuit portion where the bit 3 on the superconducting quantum chip is located are low-temperature circuits and are inside the refrigerator.

[0063] In this embodiment, the superconducting quantum chip structure includes a superconducting quantum chip and a packaging sample box 9 for packaging the superconducting quantum chip. The packaging sample box 9 includes a carrier board, on which a signal separation device 6, a first signal line 7, and a second signal line 8 are provided. The signal separation device 6 separates the combined control signal into a first control signal and a second control signal. The first control signal enters the first signal line 7 from the first input end of the first signal line 7, and then enters the first control line of the bit 3 on the superconducting quantum chip from the first output end of the first signal line 7. The second control signal enters the second signal line 8 from the second input end of the second signal line 8, and then enters the second control line of the bit 3 on the superconducting quantum chip from the second output end of the second signal line 8. Therefore, the present application realizes the separation of the first control signal and the second control signal on a carrier board of a packaging sample box 9, without the need to modify the design scheme of the current mainstream planar packaging type superconducting quantum chip, and can be used on a planar packaged superconducting quantum chip. In addition, the bit 3 and the control line of the superconducting quantum chip in the present application are on the same horizontal plane, which can eliminate the deviation of the relative capacitance of the device caused by the uneven height of the indium column, reduce the difficulty of processing and manufacturing, and improve the yield. In addition, in this embodiment, the interference between the separated first control signal and the second control signal is relatively small.

[0064] The solution of this embodiment uses only one microwave line of a dilution refrigerator to transmit the XY control signal and Z control signal of the superconducting quantum bit 3 to the superconducting quantum chip. The only cost is an increase in the number of terminals on the packaging sample box 9 on the superconducting quantum chip.

[0065] Please refer to Figure 3 Based on the above embodiments, in one embodiment of the present application, the superconducting quantum chip structure includes:

[0066] A superconducting quantum chip and a packaged sample box 9, wherein the superconducting quantum chip is packaged inside the packaged sample box 9, and a signal separation device 6, a first signal line 7, and a second signal line 8 are provided on a carrier board of the packaged sample box 9;

[0067] The signal separation device 6 is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0068] The first input end of the first signal line 7 is electrically connected to the output end of the signal separation device 6, and the first output end of the first signal line 7 is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of bit 3 on the superconducting quantum chip;

[0069] The second input end of the second signal line 8 is electrically connected to the output end of the signal separation device 6, and the second output end of the second signal line 8 is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of bit 3;

[0070] The first signal line 7 includes a first filter 71 and / or a first attenuator 72 ; the second signal line 8 includes a second filter 81 and / or a second attenuator 82 .

[0071] There are three configurations of components on the first signal line 7. The first configuration is that the first filter 71 and the first attenuator 72 are both provided on the first signal line 7. The second configuration is that the first filter 71 is provided on the first signal line 7 but the first attenuator 72 is not provided. The third configuration is that the first attenuator 72 is provided on the first signal line 7 but the first filter 71 is not provided.

[0072] There are three configurations of components on the second signal line 8. The first configuration is that the second signal line 8 is provided with both a second filter 81 and a second attenuator 82. The second configuration is that the second signal line 8 is provided with a second filter 81 but not a second attenuator 82. The third configuration is that the second signal line 8 is provided with a second attenuator 82 but not a second filter 81.

[0073] The first filter 71 can filter the first control signal entering the first signal line 7, suppress unnecessary interference signals, and improve the quality and reliability of the first control signal.

[0074] The first attenuator 72 can reduce the amplitude of the first control signal entering the first signal line 7 according to a certain ratio, reducing the amplitude of the first control signal to an appropriate level; it can also attenuate the first control signal, reduce noise and interference in the first control signal, improve the quality of the first control signal, and enhance the detectability and reliability of the first control signal.

[0075] The second filter 81 can filter the second control signal entering the second signal line 8, suppress unnecessary interference signals, and improve the quality and reliability of the second control signal.

[0076] The second attenuator 82 can reduce the amplitude of the second control signal entering the second signal line 8 according to a certain ratio, reducing the amplitude of the second control signal to an appropriate level; it can also attenuate the second control signal, reduce noise and interference in the second control signal, improve the quality of the second control signal, and enhance the detectability and reliability of the second control signal.

[0077] The first filter 71, the first attenuator 72, the second filter 81, and the second attenuator 82 can be very small, within a few hundred nanometers, and occupy a small area on the carrier of the packaged sample box 9, thereby making the carrier relatively small and having a more reasonable design size.

[0078] It should be noted that, in this embodiment, there is no limitation on the arrangement of the first filter 71 , the first attenuator 72 , the second filter 81 and the second attenuator 82 on the carrier board, and they can be selected at will.

[0079] As an implementable embodiment, the first filter 71, the first attenuator 72, the second filter 81 and the second attenuator 82 can be directly processed and prepared at corresponding positions on the carrier board.

[0080] As another possible implementation, the first filter 71 , the first attenuator 72 , the second filter 81 and the second attenuator 82 may be mounted on the carrier of the package sample box 9 by using surface mount (SM) technology.

[0081] Surface mount technology is suitable for automated production and can be implemented using equipment such as placement machines. This allows for the quick and accurate placement of the first filter 71, first attenuator 72, second filter 81, and second attenuator 82 at designated locations on the carrier board. This significantly improves production efficiency and reduces labor costs. It also reduces installation errors caused by human factors, improves product consistency and yield, and is suitable for large-scale industrial production. Furthermore, the surface-mounted first filter 71, first attenuator 72, second filter 81, and second attenuator 82 are firmly connected to the carrier board surface via soldering, providing good mechanical stability.

[0082] The frequency range of the first filter 71 is 5 GHz to 6 GHz, and the attenuation value of the first attenuator 72 is generally 20 dBm to 30 dBm; the frequency range of the second filter 81 is within 1 GHz, and the attenuation value of the second attenuator 82 is generally 0.

[0083] Please refer to Figure 4 Based on any of the above embodiments, in one embodiment of the present application, the superconducting quantum chip structure includes:

[0084] A superconducting quantum chip and a packaged sample box 9, wherein the superconducting quantum chip is packaged inside the packaged sample box 9, and a signal separation device 6, a first signal line 7, and a second signal line 8 are provided on a carrier board of the packaged sample box 9;

[0085] The signal separation device 6 is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0086] The first input end of the first signal line 7 is electrically connected to the output end of the signal separation device 6, and the first output end of the first signal line 7 is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of bit 3 on the superconducting quantum chip;

[0087] The second input end of the second signal line 8 is electrically connected to the output end of the signal separation device 6, and the second output end of the second signal line 8 is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of bit 3;

[0088] a third attenuator 10 located between the signal separation device 6 and the first input end of the first signal line 7; and / or,

[0089] a fourth attenuator 11 located between the signal separation device 6 and the second input end of the second signal line 8;

[0090] The first signal line 7 includes a first filter 71 and / or a first attenuator 72 ; the second signal line 8 includes a second filter 81 and / or a second attenuator 82 .

[0091] The superconducting quantum chip structure may include both the third attenuator 10 and the fourth attenuator 11; alternatively, the third attenuator 10 may be provided without the fourth attenuator 11; alternatively, the fourth attenuator 11 may be provided without the third attenuator 10.

[0092] The third attenuator 10 can reduce the amplitude of the first control signal output from the signal separation device 6 and before entering the first signal line 7 according to a certain proportion, thereby reducing the amplitude of the first control signal to an appropriate level; it can also attenuate the first control signal, reduce noise and interference in the first control signal, further improve the quality of the first control signal, and enhance the detectability and reliability of the first control signal.

[0093] The fourth attenuator 11 can reduce the amplitude of the second control signal output from the signal separation device 6 and before entering the second signal line 8 according to a certain proportion, thereby reducing the amplitude of the second control signal to an appropriate level; it can also attenuate the second control signal, reduce noise and interference in the second control signal, further improve the quality of the second control signal, and enhance the detectability and reliability of the second control signal.

[0094] Please refer to Figure 5 Based on any of the above embodiments, in one embodiment of the present application, the superconducting quantum chip structure includes:

[0095] A superconducting quantum chip and a packaged sample box 9, wherein the superconducting quantum chip is packaged inside the packaged sample box 9, and a signal separation device 6, a first signal line 7, and a second signal line 8 are provided on a carrier board of the packaged sample box 9;

[0096] The signal separation device 6 is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0097] The first input end of the first signal line 7 is electrically connected to the output end of the signal separation device 6, and the first output end of the first signal line 7 is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of bit 3 on the superconducting quantum chip;

[0098] The second input end of the second signal line 8 is electrically connected to the output end of the signal separation device 6, and the second output end of the second signal line 8 is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of bit 3;

[0099] a third attenuator 10 located between the signal separation device 6 and the first input end of the first signal line 7; and / or,

[0100] a fourth attenuator 11 located between the signal separation device 6 and the second input end of the second signal line 8;

[0101] A measurement and control device electrically connected to the input terminal of the signal separation device 6, for generating a combined control signal;

[0102] The first signal line 7 includes a first filter 71 and / or a first attenuator 72 ; the second signal line 8 includes a second filter 81 and / or a second attenuator 82 .

[0103] The circuit where the measurement and control device is located is a room temperature circuit.

[0104] It should be noted that, in this embodiment, there is no limitation on the structure of the measurement and control device, as long as a combined control signal can be formed.

[0105] As an implementable embodiment, the measurement and control device may include:

[0106] A first digital-to-analog converter 12 is used to generate a DC signal and a low-frequency microwave signal;

[0107] a synthesizer 13 connected to the first digital-to-analog converter 12, configured to receive a DC signal and a low-frequency microwave signal and synthesize the DC signal and the low-frequency microwave signal into a bit 3 frequency adjustment signal;

[0108] A second digital-to-analog converter 14 is used to generate an in-phase component signal and a quadrature component signal;

[0109] a signal mixer 15 connected to the second digital-to-analog converter 14, for receiving the phase component signal and the quadrature component signal and generating a bit 3 driving signal;

[0110] The second duplexer 16 connected to the signal mixer 15 and the synthesizer 13 respectively is used to combine the bit 3 frequency adjustment signal and the bit 3 driving signal in a non-mixing and non-interfering manner to form a combined control signal.

[0111] A direct current (DC) signal refers to a signal whose direction and magnitude remain constant and has no periodic changes.

[0112] The in-phase component signal may be referred to as an I signal, and the quadrature component signal may be referred to as a Q signal. The signal mixer 15 may be an IQ mixer capable of processing both the in-phase (I) and quadrature (Q) component signals simultaneously.

[0113] The bit 3 frequency adjustment signal is a bit 3 frequency adjustment Z signal, and the bit 3 drive signal is a bit 3 drive XY signal.

[0114] Second duplexer 16 is a device used for wireless communication and signal processing, primarily for simultaneously transmitting and receiving signals over the same transmission medium. It isolates transmit and receive signals, ensuring both transmit and receive functions operate simultaneously and preventing the local transmitter's transmitted signals from reaching the receiver.

[0115] The second duplexer 16 (diplexer) has a filtering function and can suppress out-of-band interference signals.

[0116] Please refer to Figure 6 Based on the above embodiments, in one embodiment of the present application, the superconducting quantum chip structure includes:

[0117] A superconducting quantum chip and a packaged sample box 9, wherein the superconducting quantum chip is packaged inside the packaged sample box 9, and a signal separation device 6, a first signal line 7, and a second signal line 8 are provided on a carrier board of the packaged sample box 9;

[0118] The signal separation device 6 is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0119] The first input end of the first signal line 7 is electrically connected to the output end of the signal separation device 6, and the first output end of the first signal line 7 is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of bit 3 on the superconducting quantum chip;

[0120] The second input end of the second signal line 8 is electrically connected to the output end of the signal separation device 6, and the second output end of the second signal line 8 is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of bit 3;

[0121] a third attenuator 10 located between the signal separation device 6 and the first input end of the first signal line 7; and / or,

[0122] a fourth attenuator 11 located between the signal separation device 6 and the second input end of the second signal line 8;

[0123] A measurement and control device electrically connected to the input terminal of the signal separation device 6, for generating a combined control signal;

[0124] The first signal line 7 includes a first filter 71 and / or a first attenuator 72; the second signal line 8 includes a second filter 81 and / or a second attenuator 82;

[0125] The measurement and control equipment may include:

[0126] A first digital-to-analog converter 12 is used to generate a DC signal and a low-frequency microwave signal;

[0127] a synthesizer 13 connected to the first digital-to-analog converter 12, configured to receive a DC signal and a low-frequency microwave signal and synthesize the DC signal and the low-frequency microwave signal into a bit 3 frequency adjustment signal;

[0128] A second digital-to-analog converter 14 is used to generate an in-phase component signal and a quadrature component signal;

[0129] a signal mixer 15 connected to the second digital-to-analog converter 14, for receiving the phase component signal and the quadrature component signal and generating a bit 3 driving signal;

[0130] The second duplexer 16 is connected to the signal mixer 15 and the synthesizer 13 respectively, and is used to combine the bit 3 frequency adjustment signal and the bit 3 drive signal in a non-mixing and non-interfering manner to form a combined control signal;

[0131] The fifth attenuator 17 has a first end connected to the second duplexer 16 , and a second end connected to the combiner 13 .

[0132] The two ends of the fifth attenuator 17 are electrically connected to the second duplexer 16 and the synthesizer 13 respectively. The fifth attenuator 17 can reduce the amplitude of the bit 3 frequency adjustment signal output from the synthesizer 13 and entering the second duplexer 16 according to a certain proportion, thereby reducing the amplitude of the bit 3 frequency adjustment signal to an appropriate level; it can also attenuate the bit 3 frequency adjustment signal, reduce the noise and interference in the bit 3 frequency adjustment signal, improve the quality of the bit 3 frequency adjustment signal, and enhance the detectability and reliability of the bit 3 frequency adjustment signal.

[0133] Based on any of the above embodiments, in one embodiment of the present application, the superconducting quantum chip structure includes:

[0134] A superconducting quantum chip and a packaged sample box 9, wherein the superconducting quantum chip is packaged inside the packaged sample box 9, and a signal separation device 6, a first signal line 7, and a second signal line 8 are provided on a carrier board of the packaged sample box 9;

[0135] The signal separation device 6 is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal;

[0136] The first input end of the first signal line 7 is electrically connected to the output end of the signal separation device 6, and the first output end of the first signal line 7 is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of bit 3 on the superconducting quantum chip;

[0137] The second input end of the second signal line 8 is electrically connected to the output end of the signal separation device 6, and the second output end of the second signal line 8 is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of bit 3;

[0138] a third attenuator 10 located between the signal separation device 6 and the first input end of the first signal line 7; and / or,

[0139] a fourth attenuator 11 located between the signal separation device 6 and the second input end of the second signal line 8;

[0140] A measurement and control device electrically connected to the input terminal of the signal separation device 6, for generating a combined control signal;

[0141] The first signal line 7 includes a first filter 71 and / or a first attenuator 72; the second signal line 8 includes a second filter 81 and / or a second attenuator 82;

[0142] The measurement and control equipment may include:

[0143] A first digital-to-analog converter 12 is used to generate a DC signal and a low-frequency microwave signal;

[0144] a synthesizer 13 connected to the first digital-to-analog converter 12, configured to receive a DC signal and a low-frequency microwave signal and synthesize the DC signal and the low-frequency microwave signal into a bit 3 frequency adjustment signal;

[0145] A second digital-to-analog converter 14 is used to generate an in-phase component signal and a quadrature component signal;

[0146] a signal mixer 15 connected to the second digital-to-analog converter 14, for receiving the phase component signal and the quadrature component signal and generating a bit 3 driving signal;

[0147] The second duplexer 16 is connected to the signal mixer 15 and the synthesizer 13 respectively, and is used to combine the bit 3 frequency adjustment signal and the bit 3 drive signal in a non-mixing and non-interfering manner to form a combined control signal;

[0148] a fifth attenuator 17 , wherein a first end of the fifth attenuator 17 is connected to the second duplexer 16 , and a second end of the fifth attenuator 17 is connected to the combiner 13 ;

[0149] The first output end of the first signal line 7 is connected to the pin of the superconducting quantum chip by wedge bonding; and / or,

[0150] The second output end of the second signal line 8 is connected to the pin of the superconducting quantum chip through wedge bonding.

[0151] This embodiment includes three situations. In the first situation, the first output end of the first signal line 7 is connected to the pin of the superconducting quantum chip by wedge welding, and the second output end of the second signal line 8 is connected to the pin of the superconducting quantum chip by wedge welding; in the second situation, the first output end of the first signal line 7 is connected to the pin of the superconducting quantum chip by wedge welding, and the second output end of the second signal line 8 is not connected to the pin of the superconducting quantum chip by wedge welding; in the third situation, the first output end of the first signal line 7 is not connected to the pin of the superconducting quantum chip by wedge welding, and the second output end of the second signal line 8 is connected to the pin of the superconducting quantum chip by wedge welding.

[0152] When the first output end of the first signal line 7 is connected to the pin of the superconducting quantum chip through wedge welding, the first output end of the first signal line 7 and the pin of the superconducting quantum chip are connected through a wedge bonding wire; when the second output end of the second signal line 8 is connected to the pin of the superconducting quantum chip through wedge welding, the second output end of the second signal line 8 and the pin of the superconducting quantum chip are connected through a wedge bonding wire.

[0153] The wedge welding method used in this embodiment can, first, enhance the connection strength between the first output end of the first signal line 7 and the pin of the superconducting quantum chip, and the connection strength between the second output end of the second signal line 8 and the pin of the superconducting quantum chip, ensuring that the connection is not prone to loosening or falling off during long-term use. Second, it can achieve a low-resistance connection, which can reduce energy loss and heat generation, thereby ensuring good electrical conductivity, effectively reducing attenuation and distortion in signal transmission, and improving circuit efficiency and stability. Third, the wedge welding method does not require complex welding equipment or advanced welding techniques, and the operation process is relatively easy to master. Generally, only simple wedge welding tools are required, and the connection can be completed manually or semi-automatically, improving work efficiency. Fourth, the heat generated during the wedge welding method is relatively small, which has a minimal thermal impact on the connecting materials, is unlikely to cause significant changes in the material properties, and causes relatively little damage to the connected components. Fifth, if the wedge welding is performed according to correct operating specifications, a relatively stable and consistent connection quality can be achieved, which is conducive to improving product consistency and reliability in mass production.

[0154] The present application also provides a superconducting quantum computer, comprising the superconducting quantum chip structure of any of the above embodiments.

[0155] A superconducting quantum computer is a device that uses superconducting qubits to perform quantum computing. These qubits are constructed using components such as superconducting Josephson junctions. By controlling parameters such as current and voltage in superconducting circuits, qubits are placed in different quantum states, and information processing and computation are performed using the superposition and entanglement properties of quantum states. Because superconducting materials exhibit properties such as zero resistance at extremely low temperatures, they can reduce energy loss and interference in qubits, improving the stability and accuracy of quantum computing.

[0156] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0157] The above is a detailed introduction to the superconducting quantum chip structure and superconducting quantum computer provided by this application. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above embodiments is only used to help understand the method and core ideas of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the scope of protection of this application.

Claims

1. A superconducting quantum chip structure, characterized in that: include: A superconducting quantum chip and a packaged sample box, wherein the superconducting quantum chip is packaged inside the packaged sample box, and a signal separation device, a first signal circuit, and a second signal circuit are provided on a carrier board of the packaged sample box; The signal separation device is used to receive the combined control signal and separate the combined control signal to generate a first control signal and a second control signal; The first input end of the first signal circuit is electrically connected to the output end of the signal separation device, and the first output end of the first signal circuit is electrically connected to the superconducting quantum chip, so that the first control signal is transmitted to the first control line of the bit on the superconducting quantum chip; The second input end of the second signal line is electrically connected to the output end of the signal separation device, and the second output end of the second signal line is electrically connected to the superconducting quantum chip, so that the second control signal is transmitted to the second control line of the bit; the first signal line and the second signal line are at the same horizontal plane as the bit.

2. The superconducting quantum chip structure according to claim 1, characterized in that: The signal separation device includes a first duplexer or a power splitter.

3. The superconducting quantum chip structure according to claim 1, characterized in that: The first signal line includes a first filter and / or a first attenuator.

4. The superconducting quantum chip structure according to claim 1, characterized in that: The second signal line includes a second filter and / or a second attenuator.

5. The superconducting quantum chip structure according to claim 1, characterized in that: Also includes: a third attenuator located between the signal separation device and the first input end of the first signal line; and / or, a fourth attenuator located between the signal separation component and the second input end of the second signal line.

6. The superconducting quantum chip structure according to claim 1, characterized in that: Also includes: The measurement and control device is electrically connected to the input end of the signal separation device and is used to generate a combined control signal.

7. The superconducting quantum chip structure according to claim 6, characterized in that: The measurement and control device comprises: a first digital-to-analog converter, configured to generate a DC signal and a low-frequency microwave signal; a synthesizer connected to the first digital-to-analog converter, configured to receive the DC signal and the low-frequency microwave signal and synthesize the DC signal and the low-frequency microwave signal into a bit frequency adjustment signal; a second digital-to-analog converter, configured to generate an in-phase component signal and a quadrature component signal; a signal mixer connected to the second digital-to-analog converter, configured to receive the phase component signal and the quadrature component signal and generate a bit driving signal; The second duplexer connected to the signal mixer and the synthesizer respectively is used to combine the bit frequency adjustment signal and the bit driving signal in a non-mixing and non-interfering manner to form the combined control signal.

8. The superconducting quantum chip structure according to claim 7, characterized in that: Also includes: a fifth attenuator, wherein a first end of the fifth attenuator is connected to the second duplexer, and a second end of the fifth attenuator is connected to the combiner.

9. The superconducting quantum chip structure according to any one of claims 1 to 8, characterized in that: The first output end of the first signal line is connected to the pin of the superconducting quantum chip by wedge bonding; and / or, The second output end of the second signal line is connected to a pin of the superconducting quantum chip through wedge bonding.

10. A superconducting quantum computer, characterized in that: Comprising the superconducting quantum chip structure according to any one of claims 1 to 9.

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