Memory device including word line grouping device and method of operating same

Abstract

The present disclosure relates to a memory device including a word line grouping device and a method of operating the same, the memory device including: a memory device including a plurality of word lines; and a word line grouping device configured to group the plurality of word lines into a specific number of groups, each group serving as a memory block such that a read performance value obtained by reading data of the word lines included in the same group using the representative read voltage satisfies the set tolerance value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2024-0022408, filed on February 16, 2024, the disclosure of which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate generally to a semiconductor integrated device, and more particularly, to a memory device including a word line grouping apparatus and an operating method thereof. Background Art

[0004] A semiconductor memory device may include a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines.

[0005] In order to store data in a semiconductor memory device or read data stored in a semiconductor memory device, voltages set according to an operation mode are applied to word lines and bit lines.

[0006] Flash memory devices, such as non-volatile memory devices, may have a hierarchical structure extending across pages (i.e., word lines), memory blocks, planes, and dies. The number of word lines per block may be increased to reduce the chip size of the flash memory device, but this may increase the number of accesses per block, leading to read disturb.

[0007] A read retry method can be used to address changes in memory cell threshold voltage caused by read disturb. When a read operation fails on a target word line, the read retry method changes the read voltage level to retry the read operation. The semiconductor memory device can retry the read operation based on a read retry table. The table stores information about the read voltage to be changed during the read retry operation, per memory block or die.

[0008] As the number of word lines stacked within a block increases, the threshold voltages of word lines included in the same block may have different distributions due to iterative read operations. Therefore, the read characteristics of word lines included in the same block may be different from each other. Summary of the Invention

[0009] Embodiments of the present disclosure provide a memory device capable of grouping a plurality of word lines in a memory block according to threshold voltage distribution, and an operating method thereof.

[0010] In an embodiment of the present disclosure, a storage device may include: a memory device including a plurality of word lines; and a word line grouping device configured to group the plurality of word lines into a specific number of groups so that a read performance value obtained by reading data of word lines included in the same group using a representative read voltage satisfies a set tolerance value.

[0011] In an embodiment of the present disclosure, a method for operating a storage device includes: a memory device including multiple word lines; and a storage controller configured to control the memory device, the method including: the storage controller grouping the multiple word lines into a specific number of groups; and the storage controller regrouping the multiple word lines so that a read performance value obtained by reading data of the word lines included in the same group using a representative read voltage meets a set tolerance value.

[0012] According to an embodiment of the present technology, a successful read operation can be guaranteed by grouping word lines having similar threshold voltage distributions and applying a read voltage to the word lines in units of groups.

[0013] These and other features, aspects, and embodiments are described in greater detail below. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The above and other aspects, features and advantages of the embodiments of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a diagram illustrating a configuration of a storage device according to an embodiment of the present disclosure;

[0016] Figure 2 is a diagram illustrating a configuration of a memory device according to an embodiment of the present disclosure;

[0017] Figure 3 is a diagram illustrating a configuration of a word line grouping device according to an embodiment of the present disclosure;

[0018] Figure 4 is a diagram showing a configuration of a representative read voltage determination circuit according to an embodiment of the present disclosure;

[0019] Figure 5 is a diagram for describing a calculation concept of a maximum failure bit count according to an embodiment of the present disclosure;

[0020] Figure 6 is a diagram for describing a calculation concept of a maximum failure bit count according to an embodiment of the present disclosure;

[0021] Figure 7A and Figure 7Bis a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure;

[0022] Figures 8A to 8C is a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure;

[0023] 9A to 9D is a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure;

[0024] Figure 10 is a diagram for describing a group size adjustment concept according to a read performance value according to an embodiment of the present disclosure; and

[0025] Figure 11 is a flowchart for describing a method of grouping word lines in a memory device of a storage apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] Various embodiments of the present disclosure are described in detail with reference to the accompanying drawings. The drawings are schematic illustrations of various embodiments and intermediate structures. Thus, variations from the illustrated configurations and shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the described embodiments should not be construed as limited to the particular configurations and shapes shown herein, but may include deviations in configurations and shapes without departing from the spirit and scope of the present teachings as defined by the appended claims.

[0027] The present teachings are described herein with reference to cross-sectional views and / or plan views of embodiments of the present disclosure. However, the embodiments of the present disclosure should not be construed as being limited to the disclosed embodiments. Although several embodiments of the present disclosure are shown and described, it will be understood by those skilled in the art that these embodiments may be modified without departing from the principles and spirit of the present disclosure.

[0028] Figure 1 is a diagram illustrating a configuration of a storage device 10 according to an embodiment of the present disclosure.

[0029] Reference Figure 1 , the storage device 10 may include a storage controller 110 and a memory device 120. The memory device 120 may include at least a plurality of nonvolatile memory devices 121, 123, and 125.

[0030] The memory controller 110 and the memory device 120 may be coupled through a plurality of channels CH1 , CH2 , and CHn.

[0031] In response to a write request from an external device (not shown), the memory device 10 may program the write-requested data into the memory device 120 according to the control of the memory controller 110 .

[0032] In response to a read request from an external device, the storage device 10 may read data stored in the memory device 120 according to the control of the storage controller 110 and provide the read data to the external device.

[0033] The storage device 10 may read data from or program data into the memory device 120 to perform read requests from external devices and internal operations of the storage device 10. The internal operations may include housekeeping operations such as garbage collection and wear leveling.

[0034] The memory controller 110 may provide an interface between an external device and the memory apparatus 120. The memory controller 110 according to an embodiment may include a word line grouping apparatus 20.

[0035] The memory device 120 may have a hierarchical structure that is expanded into pages, memory blocks, planes, and dies, where a page is a collection of memory cells sharing a word line, a memory block is a collection of a specific number of pages, a plane is a collection of a specific number of memory blocks, and a die is a collection of a specific number of planes.

[0036] The word line grouping device 20 can group the word lines of a block into specific groups. Specifically, the word line grouping device 20 according to the present technology can group the word lines so that when data stored in multiple word lines included in the same group is read using a representative read voltage at each logic level, the read performance value satisfies a set threshold.

[0037] In an embodiment, word line grouping device 20 may group the word lines within each block into a specific number of initial groups (hereinafter referred to as the initial group number) and determine a read voltage that optimizes read performance as a representative read voltage for each initial group. Furthermore, word line grouping device 20 may regroup the word lines by adjusting (expanding or reducing) the size of the groups so that the read performance value obtained by reading data from the word lines in each group using the representative read voltage for each group satisfies a set threshold.

[0038] Therefore, the word lines within the block may be divided into groups, and a representative read voltage for each group may be determined. The memory controller 110 may generate a representative read voltage for each group and an offset voltage determined according to the representative read voltage as a read retry table.

[0039] The memory cells constituting the memory device 120 can store single-bit data or multi-bit data.

[0040] When the memory cells store unit data, the representative read voltage of each group may be a read voltage that optimizes a read performance value that distinguishes a logic level of the unit data.

[0041] When a memory cell stores multi-bit data, the logic level of the data stored in the memory cell can be distinguished by different read voltages based on the bit positions of the multi-bit data. The read voltages used to distinguish the data stored in the memory cell storing multi-bit data can be composed of a set of read voltages divided according to the bit positions, and the representative read voltage of each group can be a set of read voltages with optimized read performance values.

[0042] In an embodiment, the read performance value may be determined as at least one of a maximum fail bit count (MAX FBC) and a read pass rate (RPR).

[0043] The maximum failed bit count (MAX FBC) may be a maximum value of the failed bit count (FBC) of each word line for each of a plurality of candidate read voltages when data of the word lines in each group is read using the candidate read voltage. The representative read voltage that optimizes the maximum failed bit count (MAX FBC) may be determined as the candidate read voltage that minimizes the maximum failed bit count (MAX FBC).

[0044] The read pass rate (RPR) can be defined as the ratio of the number of word lines within the group whose FBC falls within the error correction capability range (hereinafter referred to as the "word line number") to the total number of word lines (hereinafter referred to as the "total word line number") for each candidate read voltage when reading data from the word lines in each group using multiple candidate read voltages. A representative read voltage that optimizes the read pass rate (RPR) can be determined as the candidate read voltage that maximizes the read pass rate (RPR).

[0045] The word line grouping device 20 according to the present technology can improve the read pass rate (RPR) of each group by determining (obtaining) a representative read voltage of each group based on at least one read performance value of the maximum fail bit count (MAX FBC) and the read pass rate (RPR) and adjusting the group size so that the read performance value meets the set threshold.

[0046] Figure 2 is a diagram illustrating a configuration of a memory device 120 according to an embodiment of the present disclosure.

[0047] Figure 2 The memory device 120 may be Figure 1 An embodiment of the non-volatile memory devices 121, 123 and 125 in.

[0048] Reference Figure 2Memory device 120 may include a plurality of dies DIE0 and DIE1, and each of dies DIE0 and DIE1 may include a plurality of planes PLANE00 / PLANE01 and PLANE10 / PLANE11. Each of planes PLANE00 / PLANE01 and PLANE10 / PLANE11 may include a plurality of memory blocks BLOCK000 to BLOCK00N / BLOCK010 to BLOCK01N and BLOCK100 to BLOCK10N / BLOCK110 to BLOCK11N. Each of memory blocks BLOCK000 to BLOCK00N / BLOCK010 to BLOCK01N and BLOCK100 to BLOCK10N / BLOCK110 to BLOCK11N may include a plurality of pages PAGE 0 to PAGE M. Pages PAGE 0 to PAGE M may be equivalent to word lines.

[0049] Memory device 120 can input / output data through channels CHa and CHb. Channels CHa and CHb can input / output data in an interleaved manner. Each of channels CHa and CHb can branch into multiple channels WAY0 / WAY1 and WAY2 / WAY3 that share channels CHa and CHb, respectively. Multiple channels WAY0 / WAY1 and WAY2 / WAY3 can be connected to, for example, dies DIE2 / DIE0 and DIE1 / DIE3, respectively.

[0050] Figure 2 1 and 2 illustrate that the dies DIE0 / DIE2 and DIE1 / DIE3 are respectively coupled to the ways WAY1 / WAY0 and WAY2 / WAY3 branched from the channels CHa and CHb, but the embodiment is not limited thereto.

[0051] The memory controller 110 may be configured to form a super block by grouping simultaneously selectable blocks among a plurality of memory blocks.

[0052] A super block can be configured from a collection of blocks that can be selected simultaneously. For example, the word line grouping device 20 can be configured to form super blocks A1 and A2 by grouping memory blocks included in different planes within the same die, or to form super block B by grouping memory blocks included in different planes within multiple dies.

[0053] Based on the results of reading word line data (e.g., data of multiple pages PAGE 0 to PAGE M included in each of memory blocks BLOCK000 to BLOCK00N / BLOCK010 to BLOCK01N and BLOCK100 to BLOCK10N / BLOCK110 to BLOCK11) using multiple candidate read voltages, the word line grouping device 20 can group the memory blocks according to representative read voltages that meet the required read performance value. Read performance can be improved by applying an offset voltage corresponding to the representative read voltage determined (derived) for each group to a read retry operation.

[0054] Figure 3 The present invention is shown in FIG. Figure 1 FIG. 1 is a diagram illustrating a configuration of the word line grouping device 20 .

[0055] Reference Figure 3 The word line grouping device 20 may include an initialization circuit 210 , a representative read voltage determination circuit 220 , a performance determination circuit 230 , a group size adjustment circuit 240 , and a group determination circuit 250 .

[0056] The initialization circuit 210 may set initial parameters for the word line grouping.

[0057] In an embodiment, the initial parameters may include a default read voltage, an initial group number N, a first threshold TH1 , a second threshold TH2 , a third threshold TH3 , and a search direction.

[0058] The default read voltage may be threshold voltage distribution data of a memory block included in the specifications of the memory device 120. The default read voltage may be stored in a special block of the memory device 120, and the initialization circuit 210 may obtain the default read voltage from the special block.

[0059] The initial group number N may be the initial group number for each block. The initialization circuit 210 may initially group the word lines of each block according to the initial group number N. In an embodiment, the initialization circuit 210 may generate the initial groups by dividing the word lines included in the block by the initial group number N.

[0060] The first threshold TH1 may be the error correction capability of the memory controller 110 .

[0061] The second threshold TH2 may be a tolerance value of the read performance value of each group.

[0062] The third threshold TH3 may be a standard value for terminating group size adjustment and fixing the group size.

[0063] The search direction may be a selected direction for searching a target group when adjusting the group size. Addresses may be assigned to word lines within a memory block in ascending order along a specific direction, and the group search direction may be selected from a direction in which word line addresses increase and a direction in which word line addresses decrease.

[0064] Based on the read results obtained when the multiple candidate read voltages determined by the initialization circuit 210 are respectively applied to the initial group of each block, the representative read voltage determination circuit 220 can determine (obtain) a representative read voltage that optimizes the read performance value (for example, at least one of the maximum fail bit count (MAX FBC) and the read pass rate (RPR)).

[0065] In an embodiment, the candidate read voltages may include a default read voltage acquired by the initialization circuit 210 and a plurality of offset voltages that offset the default read voltage by a set amount.

[0066] In an embodiment, the read performance value may be determined as at least one of a maximum fail bit count (MAX FBC) and a read pass rate (RPR).

[0067] The maximum failed bit count (MAX FBC) can be defined as the maximum value of the failed bit count (FBC) for each word line for a plurality of candidate read voltages when data of the word lines in each group is read using the plurality of candidate read voltages. The representative read voltage that optimizes the maximum failed bit count (MAX FBC) can be determined as the candidate read voltage that minimizes the maximum failed bit count (MAX FBC).

[0068] The read pass rate (RPR) can be defined as the ratio of the number of word lines with a failed bit count (FBC) within the error correction capability (TH1) to the total number of word lines in the group for each candidate read voltage when reading data from the word lines of each group using multiple candidate read voltages. A representative read voltage that optimizes the read pass rate (RPR) can be determined as the candidate read voltage that maximizes the read pass rate (RPR).

[0069] The performance determination circuit 230 may determine whether a read performance value obtained by reading data of a word line of each group using a representative read voltage satisfies a second threshold value TH2. The performance determination circuit 230 may determine whether a read performance value of a group whose read performance value satisfies the second threshold value TH2 satisfies a third threshold value TH3 as a group fixed condition.

[0070] The group size adjustment circuit 240 may fix the search target group or enlarge or reduce the size of the search target group based on the determination result of the performance determination circuit 230 .

[0071] For example, when the read performance value of the search target group satisfies the second threshold TH2 and the third threshold TH3 at the same time, the group size adjustment circuit 240 may fix the size of the corresponding group instead of adjusting the size of the group.

[0072] The fact that the read performance value of a group satisfies the second threshold TH2 may indicate that a read pass rate (RPR) obtained by reading data stored in the corresponding group using a representative read voltage is guaranteed to be above a certain level or a maximum fail bit count (MAX FBC) is guaranteed to be below a certain level.

[0073] The fact that the read performance value of a group satisfies the third threshold TH3 may indicate that the read performance value of the corresponding group is very close to the second threshold TH2.

[0074] When the read performance value of the search target group satisfies the second threshold TH2 but does not satisfy the third threshold TH3, for example, when the degree to which the read performance value satisfies the second threshold TH2 is equal to or greater than the third threshold TH3, the group size adjustment circuit 240 may expand the size of the group by adding a word line physically adjacent to the corresponding search target group. When the read performance value of the expanded group does not satisfy the second threshold TH2, the group size adjustment circuit 240 may fix the group before the expanded group as the final group.

[0075] When the read performance value of the search target group does not meet the second threshold TH2, the group size adjustment circuit 240 may reduce the group size by deleting a portion of the word lines included in the corresponding group from the corresponding group. For example, the word lines deleted from the corresponding group may be word lines adjacent to the physical boundary of the corresponding group, but the embodiment is not limited thereto. When the read performance value of the reduced group meets the second threshold TH2, the group size adjustment circuit 240 may fix or expand the group size based on whether the read performance value of the reduced group meets the third threshold TH3.

[0076] When the read performance values of all groups satisfy the second threshold TH2 , the group size adjustment circuit 240 may terminate the group size adjustment and fix the groups.

[0077] When the group size is fixed by the group size adjustment circuit 240 , the group decision circuit 250 may output a maximum value or a minimum value of word line addresses included in the fixed group as a separator for each group.

[0078] For example, word lines of a stacked (three-dimensional, 3D) memory device may be assigned increasing word line addresses from word lines located closer to the semiconductor substrate toward word lines located further away from the semiconductor substrate. Depending on the search direction for grouping word lines, word line grouping may be performed from upper word lines toward lower word lines or from lower word lines toward upper word lines. When groups are fixed, group determination circuit 250 may output word line addresses corresponding to boundaries between physically adjacent groups as delimiters.

[0079] Figure 4 The present invention is shown in the embodiment of the present invention. Figure 3 FIG. 2 is a diagram representing the configuration of the read voltage determination circuit 220 .

[0080] Reference Figure 4 , which means that the read voltage determination circuit 220 may include a determination circuit 221 based on MAX FBC and a determination circuit 223 based on RPR.

[0081] The MAX FBC-based decision circuit 221 can calculate a maximum fail bit count (MAX FBC), which is the maximum value of the fail bit count (FBC) for each word line for a candidate read voltage when data of the word lines in each group is read using a portion of a plurality of candidate read voltages. The MAX FBC-based decision circuit 221 can determine the candidate read voltage that minimizes the maximum fail bit count (MAX FBC) as a representative read voltage.

[0082] The RPR-based decision circuit 223 can calculate a read pass rate (RPR), which is the ratio of the number of word lines with a failed bit count (FBC) within the error correction capability to the total number of word lines in each group when data of the word lines in each group is read using at least a portion of a plurality of candidate read voltages. The RPR-based decision circuit 223 can determine the candidate read voltage that maximizes the read pass rate (RPR) as a representative read voltage.

[0083] For example, in the case where the i-th candidate read voltage is applied, a read pass rate (RPR) may be calculated as in the following Equation 1.

[0084] [Equation 1]

[0085]

[0086] When a memory cell is operated to store multi-bit data, the number of word lines restored by each candidate read voltage (#WL samples restored by the i-th RR) can be obtained from the following Equation 2.

[0087] [Equation 2]

[0088]

[0089] Figure 5 is a diagram for describing a calculation concept of a maximum failure bit count (MAX FBC) according to an embodiment of the present disclosure.

[0090] Reference Figure 5 When multiple candidate read voltages OFFSET0, OFFSET1, OFFSET2, ..., OFFSETk are used to read data of multiple word lines WL0, WL1, WL2, ..., WLj included in a specific group Group 0, a word line failure bit count (FBC) for the candidate read voltages can be obtained. 0,0 、FBC 1,0 、FBC 2,0 、……、FBC j,0 ), (FBC 0,1 、……、FBC j,1 ), (FBC 0,2 、……、FBC j,2 ),……,(FBC 0,k 、……、FBC j,k ).

[0091] The MAX FBC-based determination circuit 221 may determine (obtain) the maximum value among the FBCs of the word lines WO0, WL1, WL2, ..., WLj for the candidate read voltages OFFSET0, OFFSET1, OFFSET2, ..., OFFSETk as the maximum FBC. For example, the maximum FBC of the word lines WO0, WL1, WL2, ..., WLj for the candidate read voltage OFFSET0 may be MAX{FBC}. 0,0 、FBC 1,0 、FBC 2,0 、……、FBC j,0}.

[0092] The MAX FBC-based decision circuit 221 may determine a candidate read voltage corresponding to a minimum value among the maximum fail bit counts (MAXFBC) for the candidate read voltages as a representative read voltage.

[0093] When a memory cell stores multiple bits of data, the logic level of the data stored in the memory cell can be differentiated by using different read voltages depending on the bit position of the data. The maximum failed bit count (MAX FBC) of a memory cell storing multiple bits of data may be the sum of the failed bit counts (FBC) according to the bit positions.

[0094] Figure 6is a diagram for describing a calculation concept of a maximum failure bit count (MAX FBC) according to an embodiment of the present disclosure.

[0095] Reference Figure 6 , a portion of the candidate read voltages may be selected as sample read voltages Sample RV, and a minimum value of a maximum fail bit count (MAX FBC) may be estimated based on fail bit counts (FBC) of word lines for the sample read voltages Sample RV.

[0096] In an embodiment, the MAX FBC-based decision circuit 221 may calculate a maximum value of a fail bit count (FBC) of a word line for a sample read voltage Sample RV and determine a sample read voltage that minimizes the maximum fail bit count (MAX FBC) as a representative read voltage.

[0097] In an embodiment, the decision circuit 221 may calculate a voltage corresponding to a minimum MAX FBC estimated based on a maximum fail bit count (MAX FBC) of a word line for a sample read voltage Sample RV as a representative read voltage based on the MAX FBC.

[0098] For example, the MAX FBC-based decision circuit 221 may determine the average of two read voltages A and B having relatively small maximum fail bit counts (MAX FBC) among the sample read voltages Sample RV as the representative read voltage Rep. RV.

[0099] For example, the MAX FBC-based decision circuit 221 may additionally calculate a maximum fail bit count (MAX FBC) of the offset sample read voltage and determine a voltage that minimizes the maximum fail bit count (MAX FBC) from read results corresponding to the sample read voltage and the offset sample read voltage as the representative read voltage.

[0100] In an embodiment, shifting the sample read voltage may include increasing or decreasing at least one read voltage A having a relatively small maximum fail bit count (MAX FBC) among the sample read voltages Sample RV by a specific amount. In another example, the shifted sample read voltage may be a voltage corresponding to an average voltage of at least two read voltages A and B having relatively small maximum fail bit counts (MAX FBC).

[0101] In a further example, the MAX FBC-based decision circuit 221 may calculate a vertex by fitting the coordinates of three points A, B, and C where the maximum fail bit count (MAX FBC) among the sample read voltages is relatively small to a two-dimensional (2D) curve, and determine the voltage corresponding to the vertex as the representative voltage Rep. RV.

[0102] The method of determining the representative read voltage based on the maximum fail bit count (MAX FBC) is not limited thereto, but various modifications may be made to the method of determining the read voltage that minimizes the fail bit count (FBC) as the representative read voltage.

[0103] Figure 7A and Figure 7B is a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure.

[0104] Reference Figure 7A , a memory block including word lines having word line addresses WLN of 1 to 1400 may be divided into four initial groups WLG1, WLG2, WLG3, and WLG4. The word line addresses WLN corresponding to the boundaries between the initial groups WLG1, WLG2, WLG3, and WLG4 may be set to WLN based on the number of initial groups (N=4). g1 (1) WLN g2 (350), WLN g3 (700), WLN g4 (1050).

[0105] The representative read voltage decision circuit 220 may determine (derive) the representative read voltages of the groups WLG1 , WLG2 , WLG3 , and WLG4 as OSRV1 , OSRV4 , OSRV2 , and OSRV2 based on the read performance values (MAX FBC and / or RPR).

[0106] The performance determination circuit 230 may determine whether the read performance values of the groups WLG1 , WLG2 , WLG3 , and WLG4 satisfy a second threshold TH2 .

[0107] The group size adjustment circuit 240 can be configured to expand the group size until the read performance values of the groups WLG1 to WLG4 meet the third threshold TH3 when the read performance values of the groups WLG1 to WLG4 meet the second threshold TH2, and reduce the group size when the read performance values of the groups WLG1 to WLG4 do not meet the second threshold TH2.

[0108] In an embodiment, the group size adjustment circuit 240 may adjust the group size by sequentially selecting groups according to a search direction determined based on the physical location of the word line. For example, the group size adjustment circuit 240 may adjust the group size by sequentially selecting groups in a direction of increasing word line addresses (e.g., from the first group WLG1 to the fourth group WLG4). In another example, the group size adjustment circuit 240 may adjust the group size by sequentially selecting groups in a direction of decreasing word line addresses (e.g., from the fourth group WLG4 to the first group WLG1).

[0109] Figure 7A It is shown that when the groups are grouped by selecting the groups in descending order of the word line addresses, the fourth group GWL4 satisfies the second threshold TH2.

[0110] The group size adjustment circuit 240 can adjust the group size according to the following conditions: Figure 7B The setting standard shown expands the size of the fourth group WLG4. As the size of the fourth group WLG4 expands, the word line address corresponding to the boundary between the fourth group WLG4 and the third group WLG3 can be changed from WLN g4 (1050) becomes WLN g4,new (1000). As the size of the fourth group WLG4 is expanded, word line addresses included in the new fourth group WLG4_N may be adjusted to 1000 to 1400, and word line addresses included in the third group WLG3 may be adjusted to 700 to 1000.

[0111] Subsequently, the group size adjustment circuit 240 may determine whether the read performance value of the third group WLG3 satisfies the second threshold TH2. When determining that the read performance value of the third group WLG3 does not satisfy the second threshold TH2, the group size adjustment circuit 240 may reduce the size of the third group WLG3.

[0112] As the size of the third group WLG3 decreases, the word line address corresponding to the boundary between the third group WLG3 and the second group WLG2 can be changed from WLN g3 (700) becomes WLN g3,new (750). As the size of the third group WLG3 decreases, word line addresses included in the new third group WLG3_N may be adjusted to 750 to 1000, and word line addresses included in the second group WLG2 may be adjusted to 350 to 750.

[0113] Subsequently, although not shown in the figure, the sizes of the first group WLG1 and the second group WLG2 may be adjusted according to whether the read performance values of the first group WLG1 and the second group WLG2 meet the second threshold TH2 and the third threshold TH3 .

[0114] When the read performance value of a group satisfies the second threshold TH2 and the third threshold TH3 at the same time, the group size adjustment circuit 240 may fix the size of the corresponding group instead of adjusting the group size.

[0115] When the read performance values of all the groups WLG1 to WLG4 satisfy the second threshold TH2 , the group size adjustment circuit 240 may terminate the group size adjustment.

[0116] As described above, the second threshold TH2 may be a criterion for determining the read performance value of the final fixed group.

[0117] As the initial number of groups N increases, the number of word lines included in each group may decrease, and thus the second threshold TH2 may be set to be smaller. For example, the initial number of groups N and the second threshold TH2 may be inversely proportional to each other.

[0118] In order to enlarge or reduce the group size, the following Equation 3 may be used, but the embodiment is not limited thereto.

[0119] [Equation 3]

[0120]

[0121] Equation 3 is an example in which the search direction is a direction in which the word line address decreases from the upper side to the lower side. When the search direction is reversed, the enlargement / reduction formula can be used in reverse.

[0122] The search convergence speed and overall read performance values can be changed according to the setting values of a1, a2, b1, and b2.

[0123] The group search may be iterated until all groups satisfy the second threshold TH2.

[0124] As described above, the group resizing circuit 240 may sequentially select groups according to the search direction, increase the group size when the read performance value of the selected group satisfies the second threshold TH2 so that the read performance value of the selected group satisfies the third threshold TH3, and decrease the group size when the read performance value of the selected group does not satisfy the second threshold TH2. Furthermore, the group resizing circuit 240 may terminate group resizing when the read performance values of all groups satisfy the second threshold TH2.

[0125] Figures 8A to 8C is a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure.

[0126] In this embodiment, the group size adjustment circuit 240 can select a group as a search target according to the search direction, expand the size of the selected group when the read performance value of the selected group meets the second threshold TH2, and fix the size of the search target group to the size before the read performance value of the group does not meet the second threshold TH2.

[0127] When the size of the search target group is fixed, the group size adjustment circuit 240 may perform a new group search on the remaining word lines.

[0128] Return to reference Figure 7A, a memory block including word lines having word line addresses WLN of 1 to 1400 may be divided into four initial groups WLG1, WLG2, WLG3, and WLG4. The word line addresses WLN corresponding to the boundaries between the initial groups WLG1, WLG2, WLG3, and WLG4 may be set to WLN based on the number of initial groups (N=4). g1 (1) WLN g2 (350), WLN g3 (700), WLN g4 (1050). Representative read voltages of the groups WLG1, WLG2, WLG3, and WLG4 may be obtained as OSRV1, OSRV4, OSRV2, and OSRV2, respectively.

[0129] Reference Figure 8A , the performance determination circuit 230 may set at least one word line group WLG4 as a search group and the remaining word line groups WLG1 to WLG3 as standby groups according to the search direction, and determine whether the read performance value of the search group WLG4 satisfies the second threshold TH2.

[0130] Reference Figure 8B , the group size adjustment circuit 240 may enlarge the group size when the read performance value of the search group WLG4 satisfies the second threshold TH2 .

[0131] As the size of the search group WLG4 increases, the word line address corresponding to the boundary between the fourth group WLG4 as the search group and the standby groups WLG1 to WLG3 may be changed from WLN to WLG4. g4 (1050) becomes WLNg 4,new (1000). As the size of the search group WLG4 is enlarged, the word line addresses included in the standby groups WLG1 to WLG3_N may be adjusted to 1 to 1000.

[0132] When the read performance value of the search group WLG4 meets the second threshold TH2, the group size adjustment circuit 240 can set the boundary word line address WLN of the search group WLG4 to g4 Set it to 1000, then Figure 8C As shown, the size of search group WLG4 is expanded again.

[0133] As the size of the search group WLG4 increases, the word line addresses corresponding to the boundaries between the search group WLG4 and the standby groups WLG1 to WLG3 can be increased from WLN g4 (1000) becomes WLN g4,new (950). As the size of the search group WLG4 is enlarged, the word line addresses included in the standby groups WLG1 to WLG3 may be adjusted to 1 to 950.

[0134] When the read performance value of the expanded search group WLG4 does not meet the second threshold TH2, the group size adjustment circuit 240 may adjust the group size according to the previous word line address WLN. g4 =1000 fixes the size of the corresponding group.

[0135] In another example, when the read performance value of the expanded search group WLG4 does not meet the second threshold TH2, the group size adjustment circuit 240 may reduce the size of the search target group WLG4 so that the read performance value of the search target group WLG4 meets the second threshold TH2.

[0136] Similarly, the group size adjustment circuit 240 may iteratively adjust the group sizes of the standby groups WLG1 to WLG3 .

[0137] During each iteration, the size of the group may be expanded or reduced according to the read performance value of the search group using the following Equation 4, but the embodiment is not limited thereto.

[0138] [Equation 4]

[0139]

[0140] Equation 4 is an example in which the search direction is a direction in which the word line address decreases from the upper side to the lower side. When the search direction is reversed, the enlargement / reduction formula can be used in reverse.

[0141] The search convergence speed and overall read performance values can be changed according to the setting values of a1, a2, b1, and b2.

[0142] 9A to 9D is a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure.

[0143] In an embodiment, the group size adjustment circuit 240 can divide the word lines of the storage block into two search groups WLGA and WLGB, determine whether the read performance values of the two search groups WLGA and WLGB meet the second threshold TH2, and fix the group size when the read performance values of the two groups both meet the second threshold TH2.

[0144] When the reading performance value of only one search group out of the two search groups satisfies the second threshold TH2 and the third threshold TH3 at the same time, the group size adjustment circuit 240 can fix the size of the corresponding search group, divide the remaining search group into two search groups, and determine whether the reading performance values of the two divided search groups both meet the second threshold TH2.

[0145] When the reading performance value of only one search group after the division satisfies the second threshold TH2 but does not satisfy the third threshold TH3, the group size adjustment circuit 240 can expand the size of the corresponding search group after the division and determine whether the reading performance values of the two search groups after the division both satisfy the second threshold TH2.

[0146] When the read performance values of the two divided search groups do not meet the second threshold TH2, the group size adjustment circuit 240 can change the boundary between the two divided search groups according to the specified standard and determine whether the read performance values of the two divided search groups both meet the second threshold TH2.

[0147] Reference Figure 9A The group size adjustment circuit 240 can set the representative read voltage of the initial group and then divide the initial group into search group A WLGA and search group B WLGB. The boundary word line address of search group A can be WLN gA , and the boundary word line address of the search group B can be WLN gB .

[0148] When the read performance value of the search group A WLGA satisfies the second threshold TH2, the group size adjustment circuit 240 may determine whether the read performance value of the search group A WLGA satisfies the third threshold TH3, such as Figure 9B shown.

[0149] When the read performance value of search group A WLGA meets the third threshold TH3, the group size adjustment circuit 240 can fix the size of search group A WLGA and divide search group B WLGB into two search groups WLGB and WLGC. Here, the boundary word line address between search group B WLGB and search group C WLGC can be WLN gB,new Furthermore, the group size adjustment circuit 240 may determine whether the read performance values of the two search groups WLGB and WLGC satisfy a second threshold TH2.

[0150] when Figure 9A When the read performance value of the search group WLGA does not meet the third threshold TH3, the group size adjustment circuit 140 may enlarge the size of the search group WLGA, such as Figure 9C Therefore, the boundary word line address of search group A WLGA can be changed to WLN gA,new .

[0151] Subsequently, the group size adjustment circuit 240 may determine whether the read performance values of the expanded search group A WLGA and search group B WLGB satisfy a second threshold TH2 .

[0152] when Figure 9A When the read performance values of the search group A WLGA and the search group B WLGB do not meet the second threshold TH2, the group size adjustment circuit 240 can reduce the size of one search group, for example, the size of the search group WLGA, and determine whether the read performance values of the two search groups WLGA and WLGB meet the second threshold TH2, such as Figure 9D shown.

[0153] Figure 9D Shows reducing the size of the search group WLGA and changing the boundary word line address of the search group WLGA to WLN gA,new .

[0154] During each iteration, the following Equation 5 may be used to expand or reduce the size of the group according to whether the read performance values of the two search groups meet the second threshold TH2, but the embodiment is not limited thereto.

[0155] [Equation 5]

[0156]

[0157] Equation 5 is an example in which the search direction is a direction in which the word line address decreases from the upper side to the lower side. When the search direction is reversed, the enlargement / reduction formula can be used in reverse.

[0158] The search convergence speed and overall read performance values can be changed according to the setting values of a1, a2, b1, and b2.

[0159] Figure 10 is a diagram for describing a concept of group size adjustment according to a read performance value according to an embodiment of the present disclosure.

[0160] In an embodiment, group resizing circuit 240 may divide the initial group of word lines of a memory block into two search groups with the best read performance values during each search iteration. For example, group resizing circuit 240 may divide the initial group of word lines into two search groups with the best read performance values, such that the read performance value of at least one of the two search groups meets a second threshold value TH2. Group resizing circuit 240 may then repeat the above search process for search groups whose read performance values do not meet the second threshold value TH2.

[0161] Reference Figure 10The group resizing circuit 240 may divide all k+m word lines WL in a memory block into two search groups k WL and m WL. For example, the group resizing circuit 240 may divide the k+m word lines WL so that the overall read performance value is optimized, and the read performance value 1 of one search group k WL (WLG1) of the search groups k WL and m WL satisfies the second threshold TH2.

[0162] The size of the search group k WLs ( WLG1 ) whose read performance value satisfies the second threshold TH2 may be fixed.

[0163] The group resizing circuit 240 may re-divide the search group m WL whose read performance values do not meet the second threshold TH2 into two search groups. For example, the group resizing circuit 240 may iteratively divide the word lines so that the overall read performance value is optimized and the read performance value of one search group WLG2 meets the second threshold TH2.

[0164] The group resizing concept of this embodiment may be a tree-based resizing method, and a tree may be generated with a depth equal to the number of groups to be grouped, N minus 1.

[0165] Figure 11 is a flowchart for describing a word line grouping method according to an embodiment of the present disclosure.

[0166] Reference Figure 11 , the word line grouping device 20 may acquire a default read voltage, which is threshold voltage distribution data of a memory block included in the specification of the memory device 120 , from the memory device 120 (operation S101 ).

[0167] The word line grouping device 20 may set an initial group number N, a first threshold TH1 , a second threshold TH2 , a third threshold TH3 , and a search direction (operation S103 ).

[0168] The initial group number N may be the initial group number of each memory block.

[0169] The first threshold TH1 may be an error correction capability of the memory controller 110. The second threshold TH2 may be a tolerance value of a read performance value of each group. The third threshold may be a standard value for terminating group size adjustment and fixing the group size.

[0170] The search direction may be a selected direction for searching a target group when adjusting the group size. Addresses may be assigned to word lines of a memory block in ascending order along a specific direction, and the group search direction may be selected from a direction in which word line addresses increase or a direction in which word line addresses decrease.

[0171] The word line grouping device 20 may perform initial grouping of word lines of each memory block according to the initial group number N ( S105 ). In an embodiment, the initialization circuit 210 may divide the word lines included in the memory block by the initial group number N to generate initial groups.

[0172] The word line grouping device 20 may determine (derive) a representative read voltage for optimizing read performance (eg, at least one of MAX FBC and RPR) based on results of respectively reading the initial groups of memory blocks by using a plurality of candidate read voltages (operation S107 ).

[0173] In an embodiment, the candidate read voltages may include a default read voltage and a plurality of offset voltages that offset the default read voltage by a specific amount.

[0174] In an embodiment, the read performance value may be determined as at least one of a maximum fail bit count (MAX FBC) and a read pass rate (RPR), and the representative read voltage may be determined based on a candidate read voltage that minimizes the maximum fail bit count (MAX FBC) and a candidate read voltage that maximizes the read pass rate (RPR).

[0175] The word line grouping device 20 may determine whether a read performance value obtained by reading data of the word lines of each group using the representative read voltage satisfies a second threshold value TH2 (operation S109 ).

[0176] If the read performance value does not meet the second threshold (i.e., "No" in operation S109), word line grouping apparatus 20 may change the size of the corresponding group, for example, by reducing the group size (operation S111). Furthermore, word line grouping apparatus 20 may determine whether the read performance value of the resized group meets the second threshold TH2 (operation S109). The fact that the read performance value of the group meets the second threshold TH2 can indicate that the read pass rate (RPR) obtained by reading data stored in the corresponding group using the representative read voltage is guaranteed to be above a certain level or the maximum fail bit count (MAX FBC) is guaranteed to be below a certain level.

[0177] If the read performance value satisfies the second threshold value TH2 (i.e., "Yes" in operation S109), the word line grouping device 20 may determine whether the read performance value of the corresponding group satisfies the third threshold value TH3, which is a fixed standard for the group (operation S113). The fact that the read performance value of the group satisfies the third threshold value TH3 may indicate that the read performance value of the corresponding group is very close to the second threshold value TH2.

[0178] When the read performance value satisfies the third threshold TH3 (ie, “Yes” in operation S113 ), the word line grouping device 20 may fix the size of the corresponding group and output a boundary word line address of the fixed group (operation S115 ).

[0179] When the read performance value of the search target group satisfies the second threshold value TH2 but does not satisfy the third threshold value TH3 (i.e., "No" in operation S113), for example, when the degree to which the read performance value satisfies the second threshold value TH2 is greater than the third threshold value TH3, the word line grouping device 20 may change the size of the corresponding group, for example, increase the size of the corresponding group (operation S111). The word line grouping device 20 may determine whether the read performance value of the group after the size change satisfies the second threshold value TH2 (operation S109).

[0180] The word line grouping device 20 may add or delete word lines physically adjacent to a corresponding group to change the group size.

[0181] When the read performance value of the expanded group does not satisfy the second threshold TH2 in operation S109 after the group size is fixed, the word line grouping device 20 may fix the group before expansion as the final group.

[0182] When the read performance values of all groups satisfy the second threshold TH2 , the word line grouping device 20 may terminate the group size adjustment and fix the groups.

[0183] A maximum value or a minimum value of word line addresses included in each fixed group may be output as a delimiter for each group.

[0184] Therefore, the word line grouping device 20 can group a plurality of word lines included in a memory block, thereby reading data of the word lines using a representative read voltage.

[0185] The embodiments of the present disclosure described above are intended to illustrate, not to limit, the embodiments of the present disclosure. Various alternatives and equivalents are possible. The present invention is not limited to the embodiments described herein. Nor is the present invention limited to any particular type of semiconductor device. Other additions, subtractions, or modifications apparent in light of this disclosure are intended to fall within the scope of the appended claims. Furthermore, the embodiments may be combined to form further embodiments.

Claims

1. A storage device, comprising: A memory device comprising a plurality of word lines; as well as The word line grouping device groups the plurality of word lines into a specific number of groups so that a read performance value obtained by reading data of word lines included in the same group using a representative read voltage satisfies a set tolerance value.

2. The storage device according to claim 1, wherein The word line grouping device comprises: a representative read voltage determination circuit that determines a representative read voltage for each group, the read performance value being optimized by the representative read voltage; and The group size adjustment circuit adjusts the size of each group so that the read performance value of each group meets the set tolerance value.

3. The storage device according to claim 1, wherein The read performance value includes a maximum fail bit count among fail bit counts of the word lines of each group for a plurality of candidate read voltages when data of the word lines in each group is read by using at least a portion of the plurality of candidate read voltages. The storage device according to claim 3 , wherein: The word line grouping device determines a candidate read voltage that minimizes the maximum fail bit count as the representative read voltage. The storage device according to claim 1 , wherein: The read performance value includes a read pass rate, which is a ratio of the number of word lines with failed bit counts within the error correction capability to the total number of word lines in each group for the multiple candidate read voltages when reading data of the word lines in each group by using at least a portion of the multiple candidate read voltages. The storage device according to claim 5 , wherein: The word line grouping device determines a candidate read voltage that maximizes the read pass rate as the representative read voltage.

7. The storage device according to claim 1, wherein: The word line grouping device fixes the size of the first group when a read performance value of a first group among the groups satisfies the set tolerance value and the read performance value of the first group satisfies a standard value set to terminate group size adjustment. The storage device according to claim 1 , wherein: When a read performance value of a second group among the groups satisfies the set tolerance value and the read performance value of the second group does not satisfy a standard value set to terminate group size adjustment, the word line grouping device expands the size of the second group.

9. The storage device according to claim 1, wherein: When a read performance value of a third group among the groups does not satisfy the set tolerance value, the word line grouping device reduces a size of the third group.

10. The storage device according to claim 1, wherein When the read performance values of all groups satisfy the set tolerance value, the word line grouping device fixes the sizes of all the groups.

11. A method for operating a storage device, the storage device comprising a memory device and a storage controller, the memory device comprising a plurality of word lines, the storage controller controlling the memory device, the method comprising: The memory controller groups the plurality of word lines into a specific number of groups; as well as The memory controller regroups the plurality of word lines so that a read performance value obtained by reading data of word lines included in the same group using a representative read voltage satisfies a set tolerance value.

12. The method according to claim 11, further comprising: determining the representative read voltage by which the read performance value of each group is optimized, The regrouping of the plurality of word lines includes adjusting the size of each group so that when data is read using the representative read voltage, the read performance value of each group satisfies the set tolerance value.

13. The method according to claim 11, wherein The read performance value is determined to include a maximum fail bit count among fail bit counts of the word lines of each group for a plurality of candidate read voltages when data of the word lines in each group is read by using at least a portion of the plurality of candidate read voltages.

14. The method according to claim 13, further comprising: A candidate read voltage that minimizes the maximum fail bit count is determined as the representative read voltage.

15. The method according to claim 11, wherein The read performance value is determined to include a read pass rate, the read pass rate being a ratio of the number of word lines for which a failure bit count is within an error correction capability to the total number of word lines within each group for the plurality of candidate read voltages when reading data of the word lines in each group by utilizing at least a portion of the plurality of candidate read voltages.

16. The method according to claim 15, further comprising: A candidate read voltage that maximizes the read pass rate is determined as the representative read voltage.

17. The method according to claim 11, further comprising: When a read performance value of a first group among the groups satisfies the set tolerance value and the read performance value of the first group satisfies a standard value set to terminate group size adjustment, the size of the first group is fixed.

18. The method of claim 11, further comprising: When the read performance value of a second group among the groups satisfies the set tolerance value and the read performance value of the second group does not satisfy the standard value set for terminating group size adjustment, the size of the second group is expanded.

19. The method of claim 11, further comprising: When the read performance value of a third group among the groups does not satisfy the set tolerance value, the size of the third group is reduced.

20. The method of claim 11, further comprising: When the read performance values of all groups satisfy the set tolerance value, the sizes of all groups are fixed.

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