Memory device, method of operating same, and method of operating non-volatile memory device

Abstract

A memory device, a method of operating the same, and a method of operating a non-volatile memory device are provided, the memory device including: a non-volatile memory device including a first plane and a second plane; and a memory controller configured to sequentially transmit a first command corresponding to a first operation of the first plane, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane to the nonvolatile memory device, the non-volatile memory device is configured to perform a third operation before the second operation based on the first command, the second command, and the third command.

Description

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0022397 filed on February 16, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor memory, and more particularly, to a memory device including a nonvolatile memory device, an operating method thereof, and an operating method of the nonvolatile memory device. Background Art

[0003] Semiconductor memories are classified as either volatile memory devices that lose data stored therein when power is removed (such as static random access memory (SRAM), dynamic RAM (DRAM), or synchronous DRAM (SDRAM)) or nonvolatile memories that retain data stored therein even when power is removed (such as read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)).

[0004] Flash memory devices are widely used as high-capacity storage media in user devices. With the advancement of computing technology, high-capacity storage media based on flash memory are required to have improved performance. Various technologies and devices are being developed to improve the performance of high-capacity storage media based on flash memory. Summary of the Invention

[0005] Provided are a memory device including a nonvolatile memory device having improved performance, an operating method thereof, and an operating method of the nonvolatile memory device.

[0006] According to one aspect of the disclosure, a storage device includes: a non-volatile memory device including a first plane and a second plane; and a storage controller configured to: sequentially send a first command corresponding to a first operation of the first plane, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane to the non-volatile memory device, wherein the non-volatile memory device is configured to: perform the third operation before the second operation based on the first command, the second command, and the third command.

[0007] According to one aspect of the disclosure, a method for operating a storage device includes: sequentially sending, by a storage controller of the storage device, a first command corresponding to a first operation of a first plane of a non-volatile memory device of the storage device, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane of the non-volatile memory device to the non-volatile memory device; and performing, by the non-volatile memory device, a third operation before the second operation based on the first command, the second command, and the third command.

[0008] According to one aspect of the disclosure, a method for operating a non-volatile memory device including a first plane and a second plane includes: sequentially receiving a first command corresponding to a first operation of the first plane, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane; queuing a first operation command corresponding to the first command, a second operation command corresponding to the second command, and a third operation command corresponding to the third command into a command queue, wherein the first operation command, the second operation command, and the third operation command are queued in the order in which the first operation command, the second operation command, and the third operation command are received; and executing the first operation, the second operation, and the third operation based on the order of the first operation command, the second operation command, and the third operation command, regardless of the order in which the first command, the second command, and the third command are received. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0011] Figure 2 It shows Figure 1 A block diagram of a nonvolatile memory device.

[0012] Figure 3 It shows Figure 2 Circuit diagram of the memory block.

[0013] Figure 4 is used to describe Figure 1 A diagram of an example of the operation of a storage device.

[0014] Figure 5 is used to describe Figure 1 A diagram of the operation of a storage device.

[0015] Figure 6 is used to describe Figure 5 A flowchart of an example method of operation of a storage controller is provided.

[0016] Figure 7A and Figure 7B is used to describe Figure 5 A block diagram of the operation of a nonvolatile memory device.

[0017] Figure 8 is used to describe Figure 1 FIG. 1 is a diagram of another example of the operation of a storage device.

[0018] Figure 9 is used to describe Figure 1 FIG. 1 is a diagram of another example of the operation of a storage device.

[0019] Figure 10 is used to describe Figure 1 Flowchart of a method for operating a non-volatile memory device.

[0020] Figure 11 It is used to describe in detail Figure 10 Flowchart of operation S230.

[0021] Figure 12 is used to describe Figure 1 FIG. 1 is a diagram of another example of the operation of a storage device.

[0022] Figure 13 is used to describe Figure 12 A flowchart of an example of the operation of a storage device.

[0023] Figure 14 is used to describe Figure 1 FIG. 1 is a diagram of another example of the operation of a storage device.

[0024] Figure 15 is used to describe Figure 14 A flow chart of the operation of a storage controller.

[0025] Figure 16 is a diagram for describing another example of the operation of the storage device according to an embodiment of the present disclosure.

[0026] Figure 17 is used to describe Figure 16 A flow chart of the operation of a storage controller.

[0027] Figure 18 is a block diagram illustrating a storage device according to an embodiment of the present disclosure.

[0028] Figure 19 is a diagram illustrating a data center to which a memory device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that those skilled in the art can easily perform the present disclosure.

[0030] In the specification, functional blocks corresponding to the terms "block", "unit", "logic", etc. in the drawings, respectively, can be implemented in the form of software, hardware, or a combination thereof. As used herein, multiple "units", multiple "modules", multiple "components", and multiple "blocks" can be implemented as a single component, or a single "unit", a single "module", a single "component", and a single "block" can include multiple components.

[0031] It will be understood that when an element is referred to as being “connected” or “connected” to another element, it may be directly or indirectly connected to the other element, wherein an indirect connection may include “connection via a wireless communication network”.

[0032] In addition, when a component “includes” or “comprises” an element, unless there is a specific description contrary thereto, the component may further include other elements, rather than excluding other elements.

[0033] Throughout the specification, when a member is “on” another member, this includes not only a case where the member is in contact with another member but also a case where another member exists between the two members.

[0034] As used herein, the expressions "at least one of a, b, or c" and "at least one of a, b, and c" indicate "only a," "only b," "only c," "both a and b," "both a and c," "both b and c," and "all of a, b, and c."

[0035] It will be understood that although the terms "first," "second," "third," etc. may be used herein to describe various elements, the disclosure should not be limited by these terms. These terms are only used to distinguish one element from another.

[0036] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0037] With respect to any method or process described herein, identification codes may be used for ease of description, but are not intended to specify the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be performed in an order different from the order shown. Unless the context of the disclosure clearly indicates otherwise, one or more steps or operations may be omitted.

[0038] Figure 1 is a block diagram illustrating a storage device according to an embodiment of the present disclosure. Figure 1, the storage device 100 may include a storage controller 110 and a non-volatile memory device (NVM) 120. In one embodiment, the storage device 100 may be a high-capacity storage medium such as a solid-state drive (SSD), a memory card, or a memory stick.

[0039] The memory controller 110 may control all operations of the memory device 100. For example, based on a request from an external host, the memory device 100 may store data "DATA" in the non-volatile memory device 120 or read data "DATA" stored in the non-volatile memory device 120. For example, the memory controller 110 may provide an address ADDR, a command CMD, and a control signal CTRL to the non-volatile memory device 120, and may exchange data "DATA" with the non-volatile memory device 120. In one embodiment, for efficient operation of the memory device 100, the memory controller 110 may perform various maintenance operations (e.g., wear leveling, garbage collection, and bad block management).

[0040] Under the control of the memory controller 110, the nonvolatile memory device 120 may store data "DATA" or may output the stored data "DATA." In one embodiment, the nonvolatile memory device 120 may include a NAND flash memory. However, the present disclosure is not limited thereto.

[0041] The nonvolatile memory device 120 may include a memory cell array 121 and control logic 123. The memory cell array 121 may include first to fourth planes PL1 to PL4. Each of the first to fourth planes PL1 to PL4 may include multiple memory blocks. In one embodiment, the multiple memory blocks included in the first plane PL1 may share the same bit line, the multiple memory blocks included in the second plane PL2 may share the same bit line, the multiple memory blocks included in the third plane PL3 may share the same bit line, and the multiple memory blocks included in the fourth plane PL4 may share the same bit line.

[0042] Control logic 123 controls all operations of non-volatile memory device 120. Control logic 123 generates signals for controlling memory cell array 121. Control logic 123 can be implemented as a digital signal processor (DSP), a microprocessor, and a time controller (TCON) that processes digital signals. However, the disclosure is not limited thereto, and control logic 123 may include one or more of a central processing unit (CPU), a microcontroller unit (MCU), a microprocessing unit (MPU), a controller, an application processor (AP), a graphics processor (GPU), a communication processor (CP), and an advanced reduced instruction set computer (RISC) machine (ARM) processor, or may be defined by these terms. Furthermore, control logic 123 may be implemented as a system-on-chip (SoC) or large-scale integrated circuit (LSI) with stored processing algorithms, or in the form of a field-programmable gate array (FPGA). Control logic 123 can perform various functions by executing computer-executable instructions stored in cache or memory.

[0043] In one embodiment, the nonvolatile memory device 120 according to the present disclosure can perform independent operations on each of the first to fourth planes PL1 to PL4 under the control of the control logic 123. Specifically, for example, the nonvolatile memory device 120 can simultaneously (i.e., in parallel) perform read operations on the first to fourth planes PL1 to PL4. In other words, the nonvolatile memory device 120 can perform read operations using multi-plane operations. Furthermore, for example, the nonvolatile memory device 120 can begin performing a read operation on the second plane PL2 while a read operation on the first plane PL1 is already being performed. In other words, the nonvolatile memory device 120 can perform read operations using a plane independent read (PIR) operation.

[0044] The nonvolatile memory device 120 may perform operations on the first to fourth planes PL1 to PL4 in response to a command CMD from the memory controller 110. For example, the nonvolatile memory device 120 may sequentially receive a first read command for the first plane PL1, a second read command for the first plane PL1, and a third read command for the second plane PL2 from the memory controller 110.

[0045] Because the first and second read commands correspond to the same plane (i.e., first plane PL1), the first and second read commands may not be processed simultaneously. However, because the first and third read commands correspond to different planes PL1 and PL2, the first and third read commands may be processed simultaneously through multi-plane operations.

[0046] Even if the nonvolatile memory device 120 is capable of processing the first read command and the third read command simultaneously, the nonvolatile memory device 120 may process the first read command and the third read command in order. That is, the nonvolatile memory device 120 may complete the first read operation of the first plane PL1 in response to the first read command, may complete the second read operation of the first plane PL1 in response to the second read command, and may complete the third read operation of the second plane PL2 in response to the third read command.

[0047] In this case, the operation speed of the nonvolatile memory device 120 may be relatively slow compared to a case where the first and third read commands are processed simultaneously (i.e., the first read operation of the first plane PL1 and the third read operation of the second plane PL2 are performed simultaneously) and the second read command is processed. In other words, when the nonvolatile memory device 120 processes commands from the memory controller 110 out of order, the performance of the nonvolatile memory device 120 may be improved.

[0048] The nonvolatile memory device 120 according to an embodiment of the present disclosure may change the order of processing commands CMD received from the memory controller 110 under the control of the control logic 123. That is, the nonvolatile memory device 120 according to an embodiment of the present disclosure may process the commands CMD received from the memory controller 110 in a non-sequential manner under the control of the control logic 123.

[0049] The control logic 123 may include a command queue 123a and a command reordering module 123b. Commands CMD from the storage controller 110 may be added to the command queue 123a. The command reordering module 123b may combine entries stored in the command queue 123a and determine the order in which to process the commands CMD. The operations of the command queue 123a and the command reordering module 123b will be described in detail with reference to FIG.

[0050] Figure 2 It shows Figure 1 A block diagram of a nonvolatile memory device. Figure 1 and Figure 2 , the nonvolatile memory device 120 may include a memory cell array 121 , an address decoder 122 , a control logic 123 , a page buffer 124 , a voltage generator 125 , and an input / output (I / O) circuit 126 .

[0051] The memory cell array 121 may include first to fourth planes PL1 to PL4. Each of the first to fourth planes PL1 to PL4 may include a plurality of memory blocks BLK. In each of the first to fourth planes PL1 to PL4, each of the plurality of memory blocks BLK may be connected to the address decoder 122 via a word line WL and a string select line SSL.

[0052] The plurality of memory blocks BLK included in the first plane PL1 may be connected to the page buffer 124 via a first bit line BL1. That is, the plurality of memory blocks BLK included in the first plane PL1 may share the first bit line BL1. The plurality of memory blocks BLK included in the second plane PL2 may be connected to the page buffer 124 via a second bit line BL2. That is, the memory blocks BLK included in the second plane PL2 may share the second bit line BL2. The plurality of memory blocks BLK included in the third plane PL3 may be connected to the page buffer 124 via a third bit line BL3. That is, the memory blocks BLK included in the third plane PL3 may share the third bit line BL3. The plurality of memory blocks BLK included in the fourth plane PL4 may be connected to the page buffer 124 via a fourth bit line BL4. That is, the memory blocks BLK included in the fourth plane PL4 may share the fourth bit line BL4.

[0053] The address decoder 122 may be connected to the memory cell array 121 through the string selection lines SSL, the word lines WL, and the ground selection lines GSL. The address decoder 122 may control or drive the string selection lines SSL, the word lines WL, and the ground selection lines GSL.

[0054] The control logic 123 may control the operation of the nonvolatile memory device 120 in response to a command CMD, a control signal CTRL, and an address ADDR from the memory controller 110. For example, the control logic 123 may control the address decoder 122, the page buffer 124, the voltage generator 125, and the input / output circuit 126 in response to the command CMD so that an operation corresponding to the command CMD (e.g., a program operation, a read operation, or an erase operation) is performed. The control logic 123 may provide a row address to the address decoder 122, a column address to the page buffer 124, and a voltage control signal CTRL_Vol to the voltage generator 125. In addition, as described with reference to FIG. Figure 1 As described, the control logic 123 may combine commands based on the command queue 123 a and the command reordering module 123 b and may reorder the order of the commands.

[0055] The page buffer 124 is connected to the memory block BLK included in the first plane PL1 through a first bit line BL1, to the memory block BLK included in the second plane PL2 through a second bit line BL2, to the memory block BLK included in the third plane PL3 through a third bit line BL3, and to the memory block BLK included in the fourth plane PL4 through a fourth bit line BL4. The page buffer 124 can temporarily store data to be stored in the memory cell array 121 or data read from the memory cell array 121.

[0056] The voltage generator 125 may generate various voltages for performing write operations, read operations, and erase operations on the memory cell array 121 based on the voltage control signal CTRL_Vol. In detail, the voltage generator 125 may be configured to generate word line voltages VWL (e.g., a plurality of program voltages, a plurality of program verification voltages, a plurality of pass voltages, a plurality of read voltages, and a soft erase voltage, etc.).

[0057] The input / output circuit 126 may be connected to the page buffer 124 through the data line DL and may exchange data "DATA" with the page buffer 124 through the data line DL. Under the control of the control logic 123, the input / output circuit 126 may transmit the data "DATA" to the memory controller 110 or may receive the data "DATA" from the memory controller 110.

[0058] In one embodiment, the non-volatile memory device 120 may receive commands / addresses CMD / ADDR from the memory controller 110 via a first transmission path and may exchange data "DATA" with the memory controller 110 via a second transmission path. That is, in one embodiment, the lines through which the non-volatile memory device 120 receives commands / addresses CMD / ADDR and the lines through which the non-volatile memory device 120 exchanges data "DATA" may be separate from each other. In one embodiment, the non-volatile memory device 120 may include command / address pins for receiving commands / addresses CMD / ADDR separately from the data input / output pins. However, the present disclosure is not limited thereto. For example, the non-volatile memory device 120 may receive all of the data "DATA", the command CMD, and the address ADDR from the memory controller 110 via the data input / output pins.

[0059] Figure 3 It shows Figure 2 A memory block BLK will refer to Figure 3 is described, but the present disclosure is not limited thereto. Figure 2 The plurality of memory blocks BLK in the memory cell array 121 may have Figure 3 The structure of the memory block BLK is similar or identical to that of Figure 2 and Figure 3 , the memory block BLK may include a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged in row and column directions.

[0060] Cell strings located in the same column among the plurality of cell strings CS11, CS12, CS21, and CS22 may be connected to the same bit line. Figure 3 The memory block BLK is included in Figure 2 The memory blocks in the first plane PL1, Figure 3 The bit line BL may correspond to Figure 2 Each of the plurality of cell strings CS11, CS12, CS21, and CS22 includes a plurality of cell transistors. Each of the plurality of cell transistors may be a charge trap flash (CTF) memory cell transistor, but the present disclosure is not limited thereto. The plurality of cell transistors may be stacked on a plane (e.g., a semiconductor substrate) defined by row and column directions.

[0061] Multiple cell transistors in each cell string may be connected in series between a corresponding bit line (e.g., BL1 or BL2) and a common source line CSL. For example, the multiple cell transistors may include string select transistors SSTa and SSTb, dummy memory cells DMC1 and DMC2, memory cells MC1 to MC8, and ground select transistors GSTa and GSTb. The series-connected string select transistors SSTa and SSTb may be disposed or connected between the series-connected memory cells MC1 to MC8 and the corresponding bit lines (e.g., BL1 and BL2). The series-connected ground select transistors GSTa and GSTb may be disposed or connected between the series-connected memory cells MC1 to MC8 and the common source line CSL.

[0062] In each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 , memory cells located at the same height among the memory cells MC1 to MC8 may share the same word line (eg, one of the word lines WL1 to WL8 ).

[0063] Dummy memory cells located at the same height among the dummy memory cells DMC1 and DMC2 of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may share the same dummy word line (eg, dummy word line DWL1 or DWL2 ).

[0064] String selection transistors SSTa and SSTb of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 at the same height and in the same row may share the same string selection line (eg, string selection line SSL1 a , SSL1 b , SSL2 a , or SSL2 b ).

[0065] String selection transistors located in the same row among the string selection transistors SSTa and SSTb of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may share the same string selection line.

[0066] Ground selection transistors positioned at the same height and in the same row among the ground selection transistors GSTa and GSTb of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may be connected to the same ground selection line.

[0067] The ground selection transistors GSTa and GSTb of the multiple cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line. Alternatively, the ground selection transistors GSTa and GSTb of the multiple cell strings CS11, CS12, CS21, and CS22 located at the same height may share the same ground selection line. Alternatively, the ground selection transistors GSTa and GSTb of the multiple cell strings CS11, CS12, CS21, and CS22 located in the same row may share the same ground selection line.

[0068] Figure 4 is used to describe Figure 1 An example diagram of the operation of a storage device. Figure 4 In the example of FIG, the memory controller 110 and the non-volatile memory device 120 may exchange commands / addresses and data via the transmission path CADP. Figure 4 Before the 0th time point t0, the storage device 100 may sequentially receive the first request REQ1 to the third request REQ3 from the external host 200.

[0069] For example, before the 0th time point t0, the memory controller 110 and the non-volatile memory device 120 may perform data transmission / reception through the transmission path CADP. Therefore, before the 0th time point t0, the memory controller 110 may not be able to transmit commands corresponding to the first request REQ1 to the third request REQ3 to the non-volatile memory device 120.

[0070] For example, the first request REQ1 may be a request for a first read operation for the first plane PL1 , the second request REQ2 may be a request for a second read operation for the first plane PL1 , and the third request REQ3 may be a request for a third read operation for the second plane PL2 .

[0071] The first plane PL1 targeted by the first read operation may be different from the second plane PL2 targeted by the third read operation. Therefore, the first and third read operations can be performed simultaneously. The first plane PL1 targeted by the first read operation may be the same as the first plane PL1 targeted by the second read operation. Therefore, the first and second read operations cannot be performed simultaneously.

[0072] The memory controller 110 may generate first to third read commands RD1 to RD3 corresponding to the first to third requests REQ1 to REQ3 in response to the first to third requests REQ1 to REQ3. That is, the first read command RD1 may correspond to the first request REQ1 and may be a command for a first read operation, the second read command RD2 may correspond to the second request REQ2 and may be a command for a second read operation, and the third read command RD3 may correspond to the third request REQ3 and may be a command for a third read operation.

[0073] At the 0th time point t0, data transmission / reception between the memory controller 110 and the nonvolatile memory device 120 may be terminated. Therefore, during the first command transmission period tCT1 from the 0th time point t0, the memory controller 110 may transmit a first read command RD1 to the nonvolatile memory device 120.

[0074] Thereafter, during a first time interval ti1, the nonvolatile memory device 120 may perform a first read operation in response to the first read command RD1. The first time interval ti1 may include a first read period tRD1 and a first data output period tDO1. For example, the nonvolatile memory device 120 may read data of the first plane PL1 during the first read period tRD1 and may store the read data in the page buffer 124 (refer to FIG. Figure 2 During the first data output period tDO1, the nonvolatile memory device 120 transmits the data stored in the page buffer 124 (refer to Figure 2 ) is output to the storage controller 110.

[0075] The memory controller 110 may detect that the first plane PL1 corresponding to the first read operation is different from the second plane PL2 corresponding to the third read operation. Therefore, the memory controller 110 may determine that the first and third read operations can be performed simultaneously. In this case, the memory controller 110 may send the third read command RD3 to the non-volatile memory device 120 while the first read operation is being performed (in other words, before the first read operation is completed). In other words, the memory controller 110 may send the first to third read commands RD1 to RD3 non-sequentially.

[0076] In this case, during the second time interval ti2, the nonvolatile memory device 120 may perform a third read operation in response to the third read command RD3. The second time interval ti2 may include a third read period tRD3 and a third data output period tDO3. That is, the nonvolatile memory device 120 may perform the first and third read operations through a PIR operation.

[0077] After the second time interval ti2 , the memory controller 110 may send a second read command RD2 to the nonvolatile memory device 120 during a second command transmission period tCT2 .

[0078] Thereafter, during a third time interval ti3, the nonvolatile memory device 120 may perform a second read operation in response to the second read command RD2. The third time interval ti3 may include a second read period tRD2 and a second data output period tDO2.

[0079] and Figure 4 Unlike the example shown in , the memory controller 110 may sequentially transmit the first to third read commands RD1 to RD3 to the nonvolatile memory device 120. In this case, even if the first and third read operations can be performed simultaneously, the nonvolatile memory device 120 may sequentially perform the first and third read operations. Specifically, the nonvolatile memory device 120 may complete the first read operation, complete the second read operation, and complete the third read operation. In this case, the performance of the memory controller 110 may be reduced compared to a case where the memory controller 110 transmits commands to the nonvolatile memory device 120 in a non-sequential manner.

[0080] like Figure 4 As shown in , when the storage controller 110 transmits commands in a non-sequential manner, performance degradation can be addressed. However, in this case, for example, the storage controller 110 should determine whether the command is targeted for a PIR operation (i.e., whether the target plane of the read command is different). Therefore, the storage controller 110 may include a logic circuit for analyzing the command. In this case, as the capacity of the non-volatile memory device 120 increases, the complexity of the logic circuit of the storage controller 110 may increase. In other words, when the non-sequential operation of the non-volatile memory device 120 is implemented based on the operation of the storage controller 110, the complexity of the logic circuit of the storage controller 110 may increase.

[0081] According to an embodiment of the present disclosure, the non-volatile memory device 120 can sequentially receive commands CMD from the memory controller 110. The non-volatile memory device 120 can independently and non-sequentially perform operations corresponding to the commands CMD. That is, according to an embodiment of the present disclosure, the memory device 100 can implement non-sequential operations of the non-volatile memory device 120 without increasing the complexity of the logic circuit of the memory device 100.

[0082] The operation of the memory device 100 according to an embodiment of the present disclosure will be described in detail with reference to the following drawings.

[0083] Figure 5 is used to describe Figure 1 Schematic diagram of the operation of the storage device. Figures 1 to 3 and Figure 5 , the memory controller 110 and the nonvolatile memory device 120 may exchange commands and addresses through the first transmission path CAP. The memory controller 110 and the nonvolatile memory device 120 may exchange data “DATA” through the second transmission path DP.

[0084] For example, the first transmission path CAP may be a path passing through the command / address pins. For example, the second transmission path DP may be a path passing through the data input / output pins. The first transmission path CAP and the second transmission path DP or the command / address pins and the data input / output pins may be physically distinguished from each other. In other words, the line (e.g., CAP) through which the storage controller 110 transmits the command / address to the non-volatile memory device 120 may be distinguished from the line (e.g., DP) through which the storage controller 110 transmits the data "DATA" to the non-volatile memory device 120. However, the present disclosure is not limited thereto. For example, Figure 4 As shown in , the command / address pins and the data input / output pins may be implemented in a structure in which the command / address pins and the data input / output pins are not distinguished from each other.

[0085] return Figure 5 Before the 0th time point t0 , the storage device 100 may sequentially receive the first to third requests REQ1 to REQ3 from the external host 200 .

[0086] Before the 0th time point t0 , the memory controller 110 and the nonvolatile memory device 120 may exchange data “DATA” through the second transfer path DP.

[0087] For example, the first request REQ1 may be a request for a first read operation for the first plane PL1 , the second request REQ2 may be a request for a second read operation for the first plane PL1 , and the third request REQ3 may be a request for a third read operation for the second plane PL2 .

[0088] The memory controller 110 may generate first to third enqueue commands EQ1 to EQ3 corresponding to the first to third requests REQ1 to REQ3 in response to the first to third requests REQ1 to REQ3. For example, the first enqueue command EQ1 may correspond to the first request REQ1 and may be a command for a first read operation, the second enqueue command EQ2 may correspond to the second request REQ2 and may be a command for a second read operation, and the third enqueue command EQ3 may correspond to the third request REQ3 and may be a command for a third read operation.

[0089] In one embodiment, an enqueue command (e.g., EQ1 to EQ3) may include an operation command OCMD and operation command information OCMD_info. In response to the enqueue command (e.g., EQ1, EQ2, or EQ3), the nonvolatile memory device 120 may store the operation command OCMD and operation command information OCMD_info corresponding to the enqueue command (e.g., EQ1, EQ2, or EQ3) in the command queue 123a (e.g., this is referred to as "queuing"). In one embodiment, the operation command information OCMD_info may include a processing priority of the operation command OCMD, an address ADDR of the operation command OCMD, and a queue identifier QID.

[0090] For example, the first enqueue command EQ1 may include a first read command RD1 as the operation command OCMD and first read command information. For example, the first read command information may include information indicating that the queue identifier QID of the first read command RD1 is "1," the address ADDR is associated with the first block B1 of the first plane PL1 of the nonvolatile memory device 120, and the processing priority is the first priority P1.

[0091] As described above, since the path through which commands / addresses are transmitted (i.e., the first transmission path CAP) and the path through which data "DATA" is transmitted (i.e., the second transmission path DP) are distinguished from each other, the memory controller 110 can transmit commands to the nonvolatile memory device 120 while transmission / reception of data "DATA" is being performed. Therefore, before the 0th time point t0, the memory controller 110 can transmit the first to third enqueue commands EQ1 to EQ3 to the nonvolatile memory device 120.

[0092] For example, the nonvolatile memory device 120 may store a first read command RD1 in the command queue 123a in response to a first enqueue command EQ1. The nonvolatile memory device 120 may store a second read command RD2 in the command queue 123a in response to a second enqueue command EQ2. The nonvolatile memory device 120 may store a third read command RD3 in the command queue 123a in response to a third enqueue command EQ3. The first read command RD1 may correspond to a first read operation, the second read command RD2 may correspond to a second read operation, and the third read command RD3 may correspond to a third read operation. That is, the first read command RD1 and the second read command RD2 may be commands for the first plane PL1, and the third read command RD3 may be a command for the second plane PL2.

[0093] In other words, the nonvolatile memory device 120 may sequentially store the operation commands RD1 to RD3 included in the first to third enqueue commands EQ1 to EQ3 in the command queue 123 a .

[0094] At the 0th time point t0 , data transmission / reception between the memory controller 110 and the nonvolatile memory device 120 may be terminated.

[0095] During the 0th time interval ti0 starting from the 0th time point t0, the nonvolatile memory device 120 may generate a first combined command CCMD1 based on the first to third read commands RD1 to RD3 stored in the command queue 123a. The first combined command CCMD1 may be a command generated by combining the first read command RD1 and the third read command RD3. The first combined command CCMD1 may be a multi-plane command for the first plane PL1 and the second plane PL2. For example, the nonvolatile memory device 120 may combine the first read command RD1 and the third read command RD3 based on the fact that the target plane of the first read operation (i.e., the first plane PL1) is different from the target plane of the third read operation (i.e., the second plane PL2).

[0096] Reference Figure 5 The nonvolatile memory device 120 is described as generating the first combined command CCMD1 after the transmission / reception of the data "DATA" is terminated, but the present disclosure is not limited thereto. In one embodiment, the nonvolatile memory device 120 may generate the first combined command CCMD1 based on the entry of the command queue 123a while the transmission / reception of the data "DATA" is being performed (i.e., before the 0th time point t0).

[0097] Thereafter, during the first time interval ti1, the nonvolatile memory device 120 may simultaneously perform the first read operation and the third read operation based on the first combined command CCMD1. For example, during the first read period tRD1, the nonvolatile memory device 120 may read data of the first plane PL1 and may store the read data in the page buffer 124 (refer to Figure 2 ). In addition, during the third read period tRD3, the nonvolatile memory device 120 may read data of the second plane PL2 and may store the read data in the page buffer 124 (refer to Figure 2 During the first data output period tDO1, the nonvolatile memory device 120 may transmit the data corresponding to the first read operation and stored in the page buffer 124 (refer to Figure 2 ) to the memory controller 110. During the third data output period tDO3, the nonvolatile memory device 120 may transmit the data corresponding to the third read operation and stored in the page buffer 124 (refer to Figure 2 ) is output to the memory controller 110. That is, the nonvolatile memory device 120 may perform the first read operation and the third read operation in parallel.

[0098] Thereafter, during the second time interval ti2, the nonvolatile memory device 120 may perform a second read operation based on the second read command RD2. Specifically, during the second read period tRD2, the nonvolatile memory device 120 may read data of the second plane PL2 and may store the read data in the page buffer 124 (refer to Figure 2 During the second data output period tDO2, the nonvolatile memory device 120 may transmit the data corresponding to the second read operation and stored in the page buffer 124 (refer to Figure 2 ) is output to the storage controller 110.

[0099] As described above, the nonvolatile memory device 120 may perform a third read operation before the second read operation. Figure 5 As shown in , the nonvolatile memory device 120 may perform the first and third read operations before the second read operation. In other words, the nonvolatile memory device 120 according to an embodiment of the present disclosure may process the operation commands RD1 to RD3 stored in the command queue 123a in a non-sequential manner.

[0100] According to an embodiment of the present disclosure, the memory controller 110 may sequentially transmit first to third enqueue commands EQ1 to EQ3 corresponding to first to third requests REQ1 to REQ3 from the host 200 to the nonvolatile memory device 120 .

[0101] The nonvolatile memory device 120 can change the order in which the first to third read commands RD1 to RD3 corresponding to the first to third enqueue commands EQ1 to EQ3 are processed, regardless of the order in which the first to third enqueue commands EQ1 to EQ3 are received, and can combine the first read command RD1 and the third read command RD3. In other words, the nonvolatile memory device 120 can perform operations corresponding to commands sequentially received from the memory controller 110 in a non-sequential manner. Therefore, the performance of the memory device 100 can be improved without increasing the complexity of the logic circuit of the memory controller 110.

[0102] Furthermore, according to an embodiment of the present disclosure, a transmission path (i.e., a first transmission path CAP) through which commands / addresses are transmitted between the memory controller 110 and the non-volatile memory device 120 can be distinguished from a transmission path (i.e., a second transmission path DP) through which data "DATA" is sent / received between the memory controller 110 and the non-volatile memory device 120. Therefore, the memory controller 110 can transmit the first to third enqueue commands EQ1 to EQ3 to the non-volatile memory device 120 when data is exchanged through the second transmission path DP. That is, according to the present disclosure, Figure 4 Unlike the case of , after the transmission / reception of the data "DATA" is terminated, the read command may not be transmitted separately (that is, after the transmission / reception of the data "DATA" is terminated, the command transmission periods tCT1 and tCT2 are not separately required). Therefore, the memory device 100 can operate at high speed.

[0103] and Figure 5 Unlike the example shown in FIG, in one embodiment, the first to third requests REQ1 to REQ3 may need to be processed in the order in which they are received from the host 200. In this case, the memory controller 110 may not generate the first to third enqueue commands EQ1 to EQ3. The memory controller 110 may send the first to third read commands RD1 to RD3 instead of the first to third enqueue commands EQ1 to EQ3 to the non-volatile memory device 120. In this case, the non-volatile memory device 120 may process the first to third read commands RD1 to RD3 according to the order in which they are received.

[0104] Figure 6 is used to describe Figure 5 Flowchart of an example of an operating method of a storage controller. In detail, Figure 6EQ1 to EQ3 is a flowchart for describing an example of an operation of the storage controller 110 to generate enqueue commands (eg, EQ1 to EQ3). Figure 5 and Figure 6 In operation S110 , the memory controller 110 may receive a request REQ from an external host 200 .

[0105] In operation S120, the memory controller 110 may determine whether data is being transferred via the second transfer path DP (i.e., whether data transmission / reception is being performed). When data is being transferred via the second transfer path DP, the memory controller 110 may perform operation S130. When data is not being transferred via the second transfer path DP, the memory controller 110 may not generate an enqueue command EQ. In other words, when data is not being transferred via the second transfer path DP, the memory controller 110 may not send an enqueue command EQ to the nonvolatile memory device 120.

[0106] In one embodiment, when data is not transferred through the second transfer path DP, the memory controller 110 may send an operation command (eg, a write command, a read command, or an erase command) to the nonvolatile memory device 120 instead of the enqueue command EQ.

[0107] In operation S130, the memory controller 110 may determine whether the request REQ from the host 200 corresponds to a write operation. When the request REQ corresponds to a write operation, the memory controller 110 may not send an enqueue command (e.g., EQ1, EQ2, or EQ3). When the request REQ does not correspond to a write operation, the memory controller 110 may send an enqueue command EQ to the nonvolatile memory device 120 in operation S140.

[0108] In one embodiment, when the request REQ from the host 200 corresponds to a write operation, the memory controller 110 may transmit write data and a write command to the nonvolatile memory device 120 after data transmission through the second transfer path DP is terminated.

[0109] exist Figure 6 , the memory controller 110 is shown as an example in which the memory controller 110 can transmit an enqueue command (e.g., EQ1, EQ2, or EQ3) to the non-volatile memory device 120 only when data is being transmitted through the second transmission path DP, but the present disclosure is not limited thereto. That is, in another embodiment, the memory controller 110 may send an enqueue command (e.g., EQ1, EQ2, or EQ3) to the non-volatile memory device 120 even if data is not being transmitted through the second transmission path DP.

[0110] Figure 7A and Figure 7B is used to describe Figure 5A block diagram of the operation of a nonvolatile memory device will be referred to. Figures 1 to 3 、 Figure 5 and Figure 6 To describe Figure 7A and Figure 7B . Reference Figure 7A , the control logic 123 of the nonvolatile memory device 120 may include a command queue 123 a , a command reordering module 123 b , and a command sequencer 123 c .

[0111] As reference Figure 5 As described above, the command queue 123a may store the operation command OCMD and the operation command information (eg, Figure 5 OCMD_info).

[0112] For example, the first read command RD1 may be included in the first enqueue command EQ1 , the second read command RD2 may be included in the second enqueue command EQ2 , and the third read command RD3 may be included in the third enqueue command EQ3 .

[0113] For example, the first read command RD1 may be a command having a first priority level P1 and associated with the first block B1 of the first plane PL1. For example, the second read command RD2 may be a command having a second priority level P2 and associated with the second block B2 of the first plane PL1. For example, the third read command RD3 may be a command having a first priority level P1 and associated with the third block B3 of the second plane PL2. For example, the first priority level P1 may have a higher processing priority than the second priority level P2.

[0114] In one embodiment, the command queue 123a may be implemented as a first-in-first-out (FIFO) queue type.

[0115] In one embodiment, the command queue 123a can be implemented as a circular queue type with a head pointer and a tail pointer indicating the start and end of the command lines stored in the queue, respectively. However, the present disclosure is not limited thereto. For example, the command queue 123a can be implemented in various types.

[0116] In one embodiment, Figure 7AUnlike the example shown in , command queue 123a may include multiple subqueues corresponding to priorities. Specifically, for example, command queue 123a may include a first subqueue and a second subqueue. The first subqueue may correspond to a first priority level P1, and the second subqueue may correspond to a second priority level P2. In one embodiment, control logic 123 may store operation commands OCMD (e.g., RD1 and RD3) with a first priority level P1 in the first subqueue, and may store operation commands OCMD (e.g., RD2) with a second priority level P2 in the second subqueue.

[0117] For example, the command reordering module 123b may generate a combined command by combining the operation commands OCMD that can be processed simultaneously. The command reordering module 123b may receive queue command information QCI from the command queue 123a. For example, the queue command information QCI may include the operation command OCMD stored in the command queue 123a and a plurality of operation command information (e.g., Figure 5 OCMD_info). The command reordering module 123b may determine the order in which to process the operation commands OCMD based on the queue command information QCI. Furthermore, the command reordering module 123b may combine the operation commands OCMD based on the queue command information QCI. For example, the command reordering module 123b may combine the operation commands OCMD to generate a first combined command CCMD1. In other words, the command reordering module 123b may reorder the operation commands OCMD based on the queue command information QCI.

[0118] The command reordering module 123 b may classify the operation command OCMD based on its command type (ie, whether the operation command OCMD indicates a read operation or an erase operation), its processing priority, and a plane corresponding to the operation command OCMD.

[0119] For example, the plane corresponding to the first read command RD1 (i.e., first plane PL1) may be different from the plane corresponding to the third read command RD3 (i.e., second plane PL2). Furthermore, the first read command RD1 and the third read command RD3 may have the same processing priority (i.e., first priority P1). In other words, the first read command RD1 and the third read command RD3 may be processed simultaneously.

[0120] The plane corresponding to the second read command RD2 may be the same as the plane corresponding to the first read command RD1 (i.e., the first plane PL1). Furthermore, the second read command RD2 may have a lower processing priority than the third read command RD3 (i.e., may have a second priority level P2). Therefore, the second read command RD2 may not be processed simultaneously with the first read command RD1 or the third read command RD3.

[0121] For example, the command reordering module 123b may group the first read command RD1 and the third read command RD3 into a first command group CG1, and may group the second read command RD2 into a second command group CG2. The command reordering module 123b may generate a first combined command CCMD1 by combining the first read command RD1 and the third read command RD3 belonging to the first command group CG1. The first combined command CCMD1 may be a multi-plane read command for the first plane PL1 and the second plane PL2.

[0122] That is, when a command group (eg, CG1) includes two or more commands (eg, RD1 and RD3), the command reordering module 123b may generate a combined command (eg, CCMD1) by combining the commands (eg, RD1 and RD3) included in the command group (eg, CG1).

[0123] The command reordering module 123b can determine (or identify) the order in which to process the first combined command CCMD1 and the second read command RD2 based on the processing priorities of the first through third read commands RD1 through RD3. For example, the first priority level P1 of the read commands RD1 and RD3 used to generate the first combined command CCMD1 can be higher than the second priority level P2 of the second read command RD2. Therefore, the command reordering module 123b can determine the processing priorities of the first combined command CCMD1 and the second read command RD2 so that the first combined command CCMD1 is processed before the second read command RD2.

[0124] The command reordering module 123b may send the reordered command information RCI to the command sequencer 123c. Figure 7B For example, the reorder command information RCI may include the processing order of the first combined command CCMD1 and the second read command RD2, the addresses ADDR corresponding to the first combined command CCMD1 and the second read command RD2, and information about the command types of the first combined command CCMD1 and the second read command RD2. However, the present disclosure is not limited thereto.

[0125] The command sequencer 123c may control the nonvolatile memory device 120 (refer to Figure 1 The command sequencer 123c may control the memory cell array 121 (refer to Figure 1 ) simultaneously performs the first read operation and the third read operation. After the first read operation and the third read operation are terminated, the command sequencer 123c may perform the second read operation based on the second read command RD2.

[0126] In other words, the nonvolatile memory device 120 according to an embodiment of the present disclosure can independently generate a combined command (e.g., CCMD1) for performing a multi-plane operation. Furthermore, the nonvolatile memory device 120 can determine the order in which to process commands based on the processing priority of the operation command OCMD. In other words, the nonvolatile memory device 120 can process commands in a non-sequential manner. Consequently, the performance of the memory device 100 can be improved.

[0127] For example, after the operation based on the reorder command information RCI is terminated, the command sequencer 123c may transmit operation execution information OI to the command queue 123a. For example, the operation execution information OI may include information regarding the execution of the operation corresponding to the command (e.g., CCMD1 and RD2). For example, the command queue 123a may determine whether the first to third read operations are completed or are being executed based on the operation execution information OI.

[0128] Figure 8 is used to describe Figure 1 Referring to FIG. 1 , another example of the operation of the storage device is shown. Figures 1 to 3 and Figures 5 to 7A and 7B to describe Figure 8 . Reference Figure 8 Before the 0th time point t0, the memory controller 110 may send the first to fourth enqueue commands EQ1 to EQ4 to the nonvolatile memory device 120 in response to a request from the host 200 (refer to Figure 5 Before the 0th time point t0, the memory controller 110 and the non-volatile memory device 120 may exchange data “DATA” through the second transmission path DP (refer to Figure 5 ).

[0129] For example, a first enqueue command EQ1 may include a first read command RD1, a second enqueue command EQ2 may include a second read command RD2, a third enqueue command EQ3 may include a third read command RD3, and a fourth enqueue command EQ4 may include a fourth read command RD4. The first read command RD1 may be a command having a first priority P1 and associated with a first block B1 of a first plane PL1, the second read command RD2 may be a command having a second priority P2 and associated with a first block B1 of a fourth plane PL4, the third read command RD3 may be a command having a first priority P1 and associated with a second block B2 of a second plane PL2, and the fourth read command RD4 may be a command having a second priority P2 and associated with a third block B3 of a third plane PL3.

[0130] For example, the first priority level P1 may be higher in processing priority than the second priority level P2.

[0131] In response to the first to fourth enqueue commands EQ1 to EQ4, the nonvolatile memory device 120 may sequentially store the first to fourth read commands RD1 to RD4 and first to fourth read command information (e.g., including the priority, address ADDR, and queue identifier QID of each of the first to fourth read commands RD1 to RD4) in the command queue 123a (refer to Figure 1 )middle.

[0132] For example, at time t0, the storage controller 110 (refer to Figure 5 ) and the non-volatile memory device 120 can complete the transmission / reception of the data "DATA".

[0133] For example, during the 0th time interval ti0 from the 0th time point t0, the nonvolatile memory device 120 may generate the first combined command CCMD1 and the second combined command CCMD2. In detail, the command reordering module 123b (refer to Figure 1 ) can be based on the command queue 123a (refer to Figure 1 ) to generate a first combined command CCMD1 and a second combined command CCMD2.

[0134] The nonvolatile memory device 120 may generate a first combined command CCMD1 by combining the first read command RD1 and the third read command RD3. Specifically, the nonvolatile memory device 120 may combine the first read command RD1 and the third read command RD3 based on the fact that the first plane PL1 corresponding to the first read command RD1 and the second plane PL2 corresponding to the third read command RD3 are different from each other and that the first read command RD1 and the third read command RD3 have the same processing priority (i.e., the first priority P1). In other words, the first combined command CCMD1 may be a multi-plane command for the first plane PL1 and the second plane PL2.

[0135] The nonvolatile memory device 120 may generate a second combined command CCMD2 by combining the second read command RD2 and the fourth read command RD4. Specifically, the nonvolatile memory device 120 may combine the second read command RD2 and the fourth read command RD4 based on the fact that the fourth plane PL4 corresponding to the second read command RD2 and the third plane PL3 corresponding to the fourth read command RD4 are different from each other and that the second read command RD2 and the fourth read command RD4 have the same processing priority (i.e., the second priority P2). The second combined command CCMD2 may be a multi-plane command for the third plane PL3 and the fourth plane PL4.

[0136] The processing priority P1 of commands RD1 and RD3 constituting the first combined command CCMD1 may be higher than the processing priority P2 of commands RD2 and RD4 constituting the second combined command CCMD2. Therefore, the nonvolatile memory device 120 may determine that the processing priority of the first combined command CCMD1 is higher than the processing priority of the second combined command CCMD2. In this case, the nonvolatile memory device 120 may process the first combined command CCMD1 before the second combined command CCMD2.

[0137] In detail, during the first time interval ti1, the nonvolatile memory device 120 may perform the first read operation and the third read operation based on the first combined command CCMD1. For example, during the first read period tRD1, the nonvolatile memory device 120 may read data of the first plane PL1 and may store the read data in the page buffer 124 (refer to Figure 2 ). In addition, during the third read period tRD3, the nonvolatile memory device 120 may read data of the second plane PL2 and may store the read data in the page buffer 124 (refer to Figure 2 During the first data output period tDO1, the nonvolatile memory device 120 may store the data corresponding to the first read operation and stored in the page buffer 124 (refer to Figure 2 ) to the memory controller 110. During the third data output period tDO3 after the first data output period tDO1, the nonvolatile memory device 120 may store the data corresponding to the third read operation and stored in the page buffer 124 (refer to Figure 2 ) is output to the memory controller 110. That is, during the first time interval ti1, the nonvolatile memory device 120 may perform the first read operation and the third read operation in parallel.

[0138] The planes PL1 and PL2 corresponding to the first combined command CCMD1 may not include either of the planes PL3 and PL4 corresponding to the second combined command CCMD2. Therefore, the nonvolatile memory device 120 may begin executing the second and fourth read operations based on the second combined command CCMD2 while executing the first and third read operations based on the first combined command CCMD1. In other words, the nonvolatile memory device 120 may perform a PIR operation based on the first and second combined commands CCMD1 and CCMD2.

[0139] In detail, during the second time interval ti2, the nonvolatile memory device 120 may perform the second read operation and the fourth read operation based on the second combined command CCMD2. For example, during the second read period tRD2, the nonvolatile memory device 120 may read data of the third plane PL3 and may store the read data in the page buffer 124 (refer to Figure 2 ). In addition, during the fourth read period tRD4, the nonvolatile memory device 120 may read data of the fourth plane PL4 and may store the read data in the page buffer 124 (refer to Figure 2 During the second data output period tDO2 after the second read period tRD2 and the third data output period tDO3, the nonvolatile memory device 120 may store the data corresponding to the second read operation and stored in the page buffer 124 (refer to Figure 2 ) to the memory controller 110. During the fourth data output period tDO4 after the second data output period tDO2, the nonvolatile memory device 120 may store the data corresponding to the fourth read operation and stored in the page buffer 124 (refer to Figure 2 ) is output to the memory controller 110. That is, during the second time interval ti2, the nonvolatile memory device 120 may perform the second read operation and the fourth read operation in parallel.

[0140] That is, according to an embodiment of the present disclosure, even if the planes PL1 to PL4 corresponding to the operation commands RD1 to RD4 are different from each other, the processing priorities (e.g., P1 and P2) of the operation commands RD1 to RD4 may be different from each other. In this case, the non-volatile memory device 120 may not be able to generate a single combined command by combining all the operation commands RD1 to RD4. However, the non-volatile memory device 120 can generate multiple combined commands CCMD1 and CCMD2 by combining commands with the same processing priority among the operation commands RD1 to RD4. Furthermore, the non-volatile memory device 120 can process multiple combined commands CCMD1 and CCMD2 through a PIR operation.

[0141] Figure 9 is used to describe Figure 1 Referring to FIG. 1 , another example of the operation of the storage device is shown. Figures 1 to 3 and Figures 5 to 8 To describe Figure 9 . Reference Figure 9 Before the 0th time point t0, the memory controller 110 may send the first to third enqueue commands EQ1 to EQ3 to the nonvolatile memory device 120 in response to a request from the host 200 (refer to Figure 5For example, before the 0th time point t0, the storage controller 110 (refer to Figure 5 ) and the non-volatile memory device 120 can exchange data “DATA” (refer to Figure 5 ).

[0142] For example, the first enqueue command EQ1 may include a first read command RD1, the second enqueue command EQ2 may include a second read command RD2, and the third enqueue command EQ3 may include a third read command RD3. The first read command RD1 may be a command having a first priority P1 and associated with the first block B1 of the first plane PL1 and the fourth block B4 of the fourth plane PL4. That is, the first read command RD1 may be a multi-plane command MP. The second read command RD2 may be a command having a first priority P1 and associated with the third block B3 of the third plane PL3, and the third read command RD3 may be a command having a first priority P1 and associated with the third block B3 of the second plane PL2.

[0143] For example, at time t0, the storage controller 110 (refer to Figure 5 ) and the non-volatile memory device 120 can complete the transmission / reception of the data "DATA".

[0144] For example, during the 0th time interval ti0 starting from the 0th time point t0, the nonvolatile memory device 120 may generate a first combined command CCMD1. The planes PL1 and PL4 corresponding to the first read command RD1 may be different from the plane PL3 corresponding to the second read command RD2 and the plane PL2 corresponding to the third read command RD3. Furthermore, the first through third read commands RD1 through RD3 may have the same processing priority (i.e., the first priority level P1). Therefore, the nonvolatile memory device 120 may generate the first combined command CCMD1 by combining the first through third read commands RD1 through RD3. In this case, the first combined command CCMD1 may be a multi-plane command for the first through fourth planes PL1 through PL4.

[0145] During the first time interval ti1, the nonvolatile memory device 120 may simultaneously perform the first to fourth read operations based on the first combined command CCMD1. For example, the first read operation may be a read operation on the first plane PL1 corresponding to the first read command RD1, and the second read operation may be a read operation on the fourth plane PL4 corresponding to the first read command RD1. In addition, the third read operation may be a read operation on the third plane PL3 corresponding to the second read command RD2, and the fourth read operation may be a read operation on the second plane PL2 corresponding to the third read command RD3. In detail, during the read period tRD, the nonvolatile memory device 120 may read data from the first to fourth planes PL1 to PL4, and may store the read data in the page buffer 124 (refer to Figure 2 During the first data output period tDO1, the nonvolatile memory device 120 may store the data corresponding to the first read operation and stored in the page buffer 124 (refer to Figure 2 ) outputs the data of the first plane PL1 in the second data output period tDO2 to the memory controller 110. During the second data output period tDO2, the nonvolatile memory device 120 may store the data corresponding to the second read operation and stored in the page buffer 124 (refer to Figure 2 ) outputs the data of the fourth plane PL4 to the memory controller 110. During the third data output period tDO3, the nonvolatile memory device 120 may store the data corresponding to the third read operation and stored in the page buffer 124 (refer to Figure 2 ) outputs the data of the third plane PL3 in the fourth data output period tDO4 to the memory controller 110. During the fourth data output period tDO4, the nonvolatile memory device 120 may store the data corresponding to the fourth read operation and stored in the page buffer 124 (refer to Figure 2 ) is output to the memory controller 110.

[0146] That is, the nonvolatile memory device 120 according to an embodiment of the present disclosure may generate a combined command (eg, CCMD1 ) by combining a multi-plane command (eg, RD1 ) and single-plane commands (eg, RD2 and RD3 ) from the memory controller 110 .

[0147] Figure 10 is used to describe Figure 1 A flowchart of a method for operating a nonvolatile memory device. Figures 1 to 3 and Figures 5 to 9 To describe Figure 10 . Reference Figure 10In operation S210, the nonvolatile memory device 120 may receive an enqueue command EQ from the memory controller 110. In operation S220, the nonvolatile memory device 120 may store an operation command OCMD corresponding to the enqueue command EQ in the command queue 123a (refer to Figure 1 ) (e.g., this is called "queuing").

[0148] In operation S230, the nonvolatile memory device 120 may generate a combined command CCMD. Specifically, the nonvolatile memory device 120 may generate a combined command CCMD based on the command queue 123a (refer to Figure 1 ) to generate a combined command CCMD. The combined command CCMD can be a multi-plane command.

[0149] In operation S240, the nonvolatile memory device 240 may perform command reordering. For example, the nonvolatile memory device 120 may determine the order in which to process the combined command CCMD and the operation command OCMD. For example, the nonvolatile memory device 120 may determine the processing order based on the priority of each of the combined command CCMD and the operation command OCMD.

[0150] In operation S250, the nonvolatile memory device 120 may perform operations corresponding to the operation command OCMD regardless of the order in which the enqueue command EQ is received. In detail, the nonvolatile memory device 120 may perform operations corresponding to the combined command CCMD and the operation command OCMD, respectively, based on the order in which the reordered commands are processed.

[0151] Figure 11 It is used to describe in detail Figure 10 Flowchart of operation S230. Figure 11 In operation S231, the nonvolatile memory device 120 may determine whether the operation commands OCMD have the same command type. For example, the command type may indicate a read operation, an erase operation, etc. The nonvolatile memory device 120 may not generate a combined command CCMD based on the operation commands OCMD having different command types. If the operation commands OCMD have the same command type, the nonvolatile memory device 120 may perform operation S232.

[0152] In operation S232, the nonvolatile memory device 120 may determine whether the planes corresponding to the operation command OCMD are different from each other. For example, the operation command OCMD may be associated with the same plane. In this case, the nonvolatile memory device 120 may not generate the combined command CCMD based on the operation command OCMD. For example, the operation command OCMD may correspond to different planes. In this case, the nonvolatile memory device 120 may perform operation S233.

[0153] In operation S233, the nonvolatile memory device 120 may determine whether the operation commands OCMD have the same processing priority. For example, the processing priorities of the operation commands OCMD may be different from each other. In this case, the nonvolatile memory device 120 may not generate the combined command CCMD. For example, the operation commands OCMD may have the same processing priority. In this case, the nonvolatile memory device 120 may perform operation S234.

[0154] In operation S234, the nonvolatile memory device 120 may combine the operation commands OCMD to generate a combined command CCMD. In other words, the nonvolatile memory device 120 may combine the operation commands OCMD to generate a combined command CCMD. Figure 1 ) is combined to generate a combined command CCMD by combining the operation commands OCMD that "have the same command type, correspond to different planes respectively and have the same processing priority".

[0155] Figure 12 is used to describe Figure 1 Referring to FIG. 1 , another example of the operation of the storage device is shown. Figures 1 to 3 and Figures 5 to 11 To describe Figure 12 As described above, even if commands are received from the memory controller 110 in sequence, the nonvolatile memory device 120 according to an embodiment of the present disclosure may perform operations corresponding to the commands in a non-sequential manner.

[0156] Therefore, the memory controller 110 may not know whether the operation currently being executed in the nonvolatile memory device 120 is an operation corresponding to any command. For this reason, in order to check the processing status of (one or more) commands sent to the nonvolatile memory device 120, the memory controller 110 may send a queue status read command QSR to the nonvolatile memory device 120.

[0157] In one embodiment, the memory controller 110 may include queue identifier information QID_info. For example, the queue identifier information QID_info may include information about a queue identifier QID corresponding to the operation command OCMD transmitted to the nonvolatile memory device 120. For example, the queue identifier information QID_info may include information indicating that the queue identifier QID of the first read command RD1 is "1," the queue identifier QID of the second read command RD2 is "2," the queue identifier QID of the third read command RD3 is "3," the queue identifier QID of the fourth read command RD4 is "4," and the queue identifier QID of the fifth read command RD5 is "5."

[0158] The nonvolatile memory device 120 may transmit queue status information QSI stored in the command queue 123a to the memory controller 110 in response to the queue status read command QSR. For example, the queue status information QSI may include information about the queue identifier QID and a processing status of an operation command corresponding to the queue identifier QID.

[0159] In one embodiment, the processing state may correspond to one of a first state S1 to a fourth state S4. The first state S1 may indicate a processing standby state. The second state S2 may indicate that the operation command is being processed. The third state S3 may indicate that the operation command has been completely processed. The fourth state S4 may indicate a processing failure state.

[0160] In one embodiment, similar to Figure 8 For example, the nonvolatile memory device 120 may generate a first combined command CCMD1 (refer to Figure 8 For example, the nonvolatile memory device 120 may wait for the first combined command CCMD1 (refer to Figure 8 In this case, in the queue state information QSI, a processing state corresponding to each of the queue identifier QID “1” and the queue identifier QID “3” may correspond to the first state S1.

[0161] The memory controller 110 can check (or identify) the execution status of the operation command OCMD based on the queue status information QSI (e.g., whether the operation corresponding to the command OCMD has been fully executed). In one example, the memory controller 110 can check the execution status of the operation command OCMD based on the queue identifier information QID_info and the queue status information QSI. For example, the processing status corresponding to the queue identifier QID of "1" can correspond to the first state S1. Therefore, the memory controller 110 can detect that the first read command RD1 is in the processing ready state. In other words, the memory controller 110 can determine that the execution of the first read operation corresponding to the first read command RD1 is pending.

[0162] Furthermore, the processing state corresponding to the queue identifier QID "2" may correspond to the second state S2, the processing state corresponding to the queue identifier QID "4" may correspond to the third state S3, and the processing state corresponding to the queue identifier QID "5" may correspond to the fourth state S4. Therefore, the memory controller 110 may determine that the second read operation corresponding to the second read command RD2 is in progress, may determine that the execution of the fourth read operation corresponding to the fourth read command RD4 is complete, and may determine that the execution of the fifth read operation corresponding to the fifth read command RD5 has failed.

[0163] In other words, the memory controller 110 according to an embodiment of the present disclosure may check the execution status of the operation command OCMD through the queue status read command QSR.

[0164] Figure 13 is used to describe Figure 12 Flowchart of an example of the operation of the storage device. Figure 13 In operation S310, the memory controller 110 and the non-volatile memory device 120 may initiate data transfer. In this case, the memory controller 110 and the non-volatile memory device 120 may transmit data via the second transmission path DP (refer to Figure 5 ) to exchange data.

[0165] In operation S320, the memory controller 110 may send an enqueue command EQ to the nonvolatile memory device 120. In detail, the memory controller 110 may respond to the host 200 (refer to Figure 5 ) request (for example, Figure 5 REQ1 to REQ3) and send enqueue commands (for example, Figure 5 EQ1 to EQ3).

[0166] In operation S330 , the memory controller 110 and the nonvolatile memory device 120 may terminate the data transfer.

[0167] In operation S340, the nonvolatile memory device 120 may perform an operation corresponding to the enqueue command EQ. The nonvolatile memory device 120 may perform an operation corresponding to the enqueue command EQ regardless of the order in which the enqueue command EQ is received. In detail, the nonvolatile memory device 120 may check the command queue 123a (refer to Figure 1 ), the command reordering can be performed, and the commands stored in the command queue 123a (refer to Figure 1 ) in the command (for example, Figure 5 The corresponding operation of OCMD).

[0168] In operation S350, the memory controller 110 may determine whether a reference time (or a period greater than or equal to the reference time) has elapsed. For example, if data transmission to or reception from the non-volatile memory device 120 has been terminated for a period greater than or equal to the reference time, the memory controller 110 may transmit a queue status read command QSR. For example, the memory controller 110 may determine whether the reference time has elapsed since the time when the data transfer was terminated (e.g., since the time when the data transfer was determined to be terminated in operation S330). For example, the reference time may be a preset time. In one embodiment, the reference time may refer to the average time required to perform a read operation. If the reference time has elapsed, the memory controller 110 may transmit the queue status read command QSR to the non-volatile memory device 120 (S360). If the reference time has not elapsed, the memory controller 110 may not transmit the queue status read command QSR to the non-volatile memory device 120.

[0169] In operation S370 , the nonvolatile memory device 120 may transmit queue status information QSI to the memory controller 110 in response to the queue status read command QSR.

[0170] As described above, when the reference time has not elapsed, the memory controller 110 according to an embodiment of the present disclosure may not transmit the queue status read command QSR to the nonvolatile memory device 120. That is, the memory controller 110 may not transmit the queue status read command QSR to the nonvolatile memory device 120 until the execution of the operation corresponding to the entry stored in the command queue 123a of the nonvolatile memory device 120 is completed. Therefore, the nonvolatile memory device 120 may not need to transmit the queue status information QSI to the memory controller 110. Therefore, a memory device including a nonvolatile memory device with improved performance, an operating method thereof, and an operating method of a nonvolatile memory device are provided. However, the present disclosure is not limited thereto. For example, the memory controller 110 may transmit the queue status read command QSR in various ways.

[0171] Figure 14 is used to describe Figure 1 Referring to FIG. 1 , another example of the operation of the storage device is shown. Figures 1 to 3 and Figures 5 to 13 To describe Figure 14 . Reference Figure 14For example, the memory device 100 may receive first to third requests REQ1 to REQ3 from the host 200 while data transfer is being performed (i.e., while the memory controller 110 and the non-volatile memory device 120 are exchanging data "DATA" via the second transfer path DP). For example, the first request REQ1 may be a request for a write operation associated with the first address ADDR1. For example, the second request REQ2 may be a request for a first read operation associated with the first address ADDR1. For example, the third request REQ3 may be a request for a second read operation associated with the second address ADDR2.

[0172] The write command WT should be transmitted together with the write data WDATA to the nonvolatile memory device 120. Therefore, the memory controller 110 may be unable to transmit the write command WT to the nonvolatile memory device 120 while the data "DATA" is being transmitted / received.

[0173] In contrast, the memory controller 110 does not send a read / erase command together with data. Therefore, the memory controller 110 may send an enqueue command EQ including a read command or an erase command to the nonvolatile memory device 120 while data "DATA" is being sent / received.

[0174] In one embodiment, the memory controller 110 may transmit a first write command WT1 to the nonvolatile memory device 120 in response to a first request REQ1, may transmit a first read command RD1 to the nonvolatile memory device 120 in response to a second request REQ2, and may transmit a first enqueue command EQ1 to the nonvolatile memory device 120 in response to a third request REQ3. For example, the first enqueue command EQ1 may include a second read command RD2.

[0175] In one embodiment, the memory controller 110 may transmit a first enqueue command EQ1 to the nonvolatile memory device 120 when data “DATA” is transmitted / received. Also, after transmission / reception of the data “DATA” is completed, the memory controller 110 may sequentially transmit a first write command WT1 and a first read command RD1 to the nonvolatile memory device 120.

[0176] In this case, after the transmission / reception of the data "DATA" is completed, the nonvolatile memory device 120 may perform a second read operation based on the second read command RD2 stored in the command queue 123a. Thereafter, the nonvolatile memory device 120 may sequentially perform a first write operation and a first read operation based on the first write command WT1 and the first read command RD1.

[0177] In other words, according to an embodiment of the present disclosure, while data "DATA" is being transmitted / received, the memory controller 110 may receive a request (e.g., REQ1) corresponding to a write command (e.g., WT1) from the host 200, and may then receive requests (e.g., REQ2 and REQ3) corresponding to read commands (e.g., RD1 and RD2). In this case, for example, the address (e.g., ADDR2) of the read command (e.g., RD2) may be different from the address (e.g., ADDR1) of the write command (e.g., WT1). In this case, while data "DATA" is being transmitted / received, the memory controller 110 may send an enqueue command (e.g., EQ1) including the read command (e.g., RD2) to the non-volatile memory device 120 before the write command (e.g., WT1).

[0178] Conversely, for example, the address (e.g., ADDR1) of a read command (e.g., RD1) may be the same as the address (e.g., ADDR1) of a write command (e.g., WT1). In this case, the memory controller 110 may not generate an enqueue command including the read command (e.g., RD1). Therefore, the memory controller 110 may prevent a read operation from being executed before a write operation to the same address (e.g., ADDR1).

[0179] Figure 15 is used to describe Figure 14 Flowchart of the operation of the memory controller 110. In operation S410, the memory controller 110 may determine whether data is being transferred through the second transfer path DP. When the data is being transferred, the memory controller 110 may perform operation S420.

[0180] In operation S420 , the memory controller 110 may receive a first request REQ1 corresponding to a write operation from an external host.

[0181] In operation S430 , the memory controller 110 may receive a second request REQ2 corresponding to a read operation from an external host.

[0182] In operation S440, the memory controller 110 may determine whether the address of the first request REQ1 is the same as the address of the second request REQ2. When the address of the first request REQ1 is different from the address of the second request REQ2, the memory controller 110 may send an enqueue command EQ corresponding to the second request REQ2 to the non-volatile memory device 120 (S450). For example, the enqueue command EQ may include a read command for a read operation associated with the second request REQ2. When the address of the first request REQ1 is the same as the address of the second request REQ2, the memory controller 110 may not send the enqueue command EQ to the non-volatile memory device 120 and the operation may end. In another example, when the address of the first request REQ1 is the same as the address of the second request REQ2, the memory controller 110 may not send the enqueue command EQ to the non-volatile memory device 120, and as Figure 14 As shown in , the memory controller 110 may receive a third request REQ3 corresponding to a read operation from an external host. When the address of the first request REQ1 is different from the address of the third request REQ3, the memory controller 110 may send an enqueue command EQ corresponding to the third request REQ3 to the nonvolatile memory device 120.

[0183] Figure 16 is a diagram for describing another example of the operation of the storage device according to an embodiment of the present disclosure. Figure 16 , the memory device 100 may include a memory controller 110 and a non-volatile memory device 120. Figure 16 ,and Figure 5 Unlike the case of , the memory controller 110 and the nonvolatile memory device 120 may exchange commands, addresses, and data through one transmission path CADP.

[0184] Refer again Figure 16 , the storage device 100 may sequentially receive first to third requests REQ1 to REQ3 from the external host 200 .

[0185] For example, the first request REQ1 may be a request for a first read operation for the first plane PL1 , the second request REQ2 may be a request for a second read operation for the first plane PL1 , and the third request REQ3 may be a request for a third read operation for the second plane PL2 .

[0186] The memory controller 110 may generate first to third enqueue commands EQ1 to EQ3 corresponding to the first to third requests REQ1 to REQ3 in response to the first to third requests REQ1 to REQ3. For example, the first enqueue command EQ1 may correspond to the first request REQ1 and may be a command for a first read operation, the second enqueue command EQ2 may correspond to the second request REQ2 and may be a command for a second read operation, and the third enqueue command EQ3 may correspond to the third request REQ3 and may be a command for a third read operation.

[0187] For example, during a first time interval, the memory controller 110 may sequentially send first to third enqueue commands EQ1 to EQ3 to the nonvolatile memory device 120. Figure 5 As described above, the nonvolatile memory device 120 may store the first to third read commands RD1 to RD3 in the command queue 123a (refer to FIG. Figure 5 )middle.

[0188] During the first time interval, the memory controller 110 and the non-volatile memory device 120 may not perform data transmission / reception. However, the non-volatile memory device 120 may perform internal operations. For example, the internal operation may refer to an operation that does not require data transmission / reception via the transmission path CADP (such as an erase operation). That is, when the non-volatile memory device 120 performs internal operations without data transmission / reception via the transmission path CADP, the memory controller 110 may send enqueue commands (e.g., EQ1 to EQ3) to the non-volatile memory device 120.

[0189] In this case, after the internal operation of the nonvolatile memory device 120 is completely performed, the memory controller 110 may not separately transmit the first to third read commands RD1 to RD3 to the nonvolatile memory device 120. Therefore, the performance of the memory device 100 may be improved.

[0190] For example, after an internal operation is completely executed, the nonvolatile memory device 120 may generate a first combined command CCMD1 based on the first read command RD1 and the third read command RD3. Thereafter, the nonvolatile memory device 120 may simultaneously perform the first and third read operations based on the first combined command CCMD1. After the first and third read operations are completely executed, the nonvolatile memory device 120 may perform the second read operation based on the second read command RD2. In other words, the nonvolatile memory device 120 may independently combine the operation commands RD1 to RD3 and may change the order in which the operation commands RD1 to RD3 are processed.

[0191] Figure 17 is used to describe Figure 16 Flowchart of the operation of the storage controller. Figure 17 In operation S510 , the memory controller 110 may receive a request REQ from an external host 200 .

[0192] In operation S520, the memory controller 110 may determine whether data is being transferred through the transfer path CADP. When data is being transferred, the memory controller 110 may not generate an enqueue command EQ. When data is not being transferred, the memory controller 110 may perform operation S530.

[0193] In operation S530, the memory controller 110 may determine whether the request REQ corresponds to a write operation. When the request REQ corresponds to a write operation, the memory controller 110 may not generate an enqueue command EQ. When the request REQ does not correspond to a write operation, the memory controller 110 may perform operation S540.

[0194] In operation S540, the memory controller 110 may determine whether an internal operation is being performed in the nonvolatile memory device 120. When the internal operation is being performed, the memory controller 110 may send an enqueue command EQ to the nonvolatile memory device 120. When the internal operation is not being performed, the memory controller 110 may not generate an enqueue command EQ.

[0195] Figure 18 is a block diagram illustrating a storage device according to an embodiment of the present disclosure. Figure 18 , the storage device 10 may include a storage controller 11 and a non-volatile memory device 12. The storage controller 11 may correspond to Figure 1 The non-volatile memory device 12 may correspond to a memory controller 110. Figure 1 The non-volatile memory device 120 is provided.

[0196] That is, the nonvolatile memory device 12 may receive an operation command (eg, Figure 5 In other words, the nonvolatile memory device 12 may process commands received from the memory controller 11 in a non-sequential manner.

[0197] In one embodiment, the nonvolatile memory device 12 may receive a command / address CA and a command / address clock signal CA_CLK from the memory controller 11. For example, the nonvolatile memory device 12 may obtain a command and address from the command / address CA based on the switching timing of the command / address clock signal CA_CLK. The nonvolatile memory device 12 may also receive a data signal DQ and a data strobe signal DQS from the memory controller 11. For example, the nonvolatile memory device 12 may obtain data from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0198] As reference Figure 5 As described above, the command / address pins and the data input / output pins may be physically separated from each other. Therefore, the path through which the signal CAS associated with the command / address is transmitted may be different from the path through which the signal DS associated with the data is transmitted. In detail, for example, the command / address CA may be transmitted through the first transmission path CAP (refer to Figure 5 ) is transmitted, and the data signal DQ can be transmitted through the second transmission path DP (refer to Figure 5 Therefore, according to an embodiment of the present disclosure, the memory controller 11 may send a command / address CA to the nonvolatile memory device 12 while data is being transferred through the data signal DQ.

[0199] Figure 19 is a diagram of a data center 1000 to which a memory device is applied according to an embodiment.

[0200] Reference Figure 19 Data center 1000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. Data center 1000 may be a system for operating a search engine or database, or a computing system used by a company (such as a bank) or a government agency. Data center 1000 may include application servers (e.g., application servers 1 through N) 1100 through 1100n and storage servers (e.g., storage servers 1 through M) 1200 through 1200m. The number of application servers 1100 through 1100n and the number of storage servers 1200 through 1200m may vary depending on the embodiment. The number of application servers 1100 through 1100n may differ from the number of storage servers 1200 through 1200m.

[0201] Application server 1100 or storage server 1200 may include at least one of processors 1110 and 1210 and memories 1120 and 1220. Storage server 1200 will now be described as an example. Processor 1210 may control all operations of storage server 1200, access memory 1220, and execute instructions and / or data loaded in memory 1220. Memory 1220 may be double data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, and / or non-volatile DIMM (NVM DIMM). In one or more embodiments, the number of processors 1210 and memory 1220 included in storage server 1200 may be selected differently. In one embodiment, processor 1210 and memory 1220 may provide a processor-memory pair. In one embodiment, the number of processors 1210 may be different from the number of memories 1220. Processor 1210 may include a single-core processor or a multi-core processor. The above description of the storage server 1200 can be similarly applied to the application server 1100. In one or more embodiments, the application server 1100 may not include the storage device 1150. The storage server 1200 may include at least one storage device 1250. The number of storage devices 1250 included in the storage server 1200 may be selected differently according to embodiments.

[0202] In one embodiment, the storage device 1250 may correspond to Figure 1 For example, the NAND flash memory device 1252 (or NAND 1252 ) can independently combine commands from the controller (CTRL) 1251 and can adjust the processing order of the commands.

[0203] Application servers 1100 to 1100n can communicate with storage servers 1200 to 1200m via a network 1300. Network 1300 can be implemented using Fibre Channel (FC) or Ethernet. FC is a medium for relatively high-speed data transmission and utilizes high-performance and high-availability optical switches. Storage servers 1200 to 1200m can be provided as file storage devices, block storage devices, or object storage devices, depending on the access method of network 1300.

[0204] In one embodiment, network 1300 may be a storage-specific network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN, which uses a Transmission Control Protocol (TCP) / IP network and is implemented according to the SCSI over TCP / IP or Internet SCSI (iSCSI) protocols. In another embodiment, network 1300 may be a general-purpose network, such as a TCP / IP network. For example, network 1300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabric (NVMe-oF).

[0205] Hereinafter, description will be mainly made of the application server 1100 and the storage server 1200. The description of the application server 1100 may be applied to another application server 1100n, and the description of the storage server 1200 may be applied to another storage server 1200m.

[0206] Application server 1100 can store data requested by a user or client for storage in one of storage servers 1200 to 1200m via network 1300. Furthermore, application server 1100 can obtain data requested by a user or client for reading from one of storage servers 1200 to 1200m via network 1300. For example, application server 1100 can be implemented as a network server or a database management system (DBMS).

[0207] Application server 1100 can access memory 1120n or storage device 1150n included in another application server 1100n via network 1300. Alternatively, application server 1100 can access memory 1220 to 1220m or storage devices 1250 to 1250m included in storage servers 1200 to 1200m via network 1300. Thus, application server 1100 can perform various operations on data stored in application servers 1100 to 1100n and / or storage servers 1200 to 1200m. For example, application server 1100 can execute instructions for moving or copying data between application servers 1100 to 1100n and / or storage servers 1200 to 1200m. In this case, data may be moved from the storage devices 1250 to 1250m of the storage servers 1200 to 1200m to the storages 1120 to 1120n of the application servers 1100 to 1100n directly or through the storages 1220 to 1220m of the storage servers 1200 to 1200m. The data moved over the network 1300 may be encrypted data for security or privacy.

[0208] The storage server 1200 will now be described as an example. An interface (I / F) 1254 may provide a physical connection between the processor 1210 and the controller 1251, and a physical connection between the network interconnect (NIC) 1240 and the controller 1251. For example, the interface 1254 may be implemented using a direct attached storage (DAS) solution in which the storage device 1250 is directly connected to a dedicated cable. For example, the interface 1254 may be implemented using various interface schemes such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVM Express (NVMe), Institute of Electrical and Electronics Engineers (IEEE) 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MultiMediaCard (MMC), embedded MMC (eMMC), Universal Flash Storage (UFS), embedded UFS (eUFS), and / or Compact Flash (CF) card. The interface 1254m may be similarly configured.

[0209] The storage server 1200 may further include a switch 1230 and a NIC (Network Interconnect) 1240. The switch 1230 may selectively connect the processor 1210 to the storage device 1250 or selectively connect the NIC 1240 to the storage device 1250 via the control of the processor 1210. The switches 1130, 1130n, 1230m and the NICs 1140, 1140n, and 1240m may be similarly configured.

[0210] In one embodiment, NIC 1240 may include a network interface card and a network adapter. NIC 1240 may be connected to network 1300 via a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. NIC 1240 may include internal memory, a digital signal processor (DSP), and a host bus interface, and may be connected to processor 1210 and / or switch 1230 via the host bus interface. The host bus interface may be implemented as one of the aforementioned examples of interface 1254. In one embodiment, NIC 1240 may be integrated with at least one of processor 1210, switch 1230, and storage device 1250.

[0211] In the storage servers 1200 to 1200m or the application servers 1100 to 1100n, the processor may send commands to the storage devices 1150 to 1150n and 1250 to 1250m or the memories 1120 to 1120n and 1220 to 1220m, and program or read data. In this case, the data may be data whose errors have been corrected by the ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data mask (DM) operation has been performed, and may include cyclic redundancy code (CRC) information. The data may be encrypted for security or privacy.

[0212] Memory devices 1150 to 1150n and 1250 to 1250m can transmit control signals and command / address signals to NAND flash memory devices 1252 to 1252m in response to a read command received from a processor. Therefore, when reading data from NAND flash memory devices 1252 to 1252m, a read enable (RE) signal can be input as a data output control signal, thereby outputting the data to the DQ bus. The RE signal can be used to generate the data strobe signal DQS. Command and address signals can be latched in the page buffer based on the rising or falling edge of the write enable (WE) signal.

[0213] The controller 1251 controls all operations of the storage device 1250. In one embodiment, the controller 1251 may include an SRAM. The controller 1251 may write data to the NAND flash memory device 1252 in response to a write command or read data from the NAND flash memory device 1252 in response to a read command. For example, the write and / or read commands may be provided by the processor 1210 of the storage server 1200, the processor 1210m of another storage server 1200m, or the processors 1110 to 1110n of the application servers 1100 to 1100n. The DRAM 1253 may temporarily store (or buffer) data to be written to or read from the NAND flash memory device 1252. The DRAM 1253 may also store metadata. This metadata may be user data or data generated by the controller 1251 to manage the NAND flash memory device 1252. The storage device 1250 may include a secure element (SE) for security or privacy. The controller 1251m, the NAND flash memory device 1252m, and the DRAM 1253m included in the storage device 1250m may be similarly configured.

[0214] The controller 1251 may be implemented as a digital signal processor (DSP), a microprocessor, and a time controller (TCON) for processing digital signals. However, the disclosure is not limited thereto, and the controller 1251 may include one or more of a central processing unit (CPU), a microcontroller unit (MCU), a microprocessing unit (MPU), a controller, an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), and an advanced reduced instruction set computer (RISC) machine (ARM) processor, or may be defined by these terms. In addition, the controller 1251 may be implemented as a system on chip (SoC) or a large-scale integration (LSI) with processing algorithms stored therein, or in the form of a field programmable gate array (FPGA). The controller 1251 may perform various functions by executing computer-executable instructions stored in a cache or memory.

[0215] According to an embodiment of the present disclosure, a nonvolatile memory device can sequentially receive commands from a storage controller. The nonvolatile memory device can combine commands and adjust the order in which the commands are processed. In other words, the nonvolatile memory device can independently implement non-sequential operations. Therefore, a storage device including a nonvolatile memory device with improved performance, an operating method thereof, and a method for operating a nonvolatile memory device are provided.

[0216] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the following claims.

Claims

1. A storage device comprising: A non-volatile memory device comprising a first plane and a second plane; as well as a memory controller configured to sequentially send a first command corresponding to a first operation of a first plane, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane to the nonvolatile memory device; The nonvolatile memory device is configured to perform a third operation before the second operation based on the first command, the second command, and the third command.

2. The storage device according to claim 1, wherein The storage controller is also configured to: transmitting data to or receiving data from the nonvolatile memory device via a first transmission path, and The first command, the second command, and the third command are sent to the nonvolatile memory device through the second transmission path.

3. The storage device according to claim 1, wherein The nonvolatile memory device is further configured to generate a first combined command corresponding to the first plane and the second plane based on the first command and the third command.

4. The storage device according to claim 1, wherein The first operation, the second operation, and the third operation are not write operations of the nonvolatile memory device.

5. The storage device according to claim 3, in, The nonvolatile memory device further includes a command queue, and The non-volatile memory device is further configured as follows: In response to the first command, storing a first operation command corresponding to the first operation in a command queue, In response to the second command, storing a second operation command corresponding to the second operation in the command queue, and In response to the third command, a third operation command corresponding to the third operation is stored in the command queue.

6. The storage device according to claim 5, in, The non-volatile memory device also includes: a command reordering module configured to generate a first combined command based on a processing priority of each of the first operation command, the second operation command, and the third operation command, a plane corresponding to each of the first operation command, the second operation command, and the third operation command, and an operation type of each of the first operation command, the second operation command, and the third operation command.

7. The storage device according to claim 6, wherein: The command reordering module is further configured to generate a first combined command by combining the first operation command and the third operation command based on the following items: The operation type of the first operation command is the same as the operation type of the third operation command. The plane corresponding to the first operation command is different from the plane corresponding to the third operation command, and The processing priority of the first operation command is the same as the processing priority of the third operation command.

8. The storage device according to claim 6, wherein: The command reordering module is further configured to identify an order of processing the first combined command and the second operation command based on a processing priority of each of the first operation command, the second operation command, and the third operation command.

9. The storage device according to claim 1, wherein: The storage controller is also configured to: When data is transmitted to or received from the nonvolatile memory device, a first command, a second command, and a third command are transmitted to the nonvolatile memory device.

10. The storage device according to any one of claims 1 to 9, in, The memory controller is further configured to: send a fourth command to the non-volatile memory device, The nonvolatile memory device is further configured to: send queue status information to the storage controller in response to a fourth command, and The queue status information includes information on a processing status of each of a first operation command corresponding to the first operation, a second operation command corresponding to the second operation, and a third operation command corresponding to the third operation.

11. The storage device according to claim 10, wherein: The storage controller is further configured to identify whether the first operation, the second operation, and the third operation are completely executed based on the queue status information.

12. The storage device according to claim 10, wherein: The memory controller is further configured to transmit a fourth command based on data transmission or reception to or from the nonvolatile memory device being terminated for a period greater than or equal to a reference time.

13. A method for operating a storage device, the method comprising: sequentially sending, by a memory controller of the memory device, to the nonvolatile memory device, a first command corresponding to a first operation of a first plane of the nonvolatile memory device of the memory device, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane of the nonvolatile memory device; as well as A third operation is performed by the nonvolatile memory device before the second operation based on the first command, the second command, and the third command.

14. The method according to claim 13, further comprising: The memory controller transmits the data to the non-volatile memory device via the first transmission path; receiving, by the memory controller, data from the nonvolatile memory device via a first transmission path; as well as The first command, the second command, and the third command are sent by the memory controller to the nonvolatile memory device through the second transmission path.

15. The method according to claim 13, further comprising: queuing, by the nonvolatile memory device in response to the first command, a first operation command corresponding to the first operation into a command queue; queuing, by the nonvolatile memory device in response to the second command, a second operation command corresponding to the second operation into a command queue; queuing, by the nonvolatile memory device in response to the third command, a third operation command corresponding to the third operation into the command queue; generating, by the nonvolatile memory device, a first combined command based on the first operation command and the third operation command; as well as Identify the order of processing the first combination command and the second operation command, The first combined command includes a multi-plane command related to the first plane and the second plane.

16. The method according to claim 15, wherein The steps of generating the first combined command include: identifying whether an operation type of the first operation command is the same as an operation type of the third operation command; and It is identified whether the processing priority of the first operation command is the same as the processing priority of the third operation command.

17. The method according to claim 16, wherein The step of identifying the order of processing the first combination command and the second operation command includes: The processing priorities of the first operation command and the third operation command are compared with the processing priority of the second operation command.

18. The method according to any one of claims 13 to 17, further comprising: sending, by the memory controller, a fourth command to the non-volatile memory device; as well as sending, by the nonvolatile memory device in response to a fourth command, queue status information to the memory controller, The queue status information includes information on a processing status of each of a first operation command corresponding to the first operation, a second operation command corresponding to the second operation, and a third operation command corresponding to the third operation.

19. A method of operating a non-volatile memory device, the non-volatile memory device comprising a first plane and a second plane, the method comprising: sequentially receiving a first command corresponding to a first operation of the first plane, a second command corresponding to a second operation of the first plane, and a third command corresponding to a third operation of the second plane; queuing a first operation command corresponding to the first command, a second operation command corresponding to the second command, and a third operation command corresponding to the third command into a command queue, wherein the first operation command, the second operation command, and the third operation command are queued in the order in which the first operation command, the second operation command, and the third operation command are received; reordering the first operation command, the second operation command, and the third operation command; and The first operation, the second operation, and the third operation are performed based on the order in which the first operation command, the second operation command, and the third operation command are reordered, regardless of the order in which the first command, the second command, and the third command are received.

20. The method according to claim 19, wherein The first operation, the second operation, and the third operation are not write operations of the nonvolatile memory device.

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