Semiconductor packaging structure

Abstract

The invention provides a semiconductor packaging structure which comprises a substrate, a heat dissipation ring, a chip, a heat dissipation layer and a radiator, the heat dissipation ring is located on the substrate and defines an accommodating space, the chip is located in the accommodating space and is arranged on the substrate, the heat dissipation layer is located in the accommodating space and covers the upper surface of the substrate, and the heat dissipation ring is arranged on the substrate. The heat dissipation layer is arranged on the heat dissipation ring, a heat dissipation opening for exposing the chip is formed in the heat dissipation layer, the plane where the upper surface of the heat dissipation layer is located is higher than the plane where the upper surface of the chip is located, the side wall of the heat dissipation opening and the side wall of the chip are spaced by a preset distance, the radiator covers the chip and comprises a first connecting part and a second connecting part, and the first connecting part is connected with the upper surface of the heat dissipation ring; the second connecting part is convexly arranged on the lower surface of the first connecting part and is connected with the upper surface of the heat dissipation layer. According to the semiconductor packaging structure, the heat dissipation ring and the heat dissipation layer are arranged to support the heat dissipation device, so that the heat dissipation device is prevented from being in direct contact with the chip, and the chip is prevented from being damaged when the heat dissipation device falls off.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing and relates to a semiconductor packaging structure. Background Art

[0002] With the continuous development of electronic products, chip power is getting higher and higher, and heat dissipation has become a key factor restricting chip performance. Existing heat dissipation designs mainly rely on heat conduction technology, which uses thermal interface materials between the heat dissipation layer and the chip to reduce thermal resistance and increase heat dissipation efficiency. However, as chip size increases, the chip warping problem becomes increasingly serious, and heat dissipation designs that rely solely on conduction technology can no longer meet the heat dissipation needs of high-performance chips. In order to further improve the heat dissipation effect, thermal convection cooling technology has emerged. This technology promotes the flow of air or liquid through components such as fans and radiators to take away heat, which can effectively improve the heat dissipation effect. However, in thermal convection cooling technology, the radiator component is often connected to the chip. When the package structure accidentally falls from a high place to the ground, the radiator component is easily impacted and broken, which in turn causes damage to the chip.

[0003] Therefore, how to provide a semiconductor packaging structure that can both improve the heat dissipation effect and prevent the chip from being damaged after falling has become an important problem that needs to be solved urgently by those skilled in the art.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor packaging structure for solving the problem in the prior art that the heat sink assembly is prone to damage the chip when the packaging structure falls.

[0006] To achieve the above objectives and other related objectives, the present invention provides a semiconductor packaging structure, comprising:

[0007] substrate;

[0008] A heat dissipation ring is located on the substrate and encloses a receiving space;

[0009] a chip, located in the receiving space and mounted on the substrate;

[0010] a heat dissipation layer, located in the receiving space and covering the upper surface of the substrate, wherein the heat dissipation layer is provided with a heat dissipation opening for exposing the chip, wherein the plane where the upper surface of the heat dissipation layer is located is higher than the plane where the upper surface of the chip is located, and the sidewalls of the heat dissipation opening are spaced a preset distance from the sidewalls of the chip;

[0011] The heat sink covers the chip and includes a first connecting portion and a second connecting portion, wherein the first connecting portion is connected to the upper surface of the heat dissipation ring, and the second connecting portion is protruded from the lower surface of the first connecting portion and connected to the upper surface of the heat dissipation layer.

[0012] Optionally, the number of the chips is one or more.

[0013] Optionally, an air guide hole is provided in the heat dissipation ring, and the air guide hole passes through the inner wall and the outer wall of the heat dissipation ring. An air guide channel connecting the air guide hole and the heat dissipation opening is provided in the heat dissipation layer.

[0014] Optionally, the number of the air guide holes is one or more, and the number of the air guide channels is consistent with the number of the air guide holes.

[0015] Optionally, the heat dissipation ring and the heat dissipation layer are made of the same material.

[0016] Optionally, the tensile strength of the heat dissipation layer is in the range of 200 MPa to 250 MPa.

[0017] Optionally, a first thermal interface material layer is provided between the first connecting portion and the heat dissipation ring, and a second thermal interface material layer is provided between the second connecting portion and the heat dissipation layer.

[0018] Optionally, the first thermal interface material layer and the second thermal interface material layer are made of the same material.

[0019] Optionally, the second connecting portion is located in the receiving space and contacts the inner wall of the heat dissipation ring.

[0020] Optionally, the radiator comprises an aluminum alloy radiator.

[0021] As described above, the semiconductor package structure of the present invention includes: a substrate, a heat ring, a chip, a heat dissipation layer, and a heat sink. The heat ring is located on the substrate and encloses a receiving space. The chip is located within the receiving space and mounted on the substrate. The heat dissipation layer is located within the receiving space and covers the upper surface of the substrate. The heat dissipation layer includes a heat dissipation opening for exposing the chip. The upper surface of the heat dissipation layer is located at a plane higher than the upper surface of the chip. The sidewalls of the heat dissipation opening are spaced a predetermined distance from the sidewalls of the chip. The heat sink covers the chip and includes a first connecting portion and a second connecting portion. The first connecting portion is connected to the upper surface of the heat ring, and the second connecting portion is protruding from the lower surface of the first connecting portion and connected to the upper surface of the heat dissipation layer. The semiconductor package structure of the present invention supports the heat sink by providing the heat ring and the heat dissipation layer, thereby preventing direct contact between the heat sink and the chip, thereby preventing damage to the chip caused by the heat sink if dropped. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a structural schematic diagram of a packaging structure using heat conduction technology.

[0023] Figure 2 Shown is a structural schematic diagram of a packaging structure using heat convection technology.

[0024] Figure 3 Shown is a structural schematic diagram of the semiconductor packaging structure of the present invention.

[0025] Figure 4 The top view of the semiconductor package structure of the present invention is shown with the heat sink removed.

[0026] Figure 5 Shown is another structural schematic diagram of the semiconductor package structure of the present invention.

[0027] Description of Reference Numerals

[0028] 1.2 Package structure

[0029] 101 heat sink cover

[0030] 102, 202, 302 substrate

[0031] 103, 203, and 303 chips

[0032] 104, 204 thermal medium material layer

[0033] 201, 301 heat sink ring

[0034] 205, 306 radiators

[0035] 3061 First Connection

[0036] 3062 Second connection

[0037] 304 heat dissipation layer

[0038] 305 heat dissipation opening

[0039] 307 air duct

[0040] 308 gas channel

[0041] 309 first thermal interface material layer

[0042] 310 second thermal interface material layer

[0043] 311 fixed adhesive layer

[0044] 312 filling layer DETAILED DESCRIPTION

[0045] With the continuous development of integrated circuits in recent years, the demand for higher levels of integration has increased, and the size of packaged products has gradually increased. This is primarily to meet the higher demands for chip performance and functionality in modern high-performance computing, artificial intelligence, automotive electronics, data centers, and other fields. Larger chips mean higher power consumption and heat dissipation requirements, requiring more advanced thermal management technology. Therefore, large flip-chip ball grid array products must have better thermal management design to ensure that the chip maintains a stable operating temperature under high load, thereby ensuring stable operation and a stable designed service life of the chip.

[0046] See also Figure 1 , which shows a schematic diagram of a package structure using heat conduction technology. The package structure 1 includes a heat dissipation cover 101, a substrate 102, a chip 103, and a thermal dielectric material layer 104. The thermal dielectric material layer 104 is located between the heat dissipation cover 101 and the chip 103 to reduce the thermal resistance between the chip 103 and the heat dissipation cover 101 and improve heat dissipation. In addition, by adjusting the thickness and thermal conductivity of the thermal dielectric material layer 104 and applying it evenly, bubbles and voids can be avoided, further reducing the thermal resistance between the chip 103 and the heat dissipation cover 101.

[0047] See also Figure 2 , which is a schematic diagram of a packaging structure using thermal convection technology. The packaging structure 2 includes a heat dissipation ring 201, a substrate 202, a chip 203, a thermal dielectric material layer 204, and a heat sink 205. The thermal dielectric material layer 204 is located between the heat sink 205 and the chip 203 to reduce the thermal resistance between the chip 203 and the heat sink 205 and improve heat dissipation. Thermal convection technology transfers heat through gas or liquid, and is manifested in the use of components such as fans and heat sinks to promote the flow of air or liquid to remove heat. The heat dissipation effect of "thermal convection technology" is relatively good. Figure 1 The heat dissipation design shown can improve the heat dissipation performance by about 40%.

[0048] However, see again Figures 1 to 2 The heat dissipation cover 101 and the heat sink 205 are both connected to the chip. If the package structure accidentally falls from a height, the heat dissipation cover 101 and the heat sink 205 are easily broken by the impact, thereby damaging the chip. Therefore, the present invention provides a semiconductor package structure that supports the heat sink by providing a heat dissipation ring and a heat dissipation layer to prevent direct contact between the heat sink and the chip, thereby preventing damage to the chip caused by the heat sink when it falls.

[0049] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0050] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0051] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0052] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0053] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0054] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0055] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0056] See also Figure 3 , which is a schematic diagram of a semiconductor package structure of the present invention, wherein the semiconductor package structure 3 includes a substrate 302, a heat dissipation ring 301, a chip 303, a heat dissipation layer 304, and a heat sink 306, wherein the heat dissipation ring 301 is located on the substrate 302 and encloses a receiving space, the chip 303 is located in the receiving space and mounted on the substrate 302, the heat dissipation layer 304 is located in the receiving space and covers the upper surface of the substrate 302, and a heat dissipation opening 305 is opened in the heat dissipation layer 304 to expose the chip 303, and the upper surface of the heat dissipation layer 304 is located at a plane height of In the plane where the upper surface of the chip 303 is located, the side walls of the heat dissipation opening 305 are spaced a preset distance from the side walls of the chip 303. The heat sink 306 covers the top of the chip 303 and includes a first connecting portion 3061 and a second connecting portion 3062. The first connecting portion 3061 is connected to the upper surface of the heat dissipation ring 301, and the second connecting portion 3062 is protruded from the lower surface of the first connecting portion 3061 and connected to the upper surface of the heat dissipation layer 304. It should be pointed out that there is a certain distance between the lower surface of the second connecting portion 3062 and the upper surface of the chip 303.

[0057] Specifically, the heat dissipation layer 304 is located between the heat dissipation ring 301 and the chip 303, providing additional support for the heat sink 306, thereby preventing the heat sink 306 from damaging the chip 303 when the semiconductor package structure 3 falls. Furthermore, by providing the heat dissipation openings 305 and positioning the heat dissipation layer 304 higher than the chip 303, a certain amount of space is retained between the heat dissipation layer 304 and the chip 303, and between the heat sink 306 and the chip 303. This space not only protects the chip 303 from damage by the heat sink 306 when the semiconductor package structure 3 falls, but also provides a channel for heat convection, thereby improving the heat dissipation effect of the chip 303.

[0058] As an example, the number of chips 303 is one or more. Each chip 303 can be any existing semiconductor chip suitable for packaging, and can be multiple chips of different types, such as system-on-chip (SOC) devices or memory chips such as HBM, without limitation. In addition, based on packaging efficiency and package size requirements, multiple chips 303 are generally packaged, and in most cases, the number of chips 303 is far greater than two.

[0059] As an example, see Figure 4 , which is a top view of the structure obtained by removing the heat sink 306 from the semiconductor packaging structure of the present invention, an air guide hole 307 is provided in the heat dissipation ring 301, and the air guide hole 307 passes through the inner wall and the outer wall of the heat dissipation ring 301. An air guide channel 308 connecting the air guide hole 307 and the heat dissipation opening 305 is provided in the heat dissipation layer 304. The air guide hole 307, the air guide channel 308 and the heat dissipation opening 305 constitute a heat dissipation path, which can improve the heat dissipation efficiency of the chip 303. In particular, when the heat sink 306 adopts a heat dissipation fan, the heat dissipation path can also provide a channel for air circulation, accelerate the heat exchange between the semiconductor packaging structure 3 and the external environment, thereby further improving the heat dissipation effect of the chip 303.

[0060] As an example, the number of the air guide holes 307 is one or more, and the number of the air guide channels 308 is consistent with the number of the air guide holes 307. The number of the air guide holes 307 and the air guide channels 308 can be determined according to specific circumstances and are not limited here. It should be noted that the greater the number of the air guide holes 307 and the air guide channels 308, the more heat dissipation paths the chip 303 has, the higher the heat exchange efficiency between the semiconductor package structure 3 and the outside, and the stronger the heat dissipation capability of the semiconductor package structure 3. In this embodiment, the number of the air guide holes 307 is four, and the number of the air guide channels 308 is also four.

[0061] As an example, the heat dissipation ring 301 and the heat dissipation layer 304 are made of the same material. The heat dissipation ring 301 and the heat dissipation layer 304 can be made of any metal material selected from the group consisting of copper, iron, tungsten, and molybdenum. Preferably, in this embodiment, the heat dissipation ring 301 and the heat dissipation layer 304 are made of copper.

[0062] As an example, the tensile strength of the heat dissipation layer 304 ranges from 200 MPa to 250 MPa. For example, the tensile strength of the heat dissipation layer 304 can be 210 MPa, 215 MPa, 220 MPa, 225 MPa, 230 MPa, 235 MPa, 240 MPa, or 245 MPa. In this embodiment, the heat dissipation layer 304 is made of copper and has a tensile strength of 220 MPa. The high tensile strength of the heat dissipation layer 304 can enhance the impact resistance of the semiconductor package structure 3, thereby further protecting the chip 303.

[0063] As an example, a first thermal interface material layer 309 is provided between the first connection portion 3061 and the heat dissipation ring 301, and a second thermal interface material layer 310 is provided between the second connection portion 3062 and the heat dissipation layer 304. The materials of the first thermal interface material 309 and the second thermal interface material layer 310 can be polymer TIM, solid TIM, or other materials. For example, thermally conductive silicone can be selected as the first thermal interface material layer 309. This thermal interface material layer can avoid or minimize air inclusions, thereby achieving efficient heat conduction between the heat dissipation ring 301 and the heat dissipation layer 304 and the heat sink 306. Moreover, thermally conductive silicone can also serve as an adhesive to bond the device structure. Here, the first thermal interface material layer 309 can be used to bond the lower surface of the first connection portion 3061 and the upper surface of the heat dissipation ring 301 together.

[0064] As an example, the first thermal interface material layer 309 and the second thermal interface material layer 310 are made of the same material, which enables the first thermal interface material layer 309 and the second thermal interface material layer 310 to be formed in the same step. Figure 3 The second connection portion 3062 is located in the receiving space and contacts the inner wall of the heat dissipation ring 301. Since the first thermal interface material layer 309 and the second thermal interface material layer 310 are made of the same material, a thermal interface material (not shown in the figure) can be formed between the second connection portion 3062 and the inner wall of the heat dissipation ring 301 during the same step of forming the first thermal interface material layer 309 and the second thermal interface material layer 310, thereby further improving the heat dissipation capacity of the semiconductor packaging structure. In other embodiments, please refer to Figure 5, which is a structural schematic diagram of the semiconductor packaging structure of the present invention. The side wall of the second connecting portion 3062 may also be inclined, that is, the cross-street area of the second connecting portion 3062 gradually decreases in the direction of the heat sink 306 pointing to the chip 303. There is a certain gap between the second connecting portion 3062 and the inner wall of the sidewall heat dissipation ring 301. When forming the first thermal interface material layer 309 and the second thermal interface material layer 310, if the same material is used, the gap can be filled or not.

[0065] As an example, the semiconductor package structure 3 further includes a fixing adhesive layer 311 , which is located between the heat dissipation ring 301 and the heat dissipation layer 304 and the substrate 302 , and is used to fix the heat dissipation ring 301 and the heat dissipation layer 304 .

[0066] As an example, a filling layer 312 is further provided between the chip 303 and the substrate 302 for further fixing the chip 303 .

[0067] As an example, the heat sink 306 includes an aluminum alloy heat sink 306. Aluminum alloy has a high thermal conductivity (typically 100-200 W / m·K), which can quickly conduct heat from the surface of the heat sink 306 to the external air, thereby effectively reducing the temperature of the chip 303. In addition, the density of aluminum alloy is much lower than that of other heavy metals. Under the same volume, the aluminum alloy heat sink 306 is lighter, which can effectively reduce the inertial force of the semiconductor heat sink 306 when it falls to the ground, thereby reducing the impact on the heat ring 301, the heat dissipation layer 304, and the chip 303, thereby further preventing damage to the chip 303.

[0068] In order to demonstrate the good heat dissipation capability of the semiconductor package structure 3 of the present invention, the semiconductor package structure 3 was subjected to a temperature cycle test, an accelerated life test, and a high-temperature storage test after pre-treatment. The test results of the three tests were statistically analyzed, and Table 1 was obtained:

[0069] Table 1 Test results of the semiconductor packaging structure of the present invention

[0070] Test type Test conditions Test results Temperature cycle test Temperature range: -55℃~125℃ 700 cycles Accelerated life test Temperature: 130°C; relative humidity: 85% 96 hours High temperature storage test Temperature: 150℃ 1000 hours

[0071] It can be seen from Table 1 that the semiconductor packaging structure of the present invention can achieve 700 temperature cycles in a temperature change cycle from minus 50 degrees Celsius to 125 degrees Celsius; it can be maintained for 96 hours in an environment with a temperature of 130 degrees Celsius and a relative humidity of 85%; and it can persist for 1,000 hours in a high temperature environment with a temperature of 150 degrees Celsius. This shows that the semiconductor packaging structure of the present invention has both good heat dissipation capacity (i.e., heat resistance) and reliability. Among them, the pre-treatment includes three steps: high-temperature baking, humidity testing, and multiple reflows. Specifically, the steps of the pre-treatment are: first, the semiconductor packaging structure product is placed in a high-temperature environment of 125°C for baking for 24 hours; then, the product is placed in an environment with a temperature of 30°C and a relative humidity of 60% for 96 hours; finally, the product is subjected to three reflow soldering processes.

[0072] In addition, the performance of two package structures of the same size was tested. The comparison results are shown in Table 2 below:

[0073] Table 2 Performance comparison of two package structures of the same size

[0074] Package Product yield Heat dissipation performance Loss protection Package structure 1 × × Package structure 2

[0075] Among them, the packaging structure is Figure 1 The package structure shown in FIG. 1 is the semiconductor package structure of the present invention. As can be seen from Table 2, the semiconductor package structure of the present invention is better than that of FIG. Figure 1 The package structure shown has better heat dissipation and damage resistance.

[0076] In summary, the semiconductor packaging structure of the present invention includes: a substrate, a heat dissipation ring, a chip, a heat dissipation layer, and a heat sink, wherein the heat dissipation ring is located on the substrate and encloses a receiving space, the chip is located in the receiving space and is mounted on the substrate, the heat dissipation layer is located in the receiving space and covers the upper surface of the substrate, and a heat dissipation opening is provided in the heat dissipation layer to expose the chip, the plane where the upper surface of the heat dissipation layer is located is higher than the plane where the upper surface of the chip is located, the side walls of the heat dissipation opening are spaced apart from the side walls of the chip by a preset distance, and the heat sink covers the top of the chip and includes a first connection portion and a second connection portion, the first connection portion is connected to the upper surface of the heat dissipation ring, and the second connection portion is protruding from the lower surface of the first connection portion and connected to the upper surface of the heat dissipation layer. The semiconductor packaging structure of the present invention supports the heat sink by providing a heat dissipation ring and a heat dissipation layer, thereby preventing the heat sink from directly contacting the chip and preventing the heat sink from damaging the chip when it falls. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: substrate; A heat dissipation ring is located on the substrate and encloses a receiving space; a chip, located in the receiving space and mounted on the substrate; a heat dissipation layer, located in the receiving space and covering the upper surface of the substrate, wherein the heat dissipation layer is provided with a heat dissipation opening for exposing the chip, wherein the plane where the upper surface of the heat dissipation layer is located is higher than the plane where the upper surface of the chip is located, and the sidewalls of the heat dissipation opening are spaced a preset distance from the sidewalls of the chip; The heat sink covers the chip and includes a first connecting portion and a second connecting portion, wherein the first connecting portion is connected to the upper surface of the heat dissipation ring, and the second connecting portion is protruded from the lower surface of the first connecting portion and connected to the upper surface of the heat dissipation layer.

2. The semiconductor package structure according to claim 1, wherein: The number of the chips is one or more.

3. The semiconductor package structure according to claim 1, wherein: An air guide hole is provided in the heat dissipation ring, and the air guide hole passes through the inner wall and the outer wall of the heat dissipation ring. An air guide channel connecting the air guide hole and the heat dissipation opening is provided in the heat dissipation layer.

4. The semiconductor package structure according to claim 3, wherein: The number of the air guide holes is one or more, and the number of the air guide channels is consistent with the number of the air guide holes.

5. The semiconductor package structure according to claim 1, wherein: The heat dissipation ring and the heat dissipation layer are made of the same material.

6. The semiconductor package structure according to claim 1, wherein: The tensile strength of the heat dissipation layer ranges from 200 MPa to 250 MPa.

7. The semiconductor package structure according to claim 1, wherein: A first thermal interface material layer is provided between the first connecting portion and the heat dissipation ring, and a second thermal interface material layer is provided between the second connecting portion and the heat dissipation layer.

8. The semiconductor package structure according to claim 7, wherein: The first thermal interface material layer and the second thermal interface material layer are made of the same material.

9. The semiconductor package structure according to claim 1, wherein: The second connecting portion is located in the receiving space and contacts the inner wall of the heat dissipation ring.

10. The semiconductor package structure according to claim 1, wherein: The radiator comprises an aluminum alloy radiator.

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