A load-bearing fast cold start circuit suitable for single-inductor multi-output boost chip

Abstract

The application relates to the field of power management chips, and discloses a loadable fast cold start circuit suitable for a single-inductor multi-output Boost chip. The circuit is composed of a first-stage pre-buffer, a ring oscillator, a first-stage pre-starting charge pump, a second-stage main buffer, a second-stage main charge pump and an output-stage buffer. The circuit automatically selects a higher voltage in the multi-output as a power supply voltage through a high-voltage selector of the first-stage pre-buffer and the second-stage main buffer; a backflow prevention diode is arranged between the output end of the second-stage main buffer and the output-stage buffer to form a fast starting path; the first-stage pre-starting charge pump and the second-stage main charge pump adopt a cross-coupling structure to realize one-time and three-time multiplication, and provide stable power supply and bias voltage for the output-stage buffer. The circuit has compact structure and low cost, has fast starting speed and strong load driving capacity in a wide input range, and meets various requirements of the single-inductor multi-output Boost chip on the cold start circuit.

Description

Technical Field

[0001] This application relates to the field of power management chips, and in particular to cold start circuit technology for switching power supplies. Background Technology

[0002] In the field of power management chips, Single Inductor Multiple Output (SIMO) Boost chips are widely used in portable electronic devices, IoT terminals, and wearable devices due to their high integration and low cost. These chips require a cold-start circuit to provide a stable operating voltage to the chip's internal logic circuits during the initial power-up phase, ensuring the entire power management system can start and operate normally.

[0003] Traditional cold-start circuits are typically based on simple linear regulators or single-stage charge pump structures. These circuits perform reasonably well at higher operating voltages, but often suffer from slow start-up speeds and poor driving capabilities when battery voltages are low. This is especially true in portable devices, where the battery voltage gradually decreases as the battery discharges, making the performance of the cold-start circuit particularly critical under low-voltage conditions.

[0004] Existing single-stage charge pump cold-start circuits typically offer only a limited voltage boost, making it difficult to guarantee sufficient output voltage over a wide input range, especially when the input voltage is close to the minimum operating voltage. Furthermore, these cold-start circuits generally have weak drive capability, primarily suitable for driving capacitive loads, while their drive capability is clearly insufficient for logic circuit loads requiring larger operating currents.

[0005] On the other hand, the unique operating mode of a single-inductor multi-output Boost chip requires the cold-start circuit to intelligently switch between multiple outputs to select the optimal power supply path. However, existing technologies lack cold-start circuit designs specifically optimized for the SIMO architecture, failing to fully utilize the multi-output characteristics to improve startup efficiency.

[0006] Furthermore, traditional cold-start circuits often neglect reverse-current protection in their output stage design, which can negatively impact the operating point of the charge pump in the preceding stage due to load changes in the subsequent circuits, affecting the stability of the entire system. Additionally, the output bias design often employs a simple Zener diode structure, making the output voltage highly susceptible to temperature and process fluctuations, thus failing to provide a precise and stable output voltage.

[0007] Therefore, for single-inductor multi-output Boost chips, there is an urgent need for a cold-start circuit that can start quickly over a wide input range, has strong driving capability, simple structure, and low cost, in order to meet the high-performance requirements of modern portable electronic devices for power management systems. Summary of the Invention

[0008] The purpose of this application is to provide a fast cold-start circuit with load capability suitable for single-inductor multi-output Boost chips, so as to solve the problems mentioned in the background art.

[0009] This application discloses a fast cold-start circuit suitable for single-inductor multi-output Boost chips, comprising:

[0010] The first-stage pre-buffer has its input connected to the first output voltage Vo1 and the second output voltage Vo2 of the single-inductor multi-output Boost chip, and its output output is the first-stage startup power supply voltage VS_Pre. It has a built-in high-voltage selector to select the higher of the first output voltage or the second output voltage as the power supply voltage for the first-stage pre-start charge pump.

[0011] A ring oscillator, whose input is connected to the output of the first-stage pre-buffer to receive the first-stage startup power supply voltage, and whose output output is a clock frequency fS_Pre that operates in the voltage domain of the first-stage startup power supply voltage and is related to the current Iout.

[0012] The first-stage pre-start charge pump VCP_Pre has its input terminal connected to the output terminal of the first-stage pre-buffer to receive the first-stage start-up power supply voltage and connected to the output terminal of the ring oscillator to receive the clock frequency as the bootstrap clock. Its output terminal outputs the voltage VCP_Pre after doubling the input voltage.

[0013] The second-stage main buffer SF-buffer has its input terminal connected to the output terminal of the first-stage pre-start charge pump, and its output terminal outputs the second-stage power supply voltage VS_SF.

[0014] A level shifter, whose input is connected to the output of the ring oscillator, is used to convert the clock frequency from the first-stage startup power supply voltage domain to the second-stage power supply voltage domain, and outputs a clock frequency fCP.

[0015] The second-stage main charge pump Main CP has its input terminal connected to the output terminal of the second-stage main buffer to receive the second-stage power supply voltage and its output terminal connected to the output terminal of the level shifter to receive the clock frequency as a bootstrap clock, which is used to triple the input voltage. The first-stage output terminal outputs a double voltage VCP_X2 and the second-stage output terminal outputs a triple voltage VCP_X3.

[0016] The output stage buffer has its power supply terminal connected to the first stage output terminal of the second stage main charge pump as the power supply voltage, and its bias terminal connected to the second stage output terminal of the second stage main charge pump to provide bias voltage for the Zener diode. The output terminal outputs a stable and powerful output voltage Vout.

[0017] A backflow prevention diode DO_SF is connected between the output terminal of the second-stage main buffer and the output terminal of the output stage buffer, which provides a fast start-up path for the output voltage.

[0018] In a preferred embodiment, the first-stage pre-buffer includes: a source follower output buffer MO_Pre, which eliminates the additional power consumption introduced by the operational amplifier in a traditional buffer stage; a passive reverse-current protection diode biasing a Zener diode, with the reverse breakdown voltage of the Zener diode serving as the bias voltage of the source follower output buffer, featuring a simple structure; and a high-voltage selector including a first pre-charge switch S1_Pre and a second pre-charge switch S2_Pre, wherein each path has a passive reverse-current protection diode consisting of a diode-connected NMOS and a reverse-connected NMOS. To prevent backflow current from higher voltage paths into lower voltage paths and to ensure reliable and stable power supply to the entire circuit, the ring oscillator includes a constant peak current source. The input current limiting resistor RS1 determines the input current Iin of the current source, and the gate-source voltage setting resistor RS2 determines the gate-source voltage VGSN1 of the NMOS transistor MSN1 in the current source, which in turn determines the output current. The output current provides bias current to the current-controlled ring oscillator CCO through a current mirror composed of the first PMOS transistor MSP1 and the second PMOS transistor MSP2, ensuring the stability of its output clock frequency.

[0019] In a preferred embodiment, the high-voltage selector includes a first pre-charge switch and a second pre-charge switch; when the first output voltage is high, the first pre-charge switch is closed and the second pre-charge switch is turned off, and the first output voltage supplies power to the bias circuit of the first-stage pre-buffer and the first-stage pre-start charge pump; when the second output voltage is high, the second pre-charge switch is closed and the first pre-charge switch is turned off, and the second output voltage supplies power to the bias circuit of the first-stage pre-buffer and the first-stage pre-start charge pump.

[0020] In a preferred embodiment, the first-stage pre-start charge pump includes a first NMOS switch MN1, a second NMOS switch MN2, a first PMOS switch MP1, a second PMOS switch MP2, a first capacitor CN_Pre, and a second capacitor CP_Pre. Driven by the first phase clock frequency f1_Pre and the second phase clock frequency f2_Pre output from the ring oscillator, a cross-coupled structure is used to achieve a boost output of one-times the first-stage start-up power supply voltage, thereby improving the driving performance of the charge pump.

[0021] In a preferred embodiment, the bias circuit of the second-stage main buffer includes a reverse breakdown Zener diode and a diode for threshold voltage compensation, the threshold voltage compensation diode being used to increase the voltage value and driving capability of the output bias voltage, the second-stage power supply voltage.

[0022] In a preferred embodiment, the second-stage main buffer includes a first switch S1_SF, a second switch S2_SF, and an output current-limiting resistor R1_O. When the first output voltage is high, the first switch is turned off and the second switch is closed, grounding the bias circuit on the second output voltage side, and the second-stage main buffer is powered by the first output voltage. When the second output voltage is high, the second switch is turned off and the first switch is closed, grounding the bias circuit on the first output voltage side, and the second output voltage is powered by the second main buffer.

[0023] In a preferred embodiment, the second-stage main charge pump adopts a two-stage boost cross-coupling design. Driven by the first phase clock frequency f1_SF and the second phase clock frequency f2_SF output by the level shifter, the second-stage power supply voltage is boosted by two times to output a voltage twice as the stable energy supply for the output stage buffer, and boosted by three times to output a voltage three times as the higher driving voltage for the bias branch of the output stage buffer.

[0024] In a preferred embodiment, the output stage buffer employs an output buffer stage with anti-reverse current technology, comprising: a Zener diode D1 with its anode grounded; a source follower whose input terminal is connected to the cathode of the Zener diode and whose output terminal outputs the output voltage; and a bias branch comprising a bias pull-up resistor R1, a bias pull-down resistor R2, and an anti-reverse current diode D2. The triple voltage provides bias to the Zener diode through the bias pull-down resistor and the anti-reverse current diode, and the double voltage serves as the supply voltage for the source follower, stabilizing the output voltage at approximately 5V after threshold voltage level shifting. Furthermore, the anti-reverse current technology eliminates the influence of subsequent circuitry on the charge pump's operating point.

[0025] The fast cold-start circuit for single-inductor multi-output Boost chips of the present invention has the following technical advantages:

[0026] First, a fast startup path is formed by connecting the anti-backflow diode DO_SF between the output terminal of the second-stage main buffer SF-buffer and the output terminal of the output buffer, effectively improving the circuit's startup speed. In the initial startup phase, current can flow directly from the second-stage power supply voltage VS_SF to the output voltage Vout, accelerating the rise of the output voltage and significantly shortening the cold start time.

[0027] Secondly, a multi-stage buffer boost structure is adopted, especially the first-stage pre-start charge pump VCP_Pre which doubles the first-stage startup power supply voltage VS_Pre, and the second-stage main charge pump Main CP which triples the second-stage power supply voltage VS_SF. This provides sufficiently high double voltage VCP_X2 and triple voltage VCP_X3, significantly improving the circuit's driving capability and performance. The output stage buffer can output a stable output voltage of around 5V, meeting the power supply requirements of subsequent circuits.

[0028] Third, the output buffer stage design of each stage of the buffer adopts anti-backflow technology, which effectively eliminates the influence of the subsequent circuit on the operating point of the preceding charge pump and ensures the stable operation of the circuit. At the same time, the application of the high-voltage selector in the first-stage pre-buffer and the second-stage main buffer can automatically select the higher of the first output voltage Vo1 and the second output voltage Vo2 of the single-inductor multi-output Boost chip as the power supply voltage, thereby improving the power supply capability of the circuit.

[0029] Fourth, the threshold voltage compensation design of the second-stage main buffer provides the second-stage main charge pump with a higher and more powerful second-stage power supply voltage than the Zener diode breakdown voltage, thus improving the overall circuit performance. Meanwhile, the constant peak current source design of the ring oscillator, where the input current limiting resistor RS1 and the gate-source voltage setting resistor RS2 work together, ensures the stability of the clock frequency fS_Pre and the level-shifted clock frequency fCP, providing a reliable guarantee for the normal operation of the charge pump.

[0030] Finally, this invention features a simple structure, low cost, and small footprint, making it suitable for integration into power management chips. Through its fast startup and strong drive capability over a wide input range, it effectively overcomes the limitation of traditional cold-start circuits that can only drive capacitive loads, thus meeting the various requirements of single-inductor multi-output Boost chips for cold-start circuits.

[0031] The specification of this application contains numerous technical features distributed across various technical solutions. Listing all possible combinations of these technical features (i.e., technical solutions) would make the specification excessively lengthy. To avoid this problem, the various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which are considered to have been described in this specification), unless such a combination of technical features is technically infeasible. For example, one example discloses feature A+B+C, and another example discloses feature A+B+D+E. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; they cannot be used simultaneously. Feature E can technically be combined with feature C. Therefore, the solution A+B+C+D should not be considered as described because it is technically infeasible, while the solution A+B+C+E should be considered as described. Attached Figure Description

[0032] Figure 1 This is an overall structural block diagram of a load-carrying fast cold-start circuit suitable for a single-inductor multi-output Boost chip according to an embodiment of this application.

[0033] Figure 2 This is a detailed circuit diagram of the first-stage pre-buffer in a load-carrying fast cold-start circuit suitable for a single-inductor multi-output Boost chip according to an embodiment of this application.

[0034] Figure 3 This is a detailed circuit diagram of the second-stage main buffer in a load-bearing fast cold-start circuit suitable for a single-inductor multi-output Boost chip according to an embodiment of this application.

[0035] Figure 4 This is a detailed circuit diagram of the first-stage pre-start charge pump and the second-stage main charge pump in a load-bearing fast cold-start circuit suitable for a single-inductor multi-output Boost chip according to an embodiment of this application.

[0036] Figure 5 This is a detailed circuit diagram of a ring oscillator and a level shifter in a load-capable fast cold-start circuit for a single-inductor multi-output Boost chip according to an embodiment of this application.

[0037] Figure 6 This is a detailed circuit diagram of the output stage buffer in a load-capable fast cold-start circuit suitable for a single-inductor multi-output Boost chip according to an embodiment of this application. Detailed Implementation

[0038] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0039] Explanation of some concepts:

[0040] Single Inductor Multiple Output (SIMO) Boost Chip: This refers to an integrated circuit chip that uses a single inductor to provide boost function for multiple output channels. It achieves independent control of multiple output voltages through time-division multiplexing technology, and has the advantages of high integration and low cost.

[0041] Cold start circuit: refers to the circuit that provides a stable operating voltage to the internal logic circuits of the chip during the initial power-on phase of the system, ensuring that the entire power management system can start and operate normally.

[0042] Charge pump: A switch-capacitor circuit that does not require an inductor. It achieves voltage conversion through the charging and discharging of a capacitor and is commonly used in boost and buck applications.

[0043] Cross-coupling structure: refers to the use of cross-connected switching transistors and capacitors in a charge pump, which creates a cross-coupling relationship in the charge transport path, thereby improving the driving performance and energy conversion efficiency of the charge pump.

[0044] Anti-backflow technology: refers to the technology of preventing current from flowing back from high potential to low potential through a specific circuit structure. It is often used in multi-stage power conversion circuits to prevent the subsequent circuit from having an adverse effect on the preceding circuit.

[0045] High voltage selector: refers to a circuit structure that can automatically select the higher voltage from multiple input voltages as the output, thereby improving the system's power supply capacity and reliability.

[0046] Vth compensation design: refers to the design technique of improving output voltage and driving capability by compensating for the voltage drop caused by the threshold voltage (Vth) of the MOSFET through a specific circuit.

[0047] Ring oscillator: An oscillating circuit consisting of an odd number of inverters cascaded in a ring, capable of generating a continuous clock signal to provide a bootstrap clock for a charge pump.

[0048] Level shifter: A circuit that converts a signal from one voltage domain to another, ensuring that the signal is correctly transmitted between different voltage levels.

[0049] Driving capability: refers to the ability of a circuit to provide current to a load, reflecting the strength of the circuit's ability to drive the load.

[0050] The following is a brief summary of some of the innovative aspects of this application:

[0051] The fast cold start circuit of this invention cleverly solves the cold start dilemma of single-inductor multi-output Boost chips by combining a unique multi-stage progressive voltage boost architecture with a backflow prevention complementary feedback compensation mechanism. In the system, the high-voltage selector of the first-stage pre-buffer uses an alternating switching mechanism of the first pre-charge switch S1_Pre and the second pre-charge switch S2_Pre, combined with a passive anti-backflow diode structure, to establish the basic first-stage startup power supply voltage VS_Pre. This voltage drives the clock frequency fS_Pre generated by the ring oscillator, which is boosted by one-fold through the cross-coupling structure of the first-stage pre-start charge pump VCP_Pre, and then drives the second-stage main buffer SF-buffer, which adopts a threshold voltage compensation design, to output the second-stage power supply voltage VS_SF. The second-stage power supply voltage is selected through a dedicated circuit with a switchable high-voltage path of the first switch S1_SF and the second switch S2_SF, and forms a direct startup path through the anti-backflow diode DO_SF. It works in conjunction with the two-stage boost system of the second-stage main charge pump Main CP (double voltage (VCP_X2) = 2 × second-stage power supply voltage, triple voltage (VCP_X3) = 3 × second-stage power supply voltage) to achieve fast cold start capability over a wide input range.

[0052] In particular, the grounded configuration of the Zener diode D1 in the output buffer, along with the bias branch design consisting of the bias pull-up resistor R1, the bias pull-down resistor R2, and the anti-reverse-current diode D2, enables the source follower driven by the bias voltage to output a stable 5V output voltage Vout. This ensures both driving capability and overvoltage clamping protection. During the initial low-voltage startup phase, the output voltage rise rate is limited by the setup time of the multi-stage multiplication path. The fast-path design of the anti-reverse-current diode DO_SF complements the traditional multi-stage buffer boost path, overcoming the limitation of typical cold-start circuits that can only drive capacitive loads. This achieves an unprecedented level of efficiency and speed in driving various loads.

[0053] The coupling of this special structure and working principle requires designers to find a precise balance between multi-level voltage domain conversion, clock signal bootstrapping technology and load driving capability, which cannot be easily achieved by simply superimposing existing technologies or conventional design ideas.

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0055] In this application's specification, to make the description clearer and more concise, some technical features are represented using English letter codes. It should be clarified that the technical features represented solely by letter codes in this application have the same meaning as the corresponding technical features represented by their Chinese names plus letter codes. For example, "VS_Pre" and "First-stage startup power supply voltage (VS_Pre)" refer to the same technical feature, and "VS_SF" and "Second-stage power supply voltage (VS_SF)" refer to the same technical feature. Other similar technical features represented by English letter codes are also equivalent to their corresponding technical features represented by their Chinese names plus letter codes. When reading and understanding this application, please treat the technical features represented solely by letter codes as equivalent to their corresponding technical features represented by their Chinese names plus letter codes. The technical features involving English letter codes include, but are not limited to:

[0056] Single Inductor Multiple Output (SIMO);

[0057] Output voltage (Vo) of a single-inductor multi-output Boost chip;

[0058] The first output voltage (Vo1) of a single-inductor multi-output Boost chip;

[0059] The second output voltage (Vo2) of a single-inductor multi-output Boost chip;

[0060] The first pre-charge switch (S1_Pre) in the first-stage pre-buffer;

[0061] The second pre-charge switch (S2_Pre) in the first-stage pre-buffer;

[0062] The output voltage of the first-stage pre-start charge pump is VCP_Pre;

[0063] The output source follower of the first-stage pre-buffer (MO_Pre);

[0064] The first-stage startup power supply voltage (VS_Pre) output by the first-stage pre-buffer;

[0065] The first switch (S1_SF) in the second-stage main buffer (SF-buffer);

[0066] The second switch (S2_SF) in the second-stage main buffer;

[0067] The output current-limiting resistor (R1_O) of the second-stage main buffer;

[0068] The second-stage power supply voltage (VS_SF) output by the second-stage main buffer;

[0069] Anti-backflow diode (DO_SF) between the output of the second-stage main buffer and the output stage buffer; output voltage (Vout) of the output stage buffer;

[0070] The input current limiting resistor (RS1) of the current source in the ring oscillator; the gate-source voltage setting resistor (RS2) of the ring oscillator;

[0071] The gate-source voltage (VGSN1) of the NMOS transistor in the ring oscillator;

[0072] The first NMOS transistor (MSN1) in the ring oscillator;

[0073] The second NMOS transistor (MSN2) in the ring oscillator;

[0074] The output current (Iout) of the peak current source;

[0075] The first PMOS transistor (MSP1) in the ring oscillator output current mirror;

[0076] The second PMOS transistor (MSP2) in the ring oscillator output current mirror;

[0077] The clock frequency (fS_Pre) output by the ring oscillator;

[0078] The clock frequency (fCP) output of the level shifter;

[0079] The first phase clock frequency (f1_Pre) of the first-stage pre-start charge pump;

[0080] The second phase clock frequency (f2_Pre) of the first-stage pre-start charge pump;

[0081] The first capacitor (CN_Pre) in the first-stage pre-start charge pump;

[0082] The second capacitor (CP_Pre) in the first-stage pre-start charge pump;

[0083] The first NMOS switch (MN1) in the first-stage pre-start charge pump;

[0084] The second NMOS switch (MN2) in the first-stage pre-start charge pump;

[0085] The first PMOS switch (MP1) in the first-stage pre-start charge pump;

[0086] The second PMOS switch (MP2) in the first-stage pre-start charge pump;

[0087] The first phase clock frequency (f1_SF) of the second-stage main charge pump (Main CP);

[0088] The second phase clock frequency (f2_SF) of the second-stage main charge pump;

[0089] The second-stage main charge pump outputs twice the voltage (VCP_X2);

[0090] The second-stage main charge pump outputs a triple voltage (VCP_X3);

[0091] The bias voltage of the output stage buffer bias branch;

[0092] Current-controlled ring oscillator (CCO);

[0093] Threshold voltage (Vth).

[0094] In this application, for the sake of brevity, some English codes and abbreviations may have related but slightly different meanings in different contexts. Regarding the distinction between circuit modules and voltage / signal, when an English code represents a circuit module, its corresponding Chinese name is used directly, for example, "First-stage pre-start charge pump (VCP_Pre)" represents the circuit module; when the same English code represents the voltage / signal generated by the module, it will be clearly indicated in the context, for example, "VCP_Pre voltage" represents the voltage output by the first-stage pre-start charge pump, and "VS_Pre" represents the first-stage startup power supply voltage.

[0095] Regarding the distinction between voltage value and voltage domain, "VS_Pre" can represent the specific value of the first-stage startup power supply voltage, or it can represent the voltage domain at that voltage level, such as "VS_Pre voltage domain". Similarly, "VS_SF" can represent the specific value of the second-stage power supply voltage, or it can represent the corresponding voltage domain.

[0096] Regarding the distinction between connection ports and voltage, "VCP_X2" can represent a double voltage value or refer to the first stage output terminal of the second-stage main charge pump; "VCP_X3" can represent a triple voltage value or refer to the second stage output terminal of the second-stage main charge pump; "Vout" can represent an output voltage value or refer to the output terminal of the output stage buffer.

[0097] In terms of describing switching devices and states, "S1_Pre", "S2_Pre", "S1_SF", "S2_SF" etc. not only represent the corresponding switching devices, but also use action terms such as "closed" and "off" when describing their states.

[0098] Regarding the description of paths and regions, "Vo1" and "Vo2" can represent the corresponding first and second output voltages, and can also be used to describe the region concepts such as "Vo1 side" and "Vo2 side" when describing power supply paths.

[0099] In terms of the distinction between device and function, "DO_SF" indicates a reverse-current protection diode at the device level, and also refers to the fast startup path it forms in the functional description.

[0100] Unless otherwise specified, all physical quantities used in this article are in the International System of Units (SI), with voltage in volts (V), current in amperes (A), resistance in ohms (Ω), capacitance in farads (F), time in seconds (s), and frequency in hertz (Hz).

[0101] The first embodiment of this application relates to a load-carrying fast cold-start circuit suitable for a single-inductor multi-output Boost chip, such as... Figures 1 to 6 As shown, it includes:

[0102] The first-stage pre-buffer has its input connected to the first output voltage Vo1 and the second output voltage Vo2 of the single-inductor multi-output Boost chip, and its output output is the first-stage startup power supply voltage VS_Pre. It has a built-in high-voltage selector to select the higher of the first output voltage or the second output voltage as the power supply voltage for the first-stage pre-start charge pump.

[0103] The ring oscillator has its input connected to the output of the first-stage pre-buffer to receive the first-stage startup power supply voltage VS_Pre, and its output output is a clock frequency fS_Pre that operates in the voltage domain of the first-stage startup power supply voltage VS_Pre and is related to the current Iout.

[0104] The first-stage pre-start charge pump VCP_Pre has its input terminal connected to the output terminal of the first-stage pre-buffer to receive the first-stage start-up power supply voltage VS_Pre and connected to the output terminal of the ring oscillator to receive the clock frequency fS_Pre as the bootstrap clock. Its output terminal outputs the voltage VCP_Pre after doubling the input voltage.

[0105] The second-stage main buffer SF-buffer has its input terminal connected to the output terminal of the first-stage pre-start charge pump VCP_Pre, and its output terminal outputs the second-stage power supply voltage VS_SF.

[0106] A level shifter, whose input is connected to the output of the ring oscillator, is used to convert the clock frequency fS_Pre from the first-stage startup power supply voltage VS_Pre voltage domain to the second-stage power supply voltage VS_SF voltage domain, and outputs a clock frequency fCP.

[0107] The second-stage main charge pump, Main CP, has its input terminal connected to the output terminal of the second-stage main buffer, SF-buffer, to receive the second-stage power supply voltage, VS_SF, and is also connected to the output terminal of the level shifter to receive the clock frequency fCP as a bootstrap clock. It is used to triple the input voltage. The first-stage output terminal outputs a double voltage VCP_X2, and the second-stage output terminal outputs a triple voltage VCP_X3.

[0108] The output buffer has its power supply terminal connected to the first stage output terminal of the second stage main charge pump (Main CP) as the power supply voltage, and its bias terminal connected to the second stage output terminal of the second stage main charge pump (Main CP) to provide a bias voltage for the Zener diode. The output terminal outputs a stable and powerful output voltage Vout.

[0109] A backflow prevention diode DO_SF is connected between the output terminal of the second-stage main buffer SF-buffer and the output terminal of the output stage buffer Output Buffer, which provides a fast start-up path for the output voltage Vout.

[0110] Optionally, the first-stage pre-buffer includes: a source follower output buffer MO_Pre, which eliminates the additional power consumption introduced by the operational amplifier in traditional buffer stages; a passive anti-reverse-current diode biasing a Zener diode, with the reverse breakdown voltage of the Zener diode serving as the bias voltage of the source follower output buffer MO_Pre, featuring a simple structure; a high-voltage selector including a first pre-charge switch S1_Pre and a second pre-charge switch S2_Pre, wherein each path has a passive anti-reverse-current diode composed of a diode-connected NMOS and a reverse-connected NMOS, used to prevent reverse current from the higher-voltage path from entering the lower-voltage path, achieving reliable and stable power supply to the entire circuit; the ring oscillator Ring The oscillator includes a constant peak current source, where the input current limiting resistor RS1 determines the input current Iin of the current source, and the gate-source voltage setting resistor RS2 determines the gate-source voltage VGSN1 of the NMOS transistor MSN1 in the current source, which in turn determines the output current. The output current provides bias current to the current-controlled ring oscillator CCO through a current mirror composed of the first PMOS transistor MSP1 and the second PMOS transistor MSP2, ensuring the stability of its output clock frequency fS_Pre.

[0111] Optionally, the high-voltage selector includes a first pre-charge switch S1_Pre and a second pre-charge switch S2_Pre. When the first output voltage Vo1 is high, the first pre-charge switch S1_Pre is closed and the second pre-charge switch S2_Pre is turned off. The first output voltage Vo1 supplies power to the bias circuit of the first-stage pre-buffer and the first-stage pre-start charge pump VCP_Pre. When the second output voltage Vo2 is high, the second pre-charge switch S2_Pre is closed and the first pre-charge switch S1_Pre is turned off. The second output voltage Vo2 supplies power to the bias circuit of the first-stage pre-buffer and the first-stage pre-start charge pump VCP_Pre.

[0112] Optionally, the first-stage pre-start charge pump VCP_Pre includes a first NMOS switch MN1, a second NMOS switch MN2, a first PMOS switch MP1, a second PMOS switch MP2, a first capacitor CN_Pre, and a second capacitor CP_Pre. Driven by the first phase clock frequency f1_Pre and the second phase clock frequency f2_Pre output by the Ring Oscillator, a cross-coupled structure is adopted to achieve a boost output of the first-stage start-up power supply voltage VS_Pre, thereby improving the driving performance of the charge pump.

[0113] Optionally, the bias circuit of the second-stage main buffer SF-buffer includes a reverse breakdown Zener diode and a diode for threshold voltage Vth compensation, wherein the threshold voltage Vth compensation diode is used to improve the voltage value and driving capability of the output bias voltage, the second-stage power supply voltage VS_SF.

[0114] Optionally, the second-stage main buffer SF-buffer includes a first switch S1_SF, a second switch S2_SF, and an output current-limiting resistor R1_O. When the first output voltage Vo1 is high, the first switch S1_SF is turned off, the second switch S2_SF is closed, and the bias circuit on the second output voltage Vo2 side is grounded, so that the first output voltage Vo1 supplies power to the second-stage main buffer SF-buffer. When the second output voltage Vo2 is high, the second switch S2_SF is turned off, the first switch S1_SF is closed, and the bias circuit on the first output voltage Vo1 side is grounded, so that the second output voltage Vo2 supplies power to the second-stage main buffer SF-buffer.

[0115] Optionally, the second-stage main charge pump Main CP adopts a two-stage boost cross-coupling design. Driven by the first-phase clock frequency f1_SF and the second-phase clock frequency f2_SF output by the level shifter, the second-stage power supply voltage VS_SF is boosted twice to output a double voltage VCP_X2 as the stable energy supply for the output buffer, and boosted three times to output a triple voltage VCP_X3 as the higher driving voltage for the bias branch of the output buffer.

[0116] Optionally, the output buffer stage employs an output buffer stage with anti-reverse current technology, comprising: a Zener diode D1 with its anode grounded; a source follower whose input terminal is connected to the cathode of the Zener diode D1 and whose output terminal outputs an output voltage Vout; and a bias branch comprising a bias pull-up resistor R1, a bias pull-down resistor R2, and an anti-reverse current diode D2. The triple voltage VCP_X3 provides bias voltage to the Zener diode D1 through the bias pull-down resistor R2 and the anti-reverse current diode D2, while the double voltage VCP_X2 serves as the power supply voltage for the source follower. This ensures that the output voltage Vout is stabilized at approximately 5V after being shifted by the threshold voltage Vth, and the anti-reverse current technology eliminates the influence of subsequent circuitry on the charge pump's operating point.

[0117] To make the technical solution of the present invention clearer and more understandable, it is now combined with Figures 1 to 6 Preferred embodiments of the present invention will be described in detail, but it should be understood that the described embodiments are merely exemplary and not restrictive.

[0118] Figure 1 This is a block diagram of the overall structure of the low-voltage cold start circuit of the present invention. The diagram clearly shows the various functional modules of the circuit and their connections. Figure 1 As shown, the fast cold-start circuit for single-inductor multi-output Boost chips disclosed in this invention mainly consists of seven parts: a first-stage pre-buffer, a first-stage pre-start charge pump VCP_Pre, a second-stage main buffer SF-buffer, a second-stage main charge pump Main CP, an output buffer, a ring oscillator, and a level shifter.

[0119] The first-stage pre-buffer receives the first output voltage Vo1 and the second output voltage Vo2 from the single-inductor multi-output Boost chip as inputs, and selects the higher one as the power supply voltage through a built-in high-voltage selector. The output of the pre-buffer is the first-stage startup power supply voltage VS_Pre, which is connected to the input of the first-stage pre-startup charge pump VCP_Pre and the operating voltage of the ring oscillator. The ring oscillator generates a clock frequency fS_Pre related to the current Iout. This clock signal is connected to the first-stage pre-startup charge pump VCP_Pre as its bootstrap clock signal and is also connected to a level shifter for voltage domain conversion. Driven by the clock frequency fS_Pre, the first-stage pre-startup charge pump VCP_Pre boosts the input voltage VS_Pre by one-fold, and the output voltage VCP_Pre is connected to the second-stage main buffer SF-buffer.

[0120] The second-stage main buffer SF-buffer receives the voltage VCP_Pre from the first-stage pre-start charge pump VCP_Pre, employs a threshold voltage Vth compensation design, and outputs the second-stage power supply voltage VS_SF. A level shifter converts the clock frequency fS_Pre output from the first-stage ring oscillator from the first-stage start-up power supply voltage VS_Pre voltage domain to the second-stage power supply voltage VS_SF voltage domain, outputting the clock frequency fCP. Driven by the second-stage power supply voltage VS_SF and the clock frequency fCP, the second-stage main charge pump Main CP triples the input voltage, resulting in a doubled voltage VCP_X2 for the first stage and a tripled voltage VCP_X3 for the second stage.

[0121] The output buffer's power supply terminal is connected to the first-stage output voltage VCP_X2 of the second-stage main charge pump Main CP as the power supply voltage. The bias terminal is connected to the second-stage output voltage VCP_X3 of the second-stage main charge pump Main CP as the bias voltage for the Zener diode. The output terminal outputs a stable and powerful output voltage Vout, which is stable at around 5V.

[0122] Specifically, a reverse-current protection diode DO_SF is connected between the output power supply voltage VS_SF of the second-stage main buffer SF-buffer and the output voltage Vout of the output buffer. Since the second-stage main buffer SF-buffer has a faster startup speed, the reverse-current protection diode DO_SF provides a fast startup path for the output voltage Vout, allowing current to flow to the output voltage Vout of the entire circuit during startup, thus accelerating the startup process of the entire circuit.

[0123] Through this multi-stage buffer boost structure and special fast start-up path design, the present invention achieves a cold start power supply voltage with fast start-up and strong driving capability over a wide input range.

[0124] Figure 2 This is a detailed circuit diagram of the first-stage pre-buffer of the present invention, illustrating its internal structure and working principle. Figure 2 As shown, the first-stage pre-buffer mainly includes a high-voltage selector, a bias circuit, an output buffer, and an anti-backflow diode.

[0125] The high-voltage selector includes two voltage input terminals: a first output voltage Vo1 and a second output voltage Vo2, which are connected to the first and second output voltages of a single-inductor multi-output Boost chip, respectively. When the chip starts up, the output voltage Vo of the single-inductor multi-output Boost chip gradually reaches the input voltage as the inductor charges. At this time, the high-voltage selector compares the voltages of the first output voltage Vo1 and the second output voltage Vo2, selecting the higher one as the energy supply path for the first-stage pre-buffer. When the first output voltage Vo1 is higher, the first pre-charge switch S1_Pre is closed, and the second pre-charge switch S2_Pre is turned off, with energy provided by the first output voltage Vo1. When the second output voltage Vo2 is higher, the second pre-charge switch S2_Pre is closed, and the first pre-charge switch S1_Pre is turned off, with energy provided by the second output voltage Vo2.

[0126] In the bias circuit section, the first-stage pre-buffer uses the chip output voltage Vo and the output voltage VCP_Pre of the first-stage pre-start charge pump to bias the Zener diode. Each path has a passive anti-reverse current diode consisting of a diode-connected NMOS and a reverse-connected NMOS to prevent reverse current from the higher voltage path from entering the lower voltage path, providing good isolation.

[0127] The output buffer adopts a source follower output buffer MO_Pre structure, as shown in MO1_Pre (or MO2_Pre), which eliminates the additional power consumption introduced by the op-amp in the traditional buffer stage. The reverse breakdown voltage of the Zener diode in the bias branch is used as the bias of the source follower output buffer MO_Pre, and the first-stage startup power supply voltage VS_Pre is output by the source follower output buffer MO_Pre as the first-stage startup power supply for the entire cold start circuit.

[0128] A configurable capacitor at the output is used to stabilize the first-stage startup power supply voltage VS_Pre, reduce ripple, and improve the driving capability of the first-stage pre-buffer. This first-stage startup power supply voltage VS_Pre provides the operating voltage for the Ring Oscillator and also provides the input voltage for the first-stage pre-start charge pump VCP_Pre.

[0129] This design enables the first-stage pre-buffer to provide the basic power supply for the entire circuit, drive the ring oscillator to start oscillating, and provide a stable power supply path for subsequent circuits. The use of a source follower output buffer MO_Pre as the output buffer and a passive anti-reverse-current diode to current bias the alpha diode makes the entire first-stage pre-buffer design simple and efficient.

[0130] Figure 3 This is a detailed circuit diagram of the second-stage main buffer SF-buffer of the present invention, illustrating its internal structure and working principle. Figure 3As shown, the second-stage main buffer SF-buffer employs a high-voltage selection design and a threshold voltage Vth compensation design. The second-stage main buffer SF-buffer also includes a high-voltage selector section, with the high-voltage selector circuit controlling the on / off states of the first switch S1_SF and the second switch S2_SF. Unlike the first-stage pre-buffer, the second-stage main buffer SF-buffer uses switches to turn off the bias of each path, rather than controlling the path on / off, to reduce switching losses. When the first output voltage Vo1 is high, the first switch S1_SF is off, and the second switch S2_SF is closed, pulling the bias path on the second output voltage Vo2 side to ground, allowing energy to be output from the first output voltage Vo1 side; when the second output voltage Vo2 is high, the second switch S2_SF is off, and the first switch S1_SF is closed, pulling the bias path on the first output voltage Vo1 side to ground, allowing energy to be output from the second output voltage Vo2 side. The grounding paths on both sides have current-limiting resistors R1_O as current-limiting resistors to reduce the overall power consumption of the circuit.

[0131] The bias circuit of the second-stage main buffer SF-buffer adopts a threshold voltage Vth compensation design, which includes a reverse breakdown Zener diode and a diode for compensating the output buffer threshold voltage Vth. This design makes the output second-stage power supply voltage VS_SF higher than the breakdown voltage of the Zener diode and has a stronger driving capability, thus improving the output performance of the circuit.

[0132] The output buffer section employs an output buffer stage with anti-backflow technology to prevent energy from the second-stage power supply voltage VS_SF from flowing to the low-voltage side, affecting the output voltage Vo and reducing efficiency. This design eliminates the influence of the subsequent circuitry on the operating point of the preceding charge pump, ensuring stable circuit operation.

[0133] Of particular note is that, since the second-stage main buffer SF-buffer has a faster startup speed, an anti-backflow diode DO_SF is added from the second-stage power supply voltage VS_SF and connected to the final output voltage Vout. During startup, current flows to the output voltage Vout of the entire circuit, forming a fast startup path and accelerating the startup of the entire circuit.

[0134] Through this design, the second-stage main buffer SF-buffer not only provides a higher and more powerful output bias for the second-stage main charge pump Main CP, but also improves the startup speed of the entire circuit through a fast startup path, achieving the technical goal of fast cold start.

[0135] Figure 4This is a detailed circuit diagram of the first-stage pre-start charge pump VCP_Pre and the second-stage main charge pump Main CP of this invention, showing the internal structure and working principle of the two charge pumps. Figure 4 As shown, both charge pumps employ a cross-coupling design, which effectively improves the driving performance of the charge pumps.

[0136] exist Figure 4 The left side is the first-stage pre-startup charge pump VCP_Pre, which includes a first NMOS switch MN1, a second NMOS switch MN2, a first PMOS switch MP1, a second PMOS switch MP2, a first capacitor CN_Pre, and a second capacitor CP_Pre. The first-stage pre-startup charge pump VCP_Pre adopts a 1x boost design, and its working principle is as follows: When the charge pump drive circuit outputs a high level for the first phase clock frequency f1_Pre and a low level for the second phase clock frequency f2_Pre, the second NMOS switch MN2 is turned on, and the upper plate of the first capacitor CN_Pre is charged to the first-stage startup power supply voltage VS_Pre; when the first phase clock frequency f1_Pre is low and the second phase clock frequency f2_Pre is high, since the voltage across the capacitor cannot change abruptly, the upper plate of the first capacitor CN_Pre is charged to 2 × the first-stage startup power supply voltage VS_Pre. At this time, the second PMOS switch MP2 is turned on, and 2 × the first-stage startup power supply voltage VS_Pre is transferred to the voltage VCP_Pre. The first NMOS switch MN1 and the first PMOS switch MP1 operate in the opposite state to the second NMOS switch MN2 and the second PMOS switch MP2. Therefore, the cross-coupled charge pump composed of the first NMOS switch MN1, the first PMOS switch MP1, the second NMOS switch MN2, the second PMOS switch MP2, the first capacitor CN_Pre, and the second capacitor CP_Pre achieves the ability to cross-transfer charge, providing a sufficiently high voltage bias for the first and second stage buffers when the input voltage is low.

[0137] exist Figure 4 The right side of the diagram represents the second-stage main charge pump (Main CP), which employs a double-boost design. Driven by the first-phase clock frequency f1_SF and the second-phase clock frequency f2_SF of the two-phase bootstrapping system, the second-stage power supply voltage VS_SF is doubled to a voltage doubled by VCP_X2 = 2 × VS_SF and a voltage tripled by VCP_X3 = 3 × VS_SF. The first-stage output voltage doubled by VCP_X2 provides a reliable and stable power supply to the output buffer, while the second-stage output voltage tripled by VCP_X3 provides sufficient driving performance for the bias branch of the output buffer to output a higher drive voltage.

[0138] The first-stage pre-startup charge pump VCP_Pre uses a non-overlapping clock generator as its driving circuit, while the second-stage main charge pump Main CP employs a stronger driving circuit to drive a larger bootstrap capacitor.

[0139] Through this design, the first-stage pre-start charge pump VCP_Pre multiplies the output of the first-stage pre-buffer, providing a stable and high bias voltage for the secondary buffer and improving the overall efficiency of the charge pump. Meanwhile, the second-stage main charge pump Main CP triples the output voltage of the second-stage main buffer SF-buffer, providing a stable bias and energy supply for the output buffer. This cross-coupling design of the two charge pumps effectively improves the driving performance of the charge pumps, providing a reliable and highly capable power supply voltage for the entire cold-start circuit.

[0140] Figure 5 This is a detailed circuit diagram of the Ring Oscillator and Level Shifter of the present invention, illustrating the internal structure and working principle of these two modules. Figure 5 As shown, this part is mainly divided into three functional areas: constant peak current source, current-controlled ring oscillator (CCO), and level shifter.

[0141] The constant peak current source section on the left includes a first NMOS transistor MSN1, a first PMOS transistor MSP1, a second PMOS transistor MSP2, an input current limiting resistor RS1, and a gate-source voltage setting resistor RS2. The input current limiting resistor RS1 determines the input current Iin of the current source; the gate-source voltage setting resistor RS2 determines the gate-source voltage VGSN1 of the first NMOS transistor MSN1, which in turn determines the output current Iout. The output current Iout provides bias current to the current-controlled ring oscillator CCO via a current mirror formed by the first PMOS transistor MSP1 and the second PMOS transistor MSP2, ensuring the stability of its output clock frequency fS_Pre.

[0142] The middle section is a current-controlled ring oscillator (CCO), composed of multiple inverters and capacitors. This oscillator receives a stable bias current from a constant peak current source and generates a stable clock signal, clock frequency fS_Pre. The current-controlled ring oscillator CCO operates in the voltage domain of the first-stage pre-buffer's output, the first-stage startup power supply voltage VS_Pre, and its output is used to drive the first-stage pre-start charge pump VCP_Pre.

[0143] The right side is the level shifter, which includes NMOS and PMOS transistors. The level shifter receives the clock signal frequency fS_Pre from the current-controlled ring oscillator (CCO). Through a level conversion circuit, it converts the voltage domain of the clock signal from the first-stage startup power supply voltage VS_Pre to the second-stage main buffer SF-buffer voltage domain, which is the second-stage power supply voltage VS_SF. The output clock signal frequency fCP is then used by the second-stage main charge pump Main CP.

[0144] Through this design, the ring oscillator generates a clock frequency fS_Pre that operates in the voltage domain of the first-stage startup power supply voltage VS_Pre and is related to the current Iout, providing a bootstrap clock for the entire charge pump. The level shifter then converts the clock signal from the voltage domain of the first-stage startup power supply voltage VS_Pre to the voltage domain of the second-stage power supply voltage VS_SF, outputting a clock frequency fCP. This ensures that the entire charge pump system can operate normally in different voltage domains, improving the stability and reliability of the system.

[0145] Working principle:

[0146] The present invention provides a load-bearing, fast cold-start circuit suitable for single-inductor, multi-output Boost chips. Based on low-voltage operation and fast startup technology, it mainly comprises seven functional parts, whose collaborative working principle is as follows:

[0147] When the circuit starts up, the output voltage Vo of the single-inductor multi-output Boost chip will gradually reach the input voltage as the inductor charges. The high-voltage selector built into the first-stage pre-buffer compares the first output voltage Vo1 and the second output voltage Vo2, selecting the higher one as the power supply voltage. The high-voltage selector controls the on / off state of the first pre-charge switch S1_Pre and the second pre-charge switch S2_Pre, ensuring reliable and stable power supply to the entire circuit. The first-stage startup power supply voltage VS_Pre output from the first-stage pre-buffer provides the operating voltage for the Ring Oscillator and also provides the input voltage for the first-stage pre-start charge pump VCP_Pre.

[0148] Under the bias of a constant peak current source, the ring oscillator outputs a clock frequency fS_Pre related to the current Iout. This clock signal serves as the bootstrap clock for the first-stage pre-start charge pump VCP_Pre, and is simultaneously converted by a level shifter into the clock frequency fCP of the second-stage voltage domain.

[0149] Driven by the clock frequency fS_Pre, the first-stage pre-start charge pump VCP_Pre uses a cross-coupling structure to double the first-stage startup power supply voltage VS_Pre. The output voltage VCP_Pre is connected to the second-stage main buffer SF-buffer to provide it with a stable and high bias voltage.

[0150] The second-stage main buffer SF-buffer employs a threshold voltage Vth compensation design and a high-voltage selection design. The high-voltage selector controls the on / off state of the first switch S1_SF and the second switch S2_SF, selecting the higher-voltage path for power supply. Its output second-stage power supply voltage VS_SF is connected to both the second-stage main charge pump Main CP and the output voltage Vout via the anti-backflow diode DO_SF, forming a fast-start path.

[0151] Driven by the clock frequency fCP, the second-stage main charge pump Main CP adopts a two-stage boost cross-coupling design, boosting the second-stage power supply voltage VS_SF by two times to output a double voltage VCP_X2, and boosting it by three times to output a triple voltage VCP_X3, which are respectively used as the stable energy supply for the output buffer and the higher drive voltage for the bias branch.

[0152] The output buffer stage employs anti-backflow technology. The anode of the Zener diode D1 is grounded, and the cathode receives the bias voltage provided by the triple voltage VCP_X3 through the bias branch. The source follower uses the double voltage VCP_X2 as its power supply voltage. The output voltage Vout is stabilized at around 5V after being shifted by the threshold voltage Vth.

[0153] Through this multi-stage buffer boost structure and special fast-start path design, the present invention achieves a cold-start power supply voltage with fast start-up and strong driving capability over a wide input range, effectively meeting the various requirements of single-inductor multi-output Boost chips for cold-start circuits.

[0154] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0155] The technical solution in this example is as follows: A specific first-stage pre-buffer provides the basic power supply for the entire circuit, drives the ring oscillator to start oscillating, and incorporates a higher voltage selector to select the power supply path for the entire charge pump; the first-stage pre-start charge pump multiplies the output of the first-stage pre-buffer, providing a stable and higher bias voltage for the secondary buffer, improving the overall efficiency of the charge pump; the second-stage main buffer adopts a Vth compensation design, providing a higher and more powerful output voltage for the main charge pump, and providing a fast start-up path for the output; the second-stage main charge pump triples the voltage output of the second-stage main buffer, providing a stable bias and power supply for the output stage buffer; the output stage buffer uses a simple structure to output a strong and stable 5V output voltage; the ring oscillator provides a bootstrap clock for the entire charge pump, and a level shifter is used to convert the clock to each voltage domain. This example, based on low-voltage operation and fast start-up technology, achieves a fast and powerful cold-start power supply voltage with a wide input range and high integration.

[0156] The first-stage pre-buffer uses a source follower as the output buffer, eliminating the additional power consumption introduced by the operational amplifier in traditional buffer stages. It employs a passive anti-reverse-current diode to align with the nanodiode for current biasing, resulting in a simple structure. A high-voltage selector is added to select the highest voltage path from the multiple output power management paths. The addition of this pre-buffer provides a reliable power supply for the subsequent ring oscillator and a stable energy supply path for the first-stage pre-start charge pump.

[0157] The second-stage main buffer employs a Vth compensation design in the bias stage to provide the main charge pump with a higher voltage and stronger driving capability output bias; a high-voltage selection design is added to select a higher voltage path for power supply, improving the power supply capability; an output buffer stage with anti-backflow technology is adopted to eliminate the influence of the subsequent circuit on the operating point of the preceding charge pump; and a fast start-up path is provided for the output stage buffer at its output node.

[0158] Both the first-stage pre-start charge pump and the second-stage main charge pump adopt a cross-coupling design, which effectively improves the driving performance of the charge pump. The first-stage pre-start charge pump adopts a 1x boost design to provide a sufficiently high voltage bias for the first and second stage buffers when the input voltage is low. The second-stage main charge pump adopts a 2x boost design. Its first-stage output provides a reliable and stable energy supply for the output stage buffer, while the second-stage output provides a sufficiently strong driving performance for the bias branch of the output stage buffer to output a higher driving voltage.

[0159] The output stage buffer also adopts an output buffer stage with anti-reverse current technology, eliminating the influence of the subsequent circuit on the charge pump operating point; a passive anti-reverse current diode is used in the bias branch to accelerate the start-up of the bias branch by utilizing the energy supply path; the output voltage is determined by the reverse breakdown voltage of the Zener diode, and after the Vth level is shifted by the first-stage source follower, it is stabilized at about 5V, providing overvoltage clamping protection for the subsequent circuit, and has the characteristics of simple structure and fast start-up speed.

[0160] The ring oscillator has a constant peak current source, providing a stable bias current for the current-controlled ring oscillator (CCO). The output of the CCO is the voltage domain of the first-stage pre-buffer, and the subsequent level shifter converts the voltage domain of this output into the voltage domain of the second-stage main buffer. The two outputs provide a reliable and stable bootstrap clock for the first-stage charge pump and the second-stage charge pump, respectively.

[0161] Furthermore, in this example, a fast start-up path is added to improve the output voltage start-up speed; a multi-stage buffer boost method is adopted to improve the driving capability and effectively protect the subsequent circuits; and a high-voltage path selector is added to provide a more stable and stronger driving power supply.

[0162] When the circuit starts up, the output Vo of the single-inductor multi-output Boost chip gradually reaches the input voltage as the inductor charges. At this time, the high-voltage selector in the first-stage pre-buffer compares these two voltages and selects the higher one as the energy supply path for the first-stage pre-buffer and the second-stage main buffer. When Vo1 is higher, S1_Pre in the first-stage pre-buffer is closed and S2_Pre is closed, with Vo1 providing energy; when Vo2 is higher, S2_Pre in the first-stage pre-buffer is closed and S1_Pre is closed, with Vo2 providing energy. The first-stage pre-buffer uses the chip output Vo and the output VCP_Pre of the first-stage pre-start charge pump to bias the Zener diode. Each path has a passive anti-reverse-current diode consisting of a diode-connected NMOS and a reverse-connected NMOS to prevent reverse current from flowing from the higher-voltage path into the lower-voltage path, providing good isolation. The reverse breakdown voltage of the Zener diode in the bias branch is used as the bias of the MO1_Pre (or MO2_Pre) source follower, and the output VS_Pre of MO1_Pre (or MO2_Pre) serves as the first-stage startup power supply for the entire cold start circuit.

[0163] Similarly, the second-stage main buffer also uses a high-voltage selector to control the energy supply path. It switches off the bias of each path via a switch, rather than controlling the path's on / off state to reduce switching losses. When Vo1 is high, S1_SF is off and S2_SF is closed, pulling the bias path on the Vo2 side to ground, allowing energy to be output from the Vo1 side. When Vo2 is high, S2_SF is off and S1_SF is closed, pulling the bias path on the Vo1 side to ground, allowing energy to be output from the Vo2 side. The grounding paths on both sides have R1_O as a current-limiting resistor to reduce overall circuit power consumption. The bias circuit consists of a reverse-broken Zener diode and a diode used to compensate for the output buffer Vth, increasing the output VS_SF voltage. The output buffer has an anti-backflow design to prevent VS_SF energy from flowing to the low-voltage side, affecting Vo and reducing efficiency. Since the second-stage main buffer has a faster startup speed, an anti-backflow diode DO_SF is added from VS_SF to allow current to flow to the output Vout of the entire circuit during startup, forming a fast startup path and accelerating the startup of the entire circuit.

[0164] After VS_Pre gradually starts up, energy is gradually supplied to the first-stage pre-startup charge pump and the ring oscillator. The ring oscillator has an on-chip integrated peak current source. RS1 serves as the bias resistor for the entire current source, determining the current source's Iin. RS2 is the bias resistor for MSN1, determining the overdrive voltage of MSN1 and the bias voltage of MSN2. MSN1 and MSN2 have the same width-to-length ratio, both W / L. Therefore, the current Iout output by MSN2 is:

[0165]

[0166] VGSN1 is the gate-source voltage of MSN1. Iout biases the current-controlled oscillator (CCO) through a current mirror composed of MSP1 and MSP2. The CCO outputs fS_Pre, which is current-dependent and operates in the VS_Pre voltage domain, serving as the bootstrap clock for the first-stage pre-start charge pump. VS_Pre passes through a level shifter to output fCP, which operates in the VS_SF voltage domain and serves as the bootstrap clock for the second-stage main charge pump.

[0167] Both the first-stage pre-start charge pump and the second-stage main charge pump employ a cross-coupling design, effectively improving their load driving capability. The first-stage pre-start charge pump uses a single-stage multiplication design, multiplying VS_Pre by one stage; the second-stage main charge pump uses a two-stage multiplication design, multiplying VS_SF by two stages. Their operating principles are the same. Taking the first-stage pre-start charge pump as an example, when the charge pump drive circuit outputs f1_Pre high and f2_Pre low, MN2 is turned on, and the upper-level board of CN_Pre is charged to VS_Pre. When f1_Pre is low and f2_Pre is high, since the voltage across the capacitor cannot change abruptly, the upper-level board of CN_Pre is charged to 2VS_Pre. At this time, MP2 is turned on, and 2VS_Pre is transferred to VCP_Pre. MN1 and MP1 operate in the opposite states to MN2 and MP2. Therefore, the cross-coupled charge pump composed of MN1, MP1, MN2, MP2, CN_Pre, and CP_Pre achieves the ability to cross-transfer charge. Similarly, the second-stage main charge pump is a two-stage multiplication design. Driven by the two-phase bootstrap clocks f1_SF and f2_SF, VS_SF is multiplied to VCP_X2 = 2VS_SF and VCP_X3 = 3VS_SF. Furthermore, the first-stage pre-startup charge pump uses a non-overlapping clock generator as its driving circuit, while the second-stage main charge pump employs a stronger driving circuit to drive a larger bootstrap capacitor.

[0168] The output stage buffer also employs an anti-reverse-current technology, eliminating the impact of load changes on the charge pump. VCP_X2 provides a stable and powerful voltage for the output stage buffer, while VCP_X3 provides a higher bias voltage for the output stage buffer's bias branch. Anti-reverse-current diodes are added to both the power supply path and the bias branch. The faster-starting VCP_X2 accelerates the start-up of the bias voltage Vzd_bias, thereby speeding up the start-up of the source follower output Vout. Because the output voltage is determined by the reverse breakdown voltage of the Zener diode, after the Vth level shift by the source follower, the output stabilizes at around 5V, providing overvoltage clamping protection for subsequent circuits.

[0169] In summary, the entire fast cold start circuit features a simple structure and low cost. It improves the output voltage startup speed by incorporating a fast-start energy supply path; it employs a multi-stage buffer boost method to enhance the circuit's load-carrying and driving capabilities, and features a simple overvoltage clamping protection function to effectively protect downstream circuits; and it includes a high-voltage path selector to provide a more stable and stronger driving energy supply for the entire cold start circuit. Therefore, this fast cold start circuit features rapid startup, strong driving capability, and overvoltage protection, making it suitable for single-inductor multi-output Boost chips.

[0170] The above embodiments have the following technical effects:

[0171] First, a fast startup path is formed by connecting the anti-backflow diode DO_SF between the output terminal of the second-stage main buffer SF-buffer and the output terminal of the output buffer, effectively improving the circuit's startup speed. In the initial startup phase, current can flow directly from the second-stage power supply voltage VS_SF to the output voltage Vout, accelerating the rise of the output voltage and significantly shortening the cold start time.

[0172] Secondly, a multi-stage buffer boost structure is adopted, especially the first-stage pre-start charge pump VCP_Pre which doubles the first-stage startup power supply voltage VS_Pre, and the second-stage main charge pump Main CP which triples the second-stage power supply voltage VS_SF. This provides sufficiently high double voltage VCP_X2 and triple voltage VCP_X3, significantly improving the circuit's driving capability and performance. The output stage buffer can output a stable output voltage of around 5V, meeting the power supply requirements of subsequent circuits.

[0173] Third, the output buffer stage design of each stage of the buffer adopts anti-backflow technology, which effectively eliminates the influence of the subsequent circuit on the operating point of the preceding charge pump and ensures the stable operation of the circuit. At the same time, the application of the high-voltage selector in the first-stage pre-buffer and the second-stage main buffer can automatically select the higher of the first output voltage Vo1 and the second output voltage Vo2 of the single-inductor multi-output Boost chip as the power supply voltage, thereby improving the power supply capability of the circuit.

[0174] Fourth, the threshold voltage compensation design of the second-stage main buffer provides the second-stage main charge pump with a higher and more powerful second-stage power supply voltage than the Zener diode breakdown voltage, thus improving the overall circuit performance. Meanwhile, the constant peak current source design of the ring oscillator, where the input current limiting resistor RS1 and the gate-source voltage setting resistor RS2 work together, ensures the stability of the clock frequency fS_Pre and the level-shifted clock frequency fCP, providing a reliable guarantee for the normal operation of the charge pump.

[0175] It should be noted that in this patent application, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this patent application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0176] All documents mentioned in this application are considered to be incorporated in their entirety into the disclosure of this application so that they can serve as a basis for modifications if necessary. Furthermore, it should be understood that after reading the foregoing disclosure of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A fast cold-start circuit suitable for single-inductor multi-output Boost chips, characterized in that, include: The first-stage pre-buffer has its input connected to the first output voltage (Vo1) and the second output voltage (Vo2) of the single-inductor multi-output Boost chip, and its output output is the first-stage startup power supply voltage (VS_Pre). It has a built-in high-voltage selector to select the higher of the first output voltage or the second output voltage as the power supply voltage for the first-stage pre-start charge pump. A ring oscillator, whose input is connected to the output of the first-stage pre-buffer to receive the first-stage startup power supply voltage, and whose output output is a clock frequency (fS_Pre) that operates in the voltage domain of the first-stage startup power supply voltage and is related to the current (Iout); The first-stage pre-start charge pump (VCP_Pre) has its input terminal connected to the output terminal of the first-stage pre-buffer to receive the first-stage start-up power supply voltage and connected to the output terminal of the ring oscillator to receive the clock frequency as the bootstrap clock. Its output terminal outputs the voltage (VCP_Pre) after doubling the input voltage. The second-stage main buffer (SF-buffer) has its input connected to the output of the first-stage pre-start charge pump, and its output output is the second-stage power supply voltage (VS_SF). A level shifter, whose input is connected to the output of the ring oscillator, is used to convert the clock frequency from the first-stage startup power supply voltage domain to the second-stage power supply voltage domain, and output the clock frequency (fCP). The second-stage main charge pump (Main CP) has its input terminal connected to the output terminal of the second-stage main buffer to receive the second-stage power supply voltage and its output terminal connected to the output terminal of the level shifter to receive the clock frequency as a bootstrap clock. It is used to triple the input voltage. The first-stage output terminal outputs a voltage doubled (VCP_X2), and the second-stage output terminal outputs a voltage tripled (VCP_X3). The output stage buffer has its power supply terminal connected to the first stage output terminal of the second stage main charge pump as the power supply voltage, and its bias terminal connected to the second stage output terminal of the second stage main charge pump to provide bias voltage for the Zener diode. The output terminal outputs a stable and powerful output voltage (Vout). A reverse-current protection diode (DO_SF) is connected between the output terminal of the second-stage main buffer and the output terminal of the output stage buffer, which provides a fast start-up path for the output voltage.

2. The fast cold-start circuit for a single-inductor multi-output Boost chip according to claim 1, characterized in that, The first-stage pre-buffer includes: a source follower output buffer (MO_Pre), which eliminates the additional power consumption introduced by the operational amplifier in traditional buffer stages; a passive reverse-current protection diode biasing a Zener diode, with the reverse breakdown voltage of the Zener diode serving as the bias voltage of the source follower output buffer, featuring a simple structure; and a high-voltage selector including a first pre-charge switch (S1_Pre) and a second pre-charge switch (S2_Pre), where each path has a passive reverse-current protection diode consisting of a diode-connected NMOS and a reverse-connected NMOS, used to prevent higher voltage from entering the circuit. The reverse current flows into a lower voltage path, ensuring a reliable and stable power supply to the entire circuit. The ring oscillator includes a constant peak current source, where the input current limiting resistor (RS1) determines the input current (Iin) of the current source, and the gate-source voltage setting resistor (RS2) determines the gate-source voltage (VGSN1) of the NMOS transistor (MSN1) in the current source, which in turn determines the output current. The output current provides bias current to the current-controlled ring oscillator (CCO) through a current mirror composed of the first PMOS transistor (MSP1) and the second PMOS transistor (MSP2), ensuring the stability of its output clock frequency.

3. A fast cold-start circuit for a single-inductor multi-output Boost chip according to claim 1 or 2, characterized in that, The high-voltage selector includes a first pre-charge switch and a second pre-charge switch. When the first output voltage is high, the first pre-charge switch is closed and the second pre-charge switch is turned off, and the first output voltage supplies power to the bias circuit of the first-stage pre-buffer and the first-stage pre-start charge pump. When the second output voltage is high, the second pre-charge switch is closed and the first pre-charge switch is turned off, and the second output voltage supplies power to the bias circuit of the first-stage pre-buffer and the first-stage pre-start charge pump.

4. A fast cold-start circuit suitable for single-inductor multi-output Boost chips according to claim 1 or 2, characterized in that, The first-stage pre-start charge pump includes a first NMOS switch (MN1), a second NMOS switch (MN2), a first PMOS switch (MP1), a second PMOS switch (MP2), a first capacitor (CN_Pre), and a second capacitor (CP_Pre). Driven by the first phase clock frequency (f1_Pre) and the second phase clock frequency (f2_Pre) output from the ring oscillator, a cross-coupled structure is adopted to achieve a boost output of one-times the first-stage start-up power supply voltage, thereby improving the driving performance of the charge pump.

5. A fast cold-start circuit for a single-inductor multi-output Boost chip according to claim 1 or 2, characterized in that, The bias circuit of the second-stage main buffer includes a reverse breakdown Zener diode and a diode for threshold voltage compensation, wherein the threshold voltage compensation diode is used to increase the voltage value and driving capability of the output bias voltage second-stage power supply voltage.

6. A fast cold-start circuit for a single-inductor multi-output Boost chip according to claim 1 or 2, characterized in that, The second-stage main buffer includes a first switch (S1_SF), a second switch (S2_SF), and an output current-limiting resistor (R1_O). When the first output voltage is high, the first switch is turned off and the second switch is turned on, grounding the bias circuit on the second output voltage side, and the first output voltage supplies power to the second-stage main buffer. When the second output voltage is high, the second switch is turned off and the first switch is turned on, grounding the bias circuit on the first output voltage side, and the second output voltage supplies power to the second-stage main buffer.

7. A fast cold-start circuit suitable for single-inductor multi-output Boost chips according to claim 1 or 2, characterized in that, The second-stage main charge pump adopts a two-stage boost cross-coupling design. Driven by the first phase clock frequency (f1_SF) and the second phase clock frequency (f2_SF) output by the level shifter, the second-stage power supply voltage is boosted by two times to output a voltage twice as the stable energy supply for the output stage buffer, and boosted by three times to output a voltage three times as the higher driving voltage for the bias branch of the output stage buffer.

8. A fast cold-start circuit suitable for single-inductor multi-output Boost chips according to claim 1 or 2, characterized in that, The output stage buffer employs an output buffer stage with anti-reverse current technology, comprising: a Zener diode (D1) with its anode grounded; a source follower with its input terminal connected to the cathode of the Zener diode and its output terminal outputting the output voltage; and a bias branch, including a bias pull-up resistor (R1), a bias pull-down resistor (R2), and an anti-reverse current diode (D2). The triple voltage provides bias voltage to the Zener diode through the bias pull-down resistor and the anti-reverse current diode, and the double voltage serves as the power supply voltage for the source follower, stabilizing the output voltage at approximately 5V after threshold voltage level shifting. The anti-reverse current technology also eliminates the influence of subsequent circuitry on the charge pump operating point.

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