Communication distributor, processing chip, information transmission method, device and system

Abstract

The application relates to a communication distributor, a processing chip, an information transmission method, a device and a system. The communication distributor comprises a front-end arbitrator, a plurality of buffers and a rear-end arbitrator; the output ends of the front-end arbitrator are connected with the input ends of the buffers respectively, and the output ends of the buffers are connected with the input ends of the rear-end arbitrator; the number of the buffers is less than the number of the input ports of the communication distributor; wherein the front-end arbitrator is used for performing primary arbitration processing on the input information received by the input ports of the communication distributor to obtain primary output information; each buffer is used for storing the received primary output information into a corresponding storage queue; and the rear-end arbitrator is used for obtaining the primary output information in each storage queue and performing secondary arbitration processing on each primary output information to obtain secondary output information. The communication distributor has small area and low power consumption, can avoid bus transmission conflicts of a processing chip, and improves the bus utilization rate on the processing chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a communication distributor, processing chip, information transmission method, apparatus and system. Background Technology

[0002] With the development of computer technology, more and more functions and devices are being integrated into the same processing chip in a computer system. Among these, multiple upstream processing units within the processing chip frequently access multiple downstream processing units to transmit information; therefore, the demand for information transmission capabilities within the processing chip is constantly increasing.

[0003] In related technologies, the main approach is to set up an on-chip communication distributor between multiple upstream processing units and multiple downstream processing units to realize information transmission between them.

[0004] However, the on-chip communication distributor in related technologies occupies a large area, which leads to low bus utilization on the processing chip. Summary of the Invention

[0005] Therefore, it is necessary to provide a communication distributor, a processing chip, an information transmission method, an apparatus, and a system to address the aforementioned technical problems. The communication distributor occupies a smaller area, thereby improving the bus utilization rate on the processing chip.

[0006] In a first aspect, embodiments of this application provide a communication distributor, which includes: a pre-arbitrator, multiple buffers, and a post-arbitrator; the output of the pre-arbitrator is connected to the input of each buffer, and the output of each buffer is connected to the input of the post-arbitrator; the number of buffers is less than the number of input ports of the communication distributor.

[0007] Among them, the pre-arbitrator is used to perform an arbitration process on the input information received by the input port of the communication distributor to obtain the first-level output information;

[0008] Each buffer is used to store the received first-level output information into its respective storage queue;

[0009] The post-arbitrator is used to obtain the first-level output information from each storage queue and perform secondary arbitration on each first-level output information to obtain the second-level output information.

[0010] In one embodiment, the pre-arbitrator includes: a plurality of first-stage cross switches; the output of each first-stage cross switch is connected to the input of each buffer respectively;

[0011] Each first-stage cross switch is used to perform an arbitration process on the input information to obtain the first-stage output information.

[0012] In one embodiment, the number of first-stage cross switches is less than the number of input ports of the communication distributor.

[0013] In one embodiment, the number of first-stage cross switches is equal to 2.

[0014] In one embodiment, the number of input ports of the first-stage cross switch is equal to the number of input ports of the communication distributor.

[0015] In one embodiment, the post-arbitrator includes: a plurality of second-level cross switches; the input of each second-level cross switch is connected to the output of each buffer; the number of second-level cross switches is equal to the number of output ports of the communication distributor;

[0016] Each second-level cross switch is used to acquire the first-level output information from each storage queue and perform secondary arbitration processing on each first-level output information to obtain the second-level output information.

[0017] Secondly, embodiments of this application provide a processing chip, which includes a plurality of upstream processing units, a plurality of downstream processing units, and a communication distributor as described in any of the embodiments of the first aspect.

[0018] Each upstream processing unit is connected to the input port of the communication distributor, and each downstream processing unit is connected to the output port of the communication distributor.

[0019] Thirdly, embodiments of this application provide a processing system including a central processing unit (CPU) and a processing chip as described in the second aspect embodiment, wherein the CPU is connected to the processing chip.

[0020] Fourthly, embodiments of this application provide an information transmission method applied to the communication distributor in any embodiment of the first aspect, the method comprising:

[0021] The input information sent by multiple upstream processing units in the processing chip is arbitrated once to obtain the first-level output information; the first-level output information is stored in the storage queue of each buffer.

[0022] Secondary arbitration processing is performed on the primary output information in each storage queue to obtain secondary output information, and the secondary output information is transmitted to multiple downstream processing units in the processing chip.

[0023] Fifthly, embodiments of this application provide an information transmission device, which includes:

[0024] The first arbitration processing module is used to perform an arbitration process on the input information sent by multiple upstream processing units in the processing chip to obtain the first-level output information; wherein, the first-level output information is stored in the storage queue of each buffer;

[0025] The second arbitration processing module is used to perform secondary arbitration processing on the first-level output information in each storage queue to obtain the second-level output information, and then transmit the second-level output information to multiple downstream processing units in the processing chip.

[0026] Sixthly, embodiments of this application provide a computer system, characterized in that the computer system includes a memory, a processing system, and a computer program; the computer program is stored in the memory;

[0027] The processing system is used to run computer programs to perform the steps of the information transmission method in the fourth aspect embodiment.

[0028] In a seventh aspect, embodiments of this application also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the method described in the fourth aspect embodiment.

[0029] Eighthly, embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the method described in the fourth aspect embodiment.

[0030] The communication distributor, processing chip, information transmission method, apparatus, and system provided in this application include: a pre-arbitrator, multiple buffers, and a post-arbitrator; the output of the pre-arbitrator is connected to the input of each buffer, and the output of each buffer is connected to the input of the post-arbitrator; the number of buffers is less than the number of input ports of the communication distributor; wherein, the pre-arbitrator is used to perform a first-level arbitration process on the input information received by the input ports of the communication distributor to obtain first-level output information; each buffer is used to store the received first-level output information into its respective storage queue; the post-arbitrator is used to obtain the first-level output information from each storage queue and perform a second-level arbitration process on each first-level output information to obtain second-level output information. Under the premise of ensuring information transmission, the above-mentioned communication distributor has a smaller number of buffers than the number of input ports, which reduces the area and power consumption of the communication distributor, avoids bus transmission conflicts on the processing chip, and improves the bus utilization rate on the processing chip. Attached Figure Description

[0031] Figure 1 This is a diagram illustrating an application scenario of a communication distributor in one embodiment;

[0032] Figure 2 This is a block diagram of the overall structure of the communication distributor in one embodiment;

[0033] Figure 3 This is a schematic diagram of the internal structure of the communication distributor in another embodiment;

[0034] Figure 4 This is a schematic diagram of the internal structure of the communication distributor in another embodiment;

[0035] Figure 5 This is a flowchart illustrating an information transmission method in one embodiment;

[0036] Figure 6 This is a flowchart illustrating the information transmission method in another embodiment;

[0037] Figure 7 This is an internal structure diagram of a computer system in one embodiment.

[0038] Explanation of reference numerals in the attached figures:

[0039] 10. Communication distributor; 11. Pre-arbitrator; 111. First-stage cross switch; 12. Buffer; 13. Post-arbitrator; 131. Second-stage cross switch; 20. Upstream processing unit; 30. Downstream processing unit. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0041] First, before introducing the technical solutions of the embodiments of this application in detail, the technical background or technical evolution of the embodiments of this application will be introduced.

[0042] With the development of chip technology, large-scale processing chips are widely used in various fields, such as medical, communications, artificial intelligence, robotics, and computers. These processing chips integrate numerous functions and devices, and multiple upstream processing units within the chip frequently access multiple downstream processing units to achieve information transmission (i.e., communication). Therefore, the demand for information transmission capabilities within the processing chip is constantly increasing. Related technologies primarily use on-chip communication distributors between multiple upstream and downstream processing units to achieve information transmission. However, these on-chip communication distributors in related technologies are implemented using only multiple crossbar switches, resulting in a large footprint and low bus utilization on the processing chip. Therefore, this application provides a communication distributor 10 with a smaller footprint, which can improve the bus utilization on the processing chip.

[0043] The communication distributor 10 provided in this application embodiment can be applied to... Figure 1 The m upstream processing units and n downstream processing units shown can be independent of the processing chip. However, in this embodiment, the example is given where each upstream and downstream processing unit is a processing unit on the processing chip. Optionally, the processing chip can be, but is not limited to, a graphics processing unit (GPU) chip, a central processing unit (CPU) chip, or a neural processing unit (NPU) chip.

[0044] In practical applications, the communication distributor 10 enables information transmission when multiple upstream processing units access multiple downstream processing units. The following embodiment provides a detailed description of the communication distributor 10.

[0045] like Figure 2 As shown, a communication distributor 10 provided in this application embodiment includes: a pre-arbitrator 11, a plurality of buffers 12, and a post-arbitrator 13; the output terminal of the pre-arbitrator 11 is connected to the input terminal of each buffer 12, and the output terminal of each buffer 12 is connected to the input terminal of the post-arbitrator 13; the number of buffers 12 is less than the number of input ports of the communication distributor 10.

[0046] Among them, the pre-arbitrator 11 is used to perform an arbitration process on the input information received by the input port of the communication distributor 10 to obtain the first-level output information;

[0047] Each buffer 12 is used to store the received first-level output information into its respective storage queue;

[0048] The post-arbitrator 13 is used to obtain the first-level output information from each storage queue and perform secondary arbitration processing on each first-level output information to obtain the second-level output information.

[0049] In practical applications, the pre-arbitrator 11 in the communication distributor 10 can be understood as an arbitrator directly connected to each upstream processing unit in the communication distributor 10. Optionally, the pre-arbitrator 11 can be implemented by logic circuits, registers, encoders, and / or decision circuits, etc. In this embodiment, the pre-arbitrator 11 is used to perform an arbitration process on the input information received by the input port of the communication distributor 10 to obtain a first-level output information. The input information received by the input port of the communication distributor 10 is also the input information received by the pre-arbitrator 11. Optionally, the input information can be, but is not limited to, data packets, requests, and signals.

[0050] It should be noted that the front-end arbitrator 11 has its own pre-configured arbitration mechanism. In practical applications, the front-end arbitrator 11 can perform an arbitration process according to the pre-configured arbitration mechanism. This arbitration mechanism can be implemented according to, but is not limited to, a fixed priority mechanism, a round-robin principle, or a first-come, first-served mechanism.

[0051] Meanwhile, each buffer 12 in the communication distributor 10 has the same function: receiving the output of the pre-arbitrator 11 and the output information, and storing the received first-level output information into its respective storage queue. Optionally, each buffer 12 can be implemented through storage units, control logic, and / or status registers. In this embodiment, the depth of the storage queue in each buffer 12 can be equal to the number of output ports n of the communication distributor 10, and the first-level output information stored in each storage queue is the same, that is, n first-level output information corresponding to the output of the first-level cross switch.

[0052] In practical applications, the number of buffers 12 in the communication distributor 10 is less than the number of input ports of the communication distributor 10. This makes the area of ​​the communication distributor 10 smaller, that is, the area occupied by the communication distributor 10 is smaller, thereby improving the bus utilization rate on the processing chip.

[0053] Furthermore, the post-arbitrator 13 in the communication distributor 10 can be understood as an arbitrator directly connected to each downstream processing unit in the communication distributor 10. Optionally, the post-arbitrator 13 can also be implemented by logic circuits, registers, encoders, and / or decision circuits, etc. In the embodiments of this application, the post-arbitrator 13 is used to receive the first-level output information in each storage queue in each buffer 12, and perform secondary arbitration processing on each first-level output information to obtain second-level output information.

[0054] It should be noted that the post-arbitrator 13 has its own pre-configured arbitration mechanism. In practical applications, the post-arbitrator 13 can perform secondary arbitration processing according to the pre-configured arbitration mechanism. The arbitration mechanism of the post-arbitrator 13 can be the same as or different from that of the pre-arbitrator 11. Optionally, the arbitration mechanism of the post-arbitrator 13 can also be implemented according to, but is not limited to, a fixed priority mechanism, a round-robin principle, or a first-come, first-served mechanism. In practical applications, the internal structure of the post-arbitrator 13 is different from that of the pre-arbitrator 11.

[0055] In the technical solution of this application embodiment, the communication distributor 10 includes a pre-arbitrator 11, multiple buffers 12, and a post-arbitrator 13; the output terminal of the pre-arbitrator 11 is connected to the input terminal of each buffer 12, and the output terminal of each buffer 12 is connected to the input terminal of the post-arbitrator 13; the number of buffers 12 is less than the number of input ports of the communication distributor 10; wherein, the pre-arbitrator 11 is used to perform a first-level arbitration process on the input information received by the input port of the communication distributor 10 to obtain first-level output information; each buffer 12 is used to store the received first-level output information into its respective storage queue; the post-arbitrator 13 is used to obtain the first-level output information in each storage queue and perform a second-level arbitration process on each first-level output information to obtain second-level output information. Under the premise of ensuring information transmission, the number of buffers 12 in the communication distributor 10 is less than the number of input ports of the communication distributor 10. That is, the number of buffers 12 in the communication distributor 10 is small. This can reduce the area and power consumption of the communication distributor 10, and avoid bus transmission conflicts of the processing chip, thereby improving the bus utilization rate on the processing chip.

[0056] The internal structure of the pre-arbitrator 11 in the communication distributor 10 is described below. In one embodiment, as... Figure 3 As shown, the pre-arbitrator 11 in the communication distributor 10 includes multiple first-stage cross switches 111; the output of each first-stage cross switch 111 is connected to the input of each buffer 12.

[0057] Each first-stage cross switch 111 is used to perform an arbitration process on the input information to obtain the first-stage output information.

[0058] It should be noted that the pre-arbiter 11 in the communication distributor 10 includes multiple first-level crossbar switches 111. The output of each first-level crossbar switch 111 is connected to the input of each buffer 12. In practical applications, each first-level crossbar switch 111 can output information synchronously or asynchronously, i.e., first-level output information. The first-level output information output by each first-level crossbar switch 111 can be synchronously transmitted to each buffer 12 so that each buffer 12 can store it in its respective storage queue.

[0059] Each first-stage cross switch 111 can receive input information from different input ports of the communication distributor 10. Optionally, the first-stage cross switch 111 may, but is not limited to, include multiple switching elements, control logic, and arbitration circuitry. It should be noted that when at least two input ports of the first-stage cross switch 111 are interfaced to input information, the first-stage cross switch 111 can perform an arbitration process on these input information, meaning that these input information are subject to competition.

[0060] In practical applications, each first-stage cross switch 111 is used to perform an arbitration process on the input information it receives to obtain first-stage output information.

[0061] In one embodiment, the number of first-stage cross switches 111 in the pre-arbitrator 11 is less than the number of input ports of the communication distributor 10.

[0062] In this embodiment, each first-stage crossbar switch 111 in the pre-arbitrator 11 has the same function, that is, each first-stage crossbar switch 111 has the same number of input ports and the same number of output ports. The number of first-stage crossbar switches 111 in the pre-arbitrator 11 may be less than the number of input ports of the communication distributor 10.

[0063] For example, if the number of input ports of the communication distributor 10 is m, then the number of input ports of each first-level cross switch 111 can be equal to the result of m divided by the number of first-level cross switches 111.

[0064] Meanwhile, in practical applications, the number of output ports of the first-stage crossbar switch 111 is equal to the number of buffers 12 in the communication distributor 10. In the embodiments of this application, each first-stage crossbar switch 111 can be an m×n crossbar switch, where n represents the number of output ports of the communication distributor 10.

[0065] In one embodiment, the number of first-stage cross switches 111 in the pre-arbitrator 11 is equal to 2.

[0066] In this embodiment of the application, in order to greatly reduce the area of ​​the communication distributor 10, the number of first-stage cross switches 111 in the pre-arbitrator 11 is equal to 2, that is, the number of buffers 12 in the communication distributor 10 is equal to 2. Figure 3 The diagram illustrates the internal structure of the communication distributor using an example where the number of first-level cross switches 111 is equal to 2.

[0067] Specifically, the number of input ports of each first-level cross switch 111 can be equal to m divided by the number of first-level cross switches 111, which avoids the problem of arbitration processing contention when the same first-level cross switch 111 processes the same input information. Correspondingly, each second-level cross switch in the communication distributor 10 can be a 2x1 cross switch, that is, each second-level cross switch outputs one second-level output information.

[0068] It should be noted that because the number of input ports of the second-stage cross switch is relatively small, information transmission conflicts can be minimized, thereby improving the information transmission efficiency of the communication distributor 10.

[0069] In the technical solution of this application embodiment, the pre-arbitrator 11 in the communication distributor 10 includes multiple first-level cross switches 111. The output terminal of each first-level cross switch 111 is connected to the input terminal of each buffer 12. Each first-level cross switch 111 is used to perform an arbitration process on the input information to obtain a first-level output information. The pre-arbitrator 11 in the communication distributor 10 can perform dimensionality reduction processing on the input information of the communication distributor 10, so as to provide a prerequisite for reducing the area of ​​the communication distributor 10, that is, reducing the number of buffers 12 in the communication distributor 10.

[0070] In one embodiment, such as Figure 4 As shown, the number of input ports of the first-stage cross switch 111 in the pre-arbitrator 11 is equal to the number of input ports of the communication distributor 10.

[0071] In this embodiment, the number of input ports of the first-stage cross switch 111 in the pre-arbitrator 11 can also be equal to the number of input ports of the communication distributor 10. This allows the same first-stage cross switch 111 to arbitrate multiple identical input signals sequentially when processing the same input signal, thus avoiding arbitration conflicts between multiple identical input signals.

[0072] The internal structure of the post-arbitrator 13 in the communication distributor 10 is described below. In one embodiment, see also... Figure 3 As shown, the post-arbitrator 13 in the communication distributor 10 includes multiple second-stage cross switches 131; the input terminal of each second-stage cross switch 131 is connected to the output terminal of each buffer 12; the number of second-stage cross switches 131 is equal to the number of output ports of the communication distributor 10.

[0073] Each second-level cross switch 131 is used to acquire the first-level output information in each storage queue and perform secondary arbitration processing on each first-level output information to obtain the second-level output information.

[0074] It should be noted that the post-arbitrator 13 in the communication distributor 10 includes multiple second-level crossbar switches 131. The output of each second-level crossbar switch 131 is connected to multiple downstream processing units. In practical applications, each second-level crossbar switch 131 can output information synchronously or asynchronously, i.e., secondary output information. Each second-level crossbar switch 131 can synchronously receive the primary output information from its respective storage queue transmitted by each buffer 12, and perform secondary arbitration processing on each primary output information to obtain secondary output information.

[0075] Each second-stage cross switch 131 can output second-stage output information through different output ports of the communication distributor 10. Optionally, the second-stage cross switch 131 may also include, but is not limited to, multiple switching elements, control logic, and arbitration circuits.

[0076] In the technical solution of this application embodiment, the post-arbitrator 13 in the communication distributor 10 includes multiple second-level cross switches 131. The input terminal of each second-level cross switch 131 is connected to the output terminal of each buffer 12. The number of second-level cross switches 131 is equal to the number of output ports of the communication distributor 10. Each second-level cross switch 131 is used to obtain the first-level output information in each storage queue and perform secondary arbitration processing on each first-level output information to obtain the second-level output information. The area of ​​the communication distributor 10 is relatively small. That is, when the number of buffers 12 in the communication distributor 10 is less than the number of input ports of the communication distributor 10, the communication distributor 10 can normally realize information transmission without affecting the effect of information transmission, thereby improving the success rate of information transmission through the communication distributor 10.

[0077] Please continue reading Figure 1 As shown, in one embodiment, this application provides a processing chip that includes a plurality of upstream processing units 20, a plurality of downstream processing units 30, and a communication distributor 10 as provided in any of the above embodiments;

[0078] Each upstream processing unit 20 is connected to the input port of the communication distributor 10, and each downstream processing unit 30 is connected to the output port of the communication distributor 10.

[0079] In practical applications, each upstream processing unit 20 in the processing chip can be a computing core or a wireless access point (AP) in the processing chip, and each downstream processing unit 30 in the processing chip can be a storage unit or a cache in the processing chip.

[0080] The technical solution in this application embodiment includes a processing chip comprising multiple upstream processing units 20, multiple downstream processing units 30, and a communication distributor 10 as provided in any of the above embodiments. Each upstream processing unit 20 is connected to the input port of the communication distributor 10, and each downstream processing unit 30 is connected to the output port of the communication distributor 10. The above solution realizes information transmission between each upstream processing unit 20 and each downstream processing unit 30 through a communication distributor 10 with a smaller area. On this basis, the area of ​​the processing chip can be reduced, and the applicability of the processing chip can be improved.

[0081] In one embodiment, a processing system is provided, the processing system including a central processing unit and a processing chip as described in any of the above embodiments, the central processing unit being connected to the processing chip.

[0082] In this embodiment of the application, the central processing unit and the processing chip can be connected by communication.

[0083] The processing system provided in this application embodiment can be used to execute the technical solutions in the above information transmission method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0084] This application also provides an information transmission method, applied to the communication distributor in any of the above embodiments, such as... Figure 5 As shown, the method may include the following steps:

[0085] S100: The input information sent by multiple upstream processing units in the processing chip is arbitrated once to obtain the first-level output information. The first-level output information is stored in the storage queue of each buffer.

[0086] In practical applications, the front-end arbitrator in the communication distributor can receive input information sent by multiple upstream processing units in the processing chip and perform arbitration processing on the input information sent by multiple upstream processing units in the processing chip.

[0087] In this embodiment, the pre-arbitrator can perform an arbitration process once according to a pre-configured arbitration mechanism. This arbitration mechanism can be implemented, but is not limited to, a fixed priority mechanism, a round-robin principle, or a first-come, first-served mechanism. It should be noted that the first-level output information from the pre-arbitrator can be stored in the storage queues of each buffer in the communication distributor.

[0088] S200: Perform secondary arbitration processing on the primary output information in each storage queue to obtain secondary output information, and transmit the secondary output information to multiple downstream processing units in the processing chip.

[0089] Furthermore, the post-arbitrator in the communication distributor can obtain the first-level output information from each storage queue in each buffer, and perform secondary arbitration processing on each first-level output information to obtain the second-level output information, and then transmit the second-level output information to the corresponding downstream processing unit in the processing chip.

[0090] It should be noted that the post-arbitrator has its own pre-configured arbitration mechanism. In practical applications, the post-arbitrator can perform secondary arbitration processing according to the pre-configured arbitration mechanism. The arbitration mechanism of the post-arbitrator can be the same as or different from that of the pre-arbitrator. Optionally, the arbitration mechanism of the post-arbitrator can also be implemented according to, but is not limited to, a fixed priority mechanism, a round-robin principle, or a first-come, first-served mechanism.

[0091] The technical solution in this application embodiment performs a first arbitration process on the input information sent by multiple upstream processing units in the processing chip to obtain first-level output information, and performs a second arbitration process on the first-level output information in each storage queue to obtain second-level output information, and transmits the second-level output information to multiple downstream processing units in the processing chip. The above method can realize the information transmission between each upstream processing unit and each downstream processing unit through a communication distributor 10 with a small area, which not only realizes the information transmission, but also improves the success rate of information transmission.

[0092] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0093] Based on the same inventive concept, this application also provides an information transmission apparatus for implementing the information transmission method described above. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more information transmission apparatus embodiments provided below can be found in the limitations of the information transmission method described above, and will not be repeated here.

[0094] In one embodiment, Figure 6 This is a schematic diagram of the structure of an information transmission device in one embodiment of this application. The information transmission device provided in this embodiment can be applied to the communication distributor 10 in a processing chip. Figure 6 As shown, the information transmission device in this application embodiment may include: a first arbitration processing module 21 and a second arbitration processing module 22, wherein:

[0095] The first arbitration processing module 21 is used to perform an arbitration process on the input information sent by multiple upstream processing units in the processing chip to obtain first-level output information; wherein, the first-level output information is stored in the storage queue of each buffer 12;

[0096] The second arbitration processing module 22 is used to perform secondary arbitration processing on the primary output information in each storage queue to obtain secondary output information, and transmit the secondary output information to multiple downstream processing units in the processing chip.

[0097] The information transmission device provided in this application embodiment can be used to execute the technical solutions in the above-described information transmission method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0098] Specific limitations regarding the information transmission device can be found in the limitations regarding the information transmission method described above, and will not be repeated here. Each module in the aforementioned information transmission device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processing chip in hardware form or independently of the processing chip, or stored in software form in the memory of the communication distributor 10 within the processing chip, so that the communication distributor 10 can call and execute the operations corresponding to each module.

[0099] In one embodiment, a processing system is provided, the processing system including a central processing unit and a processing chip 01 in any of the above embodiments, the central processing unit being connected to the processing chip 01.

[0100] In this embodiment of the application, the central processing unit and the processing chip 01 can be connected by communication.

[0101] The processing system provided in this application embodiment can be used to execute the technical solutions in the above information transmission method embodiments of this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0102] In one embodiment, a computer system is provided, which may be a computer system or a server, and its internal structure diagram may be as follows: Figure 7 As shown, the computer system includes a processing system, memory, network interface, and display unit connected via a system bus. The processor of the computer system provides processing power. The memory of the computer system includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer system stores various memory queues. The network interface of the computer system is used for communication with external endpoints via a network connection. When the computer program is executed by the processor, it implements an information transmission method.

[0103] Those skilled in the art will understand that Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer system to which the present application is applied. A specific computer system may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0104] In one embodiment, a computer system is also provided, including a memory and a processing system. The memory stores a computer program, and the processing system executes the computer program to implement the technical solutions in the above-described information transmission method embodiments of this application. The implementation principle and technical effects are similar, and will not be repeated here.

[0105] In one embodiment, a computer-readable storage medium is also provided, on which a computer program is stored. When the computer program is executed by a processing system, it implements the technical solution of the information transmission method described above in this application. Its implementation principle and technical effect are similar, and will not be repeated here.

[0106] In one embodiment, a computer program product is also provided, including a computer program that, when executed by a processing system, implements the technical solution of the information transmission method described above in this application. The implementation principle and technical effects are similar and will not be repeated here.

[0107] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage, etc. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc.

[0108] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0109] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A communication distributor, characterized in that, The communication distributor includes: a front arbiter, multiple buffers, and a rear arbiter; the output of the front arbiter is connected to the input of each of the buffers, and the output of each buffer is connected to the input of the rear arbiter; the number of buffers is less than the number of input ports of the communication distributor. The pre-arbitrator is used to perform an arbitration process on the input information received by the input port of the communication distributor to obtain the first-level output information. Each buffer is used to store the received first-level output information into its respective storage queue; the depth of the storage queue in each buffer is equal to the number of output ports of the communication distributor; The post-arbitrator is used to obtain the first-level output information in each of the storage queues and to perform secondary arbitration processing on each of the first-level output information to obtain the second-level output information. The pre-arbiter includes two first-stage cross switches; the output of each first-stage cross switch is connected to the input of each buffer; the number of input ports of the first-stage cross switches is equal to the number of input ports of the communication distributor divided by the number of first-stage cross switches, or the number of input ports of the first-stage cross switches is equal to the number of input ports of the communication distributor. Each of the first-level cross switches is used to perform an arbitration process on the input information to obtain the first-level output information; The post-arbitrator includes: a plurality of second-stage cross switches; the input terminal of each second-stage cross switch is connected to the output terminal of each buffer; the number of second-stage cross switches is equal to the number of output ports of the communication distributor; Each second-level cross switch is used to acquire the first-level output information in each of the storage queues, and to perform secondary arbitration processing on each of the first-level output information to obtain the second-level output information.

2. The communication distributor according to claim 1, characterized in that, Each of the first-level cross switches outputs the first-level output information synchronously or asynchronously.

3. The communication distributor according to claim 1, characterized in that, Each of the buffers includes at least one of a storage unit, control logic, and a status register.

4. The communication distributor according to claim 1, characterized in that, The second-level cross switch is a 2x1 cross switch.

5. The communication distributor according to claim 1, characterized in that, The input information includes data packets, requests, or signals.

6. A processing chip, characterized in that, The processing chip includes multiple upstream processing units, multiple downstream processing units, and a communication distributor as described in any one of claims 1-5; Each of the upstream processing units is connected to the input port of the communication distributor, and each of the downstream processing units is connected to the output port of the communication distributor.

7. A processing system, characterized in that, The processing system includes a central processing unit and the processing chip as described in claim 6, wherein the central processing unit is connected to the processing chip.

8. An information transmission method, characterized in that, The method, applied to the communication distributor according to any one of claims 1-5, comprises: The input information sent by multiple upstream processing units in the processing chip is arbitrated once to obtain the first-level output information; wherein the first-level output information is stored in the storage queue of each of the buffers; Secondary arbitration processing is performed on the primary output information in each of the storage queues to obtain secondary output information, and the secondary output information is transmitted to multiple downstream processing units in the processing chip.

9. An information transmission device, characterized in that, The device is applied to the communication distributor according to any one of claims 1-5, the device comprising: The first arbitration processing module is used to perform an arbitration process on the input information sent by multiple upstream processing units in the processing chip to obtain first-level output information; wherein, the first-level output information is stored in the storage queue of each buffer; The second arbitration processing module is used to perform secondary arbitration processing on the primary output information in each of the storage queues to obtain secondary output information, and to transmit the secondary output information to multiple downstream processing units in the processing chip.

10. A computer system, characterized in that, The computer system includes a memory, a processing system, and a computer program; the computer program is stored in the memory. The processing system is used to run the computer program to perform the steps of the information transmission method of claim 8.

Images