A message uploading method, a data processing unit, and a network processor

Abstract

This application relates to a packet uploading method, a data processing unit, and a network processor, comprising: obtaining the number of packets currently cached in the data processing unit for the target queue, determining how many descriptors need to be read, acquiring these descriptors in batches through a single PCIe read operation, writing the packets of the currently cached target queue into the host-side cache pointed to by these descriptors, and decrementing the packet count of the currently cached target queue by one for each successfully uploaded packet; if the currently read descriptors are exhausted, but there are still unprocessed packets in the target queue, the above steps are repeated, determining and reading the required descriptors again based on the remaining number of packets in the currently cached target queue, and continuing to write packets, until all packets of the currently cached target queue have been successfully moved to the host-side cache. This application improves packet uploading efficiency and bandwidth utilization by optimizing the descriptor reading method.

Description

Technical Field

[0001] This application relates to the field of Virtio technology, specifically to a message uploading method, a data processing unit, and a network processor. Background Technology

[0002] Virtio is a general-purpose paravirtualized I / O framework, comprising a Virtio driver, Virtio devices, and virtualized queues (Virtqueues). Data interaction between the Virtio driver and Virtio devices is achieved through Virtqueues. Taking SplitVirtqueues as an example, the Virtio driver mainly consists of three parts: a descriptor ring, an available ring, and a used ring. Each descriptor entry in the descriptor ring contains a buffer address, a buffer length, a flag, and a next pointer. The available and used rings store pointers (ids) that point to a descriptor entry in the descriptor ring. Before receiving a packet, the Virtio driver needs to prepare a buffer to store the packet, and then notify the Virtio device. The Virtio device then begins receiving packet data. The Virtio device's data reception process is as follows:

[0003] (1) The Virtio device receives Ethernet packets and stores them in the local cache of the Virtio device;

[0004] (2) The Virtio device initiates a read operation on the available ring table of the Virtio driver to obtain the pointer (id) of the available ring table.

[0005] (3) Read the descriptor of the descriptor table based on the pointer (id) obtained from the available ring table, and obtain information such as cache address, cache length, flag and next hop pointer;

[0006] (4) Read the Ethernet packet from the Virtio device’s local buffer and upload it to the buffer unit pointed to by the descriptor;

[0007] (5) Update the used descriptors, that is, update the index and pointer (id) of the used ring table. The Virtio driver obtains the Ethernet packets in the buffer unit by reading the index and pointer (id) of the used ring table and reclaims the descriptor entries of the descriptor table for continued use.

[0008] like Figure 1As shown, after each descriptor read, the Virtio device will only initiate the next round of descriptor reading after the current fixed number of descriptors has been used up. If the Virtio device reads one descriptor at a time, and the return time of a descriptor is 1µs, then the packet processing performance of one queue is 1Mpps (packets / second). To improve the overall performance of the Virtio system, multiple queues can be enabled for pipelined processing. However, due to limitations in the number of queues, Virtio device logical resources, and area, simply increasing the number of queues cannot improve overall performance. Moreover, the rapid development of cloud computing and artificial intelligence is placing increasingly higher demands on the performance of virtual machines, which in turn places higher demands on the performance of single queues. If the Virtio device reads a fixed number of descriptors (at least two) each time, the performance of a single queue will be improved. However, there is a problem that must be solved: the number of descriptors needed is less than the number of descriptors requested. There are two ways to handle the excess descriptors: one is to increase RAM resources to store the excess descriptors, and the other is to roll back the excess descriptors. For the first method, the cache resources of the Virtio device will be increased, and the number of queues and the number of descriptors that each queue can store will need to be balanced, which will increase the logical complexity. For the second method, the Virtio device does not use the rolled-back descriptors, which not only wastes PCIe read bandwidth and read return bandwidth, but also requires the addition of rollback processing logic to the Virtio device.

[0009] In summary, Virtio devices have certain drawbacks in that they read one or a fixed number of descriptors at a time. Summary of the Invention

[0010] The purpose of this application is to propose a message uploading method, a data processing unit, a network processor, and a computer program product to solve the problems of low single-queue message processing performance when reading one descriptor at a time, and the defects of needing to increase RAM resources and more complex logic in Virtio devices when reading a fixed number (at least two) of descriptors at a time.

[0011] To achieve the above objectives, embodiments of this application provide a message uploading method, the method comprising:

[0012] Obtain the number of packets currently cached in the data processing unit of the target queue, and determine the number of descriptors to read based on the number of packets;

[0013] The number of descriptors are read in a single PCIe read operation;

[0014] Write the packets of the target queue to the host-side buffer unit pointed to by the descriptor; wherein, each time a packet of the target queue is written to the host-side buffer unit, the current buffer packet count corresponding to the target queue is decremented by one;

[0015] If all read descriptors have been used and not all packets in the target queue have been written to the host-side cache unit, then the number of descriptors to be read is determined again based on the current number of cached packets corresponding to the target queue. The number of descriptors determined again is read through a single PCIe read operation, and the remaining packets in the target queue are written to the host-side cache unit pointed to by the descriptor read again, until all cached packets corresponding to the target queue are written to the host-side cache unit.

[0016] Preferably, determining the number of descriptor reads based on the number of messages includes:

[0017] The current number of packets in the target queue is determined as the number of descriptors read.

[0018] Preferably, the method further includes:

[0019] If any queue has a message to be written to the host side cached in the data processing unit and any queue needs to read a descriptor, then any queue is identified as a queue to be scheduled, and the target queue is determined by scheduling all queues to be scheduled.

[0020] Preferably, the method further includes:

[0021] Obtain the valid packet bitmap value and read wait bitmap value of any queue, perform a bitwise AND operation on the valid packet bitmap value and read wait bitmap value, and determine whether to identify any queue as a queue to be scheduled based on the result of the bitwise AND operation; wherein, the valid packet bitmap value indicates whether any queue has buffered packets; the read wait bitmap value indicates whether any queue needs to read descriptors; if any queue has corresponding buffered packets, then the valid packet bitmap value of any queue is set to 1, otherwise it is set to 0; if any queue needs to read descriptors, then the read wait bitmap value of any queue is set to 1, otherwise it is set to 0.

[0022] Preferably, the method further includes:

[0023] Receive a message from any queue, cache the message from any queue in the message storage module corresponding to the queue, and update the message count value in the message count cache unit corresponding to the queue.

[0024] A second aspect of this application provides a data processing unit, including a descriptor number determination module, a descriptor reading module, and a message uploading module;

[0025] The descriptor number determination module is used to obtain the number of packets currently cached in the data processing unit of the target queue, and determine the number of descriptors to be read based on the number of packets;

[0026] The descriptor reading module is used to read the number of descriptors in a single PCIe read operation;

[0027] The message uploading module is used to write the messages of the target queue into the host-side buffer unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side buffer unit, the number of buffered messages of the target queue is decremented by one;

[0028] The descriptor number determination module is also used to determine the number of descriptors to be read again based on the number of packets in the target queue if all the currently read descriptors have been used and not all packets in the currently cached target queue have been written to the host-side cache unit.

[0029] The descriptor reading module is also used to read a determined number of descriptors in a single PCIe read operation;

[0030] The message uploading module is also used to write the remaining messages of the target queue into the host-side cache unit pointed to by the descriptor that is read again.

[0031] Preferably, the descriptor number determination module is used to determine the number of messages in the target queue as the number of descriptor reads.

[0032] Preferably, the data processing unit further includes a queue scheduling module, which is used to determine any queue as a queue to be scheduled when any queue has a message to be written to the host side cached in the data processing unit and the queue needs to read a descriptor, and to schedule all queues to be scheduled to determine the target queue.

[0033] Preferably, the queue scheduling module is used to obtain the message valid bitmap value and the read waiting bitmap value of any queue, perform a bitwise AND operation on the message valid bitmap value and the read waiting bitmap value, and determine whether to identify any queue as a queue to be scheduled based on the result of the bitwise AND operation.

[0034] Wherein, the message valid bitmap value indicates whether any queue has a cached message; the read wait bitmap value indicates whether any queue needs to read a descriptor; if any queue currently has a cached message, the message valid bitmap value of any queue is set to 1, otherwise it is set to 0; if any queue needs to read a descriptor, the read wait bitmap value of any queue is set to 1, otherwise it is set to 0.

[0035] Preferably, the data processing unit further includes a message receiving module, which is used to receive messages from any queue, cache the messages of any queue in the message storage module corresponding to the queue, and update the message count value in the message count cache unit corresponding to the queue.

[0036] This application embodiment also provides a data processing unit, including:

[0037] A communication interface used to communicate with other electronic devices;

[0038] Memory is used to store computer program instructions;

[0039] A processor is configured to execute the computer program instructions to support the data processing unit in implementing the above-described method.

[0040] This application also provides a network processor, including a Virtio driver and a data processing unit as described above, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.

[0041] This application also provides a computer program product, including computer program instructions, which instruct a computer device to perform the operations corresponding to the above-described methods.

[0042] The message uploading method, data processing unit, network processor, and computer program product according to embodiments of this application have the following beneficial effects:

[0043] This application proposes an adaptive descriptor reading strategy. Based on the number of packets currently needing to be processed in the target queue (Virtqueue), the number of descriptors to be read from the host is dynamically determined. A single PCIe read operation reads the corresponding number of descriptors, and the packets of the target queue are written into the host-side buffer unit corresponding to the descriptor. If the currently read descriptors are exhausted and the packets of the target queue have not been fully uploaded, one or more PCIe read operations are performed based on the current number of packets in the target queue to obtain more descriptors until all packets are processed. This application improves the processing throughput of a single queue by minimizing the number of PCIe read operations, compensating for the low performance of reading a single descriptor. Since the number of descriptors read each time is dynamically determined based on the actual number of packets, there is no need to reserve RAM for descriptors that may not be used, nor is there a need for complex rollback processing. This effectively solves the problem of low single-queue packet processing performance when reading one descriptor at a time, and the drawback of requiring more RAM resources and more complex logic in Virtio devices when reading a fixed number (at least two) of descriptors each time. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 The above is a flowchart of the message uploading process disclosed in the background technology.

[0046] Figure 2 This is a flowchart of a message uploading method in an embodiment of this application.

[0047] Figure 3 This is a schematic diagram illustrating the interaction between the data processing unit and the Virtio driver in an embodiment of this application.

[0048] Figure 4 This is a schematic diagram of the message transmission in the embodiments of this application.

[0049] Figure 5 This is a schematic diagram of the structure of a data processing unit in an embodiment of this application. Detailed Implementation

[0050] The detailed description of the accompanying drawings is intended to illustrate the present embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functions can be accomplished by different embodiments intended to be included within the spirit and scope of this application.

[0051] See Figures 2-3 One embodiment of this application provides a message uploading method, including:

[0052] Step S10: Obtain the number of packets currently cached in the data processing unit of the target queue, and determine the number of descriptors to be read based on the number of packets;

[0053] Specifically, before receiving a message, the Virtio driver needs to prepare a buffer unit and then notify the Data Processing Unit (DPU). The DPU starts receiving messages and buffers them locally. In the DPU, the received messages are buffered according to the queue to which the message belongs, waiting to be sent to the buffer unit on the host side. When any queue is scheduled, that queue is used as the target queue. At this time, the DPU obtains the number of messages in the currently buffered target queue and determines the number of descriptors to be read based on the number of messages.

[0054] Step S20: Read the descriptor corresponding to the number of descriptors read in a single PCIe read operation;

[0055] Specifically, compared to traditional methods that may require multiple PCIe read operations (reading one descriptor at a time), this embodiment can read multiple descriptors in batches at once according to the number of packets, reducing the number of PCIe read operations. Each descriptor contains information such as the address, length, flags, and next-hop pointer of the host-side cache unit.

[0056] Step S30: Write the packets of the target queue into the host-side buffer unit pointed to by the corresponding descriptor; wherein, each time a packet of the target queue is written into the host-side buffer unit, the number of packets in the target queue is decremented by one;

[0057] Specifically, after reading the descriptors corresponding to the number of descriptor reads in batches, the packets cached in the target queue of the DPU are sequentially written into the buffer unit corresponding to the descriptor read number. In this embodiment, the number of packets in the target queue is updated in real time. Each time a packet is sent, the number of cached packets corresponding to the target is reduced by one.

[0058] Step S40: If all currently read descriptors have been used and not all packets in the currently cached target queue have been written to the host-side cache unit, then the number of descriptors to be read is determined again based on the number of packets in the currently cached target queue. The descriptor corresponding to the newly determined number of descriptors to be read is read through a single PCIe read operation. The remaining packets in the currently cached target queue are written to the host-side cache unit pointed to by the descriptor to be read again, until all packets in the target queue are written to the host-side cache unit.

[0059] Specifically, in step S40, if all the packets of the target queue cached locally by the DPU are written to the host-side cache unit, the host is notified that the packets of the target queue have been successfully uploaded; if all the currently read descriptors have been used and the packets of the target queue have not been fully written to the host-side cache unit, more descriptors need to be read to continue uploading the packets of the target queue. In this case, steps S10 to S30 are repeated until all the packets cached in the target queue are written to the host-side cache unit.

[0060] This embodiment proposes an adaptive descriptor reading strategy. Based on the current number of packets buffered in the target queue (Virtqueue), it dynamically determines the number of descriptors to be read from the host and reads the corresponding number of descriptors in a single PCIe read operation, writing the packets from the target queue into the host-side buffer unit corresponding to each descriptor. During processing, it dynamically tracks the remaining packets in the target queue. If the currently read descriptors are exhausted and the packets in the target queue have not been fully uploaded, it performs one or more PCIe read operations based on the current number of packets buffered in the target queue to obtain more descriptors. The process continues until all messages are processed. This embodiment of the application improves the processing throughput of a single queue by minimizing the number of PCIe read operations, thus compensating for the low performance of reading a single descriptor. Since the number of descriptors read each time is dynamically determined according to the actual number of messages, there is no need to reserve RAM for descriptors that may not be used, nor is there a need for complex rollback processing. This effectively solves the problem of low single-queue message processing performance when reading one descriptor at a time, and the defect that Virtio devices need to add more RAM resources and more complex logic when reading a fixed number (at least two) of descriptors each time.

[0061] In some embodiments, determining the number of descriptor reads based on the number of packets in the target queue includes:

[0062] The number of messages in the target queue is determined as the number of descriptor reads.

[0063] Specifically, in this embodiment, when the storage space of the host-side cache unit corresponding to a descriptor is greater than or equal to the data volume of a packet A, the host-side cache unit corresponding to that descriptor stores a packet separately; when the storage space of the host-side cache unit of a descriptor is less than the data volume of a packet B, different parts of the data of a packet B are stored in at least two host-side cache units corresponding to at least two descriptors respectively; different packets are stored in different host-side cache units; the number of packets in the current cached target queue is updated in real time. In this embodiment, the number of descriptors read is dynamically determined based on the number of packets in the current cached target queue, that is, the number of descriptors read back in a single operation is less than or equal to the number of descriptors actually required by the cached packets. This application can minimize the number of PCIe read operations, improve the processing throughput of a single queue, make up for the disadvantage of low performance when reading a single descriptor, and does not require reserving RAM for descriptors that may not be used, nor does it require complex rollback processing.

[0064] In some embodiments, the method further comprises:

[0065] If any queue currently has a message to be written to the host side cached in the data processing unit and any queue needs to read a descriptor, then that queue is determined as a queue to be scheduled, and all queues to be scheduled are scheduled to determine the target queue.

[0066] Specifically, the DPU can only initiate the reading of the descriptor of one queue at a time. However, the DPU and the host driver usually transmit data through multiple queues. Therefore, arbitration scheduling is required for multiple queues with scheduling needs, such as round-robin scheduling, to select one queue as the target queue. If there are packets in any queue currently in the cache and that queue needs to read the descriptor, it means that the queue has scheduling needs.

[0067] In some embodiments, the method further comprises:

[0068] Obtain the valid packet bitmap value and read wait bitmap value of any queue, perform a bitwise AND operation on the valid packet bitmap value and read wait bitmap value, and determine whether to identify any queue as a queue to be scheduled based on the result of the bitwise AND operation; wherein, the valid packet bitmap value indicates whether any queue has buffered packets; the read wait bitmap value indicates whether any queue needs to read descriptors; if any queue currently has buffered packets, then the valid packet bitmap value of any queue is set to 1, otherwise it is set to 0; if any queue needs to read descriptors, then the read wait bitmap value of any queue is set to 1, otherwise it is set to 0.

[0069] Specifically, the DPU includes a message validity bitmap and a read wait bitmap. Both the message validity bitmap and the read wait bitmap include bits that correspond one-to-one with multiple queues. Each bit in the message validity bitmap is used to fill in the message validity bitmap value of the corresponding queue, and each bit in the read wait bitmap is used to fill in the read wait bitmap value of the corresponding queue. The bitmap provides a clear and explicit way to represent the state of each queue, which is convenient for hardware or software logic to make judgments and decisions. Moreover, the bitmap occupies very little storage space (only 1 bit is needed for each queue, marked as 0 or 1), making it suitable for implementation on resource-constrained devices. Based on the message validity bitmap and the read wait bitmap, an AND operation is performed. According to the result of the AND operation, it is possible to quickly determine which queues have scheduling requirements. The queues whose AND operation result of the message validity bitmap value and the read wait bitmap value is 1 are identified as queues to be scheduled. The DPU schedules these queues to be scheduled according to a preset scheduling strategy.

[0070] In some embodiments, the method further comprises:

[0071] Receive a message from any queue, cache the message from any queue in the message storage module corresponding to the queue, and update the storage value in the message count cache unit corresponding to the queue, wherein the storage value is the current cached message count of any queue.

[0072] Specifically, the DPU buffers received packets according to queues. The DPU includes a packet storage device, which includes multiple packet storage modules corresponding one-to-one with multiple queues. Each packet storage module is used to buffer packets of its corresponding queue. In addition, the DPU also includes a packet count storage device, which includes multiple packet count cache units corresponding one-to-one with multiple queues. Each packet count cache unit is used to record the number of packets of the corresponding queue currently buffered by the DPU.

[0073] In some embodiments, the method includes:

[0074] After reading the corresponding descriptor, the read descriptor is stored in the descriptor FIFO module. The descriptor FIFO module performs dequeue management on the descriptors stored in the descriptor FIFO module according to the first-in-first-out principle.

[0075] Specifically, the DPU also includes a descriptor FIFO module. In this embodiment, the descriptor FIFO module is used to manage the read descriptors. The descriptor FIFO module acts as a buffer, decoupling the PCIe read operation of the descriptor from the packet upload operation. The PCIe read operation of the descriptor is completed quickly, but the operation of writing to the host cache unit may be slightly slower for other reasons. The descriptor FIFO module can absorb this difference and prevent data loss or processing blockage.

[0076] See Figure 4 The following is a detailed example to illustrate the message uploading method of this embodiment:

[0077] The DPU receives two messages from queue 1. Message 1 is 5000 bytes long, and message 2 is 1000 bytes long. At this point, message 2 is recorded in the memory unit corresponding to queue 1 in the descriptor read count memory (RAM), and the corresponding DPU execution... Figure 4 Step ①;

[0078] The message valid bitmap and the corresponding bit 0 in queue 1 are set to 1, which corresponds to the DPU execution. Figure 4 Step ②;

[0079] The valid bitmap and the read wait bitmap are logically ANDed to obtain a new bitmap. Since bit 0 of the valid bitmap is 1 and bit 0 of the read wait bitmap is also 1 (initial value is 1), bit 0 of the new bitmap corresponding to queue 1 is also 1, indicating that queue 1 can participate in descriptor request scheduling, corresponding to DPU execution. Figure 4 Step ③;

[0080] When queue 1 is scheduled, bit 0 of the read waiting bitmap is set to 0, indicating that queue 1 does not need to be scheduled again, and the corresponding DPU executes. Figure 4 Step 4;

[0081] Initiate a descriptor request for queue 1. The number of descriptors requested is the value of the storage unit corresponding to queue 1 in the current descriptor read count memory (RAM), which is 2. This corresponds to the DPU execution. Figure 4 Step 5;

[0082] The host driver reads two descriptors (descriptor 1, descriptor 2) from queue 1. Assuming the cache unit pointed to by the descriptors is 2048 bytes long, these two descriptors are stored in the descriptor FIFO module corresponding to queue 1. The corresponding DPU then executes... Figure 4 Step 6;

[0083] Since message 1 is 5000 bytes long and a buffer unit is 2048 bytes long, message 1 requires 3 descriptors. Therefore, the two descriptors already read can only be used to store a portion of message 1's data. The system reads a portion of message 1's data from message storage module 1 corresponding to queue 1 in the message storage memory (RAM), and reads descriptors 1 and 2 from the FIFO module corresponding to queue 1. The portion of message 1's data is then sent to the host-side buffer units pointed to by the two descriptors, and the corresponding DPU executes the corresponding steps. Figure 4 Step 7;

[0084] Since both descriptors are fully utilized, bit 0 of the read wait bitmap is set to 1, indicating that queue 1 has completed the previous round of queue scheduling, and the corresponding DPU execution... Figure 4 Step ⑧;

[0085] Since only part of the message data of message 1 was read in the message storage memory (RAM), the value of the storage cell corresponding to queue 1 in the descriptor read count memory (RAM) is still 2;

[0086] Since bit 0 of both the message valid bitmap and the read wait bitmap is 1, queue 1 can participate in a new round of descriptor request scheduling, corresponding to DPU execution. Figure 4 Step ③;

[0087] When queue 1 is scheduled, bit 0 of the read waiting bitmap is set to 0, indicating that queue 1 does not need to be scheduled again, and the corresponding DPU executes. Figure 4 Step 4;

[0088] Initiate a descriptor request for queue 1. The number of descriptors requested is equal to the current value of the descriptor read count memory (RAM), which is 2. This corresponds to the DPU execution. Figure 4 Step 5;

[0089] The host driver reads two descriptors (descriptor 3 and descriptor 4) from queue 1. The length of the cache unit pointed to by the descriptors is still 2048 bytes. These two descriptors are stored in the descriptor FIFO module corresponding to queue 1, and the corresponding DPU executes. Figure 4 Step 6;

[0090] Since the remaining 904 bytes of message 1 were not sent to the host-side buffer, the buffer pointed to by descriptor 3 in queue 1 is used to store the remaining 904 bytes of data from message 1. The buffer pointed to by descriptor 4 can fully store message 2, which is 1000 bytes long. Therefore, the processing order of messages and descriptors is as follows:

[0091] The remaining message data of message 1 is read from message storage module 1 of message storage memory (RAM), and descriptor 3 is read from descriptor storage FIFO. The remaining message data of message 1 is then sent to the buffer unit pointed to by descriptor 3, corresponding to the DPU execution. Figure 4 Step 7;

[0092] Since message 1 of queue 1 has been completely read from the message storage memory (RAM), the value of the memory cell corresponding to queue 1 in the descriptor read count memory (RAM) is decremented by 1. At this time, the value of the memory cell corresponding to queue 1 in the descriptor read count memory (RAM) becomes 1, corresponding to the DPU execution. Figure 4 Middle step 9;

[0093] The message 2 data is read from the message storage memory (RAM), and simultaneously descriptor 4 is read from the descriptor storage FIFO. The message 2 data is then sent to the buffer unit pointed to by descriptor 4, corresponding to the DPU execution. Figure 4 Step 7;

[0094] Since both descriptors are fully utilized, bit 0 of the read wait bitmap is set to 1, corresponding to DPU execution. Figure 4 Step ⑧;

[0095] Since message 2 from queue 1 has been completely read from the message storage memory (RAM), the value of the memory cell corresponding to queue 1 in the descriptor read count memory (RAM) is decremented by 1. At this point, the value of the memory cell corresponding to queue 1 in the descriptor read count memory (RAM) becomes 0. Therefore, bit 0 of the message validity bitmap is set to 0, indicating that the DPU no longer has a message from queue 1, and the corresponding DPU execution... Figure 4 Step 9.

[0096] Another embodiment of this application also provides a data processing unit (DPU) that can be used to implement the European-style message uploading method of the above embodiments. The DPU includes a descriptor number determination module 1, a descriptor reading module 2, and a message uploading module 3.

[0097] The descriptor number determination module 1 is used to obtain the number of packets currently cached in the data processing unit of the target queue, and determine the number of descriptors to be read based on the number of packets;

[0098] The descriptor reading module 2 is used to read the number of descriptors in a single PCIe read operation;

[0099] The message uploading module 3 is used to write the messages of the target queue into the host-side buffer unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side buffer unit, the number of buffered messages of the target queue is reduced by one;

[0100] The descriptor number determination module 1 is also used to determine the number of descriptors to be read again based on the number of packets in the target queue if all the currently read descriptors have been used and not all the packets in the target queue currently cached have been written to the host-side cache unit.

[0101] The descriptor reading module 2 is also used to read a determined number of descriptors in a single PCIe read operation;

[0102] The message uploading module 3 is also used to write the remaining messages of the target queue currently cached into the host-side cache unit pointed to by the descriptor to be read again.

[0103] In some embodiments, the descriptor number determination module 1 is used to determine the number of packets in the target queue as the number of descriptor reads.

[0104] In some embodiments, the DPU further includes a queue scheduling module, which is used to determine any queue as a queue to be scheduled if there are currently any queues of packets in the cache and the queue needs to read a descriptor, and to schedule all the queues to be scheduled to determine the target queue.

[0105] In some embodiments, the queue scheduling module is used to obtain the message valid bitmap value and the read waiting bitmap value of any queue, perform a bitwise AND operation on the message valid bitmap value and the read waiting bitmap value, and determine whether to identify any queue as a queue to be scheduled based on the result of the bitwise AND operation.

[0106] Wherein, the message valid bitmap value indicates whether any queue has a cached message; the read wait bitmap value indicates whether any queue needs to read a descriptor; if any queue currently has a cached message, the message valid bitmap value of any queue is set to 1, otherwise it is set to 0; if any queue needs to read a descriptor, the read wait bitmap value of any queue is set to 1, otherwise it is set to 0.

[0107] In some embodiments, the DPU further includes a message receiving module, which is configured to receive messages from any queue, cache the messages of any queue in the message storage module corresponding to the queue, and update the storage value in the message count cache unit corresponding to the queue, wherein the storage value is the current cached message count of any queue.

[0108] In some embodiments, the descriptor reading module 2 is further configured to store the read descriptor into the descriptor FIFO module after reading the corresponding descriptor, and the descriptor FIFO module performs dequeue management on the descriptors stored in the descriptor FIFO module according to the first-in-first-out principle.

[0109] In some embodiments, the DPU further includes a message memory with multiple message modules corresponding to multiple queues, a message count memory with multiple message count storage units corresponding to multiple queues, the message validity bitmap, the read wait bitmap, and the descriptor FIFO module.

[0110] It should be noted that the data processing unit in this embodiment corresponds to the method in the above embodiment. The contents of the data processing unit in this embodiment that are not described in detail can be obtained by referring to the contents of the method in the embodiment, and will not be described again in this embodiment.

[0111] Another embodiment of this application provides a data processing unit, including:

[0112] A communication interface used to communicate with other electronic devices;

[0113] Memory is used to store computer program instructions;

[0114] A processor is configured to execute the computer program instructions to support the data processing unit in implementing the method described in the above embodiments.

[0115] In this embodiment, the memory mainly includes a program storage area and a data storage area. The program storage area can store the operating device, applications required for at least one function, etc., and the data storage area can store related data, etc. Furthermore, the memory can be a high-speed random access memory, or a non-volatile memory, such as a plug-in hard disk, a smart media card (SMC), a secure digital card (SD), and a flash card, or other volatile solid-state storage devices.

[0116] The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can be any conventional processor. The processor is the control center of the data processing unit and uses various interfaces and lines to connect the various parts of the data processing unit.

[0117] Another embodiment of this application provides a network processor, including a Virtio driver and the data processing unit described in the above embodiments, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.

[0118] Another embodiment of this application provides a computer program product, including computer program instructions that instruct a computer device to perform operations corresponding to the message uploading method described in the above embodiments.

[0119] Specifically, the computer program product includes a series of computer program instructions, which are codes written in a computer program. These instructions define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and instruct the device to perform specific operations, which refer to the various steps in the message uploading method described in the above embodiments. In this way, the computer program product of this embodiment provides a complete software solution that can run on various computer devices to implement the message uploading method of the above embodiments.

[0120] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A message uploading method, applied to a data processing unit, characterized in that, The method includes: Obtain the number of packets currently cached in the data processing unit of the target queue, and determine the number of descriptors to read based on the number of packets; The number of descriptors are read in a single PCIe read operation; Write the packets of the target queue to the host-side buffer unit pointed to by the descriptor; wherein, each time a packet of the target queue is written to the host-side buffer unit, the current buffer packet count corresponding to the target queue is decremented by one; If all read descriptors have been used and not all packets in the target queue have been written to the host-side cache unit, then the number of descriptors to be read is determined again based on the current number of cached packets corresponding to the target queue. The number of descriptors determined again is read through a single PCIe read operation, and the remaining packets in the target queue are written to the host-side cache unit pointed to by the descriptor read again, until all cached packets corresponding to the target queue are written to the host-side cache unit.

2. The method according to claim 1, characterized in that, The step of determining the number of descriptors to be read based on the number of messages includes: The current number of packets in the target queue is determined as the number of descriptors read.

3. The method according to claim 2, characterized in that, The method further includes: If any queue has a message to be written to the host side cached in the data processing unit and any queue needs to read a descriptor, then any queue is identified as a queue to be scheduled, and the target queue is determined by scheduling all queues to be scheduled.

4. The method according to claim 3, characterized in that, The method further includes: Obtain the valid packet bitmap value and read wait bitmap value of any queue, perform a bitwise AND operation on the valid packet bitmap value and read wait bitmap value, and determine whether to identify any queue as a queue to be scheduled based on the result of the bitwise AND operation; wherein, the valid packet bitmap value indicates whether any queue has buffered packets; the read wait bitmap value indicates whether any queue needs to read descriptors; if any queue has corresponding buffered packets, then the valid packet bitmap value of any queue is set to 1, otherwise it is set to 0; if any queue needs to read descriptors, then the read wait bitmap value of any queue is set to 1, otherwise it is set to 0.

5. The method according to claim 1, characterized in that, The method further includes: Receive a message from any queue, cache the message from any queue in the message storage module corresponding to the queue, and update the message count value in the message count cache unit corresponding to the queue.

6. A data processing unit, characterized in that, This includes a descriptor number determination module, a descriptor reading module, and a message uploading module; The descriptor number determination module is used to obtain the number of packets currently cached in the data processing unit of the target queue, and determine the number of descriptors to be read based on the number of packets; The descriptor reading module is used to read the number of descriptors in a single PCIe read operation; The message uploading module is used to write the messages of the target queue into the host-side buffer unit pointed to by the descriptor; wherein, each time a message of the target queue is written into the host-side buffer unit, the number of buffered messages of the target queue is decremented by one; The descriptor number determination module is also used to determine the number of descriptors to be read again based on the number of packets in the target queue if all the currently read descriptors have been used and not all packets in the currently cached target queue have been written to the host-side cache unit. The descriptor reading module is also used to read a determined number of descriptors in a single PCIe read operation; The message uploading module is also used to write the remaining messages of the target queue into the host-side cache unit pointed to by the descriptor that is read again.

7. The data processing unit according to claim 6, characterized in that, The descriptor number determination module is used to determine the number of messages in the target queue as the number of descriptors to be read.

8. The data processing unit according to claim 7, characterized in that, The data processing unit further includes a queue scheduling module, which is used to determine any queue as a queue to be scheduled when any queue has a message to be written to the host side cached in the data processing unit and the queue needs to read a descriptor, and to schedule all queues to be scheduled to determine the target queue.

9. The data processing unit according to claim 8, characterized in that, The queue scheduling module is used to obtain the message valid bitmap value and the read waiting bitmap value of any queue, perform a bitwise AND operation on the message valid bitmap value and the read waiting bitmap value, and determine whether to identify any queue as a queue to be scheduled based on the result of the bitwise AND operation. Wherein, the message valid bitmap value indicates whether any queue has a cached message; the read wait bitmap value indicates whether any queue needs to read a descriptor; if any queue currently has a cached message, the message valid bitmap value of any queue is set to 1, otherwise it is set to 0; if any queue needs to read a descriptor, the read wait bitmap value of any queue is set to 1, otherwise it is set to 0.

10. The data processing unit according to claim 6, characterized in that, The data processing unit further includes a message receiving module, which is used to receive messages from any queue, cache the messages of any queue in the message storage module corresponding to the queue, and update the message count value in the message count cache unit corresponding to the queue.

11. A data processing unit, characterized in that, include: A communication interface used to communicate with other electronic devices; Memory is used to store computer program instructions; A processor for executing the computer program instructions to support the data processing unit in implementing the method of any one of claims 1 to 5.

12. A network processor, characterized in that, The device includes a Virtio driver and a data processing unit as described in any one of claims 6 to 10, wherein the Virtio driver runs on the host side and is used at least to generate the descriptor.

13. A computer program product, characterized in that, It includes computer program instructions that instruct a computer device to perform an operation corresponding to the method described in any one of claims 1 to 5.

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