E-Mode HEMT chip with high threshold voltage and manufacturing method thereof
By cascaded the voltage regulator diode and resistor part in the GaN HEMT chip, the threshold voltage is improved, and the problems of low threshold voltage and poor stability in the prior art are solved, and the E-Mode HEMT chip with high stability and low frequency loss are achieved.
Patent Information
- Application Number
- CN202510507160.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-22
- Publication Date
- 2025-08-19
AI Technical Summary
The existing GaN HEMT power devices have low threshold voltages and are susceptible to signal fluctuations in gate drive circuits. The device stability of the Cascode structure is poor and the frequency performance is impaired.
The voltage-regulating diode and resistor part are used to cascade with the GaN HEMT chip, and the voltage-regulating diode is fabricated through the GaN/AlGaN heterojunction structure. The P-GaN layer is used as the resistor to design a new chip structure to increase the threshold voltage, and junction capacitors are introduced to reduce the frequency effect without changing the chip process.
The E-Mode HEMT chip with high threshold voltage has good stability, low cost, and basically unchanged frequency performance, avoiding the introduction of additional impedance and inductance, and maintaining the low-resistance and high-frequency characteristics of the device.
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Figure CN120512918A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor power devices, and in particular to an E-Mode HEMT chip with a high threshold voltage and a manufacturing method thereof. Background Art
[0002] In existing technology, GaN HEMT (FET) power devices generally have a low threshold voltage, with an E-mode voltage typically between 1 and 2V. When subsequently applied to a circuit, these devices are susceptible to signal fluctuations in the gate drive circuit, causing the GaN HEMT device to misbehave. Therefore, the demand for HEMT isolation devices with higher threshold voltages has become the preferred switching device for application circuits.
[0003] Currently, single-chip E-Mode chips primarily utilize GaN systems, with a typical threshold voltage of 1.7V. Other manufacturers currently utilize a cascode (D-mode + MOS tube co-sealed) approach to achieve high-threshold E-Mode functionality (threshold voltages above 3V). However, the cascaded MOS tubes directly affect the overall device frequency. Furthermore, feedback from users indicates that cascode devices exhibit poor stability. Summary of the Invention
[0004] The present invention provides an E-Mode HEMT chip with a high threshold voltage and a manufacturing method thereof. These chips can effectively increase the threshold voltage of a single E-Mode GaN HEMT discrete device. Compared with discrete GaN HEMT devices fabricated using a cascode method, these chips can also effectively mitigate the impact of poor system stability caused by MOS transistor cascades and significantly reduce device frequency sacrifice.
[0005] According to a first aspect of an embodiment of the present application, an E-Mode HEMT chip with a high threshold voltage is provided, comprising a Zener diode portion, a chip portion, and a resistor portion, wherein a gate of the chip portion is connected to an anode of the Zener diode portion and to one end of the resistor portion, and a source of the chip portion is connected to the other end opposite the resistor portion.
[0006] The drain of the chip portion serves as the drain of the E-Mode HEMT chip, the cathode of the Zener diode portion serves as the gate of the E-Mode HEMT chip, and the portion of the resistor portion connected to the source of the chip portion serves as the source of the E-Mode HEMT chip.
[0007] In a possible implementation, the voltage stabilizing diode is partially manufactured using a GaN / AlGaN heterojunction structure.
[0008] In a possible implementation, the resistor portion is made of a P-GaN layer.
[0009] According to a second aspect of an embodiment of the present application, an E-Mode HEMT chip with a high threshold voltage is provided, comprising a substrate layer, and a GaN layer and an AlGaN layer sequentially grown on the surface of the substrate layer, wherein a gate, a source electrode, a drain electrode, a passivation layer, and a first P-GaN layer, a second P-GaN layer, and a third P-GaN layer are simultaneously provided on the surface of the AlGaN layer, the gate electrode and the drain electrode are respectively located near the sides, the source electrode is located near the middle, and is connected to the surface of the second P-GaN layer and the surface of the AlGaN layer;
[0010] The passivation layer consists of a first U-shaped portion, a second U-shaped portion, a third passivation layer, and a fourth passivation layer, wherein one end of the first U-shaped portion is connected to the surface of the first P-GaN layer and separates the gate and the first P-GaN layer on the surface of the AlGaN layer, and the other end separates the third P-GaN layer and the drain on the surface of the AlGaN layer, wherein one end of the second U-shaped portion is connected to the surface of the second P-GaN layer and the other end separates the source and the third P-GaN layer on the surface of the AlGaN layer, wherein the third passivation layer is embedded between the first P-GaN layer and the second P-GaN layer and vertically penetrates the AlGaN layer and is connected to the surface of the GaN layer, wherein one end of the fourth passivation layer is embedded in the source, and the other end vertically penetrates the AlGaN layer along the outer side surface of the second P-GaN layer and is connected to the surface of the GaN layer;
[0011] A metal layer is provided between the first U-shaped portion and the second U-shaped portion. The metal layer is connected to the surfaces of the first P-GaN layer, the second P-GaN layer and the third P-GaN layer at the same time, and the third passivation layer is embedded in the metal layer.
[0012] A third aspect of the present application provides a method for manufacturing an E-Mode HEMT chip with a high threshold voltage as described above, comprising the following steps:
[0013] S10, manufacturing an E-mode GaN HEMT epitaxial wafer, wherein the E-mode GaN HEMT epitaxial wafer includes a substrate layer and a GaN layer, an AlGaN layer, and a P-GaN layer sequentially grown on a surface of the substrate layer;
[0014] S20, etching the E-mode GaN HEMT epitaxial wafer, including etching the gate region, the first U-shaped portion region, the second U-shaped portion region, the third passivation layer region, the fourth passivation layer region, the source region, and the drain region on the surface of the AlGaN layer;
[0015] S30, forming N ohmic contact layers on the surface of the AlGaN layer in the region of the gate, the region of the source electrode, and the region of the drain electrode, respectively, and then forming P ohmic contact layers on the surface of the N ohmic contact layer and the surface of the P-GaN layer at the position of the metal layer and the position of the source electrode;
[0016] S40, forming a first passivation layer between the N ohmic contact layer and the adjacent P-GaN layer, in the area of the third passivation layer, and in the area of the fourth passivation layer;
[0017] S50, forming a cascade layer on the surface of the P-ohmic contact layer, wherein the cascade layers on both sides of the third passivation layer and the fourth passivation layer are connected, wherein the first passivation layer within the third passivation layer constitutes the third passivation layer, and the first passivation layer within the fourth passivation layer constitutes the fourth passivation layer;
[0018] S60, forming a second passivation layer in the range of the first U-shaped portion and the range of the second U-shaped portion, so that the surface of the second passivation layer is flush with the cascade layer;
[0019] S70, forming an interconnection layer on the surface of the cascade layer, and connecting the interconnection layer near the middle position, so that the P-ohmic contact layer near the middle position, the cascade layer, and the interconnection layer constitute the metal layer, wherein the height of the interconnection layer near both sides is flush and protrudes from the metal layer, and the first passivation layer and the second passivation layer within the range of the second U-shaped portion constitute the second U-shaped portion;
[0020] S80, forming a third passivation layer within the range of the first U-shaped portion, so that the third passivation layer is flush with the height of the interconnection layer on both sides, wherein the first passivation layer, the second passivation layer and the third passivation layer within the range of the first U-shaped portion constitute the first U-shaped portion.
[0021] Beneficial Effects: Compared with the prior art, the E-Mode HEMT chip with a high threshold voltage provided by the present application has a simple manufacturing process. The Zener diode and resistor components can both be implemented using corresponding epitaxial thin film layers, resulting in good stability and low cost. Furthermore, the desired high threshold voltage can be achieved by designing different Zener diode and resistor components without changing the chip manufacturing process. The entire device only introduces a junction capacitance similar to that of the Zener diode at the gate, which can greatly reduce the impact on the frequency of the entire device. Furthermore, since no external discrete components or wiring are integrated, the entire device can achieve a higher threshold voltage without introducing additional impedance and inductance, allowing the chip to maintain its original low resistance and high-frequency performance with little change.
[0022] These and other objects, features and advantages of the present invention will be fully reflected in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 A schematic structural diagram of an E-Mode HEMT chip with a high threshold voltage is shown in the present application.
[0024] Figure 2 The figure shows a simulation experiment of the E-Mode HEMT chip with high threshold voltage of the present application.
[0025] Figure 3 The figure shows the characteristic curve of the chip of the present application when the Vth is tested using Kingsley B1505A.
[0026] Figure 4 The figure shows the characteristic curve of the chip of the present application when the Ron is tested using Kingsley B1505A.
[0027] Figure 5 The figure shows the characteristic curve of the chip of the present application when the Id-off leakage is tested using Kingsley B1505A.
[0028] Figure 6 A schematic structural diagram of an E-Mode HEMT chip with a high threshold voltage is shown in the present application.
[0029] Figure 7 A simplified diagram of a method for manufacturing an E-Mode HEMT chip with a high threshold voltage according to the present application is shown.
[0030] Figure 8 The figure shows a simplified internal principle diagram of the E-Mode HEMT chip with high threshold voltage of the present application. DETAILED DESCRIPTION
[0031] The following description is intended to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are for illustrative purposes only, and those skilled in the art will readily appreciate other obvious variations. The basic principles of the present invention defined in the following description may be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the present invention.
[0032] Those skilled in the art should understand that, in the disclosure of the specification, the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like to indicate the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.
[0033] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the elements may be multiple, and the term "one" should not be understood as a limitation on the quantity.
[0034] refer to Figures 1 to 5 According to a first aspect of an embodiment of the present application, an E-Mode HEMT chip with a high threshold voltage is provided, comprising a Zener diode portion D1, a chip portion M1, and a resistor portion R1. The Zener diode portion D1 may be a Zener diode, the resistor portion R1 may be a pull-down resistor, and the chip portion M1 may be a GaN HEMT main chip. The gate of the chip portion M1 is connected to the anode of the Zener diode portion D1 and to one end of the resistor portion R1, and the source of the chip portion M1 is connected to the other end opposite the resistor portion R1.
[0035] The drain of the chip portion M1 serves as the drain of the E-Mode HEMT chip with a high threshold voltage of the present application, the cathode of the Zener diode portion D1 serves as the gate of the E-Mode HEMT chip of the present application, and the portion of the resistor portion R1 connected to the source of the chip portion M1 serves as the source of the E-Mode HEMT chip of the present application.
[0036] The working principle is roughly as follows: when the gate input voltage of the chip (i.e., the E-Mode HEMT chip of the present application) is less than the voltage of the Zener diode part D1, the Zener diode part D1 is in reverse cutoff, which is equivalent to the potential at the output end of the Zener diode part D1 being 0, and the chip part M1 is in the off state. When the gate input voltage is greater than the voltage of the Zener diode part D1, the Zener diode part D1 is in a reverse breakdown state, and the output voltage at the output end of the Zener diode part D1 serves as the gate voltage of the chip part M1, which is used to drive the chip part M1. At the same time, the resistor part R1 shunts the current at the output end of the Zener diode part D1, which can ensure that the gate-source current of the chip part M1 is not too large and damages the chip part M1.
[0037] The simulation experiment is as follows: the voltage stabilizing diode D1 is IN750 (nominal stable voltage is 4.7V), the chip M1 is SI7336ADP (threshold voltage is 3V), and the simulation is carried out according to the aforementioned chip connection circuit. As a result, the threshold voltage of the E-Mode HEMT chip of this application is increased from the original 3V to 4.2V. Figure 2 As shown, Figure 2 The left side of the middle is a complete simulation experiment diagram, and the right side is a partially enlarged schematic diagram of the left side diagram. The magnification can be referred to the horizontal axis values in the two figures.
[0038] Actual verification results: The voltage of the Zener diode D1 is 3V, the threshold voltage of the chip M1 is VTH = 0.5V, the internal resistance Ron = 96mΩ, and the resistor R1 is 5KΩ. The test results of the circuit are as follows:
[0039] Vth(V) Ron(mΩ) Id-off(uA) Chip part M1 0.6 96 7 This application E-Mode HEMT chip 2.7 100 8
[0040] The Vth, Ron, and Id-off leakage characteristic curves tested using Kingsley B1505A are as follows: Figure 3 、 Figure 4 、 Figure 5 As shown, through Figure 3 It can be seen that the threshold voltage of the E-Mode HEMT chip of this application can be greatly increased from 0.6V to 2.7V, wherein Figure 4 and Figure 5 It can be seen that when the threshold voltage of the E-Mode HEMT chip of the present application is greatly increased, the internal resistance and leakage of the E-Mode HEMT chip do not change significantly, indicating that the E-Mode HEMT chip provided by the present application can still operate normally.
[0041] In one embodiment, the Zener diode portion D1 is made of a GaN / AlGaN heterojunction structure and has the same function as a Zener diode.
[0042] In one embodiment, the resistor portion R1 is made of a P-GaN layer and has the same function as a pull-down resistor.
[0043] Therefore, the overall manufacturing process of the E-Mode HEMT chip with a high threshold voltage provided by the present application is relatively simple, wherein both the Zener diode portion D1 and the resistor portion R1 can be implemented using corresponding thin film layers in the epitaxial layer, resulting in better structural stability and low cost.
[0044] In addition, the required high threshold voltage can be achieved by designing different Zener diode parts D1 and resistor parts R1 without changing the chip part M1 process, which is convenient to implement and more flexible to use. The entire device only introduces the junction capacitance of the Zener diode part D1 at the gate, which can greatly reduce the impact on the frequency of the entire device.
[0045] In addition, because there is no integration of external discrete components and wires, the entire device can not only obtain a high threshold voltage, but also does not introduce additional impedance and inductance, allowing the GaN HEMT to maintain its original low resistance and high-frequency performance with almost no change.
[0046] Based on the same basic working principle, combined with Figure 6 According to a second aspect of an embodiment of the present application, an E-Mode HEMT chip with a high threshold voltage is provided, comprising a substrate layer and a GaN layer and an AlGaN layer sequentially grown on the surface of the substrate layer, wherein the surface of the AlGaN layer is provided with a gate G, a source S, a drain D, a passivation layer, and a first P-GaN layer 11, a second P-GaN layer 12, and a third P-GaN layer 13. The gate G and the drain D are respectively located on both sides, and the source S is located in the middle and is connected to the surface of the second P-GaN layer 12 and the surface of the AlGaN layer.
[0047] The passivation layer is composed of a first U-shaped portion 21, a second U-shaped portion 22, a third passivation layer 23 and a fourth passivation layer 24, wherein one end of the first U-shaped portion 21 is connected to the surface of the first P-GaN layer 11 and is embedded between the gate G and the first P-GaN layer 11, and the other end is embedded between the third P-GaN layer 13 and the drain D, wherein one end of the second U-shaped portion 22 is connected to the surface of the second P-GaN layer 12, and the other end is embedded between the source S and the third P-GaN layer 13, wherein The third passivation layer 23 is embedded between the first P-GaN layer 11 and the second P-GaN layer 12, and vertically penetrates the AlGaN layer to be connected to the surface of the GaN layer, wherein one end of the fourth passivation layer 24 is embedded in the source electrode S, and the other end vertically penetrates the AlGaN layer along the outer side surface of the second P-GaN layer 12 to be connected to the surface of the GaN layer, wherein the outer side surface of the second P-GaN layer 12 is the side surface of the second P-GaN layer 12 close to the third P-GaN layer 13;
[0048] A metal layer 25 is provided between the first U-shaped portion 21 and the second U-shaped portion 22. The metal layer 25 is connected to the surfaces of the first P-GaN layer 11, the second P-GaN layer 12 and the third P-GaN layer 13 at the same time, and the third passivation layer 23 is embedded in the metal layer.
[0049] Based on the same basic working principle, combined with Figures 6 to 8 In a third aspect, an embodiment of the present application provides a method for manufacturing an E-Mode HEMT chip with a high threshold voltage as described above, comprising the following steps in sequence:
[0050] S10, manufacturing an E-mode GaN HEMT epitaxial wafer, wherein the E-mode GaN HEMT epitaxial wafer includes a substrate layer and a GaN layer, an AlGaN layer, and a P-GaN layer sequentially grown on a surface of the substrate layer;
[0051] S20, etching the E-mode GaN HEMT epitaxial wafer by photolithography and etching processes, including etching the gate region, the first U-shaped portion region, the second U-shaped portion region, the third passivation layer region, the fourth passivation layer region, the source region, and the drain region on the surface of the AlGaN layer;
[0052] S30, forming an N-ohmic contact layer (N-Ohmic) 201 on the surface of the AlGaN layer in the region of the gate, the region of the source, and the region of the drain respectively through photolithography, coating, and lift-off processes, and performing an RTA 850° C. (N2 environment) annealing treatment, and then forming a P-ohmic contact layer (P-Ohmic) 202 on the surface of the N-ohmic contact layer 201 and the surface of the P-GaN layer at the position of the metal layer and the position of the source, and performing an RTA 550° C. (atmospheric environment) annealing treatment;
[0053] S40, forming a first passivation layer 203 between the N ohmic contact layer 201 and the adjacent P-GaN layer, within the range of the third passivation layer, and within the range of the fourth passivation layer by photolithography and polyimide oven baking;
[0054] S50, forming a cascade layer 204 on the surface of the P-ohmic contact layer 202 by photolithography, coating, and lift-off processes, wherein the cascade layer 204 on both sides of the third passivation layer and the fourth passivation layer are connected, wherein the first passivation layer within the third passivation layer constitutes the third passivation layer, and the first passivation layer within the fourth passivation layer constitutes the fourth passivation layer;
[0055] S60, forming a second passivation layer 205 in the range of the first U-shaped portion and the range of the second U-shaped portion by photolithography and polyimide oven baking, so that the surface of the second passivation layer 205 is flush with the cascade layer 204;
[0056] S70, forming an interconnection layer 206 on the surface of the cascade layer 204 by photolithography, coating, and lift-off processes, and connecting the interconnection layer 206 near the middle position, so that the P-ohmic contact layer 202 near the middle position, the cascade layer 204, and the interconnection layer 206 constitute the metal layer, wherein the height of the interconnection layer 206 near both sides is flush and protrudes from the metal layer, and the first passivation layer and the second passivation layer within the range of the second U-shaped portion constitute the second U-shaped portion;
[0057] S80, forming a third passivation layer within the range of the first U-shaped portion by photolithography and polyimide oven baking, so that the third passivation layer is flush with the height of the interconnection layers on both sides, wherein the first passivation layer, the second passivation layer, and the third passivation layer within the range of the first U-shaped portion constitute the first U-shaped portion, thus completing the manufacturing process of the E-Mode HEMT chip with a high threshold voltage of the present application;
[0058] It should be noted that, in the manufacturing process, photolithography, etching, coating, stripping, and photolithography polyimide oven baking are all existing mature technologies and will not be described in detail here.
[0059] It should be noted that the terms "first, second, third and fourth" in this application are used for descriptive purposes only and do not indicate any order. They cannot be understood as indicating or implying relative importance. These terms can be interpreted as names.
[0060] Those skilled in the art will appreciate that the embodiments of the present invention described above and shown in the accompanying drawings are intended to be illustrative only and are not intended to limit the present invention. The advantages of the present invention have been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and illustrated in the embodiments. Any variations or modifications may be made to the embodiments of the present invention without departing from the principles described.
Claims
1. E-Mode HEMT chip with high threshold voltage, characterized by: The chip comprises a voltage stabilizing diode portion, a chip portion, and a resistor portion, wherein the gate of the chip portion is connected to the anode of the voltage stabilizing diode portion and to one end of the resistor portion, and the source of the chip portion is connected to the other end opposite to the resistor portion; The drain of the chip portion serves as the drain of the E-Mode HEMT chip, the cathode of the Zener diode portion serves as the gate of the E-Mode HEMT chip, and the portion of the resistor portion connected to the source of the chip portion serves as the source of the E-Mode HEMT chip.
2. The E-Mode HEMT chip with a high threshold voltage according to claim 1, wherein: The voltage stabilizing diode is partially manufactured through a GaN / AlGaN heterojunction structure.
3. The E-Mode HEMT chip with a high threshold voltage according to claim 2, wherein: The resistor portion is made of a P-GaN layer.
4. E-Mode HEMT chip with high threshold voltage, characterized by: The invention comprises a substrate layer and a GaN layer and an AlGaN layer sequentially grown on the surface of the substrate layer, wherein the surface of the AlGaN layer is simultaneously provided with a gate, a source, a drain, a passivation layer, and a first P-GaN layer, a second P-GaN layer, and a third P-GaN layer, the gate and the drain are respectively close to both sides, the source is close to the middle, and is simultaneously connected to the surface of the second P-GaN layer and the surface of the AlGaN layer; The passivation layer consists of a first U-shaped portion, a second U-shaped portion, a third passivation layer, and a fourth passivation layer, wherein one end of the first U-shaped portion is connected to the surface of the first P-GaN layer and separates the gate and the first P-GaN layer on the surface of the AlGaN layer, and the other end separates the third P-GaN layer and the drain on the surface of the AlGaN layer, wherein one end of the second U-shaped portion is connected to the surface of the second P-GaN layer and the other end separates the source and the third P-GaN layer on the surface of the AlGaN layer, wherein the third passivation layer is embedded between the first P-GaN layer and the second P-GaN layer and vertically penetrates the AlGaN layer and is connected to the surface of the GaN layer, wherein one end of the fourth passivation layer is embedded in the source, and the other end vertically penetrates the AlGaN layer along the outer side surface of the second P-GaN layer and is connected to the surface of the GaN layer; A metal layer is provided between the first U-shaped portion and the second U-shaped portion. The metal layer is connected to the surfaces of the first P-GaN layer, the second P-GaN layer and the third P-GaN layer at the same time, and the third passivation layer is embedded in the metal layer.
5. The method for manufacturing an E-Mode HEMT chip with a high threshold voltage according to claim 4, wherein: The following steps are included in sequence: S10, manufacturing an E-mode GaN HEMT epitaxial wafer, wherein the E-mode GaN HEMT epitaxial wafer includes a substrate layer and a GaN layer, an AlGaN layer, and a P-GaN layer sequentially grown on a surface of the substrate layer; S20, etching the E-mode GaN HEMT epitaxial wafer, including etching the gate region, the first U-shaped portion region, the second U-shaped portion region, the third passivation layer region, the fourth passivation layer region, the source region, and the drain region on the surface of the AlGaN layer; S30, forming N ohmic contact layers on the surface of the AlGaN layer in the region of the gate, the region of the source electrode, and the region of the drain electrode, respectively, and then forming P ohmic contact layers on the surface of the N ohmic contact layer and the surface of the P-GaN layer at the position of the metal layer and the position of the source electrode; S40, forming a first passivation layer between the N ohmic contact layer and the adjacent P-GaN layer, in the area of the third passivation layer, and in the area of the fourth passivation layer; S50, forming a cascade layer on the surface of the P-ohmic contact layer, wherein the cascade layers on both sides of the third passivation layer and the fourth passivation layer are connected, wherein the first passivation layer within the third passivation layer constitutes the third passivation layer, and the first passivation layer within the fourth passivation layer constitutes the fourth passivation layer; S60, forming a second passivation layer in the range of the first U-shaped portion and the range of the second U-shaped portion, so that the surface of the second passivation layer is flush with the cascade layer; S70, forming an interconnection layer on the surface of the cascade layer, and connecting the interconnection layer near the middle position, so that the P-ohmic contact layer near the middle position, the cascade layer, and the interconnection layer constitute the metal layer, wherein the height of the interconnection layer near both sides is flush and protrudes from the metal layer, and the first passivation layer and the second passivation layer within the range of the second U-shaped portion constitute the second U-shaped portion; S80, forming a third passivation layer within the range of the first U-shaped portion, so that the third passivation layer is flush with the height of the interconnection layer on both sides, wherein the first passivation layer, the second passivation layer and the third passivation layer within the range of the first U-shaped portion constitute the first U-shaped portion.