Solar cell and method of manufacturing the same

Abstract

The application discloses a solar cell and a preparation method thereof, and relates to the technical field of photovoltaics. In the preparation method of the solar cell, the energy of a laser irradiation area is controlled, so that when a first doped silicon layer and a first dielectric layer in an etching exposure area are subsequently prepared, the edge etching depth of the exposure area is relatively shallow, the middle etching depth is relatively deep, and the first groove can have an inclined sidewall. When a second doped silicon layer is subsequently prepared, the second doped silicon layer will not be deposited below the first doped silicon layer. Then, by making a second groove, the first doped silicon layer and the second doped silicon layer can be completely separated, so that the minority carrier recombination and the leakage channel caused by the contact between the first doped silicon layer and the second doped silicon layer are reduced, and the performance of the solar cell is improved.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and more specifically, to a solar cell and a method for its fabrication. Background Technology

[0002] Back-contact batteries have all electrode grid lines arranged on the back of the battery, with the PN junction and metal contacts also located on the back in an interdigitated arrangement. This reduces sunlight shading by the grid lines and improves battery conversion efficiency. TBC batteries are a type of back-contact battery, formed by combining TOPCon (Tunnel Oxide Passivated Contact) and IBC (Interdigitated Back Contact) technologies, also known as POLO-IBC batteries. They combine the tunnel oxide technology of TOPCon batteries with the advantages of rear-side electrode arrangement in IBC batteries, significantly improving passivation and open-circuit voltage, thus achieving higher photoelectric conversion efficiency.

[0003] The core of TBC (Thin-Type Cell) fabrication lies in creating a PN-poly doped structure. First, the p-type polycrystalline silicon doped region needs precise patterning. Then, a portion of the p-type polycrystalline silicon layer is removed via chemical etching. Following this, an n-type polycrystalline silicon layer is fabricated, forming an interdigitated PN-poly doped structure. However, excessive lateral etching during the removal of the p-type polycrystalline silicon layer can occur, causing a portion of the subsequently deposited n-type polycrystalline silicon layer to overlap beneath the p-type polycrystalline silicon layer. This latter portion of the n-type polycrystalline silicon layer is difficult to remove and remains in the final product, leading to minority carrier recombination and leakage channels, thus affecting the performance of the solar cell. Summary of the Invention

[0004] The purpose of this application is to provide a solar cell and a method for fabricating the same, which can reduce minority carrier recombination and leakage channels, thereby improving the performance of the solar cell.

[0005] The embodiments of this application can be implemented as follows:

[0006] In a first aspect, this application provides a method for preparing a solar cell, comprising:

[0007] Obtain a silicon substrate, which has a front side and a back side facing each other;

[0008] A first dielectric layer and a first doped silicon layer are sequentially stacked on the back side of a silicon substrate;

[0009] When a laser is used to irradiate a local area of ​​the first doped silicon layer, the light energy per unit area at the edge of the exposed area is less than that per unit area in the middle of the exposed area.

[0010] The first doped silicon layer and the first dielectric layer in the exposure area are etched using a wet etching process to obtain a first trench with inclined sidewalls, wherein the angle between the inclined sidewalls and the bottom wall of the first trench is an obtuse angle.

[0011] A second dielectric layer and a second doped silicon layer are sequentially stacked within the first trench to fill the first trench;

[0012] A portion of the second dielectric layer and the second doped silicon layer in contact with the inclined sidewall is removed to form the second trench;

[0013] Passivation layers are prepared on the front and back sides of a silicon substrate, and a first electrode connected to a first doped silicon layer and a second electrode connected to a second doped silicon layer are fabricated.

[0014] In an optional embodiment, the step of irradiating a localized region of the first doped silicon layer with a laser includes:

[0015] The light spot is used to scan along n scanning paths, where n≥2. The scanning paths extend along a first direction, and the n scanning paths are arranged in a second direction. The first direction is perpendicular to the second direction, and adjacent scanning paths partially overlap.

[0016] In an optional implementation, the width W1 of the scanning path in the second direction and the width W2 of the overlapping area of ​​two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where the value of a ranges from 0.2 to 0.8.

[0017] In an optional implementation, in the first scan path and the nth scan path in the second direction, the area not covered by the adjacent scan path occupies 5% to 40% of the exposure area.

[0018] In an optional implementation, the light spot is a rectangular light spot.

[0019] In an optional implementation, the width of the light spot in the second direction is 100 μm to 400 μm.

[0020] In an optional embodiment, the step of irradiating a localized region of the first doped silicon layer with a laser includes:

[0021] The light spot is used to scan along n scanning paths, where n≥2. The scanning paths extend along a first direction, and the n scanning paths are spliced ​​together in a second direction. The first direction is perpendicular to the second direction. The scanning speed of the first scanning path and the nth scanning path in the second direction is greater than the scanning speed of the second to the (n-1)th scanning paths.

[0022] In an optional embodiment, the step of etching the first doped silicon layer and the first dielectric layer in the exposure area using a wet etching process includes:

[0023] The exposed area is immersed in the first etching solution;

[0024] Wash the exposed area with water;

[0025] The exposed area is immersed in a second etching solution;

[0026] Both the first etching solution and the second etching solution are alkaline solutions, with the first etching solution being more alkaline than the second etching solution.

[0027] In an optional embodiment, the exposure area is immersed in the first etching solution for 50s to 200s, and the exposure area is immersed in the second etching solution for 100s to 400s.

[0028] In an optional embodiment, the alkaline component in the first etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume percentage of the alkaline component in the first etching solution is 5% to 10%; the alkaline component in the second etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume percentage of the alkaline component in the second etching solution is 5% to 10%.

[0029] In an optional embodiment, the angle between the inclined sidewall and the bottom wall of the first groove is 100° to 150°.

[0030] In an optional embodiment, the first doped silicon layer is p-type doped and the second doped silicon layer is n-type doped.

[0031] In an optional embodiment, the materials of the first dielectric layer and the second dielectric layer are silicon oxide.

[0032] In an optional embodiment, the step of fabricating passivation layers on the front and back sides of the silicon substrate includes:

[0033] A first passivation layer is deposited on the front side of the silicon substrate;

[0034] A second passivation layer is deposited on the first doped silicon layer, the second doped silicon layer, and the bottom wall and inclined sidewalls of the second trench.

[0035] In an optional embodiment, the material of the passivation layer is selected from at least one of alumina, silicon oxide, silicon oxynitride, and silicon nitride.

[0036] Secondly, this application provides a solar cell, which is prepared by any of the solar cell preparation methods described in the foregoing embodiments.

[0037] The beneficial effects of the solar cells and their fabrication methods provided in this application include:

[0038] The method for fabricating a solar cell provided in this application includes: obtaining a silicon substrate having a front side and a back side; fabricating a first dielectric layer and a first doped silicon layer sequentially stacked on the back side of the silicon substrate; irradiating a local area of ​​the first doped silicon layer with a laser, wherein the light energy per unit area at the edge of the exposed area is less than the light energy per unit area in the middle of the exposed area; etching the first doped silicon layer and the first dielectric layer in the exposed area using a wet etching process to obtain a first trench with inclined sidewalls, wherein the angle between the inclined sidewalls and the bottom wall of the first trench is an obtuse angle; fabricating a second dielectric layer and a second doped silicon layer sequentially stacked in the first trench to fill the first trench; removing a portion of the second dielectric layer and the second doped silicon layer in contact with the inclined sidewalls to form a second trench; fabricating passivation layers on the front and back sides of the silicon substrate, and fabricating a first electrode connected to the first doped silicon layer and a second electrode connected to the second doped silicon layer. In this application embodiment, by controlling the energy of the laser irradiation area, the light energy per unit area at the edge of the exposed area is made less than the light energy per unit area in the middle of the exposed area. Because higher light energy makes etching easier, the edges of the first doped silicon layer and the first dielectric layer in the exposed area are etched at a shallower depth, while the center is etched at a deeper depth. This allows the first trench to have sloping sidewalls, and the opening width of the first trench is greater than its bottom width. When the second doped silicon layer is subsequently fabricated, it does not deposit beneath the first doped silicon layer. By creating the second trench, the first and second doped silicon layers can be completely separated, thus reducing minority carrier recombination and leakage channels caused by contact between the first and second doped silicon layers, and improving the performance of the solar cell.

[0039] The solar cells provided in this application embodiment are prepared by the above-described method and therefore have better photoelectric conversion efficiency. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart of a method for fabricating a solar cell in one embodiment of this application;

[0042] Figure 2 This is a schematic diagram showing the first dielectric layer and the first doped silicon layer after fabrication in one embodiment of this application;

[0043] Figure 3This is a schematic diagram of various scanning paths in one embodiment of this application;

[0044] Figure 4 This is a schematic diagram of various scanning paths in another embodiment of this application;

[0045] Figure 5 This is a schematic diagram of various scanning paths in another embodiment of this application;

[0046] Figure 6 This is a schematic diagram of the first trench after etching in one embodiment of this application;

[0047] Figure 7 This is a scanning electron microscope (SEM) image of the second trench in one embodiment of this application;

[0048] Figure 8 This is a schematic diagram of a second dielectric layer and a second doped silicon layer after fabrication, according to one embodiment of this application.

[0049] Figure 9 This is a schematic diagram of the second trench after it has been fabricated in one embodiment of this application;

[0050] Figure 10 This is a schematic diagram of the passivation layer and electrode fabricated in one embodiment of this application.

[0051] Icons: 100 - Silicon substrate; 110 - First dielectric layer; 120 - Second dielectric layer; 200 - First doped silicon layer; 210 - First trench; 211 - Inclined sidewall; 300 - Second doped silicon layer; 310 - Second trench; 400 - First passivation layer; 500 - Second passivation layer; 610 - First electrode; 620 - Second electrode. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0053] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0054] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0055] In the description of this application, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of the invention is usually placed during use, they are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0056] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0057] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0058] In related technologies, when fabricating TBC (Thin-Cell Batteries) cells, a portion of the first doped silicon layer (e.g., a p-type polycrystalline silicon layer) is removed using wet etching. Then, a second doped silicon layer (e.g., an n-type polycrystalline silicon layer) is fabricated in the area where the first doped silicon layer was removed. Next, a portion of the second doped silicon layer adjacent to the first doped silicon layer is removed, forming a trench separating the first and second doped silicon layers. However, due to the low precision of wet etching, the angle between the sidewall and bottom wall of the trench formed during the etching of the first doped silicon layer is not perpendicular, but rather an acute angle. This results in a portion of the subsequently fabricated second doped silicon layer being located at the angle between the sidewall and bottom wall, i.e., below the first doped silicon layer. When the portion of the second doped silicon layer adjacent to the first doped silicon layer is subsequently removed, the second doped silicon layer located below the first doped silicon layer is prone to remain, which can lead to minority carrier recombination and leakage channels, affecting the performance of the solar cell. In addition, existing methods require a deeper chemical etching depth, usually above 3μm, to achieve complete isolation of different doped silicon layers without residual risk. This results in the need for more chemicals and silicon substrate etching, which is not conducive to silicon substrate thinning and reducing production costs.

[0059] To address at least one deficiency in the aforementioned related technologies, this application provides a method for fabricating a solar cell. By controlling the exposure, an inclined sidewall is formed during the etching of the first doped silicon layer, preventing the subsequent fabrication of a second doped silicon layer from being partially covered by the first doped silicon layer. This reduces the risk of a second doped silicon layer remaining beneath the first doped silicon layer, improves the problem of minority carrier recombination and leakage channels caused by the overlap of the first and second doped silicon layers, and enhances the cell performance.

[0060] Figure 1 This is a flowchart illustrating a method for fabricating a solar cell according to one embodiment of this application. The method for fabricating a solar cell provided in this embodiment can be specifically used to fabricate back-contact cells, such as TBC cells. Figure 1 As shown, taking the fabrication of a TBC cell as an example, the method for preparing a solar cell provided in this application includes the following steps:

[0061] Step S100: Obtain silicon substrate 100, which has a front side and a back side.

[0062] In this embodiment, the silicon substrate 100 can be made of high-purity monocrystalline silicon. Monocrystalline silicon has very high purity, meaning it contains very few impurities, which has a significant advantage in reducing carrier recombination and improving battery efficiency. Furthermore, the atomic arrangement of monocrystalline silicon is regular and consistent, resulting in a uniform structure and reducing the impact of defects such as grain boundaries on carrier transport. Optionally, the silicon substrate 100 can be made of n-type monocrystalline silicon, which has a lower light-induced degradation effect and a higher theoretical efficiency limit. In other embodiments, the silicon substrate 100 can also be made of p-type monocrystalline silicon or other types of silicon, and the type of silicon substrate 100 can be selected according to the specific battery design requirements.

[0063] In this embodiment, the silicon substrate 100 has a front side and a back side facing each other, and the front side and the back side of the silicon substrate 100 are spaced apart in the thickness direction of the silicon substrate 100. The front side of the silicon substrate 100 corresponds to the light-facing side of the solar cell, and the back side of the silicon substrate 100 corresponds to the back-lighting side of the solar cell.

[0064] Optionally, before fabricating the first dielectric layer 110 and the first doped silicon layer 200, the back side of the silicon substrate 100 can be polished. After polishing, a square tower-like structure can be formed on the back side of the silicon substrate 100. Several tower-like structures can form a surface with certain undulations, increasing the bonding area between the subsequently grown film layer and the silicon substrate 100, and reducing the contact resistivity of the film structure. Polishing also facilitates subsequent microfabrication steps, such as laser processing or chemical etching, to form precise electrode patterns. Polishing can reduce defects on the surface of the silicon substrate 100, thus improving the overall mechanical strength of the silicon substrate 100 and reducing the risk of cracks or breakage due to stress concentration during manufacturing.

[0065] Optionally, the diagonal length of the square tower base structure is 18μm to 40μm.

[0066] In step S200, a first dielectric layer 110 and a first doped silicon layer 200 are sequentially stacked on the back side of the silicon substrate 100.

[0067] Figure 2This is a schematic diagram showing the first dielectric layer 110 and the first doped silicon layer 200 after fabrication in one embodiment of this application. Figure 2 The silicon substrate 100 has its front side facing up and its back side facing down. In this embodiment, a first dielectric layer 110 is first deposited on the back side of the silicon substrate 100. Optionally, the material of the first dielectric layer 110 is silicon oxide. Based on the quantum tunneling effect, the first dielectric layer 110 allows one type of charge carrier (typically minority carriers, such as holes in n-type silicon or electrons in p-type silicon) to pass through the first dielectric layer 110, while blocking another type of charge carrier. This selective transport characteristic helps reduce contact resistance and improve current collection efficiency. Due to the reduced contact resistance and improved selective transport efficiency of charge carriers, the fill factor of the battery is also improved, thereby further enhancing the overall performance. By forming a relatively thin first dielectric layer 110 on the surface of the silicon substrate 100, surface defects can be effectively passivated, surface recombination can be significantly reduced, thereby improving the open-circuit voltage of the battery. Furthermore, a first doped silicon layer 200 deposited on top of the tunneling oxide layer generates a built-in electric field at the interface. This electric field can attract and accumulate charge carriers, shielding the influence of surface states on charge carriers, thereby enhancing the passivation effect. This dual passivation mechanism (chemical passivation and field-effect passivation) ensures the stability and reliability of the battery during long-term operation and reduces performance degradation caused by environmental factors.

[0068] Optionally, the thickness of the first dielectric layer 110 is 1 nm to 5 nm. The first dielectric layer 110 can be fabricated using thermal oxidation or chemical vapor deposition processes, such as plasma-enhanced chemical vapor deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD). Specifically, the silicon substrate 100 can be placed in a chemical vapor deposition apparatus, and high-purity oxygen can be introduced to grow the first dielectric layer 110 on the back side of the silicon substrate 100.

[0069] In this embodiment, the first doped silicon layer 200 is p-type doped polycrystalline silicon. The first doped silicon layer 200 can be prepared by chemical vapor deposition. After the first dielectric layer 110 is formed, a silicon source (such as high-purity SiH4) is introduced to grow an intrinsic amorphous silicon layer on the first dielectric layer 110. Then, the above structure is placed in a boron diffusion furnace tube, and BCl3 is introduced for boron diffusion to transform the intrinsic amorphous silicon layer into a p-type doped amorphous silicon layer. After that, annealing is performed to achieve recrystallization, forming a p-type doped polycrystalline silicon layer, i.e., the first doped silicon layer 200.

[0070] Optionally, the intrinsic amorphous silicon layer has a deposition thickness of 200 nm to 400 nm, and the boron doping concentration of the first doped silicon layer 200 is 3 × 10⁻⁶. 19 / cm 3 ~8×10 19 / cm 3 The sheet resistance of the first doped silicon layer 200 is 100~200 Ω / sq. It should be understood that during the fabrication of the first doped silicon layer 200, a layer of borosilicate glass (not shown in the figure), abbreviated as BSG, is simultaneously formed on the surface of the first doped silicon layer 200, with a thickness of 20nm~80nm. BSG has a certain degree of corrosion resistance and can act as a mask in subsequent wet etching.

[0071] In step S300, a local area of ​​the first doped silicon layer 200 is irradiated with a laser, and the light energy per unit area at the edge of the exposed area is less than the light energy per unit area in the middle of the exposed area.

[0072] In this embodiment, the exposed area refers to the region where the second doped silicon layer 300 (n-type) needs to be fabricated subsequently, as well as the gap between the second doped silicon layer 300 and the first doped silicon layer 200, which needs to be removed; while the unexposed area is the part that will be retained later. The BSG film can be melted, vaporized, or peeled off from the doped polysilicon layer under the action of a laser to achieve laser film opening. Therefore, during subsequent wet etching, the first doped silicon layer 200 and the first dielectric layer 110 in the exposed area can be etched away, while the BSG film in the unexposed area acts as a mask to protect the first doped silicon layer 200 and the first dielectric layer 110 it covers from being etched.

[0073] It should be understood that the greater the light energy per unit area, the easier it is to be etched during subsequent wet etching; conversely, the smaller the light energy per unit area, the less likely it is to be etched. In the embodiments of this application, the light energy per unit area at the edge of the exposure area is less than that in the middle of the exposure area. Therefore, the etching depth of the edge area is relatively shallow during subsequent etching, while the etching depth of the middle area is relatively deep.

[0074] Optionally, the illuminance per unit area in the central part of the exposure area is 210 mJ / cm². 2 ~380 mJ / cm 2 The light energy per unit area at the edge is 150 mJ / cm². 2 ~300 mJ / cm 2 .

[0075] Figure 3 This is a schematic diagram of various scanning paths in one embodiment of this application. For example... Figure 3As shown, in this embodiment, the step of irradiating a local area of ​​the first doped silicon layer 200 with a laser includes: scanning along n scanning paths using a light spot, where n ≥ 2. The scanning paths extend along a first direction, and the n scanning paths are arranged in a second direction, with the first direction perpendicular to the second direction, and adjacent scanning paths partially overlapping. It can be understood that the first doped silicon layer 200 and the second doped silicon layer 300 on the ultimately fabricated solar cell are arranged alternately along the second direction, i.e., according to... Figure 3 The laser beams are arranged in a left-right direction; the width of the scanning path in the second direction is the laser spot width.

[0076] Figure 3 There are four scanning paths in total, namely: Figure 3 L1, L2, L3, and L4 are defined in the exposure area. In the exposure area, multiple scan paths are arranged along the second direction, while the two ends of the exposure area in the second direction are exposed only once. This part is the edge of the exposure area, and the illumination energy per unit area is relatively low. The scan paths in the middle of the exposure area overlap, so the illumination energy per unit area is relatively high. Figure 3 In the middle section, a portion of scan path L1 on the left is not covered by adjacent scan paths, thus forming the left edge of the exposure area; a portion of scan path L4 on the right is not covered by adjacent scan paths, thus forming the right edge of the exposure area; the middle section ( Figure 3 The shaded area has at least two overlapping scan paths.

[0077] Optionally, the width W1 of the scanning path in the second direction and the width W2 of the overlapping area of ​​two adjacent scanning paths in the second direction satisfy the relationship: W2 = a × W1, where a ranges from 0.2 to 0.8. a can take any value from 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, and 0.8, or a value between any two points. Figure 3 In the embodiment shown, W2 = 0.5 × W1, that is, the width of the overlapping area of ​​two adjacent scanning paths accounts for 50% of the width of a single scanning path.

[0078] The width of the scanning path (i.e., the width of the light spot), the number of scanning paths, and the overlap ratio of two adjacent scanning paths can be adjusted as needed. Figure 4 This is a schematic diagram of various scanning paths in another embodiment of this application. Figure 4 In the illustrated embodiment, there are three scanning paths, M1, M2, and M3 from left to right. A portion of scanning path M1 on the left is not covered by adjacent scanning paths, thus forming the left edge of the exposure area. A portion of scanning path M3 on the right is not covered by adjacent scanning paths, thus forming the right edge of the exposure area; the middle portion ( Figure 3In the shaded area, at least two scan paths overlap. It should be noted that in... Figure 4 In this embodiment, the exposure energy increases in a stepwise manner from the edge to the center of the exposure area. The two outer thirds of scan path M2 overlap with scan paths M1 and M3 respectively, and this portion is exposed twice; the middle third of scan path M2 overlaps with both scan paths M1 and M3, and this portion is exposed three times. Figure 4 In the embodiment shown, the width W1 of the scanning path in the second direction and the width W2 of the overlapping area of ​​two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where a is 2 / 3.

[0079] Optionally, in the first and nth scan paths in the second direction, the areas not covered by adjacent scan paths each account for 5% to 40% of the exposure area. For example, in Figure 3 In this embodiment, the first scanning path is scanning path L1, and the nth scanning path is L4. The areas of each path not covered by adjacent scanning paths each account for 20% of the exposure area. That is, in the entire exposure area, the weaker edge areas account for 40%, and the stronger central areas account for 60%. Figure 4 In this embodiment, the first scanning path is scanning path M1, and the nth scanning path is M3. The areas of each path not covered by adjacent scanning paths account for 20% of the exposure area. That is, in the entire exposure area, the weaker edge areas account for 40%, and the stronger middle areas account for 60%. In other embodiments, the proportion of the area that is only exposed once to the total exposure area can be adjusted as needed.

[0080] To ensure that the illumination energy per unit area at the edge of the exposure area is less than that at the center, other methods can also be used. For example, in other embodiments, the step of irradiating a local area of ​​the first doped silicon layer 200 with a laser includes:

[0081] The laser spot is used to scan along n scanning paths, where n ≥ 2. The scanning paths extend along a first direction, and the n scanning paths are spliced ​​together in a second direction. The first direction is perpendicular to the second direction. The scanning speed of the first scanning path and the nth scanning path in the second direction is less than the scanning speed of the second to (n-1)th scanning paths. In this embodiment, the n scanning paths are spliced ​​together in the second direction, meaning that adjacent scanning paths are connected without overlapping, or with only a slight overlap (e.g., less than 5% of the scanning path width). It can be understood that, with a constant laser power, a faster scanning speed means a shorter illumination time for the scanning path and a lower illumination energy per unit area; a slower scanning speed means a longer illumination time for the scanning path and a higher illumination energy per unit area. Therefore, the faster scanning speeds of the first and nth scanning paths, which are at the edge of the exposure area, and the slower scanning speeds of the second to (n-1)th scanning paths, result in lower illumination energy per unit area at the edge of the exposure area compared to the center.

[0082] Figure 5 This is a schematic diagram of various scanning paths in another embodiment of this application. For example... Figure 5 As shown, there are four scan paths in total, namely... Figure 5 The scan paths are N1, N2, N3, and N4; each scan path is connected but does not overlap. In the exposure area, multiple scan paths are arranged along the second direction. The scanning speeds of the first scan path N1 and the fourth scan path N4 are higher than those of the second scan path N2 and the third scan path N3. Therefore, the illumination energy per unit area is relatively low at the first scan path N1 and the fourth scan path N4; and relatively high at the second scan path N2 and the third scan path N3.

[0083] Optionally, the scanning speed of each scanning path is 10m / s to 100m / s, wherein the scanning speed of the first scanning path and the nth scanning path is V1, and the scanning speed of the second to the (n-1)th scanning paths is V2, where V1 = b × V2, and the value of b ranges from 1.2 to 3.

[0084] Optionally, the laser spot is a rectangular spot; further, the width of the spot in the second direction is 100μm~400μm. It should be understood that in other embodiments, the size and shape of the spot can be selected as needed, such as a circular spot. Optionally, the laser is either green or ultraviolet light, and the laser frequency is picosecond or sub-femtosecond. The laser power is 80kW~120kW.

[0085] In step S400, the first doped silicon layer 200 and the first dielectric layer 110 in the exposure area are etched using a wet etching process to obtain a first trench 210 with inclined sidewalls 211, wherein the angle between the inclined sidewalls 211 and the bottom wall of the first trench 210 is an obtuse angle.

[0086] Figure 6 This is a schematic diagram showing the first trench 210 after etching in one embodiment of this application. Figure 6 As shown, due to the uneven exposure in step S300, the edge etching depth of the exposed area is relatively shallower than the center etching depth. Therefore, the second trench 310 forms inclined sidewalls 211 on both sides spaced apart in the width direction (corresponding to the second direction of laser scanning). Figure 7 This is a scanning electron microscope (SEM) image of the inclined sidewall 211 in one embodiment of this application.

[0087] Optionally, step S400 may specifically include:

[0088] Step S410: Immerse the exposed area with the first etching solution;

[0089] Step S420: Wash the exposed area with water;

[0090] Step S430: Immerse the exposed area with the second etching solution.

[0091] Both the first etching solution and the second etching solution are alkaline solutions, with the first etching solution being more alkaline than the second etching solution.

[0092] In this embodiment, using a strongly alkaline first etching solution significantly improves etching efficiency, and the first trench 210 is basically formed after the first etching. The inner wall of the first trench 210 may be relatively rough after the first etching, but using a weakly alkaline second etching solution can refine the first trench 210, making its inner wall smooth and flat. The unexposed areas are protected by the BSG film, therefore the first doped silicon layer 200 and the first dielectric layer 110 in the unexposed areas will not be corroded.

[0093] In this embodiment, the included angle A between the inclined sidewall 211 and the bottom wall of the first groove 210 is 100°~150°, for example, the included angle A is a point value of 100°, 110°, 120°, 130°, 140° and 150° or a value between any two points.

[0094] Optionally, the exposure area is immersed in the first etching solution for 50s to 200s, and the exposure area is immersed in the second etching solution for 100s to 400s.

[0095] Optionally, the alkaline component in the first etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume percentage of the alkaline component in the first etching solution is 5% to 10%; the alkaline component in the second etching solution includes sodium hydroxide and / or potassium hydroxide, and the volume percentage of the alkaline component in the second etching solution is 5% to 10%. Further, the first etching solution may also include 0.1% to 1% of a surfactant and 1% to 5% of an oxidant by volume; the second etching solution may also include 0.1% to 1% of a surfactant by volume. The surfactant may be sodium dodecylbenzenesulfonate, and the oxidant may be sodium hypochlorite.

[0096] After etching with the first etching solution, the thickness of the BSG film on the first doped silicon layer 200 is reduced by 5nm to 20nm. After etching with the second etching solution, the thickness of the BSG film on the first doped silicon layer 200 is reduced by 5nm to 30nm. The final depth of the first trench 210 is 0.2μm to 4μm. It should be understood that the depth of the first trench 210 should be greater than the total thickness of the first dielectric layer 110, the first doped silicon layer 200, and the BSG film, so that the bottom wall of the first trench 210 is formed by the silicon substrate 100.

[0097] Since the first trench 210 in this embodiment is an inverted trapezoid (narrow at the bottom and wide at the opening), the amount of etching solution used in this embodiment is relatively small when etching to form trenches with the same opening width, thus saving costs; at the same time, it can also reduce the precision requirements for laser film opening and wet etching.

[0098] In step S500, a second dielectric layer 120 and a second doped silicon layer 300 are sequentially stacked in the first trench 210 to fill the first trench 210.

[0099] Figure 8 This is a schematic diagram illustrating the fabrication of the second dielectric layer 120 and the second doped silicon layer 300 according to one embodiment of this application. In this embodiment, the material of the second dielectric layer 120 is silicon oxide. The second dielectric layer 120 can perform surface passivation, field-effect passivation, and selective carrier transport. The specific function, principle, and fabrication method of the second dielectric layer 120 can be referred to the first dielectric layer 110, and will not be repeated here.

[0100] In this embodiment, the second doped silicon layer 300 is n-type doped polycrystalline silicon. The second doped silicon layer 300 can be prepared by chemical vapor deposition. After the second dielectric layer 120 is formed, a silicon source (such as high-purity SiH4) is introduced to grow an intrinsic amorphous silicon layer on the second dielectric layer 120. Then, the above structure is placed in a phosphorus diffusion furnace tube, and POCl3 is introduced for phosphorus diffusion to transform the intrinsic amorphous silicon layer into an n-type doped amorphous silicon layer. After that, annealing is performed to achieve recrystallization, forming an n-type doped polycrystalline silicon layer, i.e., the second doped silicon layer 300.

[0101] It should be understood that because the first trench 210 has inclined sidewalls 211, it has an open structure with a bottom width narrower than the opening width. Therefore, when depositing the second dielectric layer 120 and the second doped silicon layer 300, the second doped silicon layer 300 will not be deposited below the first doped silicon layer 200; a portion of the second doped silicon layer 300 will be deposited above the first doped silicon layer 200. This portion of the second doped silicon layer 300 above the first doped silicon layer 200 will also be removed in a subsequent step (S600), ultimately achieving complete isolation between the first doped silicon layer 200 and the second doped silicon layer 300. It should be understood that in this embodiment, "below the first doped silicon layer 200" refers to the side of the first doped silicon layer 200 closest to the silicon substrate 100.

[0102] Optionally, the intrinsic amorphous silicon layer used to fabricate the second doped silicon layer 300 has a deposition thickness of 200 nm to 400 nm, and the phosphorus doping concentration of the second doped silicon layer 300 is 3 × 10⁻⁶. 19 / cm 3 ~8×10 19 / cm 3 The sheet resistance of the first doped silicon layer 200 is 100~200 Ω / sq. It should be understood that during the fabrication of the second doped silicon layer 300, a layer of phosphosilicate glass (not shown in the figure), abbreviated as PSG, is simultaneously formed on the surface of the second doped silicon layer 300, with a thickness of 20nm~80nm. The PSG film has a certain degree of corrosion resistance and can act as a mask in subsequent wet etching.

[0103] In step S600, a portion of the second dielectric layer 120 and the second doped silicon layer 300 in contact with the inclined sidewall 211 are removed to form the second trench 310.

[0104] Figure 9 This is a schematic diagram of the fabrication of the second trench 310 in one embodiment of this application. In this embodiment, a laser can be used to irradiate the PSG film on the second doped silicon layer 300 to be removed, thereby achieving film opening; then, a wet etching process is used to remove a portion of the second dielectric layer 120 and the second doped silicon layer 300 connected to the inclined sidewall 211 to form the second trench 310. The PSG film in the area not irradiated by the laser acts as a mask, including the second doped silicon layer 300 and the second dielectric layer 120 it covers, which are not etched. It should be understood that one of the sidewalls of the second trench 310 is the inclined sidewall 211 of the first trench 210; therefore, the angle between at least one sidewall of the second trench 310 and its bottom wall is an obtuse angle.

[0105] Since the first doped silicon layer 200 does not cover the second doped silicon layer 300, when removing a portion of the second dielectric layer 120 and the second doped silicon layer 300 that is in contact with the inclined sidewall 211, the second doped silicon layer 300 that is in contact with the first doped silicon layer 200 can be easily and completely removed, leaving little residue. This improves upon the problem in the prior art where a portion of the second doped silicon layer 300 is easily left in contact with the first doped silicon layer 200. After the second trench 310 is fabricated, the first doped silicon layer 200 and the second doped silicon layer 300 are completely separated.

[0106] In addition, since the second trench 310 in this embodiment is an inverted trapezoid (narrow at the bottom and wide at the opening), less etching fluid is used in this embodiment when etching to form a trench with the same opening width, thus saving costs.

[0107] In this embodiment, the other sidewall of the second groove 310 opposite to the inclined sidewall 211 is vertical, that is, it forms an angle of approximately 90° with the bottom wall. In other optional embodiments, the other sidewall of the second groove 310 opposite to the inclined sidewall 211 can also be set to form an obtuse angle with the bottom wall, such as an obtuse angle of 100° to 150° with the bottom wall.

[0108] In step S700, passivation layers are prepared on the front and back sides of the silicon substrate 100, and a first electrode 610 connected to the first doped silicon layer 200 and a second electrode 620 connected to the second doped silicon layer 300 are fabricated.

[0109] Figure 10 This is a schematic diagram showing the passivation layer and electrode fabrication in one embodiment of this application. In this embodiment, before fabricating the passivation layer, the silicon substrate 100, on which the first doped silicon layer 200 and the second doped silicon layer 300 are deposited, can be acid-washed, and texturing can be performed on the front side of the silicon substrate 100 to form a textured surface. The textured surface can reduce light reflection loss, improve light absorption efficiency, and reduce surface recombination, thereby improving battery performance.

[0110] Optionally, the passivation layer is made of at least one of alumina, silicon oxide, silicon oxynitride, and silicon nitride. The passivation layer can be a single-layer structure (e.g., an alumina layer, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer) or a composite layer structure of multiple materials. The passivation layer can be fabricated using atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0111] Optionally, the step of preparing passivation layers on the front and back sides of the silicon substrate 100 includes: depositing a first passivation layer 400 on the front side of the silicon substrate 100; and depositing a second passivation layer 500 on the first doped silicon layer 200, the second doped silicon layer 300, and the bottom wall and inclined sidewall 211 of the second trench 310.

[0112] During electrode fabrication, a second electrode 620 can be printed on the second passivation layer 500 in the region corresponding to the second doped silicon layer 300; subsequently, a first electrode 610 is printed on the first passivation layer 400 in the region corresponding to the first doped silicon layer 200; finally, the first electrode 610 and the second electrode 620 are sintered. The final result is as follows: Figure 10 The solar cells shown should be understood as follows: Figure 10 The structure shown is only a partial cross-section of the solar cell. In this embodiment, the first electrode 610 and the second electrode 620 are grid-line structures. The materials of the first electrode 610 and the second electrode 620 can be one or more combinations of silver, aluminum, and copper.

[0113] This application also provides a solar cell, specifically a TBC cell, which can be prepared by the solar cell preparation method provided in the above embodiments.

[0114] In summary, this application provides a solar cell and its fabrication method. The solar cell fabrication method includes: obtaining a silicon substrate 100, the silicon substrate 100 having a front side and a back side; fabricating a first dielectric layer 110 and a first doped silicon layer 200 sequentially stacked on the back side of the silicon substrate 100; irradiating a local area of ​​the first doped silicon layer 200 with a laser, wherein the light energy per unit area at the edge of the exposed area is less than the light energy per unit area in the middle of the exposed area; and etching the first doped silicon layer 200 and the first dielectric layer 110 in the exposed area using a wet etching process to obtain a first trench 21 with inclined sidewalls 211. 0. The angle between the inclined sidewall 211 and the bottom wall of the first trench 210 is an obtuse angle. A second dielectric layer 120 and a second doped silicon layer 300 are sequentially stacked within the first trench 210 to fill it. A portion of the second dielectric layer 120 and the second doped silicon layer 300 connected to the inclined sidewall 211 is removed to form a second trench 310. Passivation layers are prepared on the front and back sides of the silicon substrate 100, and a first electrode 610 connected to the first doped silicon layer 200 and a second electrode 620 connected to the second doped silicon layer 300 are fabricated. In this embodiment, by controlling the energy of the laser irradiation area, the unit area irradiation energy at the edge of the exposure area is less than the unit area irradiation energy in the middle of the exposure area. Because higher light energy makes etching easier, the edges of the first doped silicon layer 200 and the first dielectric layer 110 in the exposure area are etched at a shallower depth, while the center is etched at a deeper depth. This allows the first trench 210 to have sloping sidewalls 211, and the opening width of the first trench 210 is greater than its bottom width. When the second doped silicon layer 300 is subsequently fabricated, it will not deposit beneath the first doped silicon layer 200. By fabricating the second trench 310, the second doped silicon layer 300 in contact with the first doped silicon layer 200 can be completely removed, effectively separating the two layers. This reduces minority carrier recombination and leakage channels caused by the contact between the first and second doped silicon layers 200, thus improving the performance of the solar cell. Since the opening width of the first trench 210 is greater than the bottom width, the first doped silicon layer 200 and the second doped silicon layer 300 can be effectively isolated without a deep etching depth, thereby increasing the process window, which is beneficial for future wafer thinning and reducing the precision requirements of patterning equipment, greatly reducing production costs and facilitating mass production.

[0115] The solar cells provided in this application embodiment are prepared by the above-described method and therefore have better photoelectric conversion efficiency.

[0116] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for preparing a solar cell, characterized in that, include: Obtain a silicon substrate having opposing front and back sides; A first dielectric layer and a first doped silicon layer are sequentially stacked on the back side of the silicon substrate; A laser is used to irradiate a local area of ​​the first doped silicon layer, and the light energy per unit area at the edge of the exposed area is less than the light energy per unit area in the middle of the exposed area. The first doped silicon layer and the first dielectric layer in the exposure area are etched using a wet etching process to obtain a first trench with inclined sidewalls, wherein the angle between the inclined sidewalls and the bottom wall of the first trench is an obtuse angle. A second dielectric layer and a second doped silicon layer are sequentially stacked within the first trench to fill the first trench; A portion of the second dielectric layer and the second doped silicon layer in contact with the inclined sidewall are removed to form a second trench; Passivation layers are prepared on the front and back sides of the silicon substrate, and a first electrode connected to the first doped silicon layer and a second electrode connected to the second doped silicon layer are fabricated.

2. The method for preparing a solar cell according to claim 1, characterized in that, The step of irradiating a localized region of the first doped silicon layer with a laser includes: The light spot is used to scan along n scanning paths, where n≥2. The scanning paths extend along a first direction, and the n scanning paths are arranged in a second direction. The first direction is perpendicular to the second direction, and two adjacent scanning paths partially overlap.

3. The method for preparing a solar cell according to claim 2, characterized in that, The width W1 of the scanning path in the second direction and the width W2 of the overlapping area of ​​two adjacent scanning paths in the second direction satisfy the relationship: W2=a×W1, where a ranges from 0.2 to 0.

8.

4. The method for preparing a solar cell according to claim 2, characterized in that, In the first and nth scan paths in the second direction, the areas not covered by adjacent scan paths each account for 5% to 40% of the exposure area.

5. The method for preparing a solar cell according to claim 2, characterized in that, The light spot is a rectangular light spot.

6. The method for preparing a solar cell according to claim 2, characterized in that, The width of the light spot in the second direction is 100μm~400μm.

7. The method for preparing a solar cell according to claim 1, characterized in that, The step of irradiating a localized region of the first doped silicon layer with a laser includes: The light spot is used to scan along n scanning paths, where n≥2. The scanning paths extend along a first direction, and the n scanning paths are spliced ​​together in a second direction. The first direction is perpendicular to the second direction. The scanning speed of the first scanning path and the nth scanning path in the second direction is greater than the scanning speed of the second to the (n-1)th scanning paths.

8. The method for preparing a solar cell according to any one of claims 1-7, characterized in that, The step of etching the first doped silicon layer and the first dielectric layer in the exposed area using a wet etching process includes: The exposed area is immersed in a first etching solution; The exposed area is then washed with water; The exposed area is immersed in a second etching solution; Both the first etching solution and the second etching solution are alkaline solutions, with the first etching solution being more alkaline than the second etching solution.

9. The method for preparing a solar cell according to claim 8, characterized in that, The exposure area is immersed in the first etching solution for 50s to 200s, and the exposure area is immersed in the second etching solution for 100s to 400s.

10. The method for preparing a solar cell according to claim 8, characterized in that, The alkaline components in the first etching solution include sodium hydroxide and / or potassium hydroxide, and the volume percentage of the alkaline components in the first etching solution is 5% to 10%; the alkaline components in the second etching solution include sodium hydroxide and / or potassium hydroxide, and the volume percentage of the alkaline components in the second etching solution is 5% to 10%.

11. The method for preparing a solar cell according to any one of claims 1-7, characterized in that, The angle between the inclined sidewall and the bottom wall of the first trench is 100°~150°.

12. The method for preparing a solar cell according to any one of claims 1-7, characterized in that, The first doped silicon layer is p-type doped, and the second doped silicon layer is n-type doped.

13. The method for preparing a solar cell according to any one of claims 1-7, characterized in that, The materials of the first dielectric layer and the second dielectric layer are silicon oxide.

14. The method for preparing a solar cell according to any one of claims 1-7, characterized in that, The step of fabricating passivation layers on the front and back sides of the silicon substrate includes: A first passivation layer is deposited on the front side of the silicon substrate; A second passivation layer is deposited on the first doped silicon layer, the second doped silicon layer, the bottom wall of the second trench, and the inclined sidewall.

15. The method for preparing a solar cell according to any one of claims 1-7, characterized in that, The material of the passivation layer is selected from at least one of aluminum oxide, silicon oxide, silicon oxynitride, and silicon nitride.

16. A solar cell, characterized in that, The solar cell is prepared by any one of claims 1-15.

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