Crystalline silicon solar cell and perovskite / crystalline silicon laminated solar cell

Abstract

The invention provides a crystalline silicon solar cell and a perovskite / crystalline silicon laminated solar cell, and belongs to the technical field of solar cells. The crystalline silicon solar cell comprises a cell body, the surface of the cell body is provided with a suede structure, the suede structure comprises a plurality of first pyramids, and each first pyramid comprises a first tower bottom and a first tower top which are arranged in the direction away from the surface of the cell body; and gaps exist between the first tower bottom boundaries of at least part of adjacent first pyramids in the plurality of first pyramids. The crystalline silicon solar cell or the perovskite / crystalline silicon laminated solar cell is based on the improvement of the textured structure, has better light utilization rate and passivation effect, and is beneficial to improving the cell performance.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a crystalline silicon solar cell and a perovskite / crystalline silicon stacked solar cell. Background Art

[0002] With the advancement of solar cell physics technology, crystalline silicon solar cells have become the leading photovoltaic cell product. For traditional crystalline silicon solar cells, wet texturing is an essential step in the manufacturing process. The pyramids on the textured surface, with an average size of approximately 2μm, provide excellent light trapping, thereby improving light utilization. However, depositing uniform, high-quality films on a textured surface with these larger pyramids, around 2μm in size, presents certain challenges.

[0003] This is particularly true for perovskite / crystalline silicon tandem solar cells. The pyramids on the traditional velvet structure of crystalline silicon solar cells, which serve as the bottom cell, are not conducive to the growth of high-quality perovskite thin films and make it difficult to form good tandem interface contact. To ensure that the perovskite can better cover the pyramid structure in the crystalline silicon solar cell, higher requirements are placed on the morphology and size of the pyramid structure in the crystalline silicon solar cell, thereby balancing the improvement of light utilization efficiency and interface contact performance. Summary of the Invention

[0004] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a crystalline silicon solar cell and a perovskite / crystalline silicon tandem solar cell.

[0005] According to an embodiment of one aspect of the present application, a crystalline silicon solar cell is provided, comprising: a cell body, a surface of the cell body having a velvet structure, the velvet structure comprising a plurality of first pyramids, the first pyramids comprising a first tower bottom and a first tower top arranged in a direction away from the surface of the cell body; wherein gaps exist between boundaries of the first tower bottoms of at least some adjacent first pyramids in the plurality of first pyramids.

[0006] According to the embodiments of the present application, the velvet structure of the crystalline silicon solar cell is improved, and a gap is formed between adjacent first pyramids in the velvet structure. The existence of the gap is beneficial to reducing the velvet light reflectivity by increasing the number of light reflections, thereby improving light utilization. As a result, there is no need to use pyramids of excessive size, and both the light trapping effect and the improvement of the film quality can be taken into account.

[0007] According to an embodiment of another aspect of the present application, a perovskite / crystalline silicon tandem solar cell is provided, comprising: a crystalline silicon bottom cell having the structure of the above crystalline silicon solar cell; and a perovskite top cell located on the velvet structure of the crystalline silicon bottom cell.

[0008] According to the embodiments of the present application, when the crystalline silicon solar cell of the present application is used as the bottom cell and a stacked structure of a perovskite top cell is formed on its velvet structure, the stress release at the bottom of the pyramid of the perovskite layer during the crystallization growth process can be better alleviated, thereby forming a good interface contact, improving the film formation quality of the perovskite layer, and further significantly improving the cell performance of the perovskite / crystalline silicon stacked solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0010] Figure 1 This is a schematic structural diagram of a crystalline silicon solar cell according to an embodiment of the present application;

[0011] Figure 2 This is a scanning electron microscope (SEM) top view of the traditional velvet structure in this application;

[0012] Figure 3 This is a SEM top view of the velvet structure in the cell body of the crystalline silicon solar cell according to an embodiment of the present application;

[0013] Figure 4 This is a SEM cross-sectional view of a velvet structure in a cell body of a crystalline silicon solar cell according to an embodiment of the present application;

[0014] Figure 5 A schematic structural diagram of a tunneling oxide passivation contact (TOPCon) cell according to an exemplary embodiment of the present application;

[0015] Figure 6 A schematic structural diagram of a double-sided heterojunction (HJT) battery according to another exemplary embodiment of the present application;

[0016] Figure 7 This is a schematic structural diagram of a perovskite / crystalline silicon tandem solar cell according to an embodiment of the present application;

[0017] Figure 8 This is a schematic structural diagram of a perovskite / crystalline silicon tandem solar cell according to another exemplary embodiment of the present application;

[0018] Figure 9 These are SEM images of the textured structures in the crystalline silicon bottom cells of different embodiments of the present application, wherein a to d are the textured structures of embodiments 1 to 4 respectively;

[0019] Figure 10 These are SEM cross-sectional images of the perovskite layer in the perovskite top cell according to different embodiments of the present application, wherein a to d are cross-sectional images of the perovskite layer according to embodiments 1 to 4, respectively;

[0020] Figure 11This is an SEM image of the stacked solar cell of Comparative Example 1 of the present application, wherein a is the suede structure and b is the cross section of the perovskite layer. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of this application more clear, this application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] In the detailed description that follows, for ease of explanation, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may be implemented without these specific details. Furthermore, in the following description, descriptions of known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present application.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The term "comprising" used herein indicates the existence of features, steps, operations, but does not exclude the existence or addition of one or more other features.

[0024] When expressions such as “at least one of A, B, and C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, and C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.). When expressions such as “at least one of A, B, or C, etc.” are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, “a system having at least one of A, B, or C” should include but is not limited to systems having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, and C, etc.).

[0025] References to the relative position between two components (e.g., layers or regions) herein, such as “above,” “upper,” or “above,” may refer to the two components being in direct contact, or may refer to the two components being in indirect contact. Similarly, references to the relative position between two components herein, such as “under,” “lower,” or “below,” may refer to the two components being in direct contact, or may refer to the two components being in indirect contact. For example, when one component (e.g., a layer or region) is referred to as being “on another component,” it may be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as being “directly on another component,” there is no component between the two. In addition, when one component is referred to as being “on another component,” the two have a top-down relationship in a top-down direction, and the component may be above or below the other component, so that the top-down relationship depends on the orientation of the device.

[0026] As a key feature of crystalline silicon solar cells, the velvet structure must balance light trapping with uniform thin film deposition, placing high demands on its morphology and dimensions. Optimizing the velvet structure involves rounding the tops and bottoms of the pyramids to improve the quality of film deposition. However, experiments have shown that rounding significantly enhances optical reflectance, resulting in lower light utilization and, consequently, lower short-circuit current (Jsc) in crystalline silicon solar cells.

[0027] Moreover, it was further discovered that in the perovskite / crystalline silicon tandem solar cells, the rounded velvet structure did not show an obvious effect of alleviating the stress release during the crystallization of the perovskite layer, resulting in more pores at the interface between the perovskite layer and the velvet structure, which in turn led to poor interface contact and reduced the open circuit voltage and fill factor of the tandem solar cell.

[0028] In the process of realizing the concept of this application, it was found that this application can form gaps between adjacent pyramids in the velvet structure by optimizing the velvet making process, which is beneficial to reducing the velvet light reflectivity by increasing the number of light reflections, thereby improving light utilization. Furthermore, a smaller-sized pyramid or platform area can be set in the gap. When a film layer is deposited on the velvet structure, the stress caused by the overly sharp bottom of the tower can be relieved or released, which is beneficial to forming a good interface contact between the film layer and the velvet structure. Therefore, the velvet structure is applied to crystalline silicon solar cells or perovskite / crystalline silicon stacked solar cells, which has a significant improvement effect on battery performance.

[0029] Specifically, according to an embodiment of one aspect of the present application, a crystalline silicon solar cell is provided. Figure 1This is a schematic structural diagram of a crystalline silicon solar cell according to an embodiment of the present application. Figure 1 As shown, the crystalline silicon solar cell includes a cell body 1, wherein:

[0030] The surface of the battery body 1 has a velvet structure 11, which includes a plurality of first pyramids 111. The first pyramids 111 include a first tower bottom 1111 and a first tower top 1112 arranged in a direction away from the surface of the battery body 1; wherein, gaps 1113 are formed between the boundaries of the first tower bottoms 1111 of at least some adjacent first pyramids 111 among the plurality of first pyramids 111.

[0031] According to the embodiments of the present application, the velvet structure of the crystalline silicon solar cell is improved, and a gap is formed between adjacent first pyramids in the velvet structure. The gap is conducive to reducing the velvet light reflectivity by increasing the number of light reflections, thereby improving light utilization. As a result, there is no need to use pyramids of excessive size, and both the light trapping effect and the improvement of the film quality can be taken into account.

[0032] According to an embodiment of the present application, the velvet structure 11 of the present application may be located in at least a partial area of the surface of the battery body 1, that is, it may be located in the entire surface of the battery body 1 or in a partial area of the surface of the battery body 1. In order to form the velvet structure 11, the battery body 1 may include a silicon substrate 1, and the same or substantially the same velvet structure 12 is formed on the silicon substrate 1. Specifically, at least a partial area of the surface of the silicon substrate 1 may be subjected to a velvet treatment, and then, after conformally depositing a film layer, such as a semiconductor layer 2, on the velvet structure 12 of the silicon substrate 1, a velvet structure 11 including a plurality of first pyramids 111 may be observed, as shown in FIG. Figure 1 However, the present invention is not limited thereto, and the textured structure 11 can be directly formed on the silicon substrate 1 . In this case, the silicon substrate 1 can be doped internally to form a diffusion layer on the surface of the silicon substrate 1 as the semiconductor layer 2 .

[0033] According to an embodiment of the present application, the material of the silicon substrate 1 can be an N-type, P-type, or intrinsic crystalline silicon substrate, for example, a semiconductor material selected from the group consisting of single crystal silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type single crystal silicon substrate. The conversion efficiency of cells based on single crystal silicon substrates is higher than that of other types, such as polycrystalline silicon cells. By introducing donor impurities such as Group VA elements such as phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, an N-type crystalline silicon substrate is obtained, while by introducing acceptor impurities such as Group IIIA elements such as boron (B), aluminum (Al), or gallium (Ga), a P-type crystalline silicon substrate is obtained.

[0034] According to the embodiment of the present application, the surface of the battery body 1 having a suede structure can be the front or back of the battery, without limitation. Generally speaking, the front of the battery serves as the light-receiving surface and the back serves as the backlight surface, or the battery can also receive light on both sides, with both the front and back serving as light-receiving surfaces.

[0035] According to an embodiment of the present application, the textured structure 11 of the present application may be located on at least a portion of the surface of the battery body 1, that is, may be located on the entire surface of the battery body 1 or on a portion of the surface of the battery body 1. The first pyramid 111 may be a pyramidal structure that protrudes in a direction away from the surface of the battery body 1. Of course, this is not limited to this, and may also be, for example, a conical structure, a truncated pyramid structure, etc.

[0036] Further optionally, the gap 1113 between adjacent first pyramids 111 may represent a small space between adjacent first pyramids 111, unlike in a conventional suede structure where there is no gap between the bottom edges of the pyramids, or the gap is less than 10 nm, making it difficult to observe. Furthermore, the "gap" also includes a smaller lateral dimension than the bottom edges of the first pyramids on either side of the gap.

[0037] In order to further understand the difference between the suede structure 11 of the present application and the traditional suede structure, Figure 2 This is a scanning electron microscope (SEM) top view of the traditional velvet structure in this application; Figure 3 This is a SEM top view of the velvet structure in the cell body of the crystalline silicon solar cell according to an embodiment of the present application; Figure 2 As shown in FIG, it is difficult to observe that there are gaps between the bottom boundaries of adjacent pyramids on the traditional velvet structure; Figure 3 As shown, it can be easily observed on the textured structure 11 provided in the present application that there is a gap 1113 between the boundaries of the first pyramid bottoms 1111 of adjacent first pyramids 111 .

[0038] According to an embodiment of the present application, the ratio between the width of gap 1113 and the lateral dimension of the first tower bottom 1111 is 0.04 to 0.8, for example, 0.04, 0.08, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, etc. A suitable ratio between the width and the lateral dimension of gap 1113 is beneficial for reducing the light reflectivity of the suede structure. At the same time, gap 1113 at the first tower bottom 1111 can alleviate stress release of the film layer on the suede structure during the deposition process, thereby improving the deposition of the film layer on the suede structure.

[0039] like Figure 3As shown, the width of gap 1113 can be the shortest distance between the boundary lines of the first tower bottoms 1111 located on both sides of gap 1113. For example, if the boundaries of adjacent first tower bottoms 1111 are substantially parallel, the width of gap 1113 can be the distance L1 between the two boundary lines. Alternatively, if the boundaries of adjacent first tower bottoms 1111 are non-parallel, the width of gap 1113 can be the minimum value L2 of the distance from any point on one boundary line to the other boundary line. The lateral dimension of first tower bottom 1111 can be the dimension of first tower bottom 1111 in the direction in which the surface of battery body 1 extends, which can be, for example, the side length or diagonal length of first tower bottom 1111.

[0040] Exemplarily, based on the SEM top view of the velvet structure, the size of the gap 1113 between the first pyramid 111 and the boundary of the first tower bottom 1111 of the adjacent first pyramid 111 is measured, and the width of the gap 1113 can be 20~80nm, for example, it can be 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, etc.; and / or, the lateral dimension of the first tower bottom 1111 is 0.3~1.2μm, for example, it can be 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, 1.0μm, 1.1μm, 1.2μm, etc.

[0041] Further optionally, Figure 4 This is a SEM cross-sectional view of the velvet structure in the cell body of the crystalline silicon solar cell according to an embodiment of the present application; Figure 4 As shown in the SEM cross-sectional view of the velvet structure, the height of the first pyramid 111 from the first pyramid base 1111 to the first pyramid top 1112 is 0.4-0.8 μm, and can be, for example, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, etc. A suitable height for the first pyramid 111 is beneficial for balancing uniformity in film deposition and light trapping. Furthermore, the smaller pyramid size relative to existing dimensions further facilitates repeated refraction of light, further dispersing the light within a unit area and thereby absorbing it through repeated refraction. Furthermore, this embodiment does not solely consider reducing the size of the pyramids to enhance light trapping and absorption. Furthermore, by increasing the appropriate gaps between the pyramids while ensuring the number of pyramids, this gap is increased, ensuring that the functional film layer on the battery body is properly filled and encapsulated, allowing the functional film layer to fully utilize its performance. Here, the “height” is the distance between the bottom 1111 of the first tower and the top 1112 of the first tower in the thickness direction of the battery body I.

[0042] According to the embodiment of the present application, Figure 1 and Figure 3 As shown, the velvet structure 11 may further include a plurality of second pyramids 112, each located in a gap between adjacent first pyramids 111; wherein the second pyramid 112 includes a second tower bottom 1121 and a second tower top 1122 arranged in a direction away from the surface of the battery body 1; the ratio of the lateral dimension of the second tower bottom 1122 to the lateral dimension of the first tower bottom 1121 is 0.008-0.65, for example, 0.008, 0.01, 0.05, 0.075, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, etc., and may further be 0.05-0.5. Here, the "lateral dimension" of the second tower bottom 1122 has the same meaning as described above and will not be repeated here.

[0043] With such a configuration, through the cooperation between the first pyramid 111 and the second pyramid 112 having a large size difference, on the one hand, the number of reflections of the light incident on the velvet structure 11 can be increased, thereby improving the light utilization efficiency. On the other hand, the second pyramid 112 is located between the first tower bottoms 1111 of adjacent first pyramids 111. Compared with not setting the second pyramid 112 or the traditional velvet structure, it is more conducive to releasing stress when depositing a film layer on the velvet structure 11, thereby improving the film deposition quality and interface contact.

[0044] For example, based on an SEM top view of the textured structure, the dimensions of the second pyramid 112 are measured, and the lateral dimension of the second pyramid base 1121 of the second pyramid 112 is 10-190 nm, for example, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 190 nm, etc. Setting the dimensions of the second pyramid 112 within the above range facilitates stress relief at the first pyramid base 1111 of the first pyramid 111 during film deposition. Furthermore, a second pyramid 112 of appropriate size improves light utilization by increasing the number of light reflections.

[0045] According to the embodiment of the present application, Figure 1 and Figure 3 As shown, the number of the second pyramids 112 on at least part of the gap 1113 is greater than or equal to 1. For example, as Figure 3As shown, the dotted circle shows the case where the number of second pyramids 112 in the gap 1113 is 1, and the dotted rectangle shows the case where the number of second pyramids 112 in the gap 1113 is 2. However, the present invention is not limited thereto, and the number of second pyramids 112 in the gap 1113 can also be 3, 4, 5, 6, and so on. An appropriate number of second pyramids 112 is beneficial for improving light utilization efficiency and film deposition quality in the textured structure.

[0046] Furthermore, based on the textured structure 11 of the battery described above, a platform region 1114 exists between the bottom boundaries of the first pyramids of at least some adjacent first pyramids in the plurality of first pyramids, and the platform region 1114 constitutes at least a portion of the gap 1113. With this arrangement, since the silicon substrate 1 has the same or substantially the same textured structure 12, and accordingly, the platform region 1114 also exists, this allows for the stress caused by the overly sharp bottoms of the pyramids to be alleviated or released when a film layer is deposited on the textured structure 12 of the silicon substrate 1, thereby facilitating the formation of a good interface contact between the film layer and the textured structure.

[0047] Furthermore, there is a gap 1113 between the first pyramid bottoms 1111 of adjacent first pyramids 111, and at least part of the gap 1113 can be provided with the gap 1113 and the second pyramid 112. The coexistence of the gap 1113 and the second pyramid 112 is more conducive to the simultaneous improvement of light utilization and film deposition quality.

[0048] In order to obtain the above-mentioned velvet structure, the surface of the cleaned and polished silicon wafer can be treated with a velveting solution. The formula of the velveting solution is 1 part by mass of the additive, 3 to 6 parts by mass (for example, 3 parts by mass, 3.5 parts by mass, 4 parts by mass, 4.5 parts by mass, 5 parts by mass, 5.5 parts by mass, 6 parts by mass, etc.) of alkali, 85 to 90 parts by mass (for example, 85 parts by mass, 86 parts by mass, 87 parts by mass, 88 parts by mass, 89 parts by mass, 90 parts by mass, etc.) of water, the velveting temperature is 70°C-80°C (for example, 70°C, 71°C, 72°C, 73°C, 74°C, 75°C, 76°C, 77°C, 78°C, 79°C, 80°C, etc.), and the time is 470 to 490 s (for example, it can be 470°C, 472°C, 474°C, 476°C, 478°C, 480°C, 482°C, 484°C, 486°C, 488°C, 490°C, etc.).

[0049] According to the embodiments of the present application, the above-mentioned velvet structure of the present application can be widely used in various types of crystalline silicon solar cells, such as Passivated Emitter Rear Cell (PERC) cells, Tunnel Oxide Passivating Contacts (TOPCon), Heterojunction with Intrinsic Thin-layer (HJT), Interdigitated back-contact cell (IBC), Honeycomb-shaped back-contact cell (HBC), hybrid back contact cells such as TBC (TopCon-Back Contact)-HJT combined hybrid cells, etc.

[0050] At this time, Figure 1 As shown, the battery body 1 may further include a semiconductor layer 2, which is located on or within the surface of the silicon substrate 1. The semiconductor layer 2 may be an N-type and / or P-type doped semiconductor layer, and its material may include at least one semiconductor material selected from the group consisting of single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.

[0051] By introducing donor impurities such as VA group elements such as phosphorus (P), arsenic (As) or antimony (Sb) into these semiconductor materials, an N-type doped semiconductor layer is obtained, or by introducing acceptor impurities such as IIIA group elements such as boron (B), aluminum (Al) or gallium (Ga) into these semiconductor materials, a P-type doped semiconductor layer is obtained.

[0052] As an optional embodiment, the semiconductor layer 2 can be formed on the silicon substrate 1 by chemical vapor deposition. In this case, based on the velvet structure 12 of the silicon substrate 1, the semiconductor layer 2 can be deposited on the velvet structure 12 of the silicon substrate 1 with high quality, thereby obtaining a velvet structure 11 that is identical or substantially identical to the velvet structure 12 of the silicon substrate 1. As another optional embodiment, the semiconductor layer 2 can also be a diffusion layer formed on the surface of the silicon substrate 1 by boron diffusion or phosphorus diffusion.

[0053] Further optionally, the battery body 1 may further include a passivation layer (not shown in the figure). In one embodiment, when the semiconductor layer 2 is deposited on the textured structure 12 of the silicon substrate 1, the passivation layer is located between the silicon substrate 1 and the semiconductor layer 2. In another embodiment, when the semiconductor layer 2 is deposited on the surface of the silicon substrate 1 having the textured structure 12, the passivation layer is located on the surface of the semiconductor layer 2, that is, in direct contact with the surface of the silicon substrate 1.

[0054] Optionally, the passivation layer may be composed of one or more layers, and its optional materials may include one or more of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, silicon carbide, and amorphous silicon.

[0055] In both of the above-mentioned optional embodiments, the passivation layer plays the role of passivating the dangling bonds on the surface of the silicon substrate 1. In this case, the textured structure 12 based on the silicon substrate 1 is conducive to improving the film formation quality of the passivation layer, so that the passivation layer forms a good coating on the surface of the silicon substrate 1, thereby improving the passivation effect of the passivation layer.

[0056] Further optionally, the crystalline silicon solar cell may further include an electrode (not shown in the figure), which is located on the surface of the cell body 1 and further electrically contacts the semiconductor layer 2 in the cell body 1. In this case, when the semiconductor layer 2 is located within or on the surface of the velvet structure 12, the electrode directly contacts the velvet structure 12 of the silicon substrate 1 or contacts the velvet structure 11 of the semiconductor layer 2, which is beneficial for improving the contact interface between the electrode and the cell body 1, thereby increasing the contact tension of the electrode.

[0057] Furthermore, the electrodes can be made of copper, silver-coated copper, aluminum, or silver, and can be produced by printing, electrodeposition, thermal evaporation, or other methods. For example, a metal slurry can be printed onto the battery body 1, and then the metal slurry is sintered to achieve metallization. Printing methods can include, for example, screen printing or inkjet printing, preferably the more cost-effective screen printing method. However, this is not limiting. For example, metal electrodes can be deposited on the battery body 1 by thermal evaporation, and then the electrodes are sintered.

[0058] For ease of understanding, illustratively, taking a TOPCon cell as an example, the applicability of a cell body with a suede structure in a crystalline silicon solar cell is described. Figure 5 Schematic diagram of the structure of a tunneling oxide passivation contact (TOPCon) cell according to an exemplary embodiment of the present application, as shown in FIG. Figure 5 As shown, the crystalline silicon solar cell includes a cell body I and an electrode II, and the electrode II is located on the surface of the cell body I.

[0059] More specifically, the battery body 1 includes a silicon substrate 1, a semiconductor layer 2, and a passivation layer 3. The silicon substrate 1 includes a first surface 1a and a second surface 1b, each of which has a velvet structure 12. However, this is not limiting, and either surface 1a or the other surface 1b may have the velvet structure 12. The semiconductor layer 2 includes a first semiconductor layer 21 and a second semiconductor layer 22, with the first semiconductor layer 21 located on the first surface 1a of the silicon substrate 1 and the second semiconductor layer 22 located on the second surface 1b of the silicon substrate 1. The passivation layer 3 includes a first passivation layer 31 and a second passivation layer 32, with the first passivation layer 31 located on a surface of the first semiconductor layer 21 away from the silicon substrate 1, and the second passivation layer 31 located between the silicon substrate 1 and the second semiconductor layer 22.

[0060] Furthermore, the first semiconductor layer 21 can be a P-type diffusion layer obtained by inward doping on the silicon substrate 1 through a boron diffusion process; the second semiconductor layer 22 can be an N-type doped polysilicon layer produced by low-pressure chemical vapor deposition (LPCVD). The first passivation layer 31 can be a stacked film of aluminum oxide and silicon nitride. An aluminum oxide passivation layer can be first produced by ALD (atomic layer deposition), followed by one or more silicon nitride layers formed thereon by PECVD (plasma chemical vapor deposition). The second passivation layer 32 can be a silicon dioxide layer produced by LPCVD. The second passivation layer 32 and the second semiconductor layer 22 form a tunneling oxide passivation contact structure.

[0061] At this point, because the first surface 1a and the second surface 1b of the silicon substrate 1 are textured throughout to form a textured structure 12, and a film layer is conformally deposited on the textured structure 12, both surfaces of the battery body 1 also have a textured structure 11, which helps improve light utilization. Furthermore, a first passivation layer 31 and a second passivation layer 32 of high film quality are deposited on the textured structures of the first surface 1a and the second surface 1b, respectively, to coat the surface of the silicon substrate 1, thereby improving the passivation effect.

[0062] Optionally, the cell body 1 may further include a passivation anti-reflection layer 4 located on the surface of the second semiconductor layer 22 away from the silicon substrate 1. The passivation anti-reflection layer 4 can protect and passivate the underlying silicon substrate or functional layers, such as the second semiconductor layer 22, and reduce the reflection of light incident on the second surface 1b. The passivation anti-reflection layer 4 can be a single layer formed of silicon dioxide, aluminum dioxide, silicon nitride, or silicon oxynitride, or a laminated layer comprising one or more of these materials.

[0063] Furthermore, the electrode II may include a first electrode IIA and a second electrode IIB, wherein the first electrode IIA passes through the first passivation layer 31 to contact the first semiconductor layer 21, and the second electrode IIB passes through the passivation anti-reflection layer 4 to contact the second semiconductor layer 22. In this case, since the first electrode IIA contacts the first surface 1a of the silicon substrate 1, the textured structure 12 on the first surface 1a improves the contact performance between the first electrode IIA and the battery body I, thereby increasing the contact tension of the first electrode IIA. The second electrode IIB contacts the surface of the second semiconductor layer 22 away from the silicon substrate 1. The textured structure 11 on the surface of the second semiconductor layer 22 improves the contact performance between the second electrode IIB and the battery body I, thereby increasing the contact tension of the second electrode IIB.

[0064] For example, the crystalline silicon solar cell may also be a HJT cell. Figure 6 FIG. 1 is a schematic structural diagram of a double-sided heterojunction (HJT) battery according to another exemplary embodiment of the present invention; FIG. Figure 6 As shown, the main difference between this HJT cell and the TOPCon cell is that the first semiconductor layer 21 can be a P-type doped amorphous silicon layer prepared by plasma chemical vapor deposition (PECVD), and the second semiconductor layer 22 can be an N-type doped amorphous silicon layer prepared by PECVD; the first passivation layer 31 is located between the silicon substrate 1 and the first semiconductor layer 21, and the second passivation layer 31 is located between the silicon substrate 1 and the second semiconductor layer 22. The first passivation layer 31 and the second passivation layer 32 can each be an intrinsic amorphous silicon layer prepared by PECVD. In this case, a heterojunction contact structure is formed between the first passivation layer 31 and the second semiconductor layer 21, and between the second passivation layer 32 and the second semiconductor layer 22. Similarly, the provision of the velvet structure 12 on the first surface 1a and the second surface 1b of the silicon substrate 1 allows the velvet structure 11 to be conformally formed on the surface of the battery body 1, which can take into account both the improvement of light utilization efficiency and the improvement of passivation effect.

[0065] Further optionally, the cell body I of the HJT cell may further include a first transparent conductive layer 51 and a second transparent conductive layer 52, wherein the first transparent conductive layer 51 is located on a surface of the first semiconductor layer 21 away from the silicon substrate 1, and the second transparent conductive layer 52 is located on a surface of the second semiconductor layer 22 away from the silicon substrate 1. In this case, the first electrode 11A may be located on the first transparent conductive layer 51, and the second electrode 11B may be located on the second transparent conductive layer 52.

[0066] The above example uses a bifacial cell as an example, but is not limited thereto. It is also applicable to back-contact cells. The main difference is that the electrodes II are both disposed on the back of the cell body I to effectively reduce the light-shielding area of the light-receiving surface. Specifically, the front of the cell body can be the light-receiving surface, and the back of the cell body can be the backlight surface. In this case, a first semiconductor layer 21 and a second semiconductor layer 22 are disposed on the back of the cell body, each extending along a first direction and alternately distributed along a second direction intersecting the first direction on the back of the cell body. In this case, a velvet structure 11 can also be disposed on both the front and back of the cell body I to achieve both improved light utilization and passivation effects.

[0067] The above describes in detail the applicability of the velvet structure in crystalline silicon solar cells, but is not limited to this. The above-mentioned velvet structure of the present application, when applied to perovskite / crystalline silicon tandem solar cells, not only exhibits a lower optical reflectivity, which is beneficial to improving the cell performance of the tandem solar cell, such as short-circuit current (Jsc), but also further, it is found that it has a particularly significant improvement on the crystallization effect of the perovskite layer, which can better alleviate the release of stress during the crystallization growth of the perovskite layer, thereby forming a good silicon / perovskite interface contact.

[0068] Specifically, according to another embodiment of the present application, a perovskite / crystalline silicon tandem solar cell is provided. Figure 7 This is a schematic structural diagram of a perovskite / crystalline silicon tandem solar cell according to an embodiment of the present application. Figure 7 As shown, the stacked solar cell may include a crystalline silicon bottom cell 10 and a perovskite top cell 20 , wherein: the crystalline silicon bottom cell 10 has the structure of the above-mentioned crystalline silicon solar cell; the perovskite top cell 20 is located on the velvet structure of the crystalline silicon bottom cell 10 .

[0069] According to an embodiment of the present application, more specifically, a crystalline silicon bottom cell 10 may include a cell body I and an electrode II located on the cell body I. The surface of the cell body I of the crystalline silicon bottom cell 10, which is adjacent to the perovskite top cell 20, has a textured structure. Since the specific configuration of the textured structure of the crystalline silicon bottom cell 10 has been described above, it will not be repeated here.

[0070] According to the embodiments of the present application, since the crystalline silicon bottom cell 10 has the structure of the above-mentioned crystalline silicon solar cell, that is, the crystalline silicon bottom cell 10 has a textured structure 11, it is beneficial to reduce the light reflectivity of the tandem cell, thereby improving the cell performance of the tandem solar cell, such as the short-circuit current (Jsc). In addition, the perovskite top cell 20 is formed on the crystalline silicon bottom cell 10. During the conformal preparation process of the perovskite top cell 20, the textured structure 11 can alleviate or release the stress generated during the crystal growth of the perovskite layer, thereby forming a good silicon / perovskite interface contact, thereby improving the cell performance of the perovskite / crystalline silicon tandem solar cell.

[0071] According to an embodiment of the present application, the tandem solar cell provided herein may be a two-terminal tandem cell or a three-terminal tandem cell. For example, the crystalline silicon bottom cell 10 may be a PERC cell, a TOPCon cell, or an HJT cell, etc. In this case, the crystalline silicon bottom cell 10 and the perovskite top cell 20 may form a two-terminal tandem cell. Alternatively, for example, the crystalline silicon bottom cell 10 may be an IBC cell, an HBC cell, or a hybrid back contact cell, such as a hybrid cell combining TBC (TopCon-Back Contact) and HJT, etc. In this case, the crystalline silicon bottom cell 10 and the perovskite top cell 20 may form a three-terminal tandem cell.

[0072] According to the embodiment of the present application, Figure 7 As shown, the perovskite top cell 20 can be one of an inorganic perovskite cell and an organic-inorganic hybrid perovskite cell, and can include another cell body III and an electrode IV located on the other cell body III. In the direction away from the crystalline silicon bottom cell 10, the cell body III of the perovskite top cell 20 mainly includes a first transport layer, a perovskite layer, a second transport layer, and a transparent electrode layer. The first transport layer is conformally prepared on the textured structure of the crystalline silicon bottom cell 10.

[0073] According to the embodiments of the present application, the thickness of the perovskite layer is 0.4 to 0.7 μm, for example, it can be 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, etc. The thickness of the perovskite layer here is the thickness from the surface of the perovskite layer to the top of the pyramid on the surface of the crystalline silicon bottom cell 10. Usually, in order to obtain a higher quality perovskite layer, its thickness needs to be more than 1 μm. However, based on the aforementioned velvet structure, the present application does not need to prepare an overly thick perovskite layer, and can meet the thickness requirement for achieving a better photoelectric conversion effect.

[0074] Furthermore, the perovskite layer of the present invention may comprise perovskite grains extending through the thickness of the perovskite layer. In this case, the perovskite layer exhibits poorly observable grain boundaries using SEM measurements and lacks significant voids at the perovskite / silicon interface, demonstrating superior crystallization quality and interface contact quality.

[0075] According to the embodiments of the present application, the perovskite layer can be formed by spin coating a perovskite precursor solution, followed by heating and annealing. Of course, this is not limited to this, and the film can also be formed by a dry method or a dry-wet hybrid method. Since the selected film formation methods are well known in the art, they are not listed here one by one.

[0076] According to an embodiment of the present application, one of the first transport layer and the second transport layer includes an electron transport layer, and the other includes a hole transport layer. Exemplarily, the first transport layer may include an electron transport layer, and the second transport layer may include a hole transport layer. In this case, the perovskite top cell 20 is a nip positive perovskite cell structure; or, the first transport layer may include a hole transport layer, and the second transport layer may include an electron transport layer. In this case, the perovskite top cell 20 is a pin inverted perovskite cell structure.

[0077] Alternatively, the electron transport layer may include at least one of tin oxide (SnO2), titanium dioxide (TiO2), C60, fullerenes, and their derivatives, including PCBM. For example, a C60 electron transport layer can be deposited using thermal evaporation to a thickness of 15-20 nm. A tin oxide electron transport layer can be deposited using atomic layer deposition (ALD) to a thickness of 15-20 nm.

[0078] The hole transport layer may include at least one of 2-(9H-carbazol-9-yl)ethyl)phosphonic acid (2PACz), 4-(3,6-dimethyl-9H-carbazol-9-yl)butyl]phosphonic acid (Me-4PACz), 2-(3,6-dimethoxy-9H-carbazol-9-yl)ethyl]phosphonic acid (MeO-2PACz), 6-(3,6-dimethoxy-9H-carbazol-9-yl)hexyl]phosphonic acid (MeO-6PACz), poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine] (PTAA), 2,2',7,7'-tetrakis[N,N-di(4-methoxyphenyl)amino]-9,9'-spirobifluorene (spiro-OMeTAD), nickel oxide (NiOx), or cuprous thiocyanate (CuSCN). The hole transport layer can be prepared by spin coating and the thickness can be 10~30nm.

[0079] According to embodiments of the present application, the first transport layer and the second transport layer may further include other functional film layers suitable for improving carrier transport performance, such as insulating layers, barrier layers, buffer layers, etc. Since these are not critical to the present application and are well known in the art, they will not be listed here one by one.

[0080] According to an embodiment of the present application, the transparent electrode layer may be, for example, one of indium zinc oxide (IZO), indium tin oxide (ITO), and aluminum-doped zinc oxide (AZO).

[0081] According to an embodiment of the present application, the cell body III of the perovskite top cell 20 may further include an anti-reflection layer. The anti-reflection layer may be made of one of lithium fluoride (LiF), magnesium fluoride (MgF2), aluminum nitride (AlN), zinc sulfide (ZnS), silicon nitride (Si3N4), silicon oxide (SiO2), or titanium oxide (TiO2), with a thickness of 0-3 mm. In this case, electrode IV passes through the anti-reflection layer to contact the transparent electrode layer.

[0082] According to the embodiment of the present application, Figure 6 As shown, the tandem solar cell of the present application may further include an intermediate recombination layer V located between the crystalline silicon bottom cell 10 and the perovskite top cell 20. The intermediate recombination layer V primarily serves to connect the crystalline silicon bottom cell 10 and the perovskite top cell 20, ensuring efficient recombination of majority carriers. The intermediate recombination layer V may be, for example, a tunnel junction, indium zinc oxide (IZO), indium tin oxide (ITO), or aluminum-doped zinc oxide (AZO). Of course, in other embodiments, the recombination layer may not be present.

[0083] In order to facilitate understanding of the structure of the perovskite / crystalline silicon tandem solar cell, this application takes the crystalline silicon bottom cell 10 as an HJT cell as an example to describe the structure of the tandem solar cell in detail as follows. Figure 8 FIG. 1 is a schematic structural diagram of a perovskite / crystalline silicon tandem solar cell according to another exemplary embodiment of the present invention. Figure 1 and Figure 8 As shown, the tandem solar cell of the present application may include a crystalline silicon bottom cell 10, a perovskite top cell 20 and an intermediate composite layer V, wherein:

[0084] The crystalline silicon bottom cell 10 includes a cell body I and an electrode II located on the cell body I, wherein the cell body I includes a silicon substrate 1, the silicon substrate 1 includes a first surface 1a and a second surface 1b relative to each other, and the first surface 1a and the second surface 1b respectively have a velvet structure 12. Of course, it is not limited to this, and only the first surface 1a can also have a velvet structure 12.

[0085] The cell body 1 of the crystalline silicon bottom cell 10 further includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 is located on the first surface 1a of the silicon substrate 1, and the second semiconductor layer 22 is located on the second surface 1b of the silicon substrate 1. Furthermore, the cell body 1 further includes a first passivation layer 31 and a second passivation layer 32. The first passivation layer 31 is located between the silicon substrate 1 and the first semiconductor layer 21, and the second passivation layer 31 is located between the silicon substrate 1 and the second semiconductor layer 22. The provision of the velvet structure 12 on the first surface 1a and the second surface 1b of the silicon substrate 1 ensures that the surface of the cell body 1, i.e., the surface of the first semiconductor layer 21 and the second semiconductor layer 22 facing away from the silicon substrate 1, conformally forms the velvet structure 11.

[0086] The velvet structure 11 includes a plurality of first pyramids 111, and there are gaps 1113 or platform areas 1114 between the boundaries of the first tower bottoms 1111 of at least some adjacent first pyramids 111. Furthermore, the velvet structure 11 may also include a plurality of second pyramids 112, which are located between adjacent first pyramids 111, or on the platform areas 1114. The arrangement of the first pyramids 111, the second pyramids 112, and the gaps 1113 is the same as described above, so they are not repeated here. Among them, the first semiconductor layer 21 can be a P-type doped amorphous silicon layer prepared by plasma chemical vapor deposition (PECVD), and the second semiconductor layer 22 can be an N-type doped amorphous silicon layer prepared by PECVD. Of course, in other embodiments, the first semiconductor layer 21 can be an N-type doped amorphous silicon layer, and the second semiconductor layer 22 can be a P-type doped amorphous silicon layer. The first passivation layer 31 and the second passivation layer 32 can be intrinsic amorphous silicon layers prepared by PECVD method respectively. A heterojunction contact structure is formed between the first passivation layer 31 and the second semiconductor layer 21 , and between the second passivation layer 32 and the second semiconductor layer 22 .

[0087] The cell body I of the crystalline silicon bottom cell 10 may further include a transparent conductive layer 5 and an electrode II. The transparent conductive layer 5 is located on the surface of the second semiconductor layer 22 away from the silicon substrate 1 . The electrode II is located on the surface of the transparent conductive layer 5 away from the silicon substrate 1 .

[0088] The perovskite top cell 20 includes a cell body III and an electrode IV located on the cell body III. In a direction away from the crystalline silicon bottom cell 10, the cell body III may include a first transport layer 301, a perovskite layer 302, a second transport layer 304, and a transparent electrode layer 305. The first transport layer 301 comprises a hole transport layer, and the second transport layer 304 comprises an electron transport layer. Furthermore, the cell body III may also include an electrically insulating layer 303 and an anti-reflection layer 306. The electrically insulating layer 303 is located between the perovskite layer 302 and the second transport layer 304. The anti-reflection layer 306 is located on the transparent electrode layer 305 in a direction away from the crystalline silicon bottom cell 10. The electrode IV contacts the transparent electrode layer 305 through the anti-reflection layer 306.

[0089] The intermediate composite layer V is located between the crystalline silicon bottom cell 10 and the perovskite top cell 20 , and in this exemplary embodiment may be a transparent conductive layer such as IZO, ITO or AZO.

[0090] Since the perovskite top cell 20 is located on the velvet structure 11 of the crystalline silicon bottom cell 10, and the film layers located between the cell body I of the crystalline silicon bottom cell 10 and the perovskite layer 302 are conformally prepared on the velvet structure 11, during the crystallization growth process of the perovskite layer 302, the second pyramid 112 and / or platform area 1114 of the velvet structure 11 help to release the stress of the perovskite layer 302 at the first tower bottom 1111 of the first pyramid 111, thereby forming a good interface contact structure and improving the crystallization effect of the perovskite layer 302.

[0091] The following examples are based on different texturing conditions to prepare the textured structure 11 of the crystalline silicon bottom cell 10. Figure 8 The preparation process and test results of the perovskite / crystalline silicon tandem solar cell shown are further explained.

[0092] Example 1:

[0093] The method for preparing the perovskite / crystalline silicon tandem solar cell includes operations S1 to S2.

[0094] In operation S1 , a crystalline silicon bottom cell 10 is prepared.

[0095] Specifically, first, a texturing solution is used to texturize the surface of a cleaned and polished silicon wafer to obtain a silicon substrate 1. The texturizing solution formula is 1 part additive, 3 parts alkali, and 88 parts water. The texturizing temperature is 75° C. and the time is 480 s.

[0096] Next, an intrinsic amorphous silicon layer as the first passivation layer 31, a phosphorus-doped amorphous silicon layer as the first semiconductor layer 21, and a transparent conductive layer as the intermediate composite layer V are deposited on the first surface 1a of the textured silicon substrate 1. An intrinsic amorphous silicon layer as the second passivation layer 32, a boron-doped amorphous silicon layer as the second semiconductor layer 22, and another transparent conductive layer 5 are deposited on the second surface 1b. Electrode II is formed on the other transparent conductive layer 5. This results in a crystalline silicon bottom cell 10.

[0097] The velvet structure 11 obtained after depositing the first semiconductor layer 21 is as follows: Figure 9 As shown in Figure (a), it includes the first pyramid, the second pyramid and the gap between the first pyramids, where the lateral size of the second pyramid is distributed in the range of 10~50nm, and the measured suede reflectivity is 9.38%.

[0098] In operation S2 , a perovskite top cell 20 is prepared.

[0099] Specifically, first, a hole transport layer with a thickness of 20 nm is prepared on the intermediate composite layer 10 by spin coating as the first transport layer 301 .

[0100] Next, press Cs 0.05 FA 0.8 MA 0.15 Pb(I 0.75 Br 0.25 )3 ratio of the perovskite precursor solution, the film is formed by spin coating and then heated annealing, the thickness of the perovskite layer 302 from the upper surface to the pyramid base is 1.1 μm, and the thickness from the upper surface to the pyramid top is 0.5 μm. The cross section of the obtained perovskite layer 302 is as follows Figure 10 As shown in Figure (a), the perovskite grain size is consistent throughout the film thickness, but there are distinct grain boundaries. No obvious holes are found at the perovskite / Si interface, demonstrating that the stress is well relieved during the growth of the perovskite layer on this textured structure.

[0101] Again, a LiF electrical insulation layer with a thickness of 3 nm and a C60 electron transport layer with a thickness of 18 nm are sequentially deposited by thermal evaporation, and then an SnO2 electron transport layer with a thickness of 18 nm is prepared by atomic layer deposition (ALD) technology. The C60 electron transport layer and the SnO2 electron transport layer together serve as the second transport layer 304.

[0102] Next, a transparent electrode layer 305 is deposited on the second transmission layer 304 by physical vapor deposition, and a MgF2 anti-reflection layer 306 and an electrode IV are sequentially deposited on the transparent electrode layer by thermal evaporation. Thus, a perovskite top cell 20 is obtained.

[0103] Example 2:

[0104] The operation is similar to that of Example 1, except that:

[0105] In the process of preparing the crystalline silicon bottom cell 10, the texturing solution formula is 1 part additive, 3.8 parts alkali, 88 parts water, the texturing temperature is 75°C, and the time is 480 seconds. The resulting textured structure 11 is as shown in FIG. Figure 9 As shown in Figure (b), the lateral size distribution of the second pyramid is 50~70 nm, and the measured suede reflectivity is 9.47%.

[0106] In the process of preparing the perovskite top cell 20, the cross section of the obtained perovskite layer 302 is as follows: Figure 10 As shown in Figure (b), the perovskite layer has no obvious grain boundaries and the upper surface is relatively flat, which is conducive to the deposition and growth of LiF thin film. In addition, no obvious holes are found at the perovskite / Si interface, which proves that the perovskite has better crystallinity on this velvet structure and the stress is well released during the film growth process.

[0107] Example 3:

[0108] The operation is similar to that of Example 1, except that:

[0109] In the process of preparing the crystalline silicon bottom cell 10, the texturing solution formula is 1 part additive, 4.5 parts alkali, 88 parts water, the texturing temperature is 75°C, and the time is 480 seconds. The obtained textured structure 11 is as shown in FIG. Figure 9 As shown in Figure (c), the lateral size distribution of the second pyramid is 70~160 nm, and the measured suede reflectivity is 9.44%.

[0110] In the process of preparing the perovskite top cell 20, the thickness of the obtained perovskite layer 302 from the upper surface to the bottom of the pyramid is 1.1 μm, and the thickness from the upper surface to the top of the pyramid is 0.5 μm. Figure 10 As shown in Figure (c), the perovskite layer 302 also has no obvious grain boundaries, but the overall thickness is slightly thinner. The thinning is due to the larger size of the second pyramid in the platform area. In addition, no obvious holes are found at the perovskite / Si interface, but the flatness of the interface contact is reduced, proving that the stress release of the perovskite layer based on this velvet structure is deteriorated during the crystallization growth process.

[0111] Example 4:

[0112] The operation is similar to that of Example 1, except that in the process of preparing the crystalline silicon bottom cell 10, the texturing solution formula is 1 part additive, 4.5 parts alkali, 88 parts water, the texturing temperature is 75°C, and the time is 480 s. The obtained textured structure 11 is as shown in FIG. Figure 9As shown in Figure (c), the lateral size distribution of the second pyramid is between 160 and 190 nm, and the measured suede reflectivity is 9.62%.

[0113] In the process of preparing the perovskite top cell 20, the thickness of the obtained perovskite layer 302 from the upper surface to the bottom of the pyramid is 1.1 μm, and the thickness from the upper surface to the top of the pyramid is 0.5 μm. Figure 10 As shown in Figure (d), as the size of the second pyramid in the velvet structure continues to increase, obvious grain boundaries appear in the perovskite layer. In addition, there are pores left at the perovskite / Si interface during the perovskite crystallization process, proving that the stress of the perovskite layer based on this velvet structure cannot be released in time during the crystallization growth process, resulting in poor interface contact quality.

[0114] Comparative Example 1:

[0115] The operation is similar to that of Example 1, except that in the process of preparing the crystalline silicon bottom cell 10, the texturing solution is formulated as 1 part additive, 1.4 parts alkali, 88 parts water, the texturing temperature is 70°C, and the time is 420 s. The resulting velvet structure is as follows: Figure 11 As shown in Figure (a), the suede surface is composed of pyramids of relatively uniform size, and the suede reflectivity is 10.8%.

[0116] In the process of preparing the perovskite top cell 20, the cross section of the obtained perovskite layer 302 is as follows: Figure 11 As shown in Figure (b), the perovskite film has obvious grain boundaries. In addition, large holes appear at the perovskite / Si interface, resulting in poor interface contact. This is because the velvet surface with a complete pyramid structure is not conducive to the release of stress during the crystallization growth of the perovskite film.

[0117] IV tests were performed on the perovskite / crystalline silicon tandem solar cells obtained in Examples 1 to 4 and Comparative Example 1, and the results are shown in Table 1 below.

[0118] Table 1

[0119]

[0120] From the IV test results of Examples 1 to 4 and Comparative Example 1 shown in Table 1, it can be seen that the perovskite / crystalline silicon stacked solar cells prepared based on the velvet structure of Examples 1 to 4 show higher energy conversion efficiency, open circuit voltage, short-circuit current density and fill factor than Comparative Example 1. This is because the velvet making method of the present application can form a gap between the first pyramids and form a second pyramid and / or platform area on the gap. The first pyramid and the second pyramid are two types of pyramid structures with a large size difference, which is beneficial to reducing the light reflectivity at the velvet structure, and improving the crystallization quality of the perovskite layer, thereby inhibiting the formation of holes at the interface between it and the crystalline silicon bottom cell.

[0121] Therefore, the perovskite / crystalline silicon tandem solar cell of the present application has the following advantages: First, due to the low reflectivity of the velvet surface, the prepared tandem solar cell has a higher Jsc; second, the second pyramids between adjacent first pyramids in the velvet structure help release the stress generated during the crystallization of the perovskite layer, ensuring good contact between the prepared perovskite layer and the silicon interface. In addition, SEM cross-sectional images and IV test results show that the size of the second pyramids is in the range of 10-190 nm, which can effectively relieve the stress generated during the crystallization of the perovskite film.

[0122] According to another embodiment of the present application, a photovoltaic module is provided, comprising: a plurality of the above-mentioned crystalline silicon solar cells or perovskite / crystalline silicon stacked solar cells, connected in series to form a solar cell string; and a packaging structure covering the surface of the solar cell string.

[0123] According to an embodiment of the present application, the number of solar cells connected in series can be 4 to 20. Multiple solar cells can be formed into several solar cell strings, each solar cell string has the same number of solar cells, and the solar cell strings can be connected in series or in parallel.

[0124] According to embodiments of the present application, the encapsulation structure may include a backsheet, an encapsulation film, and a glass panel to enhance the stability of the solar cell string. The glass panel is located on the front of the solar cell string, while the backsheet is located on the back of the solar cell string, both providing protection. The adhesive film, which acts as a bonding agent between the solar cell string, the glass panel, and the backsheet, must be made of a transparent material.

[0125] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of this application. It should be understood that the above is only a specific embodiment of this application and is not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A crystalline silicon solar cell, comprising: A battery body, wherein a surface of the battery body has a velvet structure, the velvet structure includes a plurality of first pyramids, each of the first pyramids including a first tower bottom and a first tower top arranged in a direction away from the surface of the battery body; Wherein, there are gaps between first tower bottom boundaries of at least some adjacent first pyramids among the plurality of first pyramids.

2. The crystalline silicon solar cell according to claim 1, wherein: The ratio of the width of the gap to the transverse dimension of the bottom of the first tower is 0.04-0.

8.

3. The crystalline silicon solar cell according to claim 2, wherein: The width of the gap is 20-80 nm; and / or the lateral dimension of the bottom of the first tower is 0.3-1.2 μm; and / or the height from the bottom of the first tower to the top of the first tower is 0.4-0.8 μm.

4. The crystalline silicon solar cell according to any one of claims 1 to 3, wherein: The velvet structure further includes a plurality of second pyramids, wherein the second pyramids are located in gaps between adjacent first pyramids; The second pyramid includes a second tower bottom and a second tower top arranged in a direction away from the surface of the battery body; the ratio of the lateral dimension of the second tower bottom to the lateral dimension of the first tower bottom is 0.008-0.

65.

5. The crystalline silicon solar cell according to claim 4, wherein: The lateral dimension of the bottom of the second tower is 10-190 nm.

6. The crystalline silicon solar cell according to claim 4, wherein: The number of the second pyramids in at least part of the gap is greater than or equal to 1.

7. The crystalline silicon solar cell according to claim 1, wherein: There is a platform area between the bottom boundaries of the first pyramids of at least some adjacent first pyramids among the plurality of first pyramids, and the platform area constitutes at least a part of the gap.

8. A perovskite / crystalline silicon tandem solar cell, comprising: A crystalline silicon bottom cell having the structure of a crystalline silicon solar cell according to any one of claims 1 to 7; as well as The perovskite top cell is located on the textured structure of the crystalline silicon bottom cell.

9. The perovskite / crystalline silicon tandem solar cell according to claim 8, wherein: The perovskite top cell includes a perovskite layer, and the thickness of the perovskite layer is 0.4-0.7 μm.

10. The perovskite / crystalline silicon tandem solar cell according to claim 8, wherein: The perovskite layer has perovskite grains, and along a thickness direction of the perovskite layer, the perovskite grains penetrate the perovskite layer.

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