Shielding structure for vertical III-nitride semiconductor device

Abstract

A method for manufacturing an intermediate for a vertical group III nitride semiconductor device comprising a shielding structure (5), the method comprising: a. Obtaining a stack (3) in a reaction chamber of a vapor phase epitaxy reactor, the stack (3) comprising: a group III nitride semiconductor stack (1), and a patterned mask layer (2), the pattern comprises a first region (21) comprising a mask material and a second region (22) not comprising a mask material and exposing a region (10) of the group III nitride semiconductor stack (1), and b. Controlling the reactor, and b2. Forming a shielding structure (5) by epitaxially growing the Group III nitride material doped with a p-type dopant in the trench, b1. Selectively desorbing material from the region (10) of the Group III nitride semiconductor stack (1) exposed by the second region (22) of the patterned mask layer (2) so as to form the trench (4), and then b2. Forming the shielding structure (5) by epitaxially growing the Group III nitride material doped with a p-type dopant in the trench.

Description

Technical Field

[0001] The present invention relates to the field of vertical III-nitride semiconductor devices, and in particular to the field of methods for manufacturing vertical III-nitride semiconductor devices including shielding structures. Background Art

[0002] The active layer of a vertical III-nitride semiconductor device typically includes a III-nitride semiconductor stack that includes, from top to bottom, an n+-doped III-nitride source layer, a p-doped III-nitride bulk layer, an n-doped III-nitride drift layer, and an n+-doped III-nitride drain layer. A vertical III-nitride metal oxide semiconductor field effect transistor (MOSFET) includes a trench gate that typically extends through the source layer and bulk layer, with its bottom located in the drift layer. When in a blocking state, this can result in a high electric field in the bottom corner of the trench gate. The high electric field is a characteristic of the trench gate shape. This is particularly true if the MOSFET is used as a power device. This local maximum electric field can lead to early device failure and may also determine the lifetime of the gate oxide in the blocking state. To address this issue, a shielding structure can be formed around the trench gate to shield the trench gate from the effects of high electric fields. The shielding structure includes a p+ doped III-nitride filled trench that extends through the source layer and the body layer and then into the drift layer, wherein the bottom of the trench is located in the drift layer.

[0003] A typical method for forming a shield structure involves forming a patterned mask on a III-nitride semiconductor stack, dry etching a trench around the trench gate location, and then regrowing p-doped III-nitride in the cleaned trench. However, in the prior art, the interface between the shield structure and the III-nitride semiconductor stack may become contaminated, thereby reducing the shielding performance of the shield structure. In addition, the trench may be damaged due to the dry etching process used to form the trench of the shield structure.

[0004] Therefore, there remains a need in the art for apparatus and methods that address at least some of the above-mentioned problems. Summary of the Invention

[0005] It is an object of the present invention to provide a good method for producing an intermediate body for a vertical III-nitride semiconductor device including a shield structure.

[0006] The above objects are achieved by the method and device according to the present invention.

[0007] An advantage of various embodiments of the present invention is that contamination at the interface between the shield structure and the III-nitride semiconductor stack can be avoided. Another advantage of various embodiments of the present invention is that damage to the trenches used to form the shield structure, and thus damage at the interface, can be limited. Therefore, an advantage of various embodiments of the present invention is that the shield structure can effectively shield the trench gate of a vertical III-nitride semiconductor device from the high electric fields that may exist at the bottom corners of the trench gate.

[0008] The present invention relates to a method for manufacturing an intermediate body for a vertical III-nitride semiconductor device including a shielding structure, the method comprising:

[0009] a. Obtaining a stack in a reaction chamber of a vapor phase epitaxial reactor, the stack comprising:

[0010] A Group III nitride semiconductor stack formed of a Group III nitride semiconductor material, the Group III nitride semiconductor stack comprising:

[0011] a drain layer doped with an n-type dopant,

[0012] a drift layer on the drain layer, wherein the drift layer is doped with an n-type dopant, wherein

[0013] The concentration of n-type dopants in the drift layer is lower than that in the drain layer.

[0014] a body layer on the drift layer, wherein the body layer is doped with a p-type dopant, and a source layer on the body layer, wherein the source layer is doped with an n-type dopant, and a patterned mask layer on the source layer, the pattern including a first region containing a mask material and a second region not containing the mask material and exposing a region of the III-nitride semiconductor stack, and

[0015] b. Control the reactor so that:

[0016] b1. selectively desorbing material from the region of the III-nitride semiconductor stack exposed by the second region of the patterned mask layer to form a trench extending through the source layer and the body layer and into the drift layer, wherein the bottom of the trench is located in the drift layer, and then

[0017] b2. Forming a shielding structure by epitaxially growing a Group III nitride material doped with a p-type dopant in the trench.

[0018] Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with features of the independent claims as appropriate and with features of other dependent claims, and not merely as explicitly set out in the claims.

[0019] While devices in the art are constantly improving, changing, and evolving, the present inventive concepts are believed to represent a substantially new and inventive advancement involving a departure from prior practice, thereby providing a more efficient, stable, and reliable device of this nature.

[0020] The above and other characteristics, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention by way of example. This description is given for illustrative purposes only and does not limit the scope of the invention. The reference figures cited below refer to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 and Figure 2 is a schematic vertical cross-sectional view of a Group III nitride semiconductor stack in an exemplary method according to an embodiment of the present invention.

[0022] Figure 3A and Figure 3B Schematic diagrams of a vertical cross-section and a top view, respectively, of a stack in an exemplary method according to an embodiment of the present invention.

[0023] Figure 4A Graphs of the flow rates of N2, H2, and NH3 in standard liters per minute (slm) versus time and the temperature of the stack versus time were used in experiments performing the desorption step of the present invention.

[0024] Figure 4B is a schematic representation of a vertical cross-section of a stack after selective desorption of material to form trenches in an exemplary method according to an embodiment of the present invention.

[0025] Figure 5 is a schematic diagram of a vertical cross-section of a stack after forming a shielding structure in a trench in an exemplary method according to an embodiment of the present invention.

[0026] Figure 6 is a schematic diagram of a vertical cross-section of the stack after forming another trench for a gate in an exemplary method according to an embodiment of the invention.

[0027] Figure 7A and Figure 7B Schematic diagrams of a vertical cross section and a horizontal cross section of a stack after forming a trench gate in an exemplary method according to an embodiment of the present invention, respectively.

[0028] The same reference numbers in different drawings refer to the same or similar elements. DETAILED DESCRIPTION

[0029] The present invention will be described with respect to specific embodiments and with reference to certain drawings, but the invention is not limited thereto but only by the claims. The drawings described are merely illustrative and non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn to scale for illustrative purposes. Dimensions and relative dimensions do not correspond to actual reductions to which the invention may be practiced.

[0030] Furthermore, the terms first, second, third, etc. in the description and claims are used to distinguish similar elements and are not necessarily used to describe a sequential order in time, space, ranking, or any other manner. It should be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in a sequence other than that described or illustrated herein.

[0031] Furthermore, the terms top, bottom, over, under, etc. in the specification and claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the invention described herein are capable of operation in orientations other than those described or illustrated herein.

[0032] It should be noted that the term "comprising" used in the claims should not be interpreted as being limited to the means listed thereafter; it does not exclude other elements or steps. Thus, the term should be interpreted as specifying the presence of the stated features, integers, steps or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Therefore, the term "comprising" covers the case where only the stated features are present as well as the case where these features and one or more other features are present. The word "comprising" according to the present invention therefore also includes an embodiment in which no other components are present. Thus, the scope of the expression "a device comprising means A and B" should not be interpreted as being limited to a device consisting only of components A and B. This means that for the purposes of the present invention, the only relevant components in the device are A and B.

[0033] Similarly, it should be noted that the term "coupled" should not be interpreted as limited to only direct connections. The terms "coupled" and "connected," along with their derivatives, may be used. It should be understood that these terms are not intended to be synonymous with each other. Thus, the scope of the phrase "device A is coupled to device B" should not be limited to devices or systems in which the output of device A is directly connected to the input of device B. This means that there is a path between the output of device A and the input of B, which may be a path that includes other devices or apparatuses. "Coupled" can mean that two or more elements are in direct physical or electrical contact, or it can mean that two or more elements are not in direct contact with each other but still cooperate or interact with each other.

[0034] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in various embodiments" in various places throughout this specification do not necessarily all refer to the same embodiment, but may refer to different embodiments. Furthermore, in one or more embodiments, the particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0035] Similarly, it should be appreciated that in the description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, this approach to disclosure should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, inventive aspects lie in fewer features than all of the features of a single preceding disclosed embodiment. Accordingly, the claims appended to the detailed description are hereby expressly incorporated into this detailed description, with each claim itself representing a separate embodiment of the present invention.

[0036] Furthermore, although some embodiments described herein include some features included in other embodiments but do not include other features included in other embodiments, as will be understood by those skilled in the art, combinations of features from different embodiments are intended to fall within the scope of the present invention and form different embodiments. For example, in the appended claims, any of the claimed embodiments may be used in any combination.

[0037] In addition, some of the embodiments are described herein as methods or combinations of elements of methods that can be implemented by a processor of a computer system or by other devices that implement the functions. Thus, a processor with the necessary instructions for executing such methods or elements of a method forms a device for executing the method or elements of a method. In addition, the elements described herein of the device embodiments are examples of devices for implementing the functions performed by the elements that achieve the purposes of the present invention.

[0038] In the description provided herein, numerous specific details are set forth. However, it should be understood that embodiments of the present invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques are not shown in detail to avoid obscuring an understanding of this specification.

[0039] The present invention will now be described in detail by describing several embodiments of the present invention. Obviously, other embodiments of the present invention can be configured according to the knowledge of those skilled in the art without departing from the technical teachings of the present invention, and the present invention is only limited by the terms of the appended claims.

[0040] Reference will be made to a transistor which is a three terminal device having a first main electrode such as a drain, a second main electrode such as a source, and a control electrode such as a gate for controlling the flow of charge between the first and second main electrodes.

[0041] The present invention relates to a method for manufacturing an intermediate body for a vertical III-nitride semiconductor device including a shielding structure, the method comprising:

[0042] a. Obtaining a stack in the reaction chamber of a vapor phase epitaxial reactor, the stack comprising:

[0043] A Group III nitride semiconductor stack formed of a Group III nitride semiconductor material, the Group III nitride semiconductor stack comprising:

[0044] a drain layer doped with an n-type dopant,

[0045] a drift layer on the drain layer, wherein the drift layer is doped with an n-type dopant, wherein a concentration of the n-type dopant in the drift layer is lower than a concentration of the n-type dopant in the drain layer,

[0046] a body layer on the drift layer, wherein the body layer is doped with a p-type dopant, and a source layer on the body layer, wherein the source layer is doped with an n-type dopant, and a patterned mask layer on the source layer, the pattern comprising a first region comprising a mask material and a second region not comprising the mask material and exposing a region of the III-nitride semiconductor stack, and

[0047] b. Controlling the reactor so as to:

[0048] b1. selectively desorbing material from the region of the III-nitride semiconductor stack exposed by the second region of the patterned mask layer to form a trench extending through the source layer and the body layer and into the drift layer, wherein the bottom of the trench is located in the drift layer, and then

[0049] b2. Forming a shielding structure by epitaxially growing a Group III nitride material doped with a p-type dopant in the trench.

[0050] In various embodiments, the method may further include a step c of removing at least a portion of the patterned mask layer. When the patterned mask layer includes a silicon nitride layer and a SiO2 layer, step c may include removing the SiO2 layer and leaving the silicon nitride layer. Removing at least a portion of the patterned mask layer allows for reducing the aspect ratio of the trench.

[0051] In various embodiments, the method further includes forming a trench gate laterally separated from the shield structure, including after step b:

[0052] c. removing (preferably completely removing) the patterned mask layer, and either after step c or in step a, including the following steps:

[0053] d. providing another trench extending through the source layer and the body layer and into the drift layer, wherein the bottom of the another trench is located in the drift layer, and

[0054] After steps c and d,

[0055] e. forming a trench gate in another trench by the following steps:

[0056] e1. Depositing a dielectric material on the surface of another trench, and then,

[0057] e2. Depositing a conductive material on the dielectric material, wherein a height of the conductive material within the III-nitride semiconductor stack at a bottom portion is lower than a height of the conductive material within the III-nitride semiconductor stack at a top portion of the drift layer.

[0058] In various embodiments, step c comprises wet etching of the patterned mask layer. An advantage of these embodiments is that wet etching can result in removal of the patterned mask layer without damaging the shielding structure.

[0059] In various embodiments, the patterned mask layer comprises silicon nitride or silicon oxide. An advantage of these embodiments is that selective deposition of the Group III nitride material doped with a p-type dopant can be achieved, which is selective with respect to the patterned mask layer.

[0060] In various embodiments, the method may further include, between steps a and b, an etching step a', etching material from the region of the III-nitride semiconductor stack exposed by the second region of the patterned mask layer to form a trench extending through a portion of the thickness of a substack comprising a source layer, a bulk layer, and a drift layer, provided that the trench spans at most a portion of the thickness of the drift layer. Step a' may be a dry etching step, a wet etching step, or a combination of both. This provides greater control over the shape of the trench and is generally less expensive and faster than forming the entire trench via the desorption step b1. In various embodiments, the optional etching step a' may etch material from the region of the III-nitride semiconductor stack exposed by the second region of the patterned mask layer to form a trench extending through a portion of the source layer, wherein the bottom of the trench is located in the source layer, or a trench extending through a portion of the source layer and the bulk layer, wherein the bottom of the trench is located in the bulk layer, or a trench extending through the source layer and the bulk layer and into the drift layer, wherein the bottom of the trench is located in the drift layer. In this last embodiment, step b1 is performed in order to deepen the trench further into the drift layer than after step a'.In this last embodiment, step b1 may be performed in order to deepen the trench by 1 to 3 nm.

[0061] The dry etching may be, for example, atomic layer etching.

[0062] If a wet etching step is performed, it may be possible to use TMAH, for example, to create vertical facets.

[0063] In embodiments including step a', the patterned mask layer is adapted to resist the etching process of step a', ensuring that portions of the mask remain after the etching step is completed. For example, the patterned mask layer may have a thickness of at least 110 nm. In various embodiments, the patterned mask layer may include a silicon nitride bottom layer having a thickness of 10 to 100 nm and a SiO2 top layer having a thickness of 100 nm to 1 μm. In various embodiments, the height within the drift layer at the bottom of the further trench is higher than the height within the drift layer at the bottom of the trench. In various embodiments, a ratio of a first distance from the bottom of the drift layer to the height of the bottom of the further trench in the drift layer to a second distance from the bottom of the drift layer to the top of the drift layer is from 0.60 to 0.95. In various embodiments, a ratio of a third distance from the bottom of the drift layer to the height of the bottom of the trench in the drift layer to the second distance from the bottom of the drift layer to the top of the drift layer is from 0.50 to 0.90. In various embodiments, a ratio of a fourth distance from the height of the bottom of the trench in the drift layer to the height of the bottom of another trench in the drift layer to a second distance from the bottom of the drift layer to the top of the drift layer is at least 0.05, preferably at least 0.10. These embodiments have the advantage that the trench gate can be more effectively shielded from strong electric fields by the shielding structure.

[0064] In various embodiments, the lateral distance separating the trench gate and the shield structure is from 0.5 μm to 50 μm, preferably from 0.5 μm to 10 μm. An advantage of these embodiments is that good shielding can be achieved when the trench gate and the shield structure are close to each other.

[0065] In various embodiments, the Group III nitride semiconductor material is gallium nitride.

[0066] In various embodiments, the drain layer includes 10 17 to 10 20 atoms / cm -3 , preferably 10 18 to 10 19 atoms / cm -3 In various embodiments, the drift layer includes 5×10 14 to 10 18 atoms / cm -3 , preferably 5×10 15 to 10 17 atoms / cm -3 In one embodiment, the main layer includes 10 17 to 10 20 atoms / cm -3 , preferably 10 18 to 10 19 atoms / cm -3 In various embodiments, the source layer includes 10 17 to 10 20 atoms / cm -3 , preferably 10 18 to 10 19 atoms / cm -3 In various embodiments, the concentration of the n-type dopant in the drift layer is at least two times lower than the concentration of the n-type dopant in the drain layer, preferably at least ten times lower.

[0067] In various embodiments, the concentration of the p-type dopant in the shielding structure is 10 16 to 10 20 atoms / cm 3 , preferably 10 17 to 10 20 atoms / cm 3 , more preferably 10 18 to 10 20 atoms / cm 3 In a preferred embodiment, the concentration of the p-type dopant in the shielding structure is higher than the concentration of the p-type dopant in the bulk layer. An advantage of these embodiments is that good shielding can be achieved.

[0068] In embodiments where the III-nitride semiconductor material is gallium nitride, the surfaces of the trench are preferably parallel to planes belonging to a set of planes having Bravais-Miller indices {1-100}. Good epitaxial growth of gallium nitride can be achieved on surfaces parallel to planes having Bravais-Miller indices {1-100}, although epitaxial growth is also possible on surfaces parallel to planes having Bravais-Miller indices {1-101}.

[0069] In various embodiments, step b1 comprises heating the stack to a temperature of 700 to 1200° C., preferably 900 to 1100° C. In various embodiments, step b1 comprises applying a pressure of 10 to 200 Torr, preferably 50 to 100 Torr. In various embodiments, in step b1, the atmosphere of the reaction chamber contains 30 to 80 volume percent of H 2 , 10 to 40 volume percent of an inert gas (e.g. N2), and 10 to 30 volume percent of NH3. An advantage of these embodiments is that selective desorption from the exposed areas can be achieved, which is selective with respect to the mask material. The desorption can result in the surfaces of the trench comprising crystalline Group III nitrides. The desorption can be terminated when the trench has reached a preferred depth, for example when the bottom of the trench is located in the drift layer. Here, the desorption can be terminated by cooling the stack to room temperature. Here, the desorption can be terminated by reducing the concentration of H2 in the air of the reaction chamber, for example, to a concentration below 10 volume percent, preferably below 5 volume percent, and more preferably below 1 volume percent. An advantage of the embodiments of the present invention is that, since the desorption is carried out in a gas phase epitaxial reactor, after the desorption, the epitaxial growth can be carried out in the same chamber as step b1 in which the desorption is carried out.

[0070] In various embodiments, the method includes, between steps b1 and b2, a step b1' of surface treating each surface of the trench to form an epitaxial growth front. In these embodiments, in step b2, a Group III nitride material doped with a p-type dopant is epitaxially grown on the epitaxial growth front. These embodiments offer the advantage of a shielding structure having favorable properties, such as a uniform structure. Advantageously, since the desorption is performed in a vapor phase epitaxy reactor, the epitaxial growth front can be formed after desorption in the same chamber as the desorption step b1.

[0071] In various embodiments, step b2 may include epitaxially growing a III-nitride material doped with an n-type dopant in the trench before epitaxially growing a III-nitride material doped with a p-type dopant in the trench. This is advantageous because it provides a better transition from the old epi to the new epi.

[0072] In various embodiments, in step b2 , the trench is completely filled with the Group III nitride semiconductor material doped with a p-type dopant.

[0073] In various embodiments, step b is performed without removing the stack from the reaction chamber. By performing each step in the same reactor without removing the stack from the reaction chamber, contamination of the shield structure by any contaminants in the air can be avoided. Specifically, when the stack is removed from the reaction chamber between steps b1 and b2, contaminants may be deposited on the surfaces of the trench. This may lead to contamination of the interface between the III-nitride semiconductor stack and the shield structure subsequently formed in the trench.

[0074] In various embodiments, in a plane parallel to the top surface of the III-nitride semiconductor stack, the cross-section of the shielding structure forms a ring of III-nitride material doped with a p-type dopant, which surrounds the III-nitride material doped with an n-type dopant. In various embodiments, the cross-section may have a circular, rectangular, or square form. In various embodiments including a trench gate, in a plane parallel to the top surface of the III-nitride semiconductor stack, the cross-section of the shielding structure forms a ring of III-nitride material doped with a p-type dopant, which surrounds the trench gate. An advantage of these embodiments is that effective shielding of the trench gate can be achieved by the shielding structure. In a preferred embodiment including a trench gate, the trench gate is formed in the center of the ring.

[0075] In various embodiments, the vapor phase epitaxy reactor includes an outlet fluidically coupled to the reaction chamber, a vacuum pump fluidically coupled to the outlet, and a pressure gauge for detecting the pressure in the reaction chamber. In various embodiments, the vapor phase epitaxy reactor includes an inlet and a pump for introducing gas and / or vapor into the reaction chamber through the inlet. In various embodiments, the vapor phase epitaxy reactor includes a heater for heating the stack.

[0076] In various embodiments, the vapor phase epitaxy reactor is selected from a metal organic chemical vapor deposition reactor and a molecular beam epitaxy reactor. The molecular beam epitaxy reactor may include a Knudsen cell for evaporating a Group III material, such as Ga, and beaming the evaporated Group III material onto the stack. Preferably, the vapor phase epitaxy reactor is a metal organic chemical vapor deposition reactor.

[0077] Example: Intermediate for fabricating a vertical III-nitride semiconductor device including a shield structure

[0078] refer to Figure 1 , Figure 1is a vertical cross-sectional view of a III-nitride semiconductor stack 1. The III-nitride semiconductor stack 1 is formed of a III-nitride semiconductor material, preferably gallium nitride. The III-nitride semiconductor stack 1 includes a drain layer 11 doped with an n-type dopant. The III-nitride semiconductor stack 1 also includes a drift layer 12 on the drain layer 11. The drift layer 12 is doped with an n-type dopant. The concentration of the n-type dopant in the drift layer 12 is lower than the concentration of the n-type dopant in the drain layer 11. The III-nitride semiconductor stack 1 also includes a body layer 13 on the drift layer 12, wherein the body layer 13 is doped with a p-type dopant. The III-nitride semiconductor stack 1 also includes a source layer 14 on the body layer 13, wherein the source layer 14 is doped with an n-type dopant.

[0079] refer to Figure 2 Subsequently, in this example, so-called mesa etching is performed, in which portions of the source layer 14 are removed in order to electrically isolate the vertical III-nitride semiconductor device including the trench gates to be formed in the regions of the III-nitride semiconductor stack 1 from which the source layer 14 is not removed.

[0080] Also refer to Figure 3A and Figure 3B , Figure 3A is a vertical cross-sectional view of a schematic representation of a stack 3 according to an embodiment of the present invention, Figure 3B Here is its top view. Figure 3A Indicates along Figure 3B . A patterned mask layer 2 is formed on source layer 14 over III-nitride semiconductor stack 1. The pattern of patterned mask layer 2 includes a first region 21 containing a mask material and a second region 22 not containing a mask material. Second region 22 exposes III-nitride semiconductor stack 1, specifically, region 10 of source layer 14 of III-nitride semiconductor stack 1. In this example, second region 22 forms a square ring.

[0081] Also refer to Figure 4A and Figure 4B ,in Figure 4A is a graph of the flow rates of N2, H2 and NH3 in standard liters per minute (slm) versus time and a graph of the temperature of the stack 3 versus time, which were used in an experiment to perform step b1 of the present invention, and Figure 4B3 is a vertical cross-section of the stack 3 after the desorption. The stack 3 is introduced into the reaction chamber of the vapor phase epitaxy reactor. In the experiment to achieve desorption, the stack 3 similar to the present example was heated from room temperature to 1010°C, wherein the air in the reaction chamber contained N2 and NH3, and they were introduced into the reaction chamber using a volume flow rate of 190 standard liters per minute (slm) and 50 slm, respectively. The pressure in the reaction chamber was 75 Torr. Subsequently, the air in the reaction chamber was changed within 60 seconds so that it contained H2, N2 and NH3, and they were introduced into the reaction chamber using a volume flow rate of 120 slm, 64 slm and 50 slm, respectively. H2 can cause desorption by selectively reacting with the III-nitride semiconductor material. The temperature of the stack 3 was maintained at 1010°C so that the III-nitride semiconductor material was selectively desorbed from the region 10 of the III-nitride semiconductor stack 1 exposed by the second region 22 of the patterned mask layer 2. The temperature of the stack 3 is maintained at 1010°C until the grooves 4 are formed with the preferred depth. When the preferred depth is reached, the temperature of the stack 3 is lowered to room temperature, thereby terminating the desorption. At the same time, the volume flow of H2 is reduced to zero. Figure 4A Indicated are the combined ranges of volumetric flow rates of H2, N2 and NH3 and temperature that achieve the desorption. The above experiments were carried out in a Veeco Maxbright reactor, wherein stack 3 was held at 1010°C for 160 seconds, wherein a trench with a depth of 1.5 μm was obtained. Although the above values resulted in good desorption in the Veeco Maxbright reactor used, the skilled person will recognize that when using a different vapor phase epitaxy reactor, it may be necessary to apply different temperatures (e.g. in the range of 700-1200°C) and pressures (e.g. in the range of 10-200 Torr) as well as different volumetric flow rates of H2, N2 and NH3 (e.g. in the range of 30 to 80 volume percent H2, 10 to 40 volume percent inert gas and 10 to 30 volume percent NH3).

[0082] Thus, for example, using the above-described parameters in a vapor phase epitaxy reactor, the III-nitride semiconductor material is selectively desorbed from the region 10 of the III-nitride semiconductor stack 1 that is exposed by the second region 22 of the patterned mask layer 2. The desorption is performed so as to form a trench 4 that extends through the source layer 14 and the body layer 13 and into the drift layer 12. Here, the bottom 41 of the trench 4 is located in the drift layer 12. Preferably, in particular when the III-nitride semiconductor material is GaN, the trench 4 includes at least one surface 42, for example, a surface parallel to a plane belonging to a set of planes having Bravais-Miller indices {1-100}, on which good epitaxial growth of the III-nitride semiconductor material, such as GaN, can be achieved.

[0083] After forming the trench 4, in this example, an optional surface treatment can be performed on the surface 43 (e.g., all surfaces) of the trench 4. The surface treatment can be performed after forming the trench without removing the stack 3 from the reaction chamber. Thus, an epitaxial growth front can be formed, for example, by saturating all dangling bonds on the surface 43 of the trench 4. The dangling bonds can be the result of a desorption process and can inhibit epitaxial growth from the surface 43 of the trench 4.

[0084] refer to Figure 5 After the surface treatment, the p-type dopant-doped III-nitride material can be epitaxially grown on the epitaxial growth front formed by the surface 43 of the trench. Epitaxial growth is typically performed after the surface treatment without removing the stack 3 from the reaction chamber. The p-type dopant-doped III-nitride material in the trench forms a shielding structure 5 in the trench. In this example, the p-type dopant-doped III-nitride material completely fills the trench.

[0085] refer to Figure 6 After forming the shield structure 5, the patterned mask layer 2 is removed from the top of the III-nitride semiconductor stack 1. Subsequently, another trench 6 is formed in the center of the ring formed by the shield structure 5. Here, the other trench 6 extends into the drift layer 12. In this example, the height within the drift layer 12 at the bottom 61 of the other trench 6 is higher than the height within the drift layer 12 at the bottom of the trench (i.e., the bottom 51 of the shield structure 5).

[0086] Also refer to Figure 7A and Figure 7B ,in Figure 7A is a schematic vertical cross-sectional view of a III-nitride semiconductor stack after forming a shield structure 5 and a trench gate 60 according to an embodiment of the present invention, and Figure 7B is its horizontal cross-section. Here, Figure 7A The dotted line in Figure 7B The dotted line in is the same line. On the surface 63 of another groove 6 (see Figure 6 ), first, a dielectric material 61 may be deposited, and then a conductive material 62 may be deposited on the dielectric material 61. Here, the bottom 621 of the conductive material 62 is lower in height within the III-nitride semiconductor stack 1 than the top 121 of the drift layer 12 is in height within the III-nitride semiconductor stack 1. Figure 7BAs can be observed, in a plane parallel to the top surface 19 of the III-nitride semiconductor stack 1, the cross-section of the shielding structure 5 forms a ring of the III-nitride material doped with a p-type dopant, and the III-nitride material doped with a p-type dopant forms the shielding structure 5, and the ring surrounds the III-nitride material doped with an n-type dopant, and the III-nitride material doped with an n-type dopant forms the drift layer 12.

[0087] It should be understood that although preferred embodiments, specific configurations and arrangements, and materials have been discussed herein for devices according to the present invention, various changes or modifications in form and detail may be made without departing from the scope of the present invention. Steps may be added to or deleted from the described methods within the scope of the present invention.

Claims

1. A method for manufacturing an intermediate body of a vertical III-nitride semiconductor device including a shielding structure (5), the method comprising: a. Obtaining a stack (3) in a reaction chamber of a vapor phase epitaxy reactor, the stack (3) comprising: A Group III nitride semiconductor stack (1) formed of a Group III nitride semiconductor material, the Group III nitride semiconductor stack (1) comprising: a drain layer (11) doped with an n-type dopant, a drift layer (12) on the drain layer (11), wherein the drift layer (12) is doped with an n-type dopant, wherein a concentration of the n-type dopant in the drift layer (12) is lower than a concentration of the n-type dopant in the drain layer, a bulk layer (13) on the drift layer (12), wherein the bulk layer (13) is doped with a p-type dopant, and a source layer (14) on the body layer (13), wherein the source layer (14) is doped with the n-type dopant, and a mask layer (2) patterned with the source layer (14), the pattern comprising a first region (21) containing a mask material and a second region (22) not containing a mask material and exposing a region (10) of the III-nitride semiconductor stack (1), and b. Controlling the reactor so as to: b1. selectively desorbing material from the region (10) of the III-nitride semiconductor stack (1) exposed by the second region (22) of the patterned mask layer (2), so as to form a trench (4) extending through the source layer (14) and the body layer (13) and then into the drift layer (12), wherein the bottom (41) of the trench (4) is located in the drift layer (12), and then b2. Forming the shielding structure (5) by epitaxially growing the III-nitride material doped with a p-type dopant in the trench.

2. The method according to claim 1, characterized in that The method further includes forming a trench gate (60) laterally separated from the shielding structure (5), comprising: after step b: c. removing the patterned mask layer (2), and Either after step c or in step a, include the following steps: d. providing a further trench (6) extending through the source layer (14) and the body layer (13) and into the drift layer (12), wherein the bottom (61) of the further trench (6) is located in the drift layer (12), and After steps c and d, e. forming the trench gate (60) in the other trench (6) by the following steps: e1. depositing a dielectric material (61) on the surface (63) of the further trench (6), Then, e2. Depositing a conductive material (62) on the dielectric material (61), wherein a height of the bottom (621) of the conductive material (62) within the III-nitride semiconductor stack (1) is lower than a height of the top (121) of the drift layer (12) within the III-nitride semiconductor stack (1).

3. The method according to claim 2, characterized in that A height within the drift layer (12) at the bottom (61) of the further trench (6) is higher than a height within the drift layer (12) at the bottom of the trench (41).

4. The method according to claim 2 or 3, characterized in that The lateral distance separating the trench gate (60) and the shielding structure (5) is from 0.5 μm to 10 μm.

5. The method according to any one of the preceding claims, characterized in that The concentration of the p-type dopant in the shielding structure (5) is 10 16 to 10 20 atoms / cm 3 .

6. The method according to any one of the preceding claims, characterized in that The Group III nitride semiconductor material is gallium nitride.

7. The method according to claim 6, characterized in that The surface (43) of the groove (4) is parallel to a plane belonging to a set of planes with Bravais-Miller indices {1-100}.

8. The method according to any one of the preceding claims, characterized in that In step b2, the trench (4) is completely filled with a Group III nitride semiconductor material doped with a p-type dopant.

9. The method according to any one of the preceding claims, characterized in that Step b is performed without removing the stack (1) from the reaction chamber.

10. The method according to any one of the preceding claims, characterized in that In a plane parallel to the top surface (19) (of the III-nitride semiconductor stack (1)), a cross-section of the shielding structure (5) forms a ring of the III-nitride material doped with a p-type dopant, which surrounds the III-nitride material doped with an n-type dopant.

11. The method according to claim 10 as appended to claim 2, characterized in that The trench gate (60) is formed at the center of the ring.

12. The method according to any one of the preceding claims, characterized in that The patterned mask layer (2) comprises silicon nitride or silicon oxide.

13. The method according to any one of the preceding claims, characterized in that Step b1 includes heating the stack to a temperature of 700 to 1200°C.

14. The method according to any one of the preceding claims, characterized in that in, In step b1, the air in the reaction chamber contains 30 to 80% by volume of H2, 10 to 40% by volume of an inert gas, and 10 to 30% by volume of NH3.

15. Method according to any one of the preceding claims, characterized in that Step b1 includes applying a pressure of 10 to 200 Torr.

16. The method according to any one of the preceding claims, characterized in that Also included between step a and step b is an etching step a' of etching material from the region of the III-nitride semiconductor stack exposed by the second region of the patterned mask layer to form a trench extending through a portion of the thickness of a substack, the substack including the source layer, the body layer and the drift layer, provided that the trench spans at most a portion of the thickness of the drift layer.

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