Firmware updating method

Abstract

The invention discloses a firmware updating method. The firmware updating method comprises the following steps: receiving a firmware updating instruction containing reset type information; responding to the firmware updating instruction, and storing firmware data to a storage unit of the substrate management controller; storing the firmware data to a storage unit of the baseboard management controller, and storing the updated type value to the storage unit of the controller according to the reset type information; and reading the updating type value, and executing a firmware updating program on the substrate management controller according to the updating type value.

Description

Technical Field

[0001] The present invention relates to a remote update method for a baseboard management controller (BMC) by using a warm reset, and more particularly to a firmware update method. Background Art

[0002] Generally speaking, when a machine wants to update the firmware of the Baseboard Management Controller (BMC), the machine will use a cold reset or warm reset to restart the system to update the system. When the machine uses a cold reset, the system operates normally after the update.

[0003] However, when the machine uses a hot boot, the system can still operate normally after the update. However, the timer used to detect the platform controller hub (PCH) in its field programmable gate array (FPGA) cannot be shut down properly. As a result, after the system has been running for a period of time, the timer will time out, causing the FPGA to perform an unexpected system recovery. Summary of the Invention

[0004] In some embodiments, a firmware update method includes: receiving a firmware update command including reset type information; in response to the firmware update command, storing firmware data in a storage unit of a baseboard management controller; after storing the firmware data in the storage unit of the baseboard management controller, storing an update type value in a storage unit of a controller based on the reset type information; and reading the update type value, and executing a firmware update program on the baseboard management controller based on the update type value.

[0005] In some embodiments, the firmware update procedure includes: providing a sleep signal to cause a platform path controller to enter a sleep mode; when the platform path controller enters the sleep mode, updating the baseboard management controller according to the firmware data; when the baseboard management controller completes the update according to the firmware data, providing a wake-up signal to wake up the platform path controller; after waking up the platform path controller, the platform path controller stores first check information to a storage unit of the controller; reading the first check information to confirm whether a boot block of the platform path controller is operating normally; the platform path controller stores second check information to the storage unit of the controller; and reading the second check information to confirm whether a verification code module of the platform path controller is operating normally.

[0006] In some embodiments, the firmware update method further includes: providing a reset signal to reset the platform path controller before providing the sleep signal; starting a first timer in response to the reset signal; and stopping the first timer after confirming that the boot block and the verification code module of the platform path controller are operating normally.

[0007] In some embodiments, the firmware update method further includes: after the baseboard management controller completes the update according to the firmware data, the baseboard management controller stores third inspection information in the storage unit of the controller; and reading the third inspection information to confirm whether the baseboard management controller operates normally.

[0008] In some embodiments, the firmware update method further includes: starting a second timer after the baseboard management controller completes the update according to the firmware data; and stopping the second timer after confirming that the baseboard management controller operates normally.

[0009] In some embodiments, the firmware update procedure includes: updating the baseboard management controller according to the firmware data; when updating the baseboard management controller according to the firmware data, a platform path controller stores first check information to a first storage location of a storage unit of the controller; the platform path controller stores second check information to a second storage location of the storage unit of the controller; reading the first check information to confirm whether a boot block of the platform path controller is operating normally; and reading the second check information to confirm whether a verification code module of the platform path controller is operating normally.

[0010] In some embodiments, the firmware update method further includes: providing a reset signal to reset the platform path controller before updating the baseboard management controller according to the firmware data; starting a first timer in response to the reset signal; and stopping the first timer after confirming that the boot block and the verification code module of the platform path controller are operating normally.

[0011] In some embodiments, the firmware update procedure includes: a platform path controller storing first check information to a storage unit of the controller; reading the first check information to confirm that a boot block of the platform path controller is operating normally; the platform path controller storing second check information to the storage unit of the controller; reading the second check information to confirm that a verification code module of the platform path controller is operating normally; and after confirming that the boot block and the verification code module of the platform path controller are operating normally, updating the baseboard management controller according to the firmware data.

[0012] In some embodiments, the firmware update method further includes: providing a reset signal to reset the platform path controller before the platform path controller stores the first check information in the controller's storage unit; starting a first timer in response to the reset signal; and stopping the first timer after confirming that the boot block and the verification code module of the platform path controller are operating normally.

[0013] Compared with the prior art, the system of any embodiment of the firmware update method of the present invention can read the first check information and the second check information in real time and accurately, thereby preventing the first timer of the system from timing out and causing the system to perform unexpected system recovery.

[0014] The detailed features and advantages of the present invention are described in detail in the following embodiments. The content is sufficient to enable anyone skilled in the relevant art to understand the technical content of the present invention and implement it accordingly. Moreover, based on the content disclosed in this specification, the claims and the drawings, anyone skilled in the relevant art can easily understand the relevant purposes and advantages of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other features and effects of the present invention will be more clearly seen in the following embodiments with reference to the accompanying drawings, in which:

[0016] Figure 1 A block diagram of an embodiment of a system for a firmware update method;

[0017] Figure 2 A flowchart of an embodiment of a method for updating firmware;

[0018] Figure 3 A flowchart of an embodiment of a firmware update procedure;

[0019] Figure 4 A schematic diagram of an embodiment of a firmware update method;

[0020] Figure 5 A schematic diagram of the prior art during hot start;

[0021] Figure 6 A waveform diagram of an embodiment of a reset signal;

[0022] Figure 7 A flowchart of another embodiment of a firmware update procedure;

[0023] Figure 8 A schematic diagram of another embodiment of a firmware update method;

[0024] Figure 9 A schematic diagram of an embodiment of a storage unit of a controller;

[0025] Figure 10 A flowchart of another embodiment of a firmware update procedure; and

[0026] Figure 11 FIG. 1 is a schematic diagram of another embodiment of a firmware update method. DETAILED DESCRIPTION

[0027] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.

[0028] See also Figure 1 . A system 1 suitable for a firmware update method includes a baseboard management controller (BMC) 10, a controller 20, and a platform path controller (PCH) 30. The baseboard management controller 10 is coupled to the platform path controller 30. The controller 20 is coupled to the baseboard management controller 10 and the platform path controller 30. In some embodiments, the controller 20 is a field programmable gate array (FPGA), but the present invention is not limited to this. In some embodiments, the controller 20 may also be a system on chip (SoC) or a complex programmable logic device (CPLD). In some embodiments, the platform path controller 30 is located in the controller 20. The baseboard management controller 10 includes a control unit 11 and a storage unit 12. The controller 20 includes a processing unit 21 and a storage unit 22. The platform path controller 30 includes a boot block 31 and a verification code module 32.

[0029] See also Figure 1 and Figure 2 . In some embodiments, the baseboard management controller 10 is used to receive a firmware update command I1 (step S01) and firmware data D1 including reset type information. In some embodiments, the baseboard management controller 10 directly receives the firmware update command I1 through a local area network (LAN), but the present invention is not limited to this. In some embodiments, the firmware update command I1 is input to the baseboard management controller 10 through an external input device such as a keyboard or a mouse. In some embodiments, the baseboard management controller 10 directly receives the firmware data D1 through a local area network (LAN). In some embodiments, the firmware data D1 is input to the baseboard management controller 10 through an external storage device such as a USB device. In some embodiments, the firmware update command I1 is input to the platform path controller 30 through an external input device such as a keyboard or a mouse, and the firmware data D1 is input to the platform path controller 30 through an external storage device such as a USB device. In this case, the baseboard management controller 10 indirectly receives the firmware update command I1 and the firmware data D1 through the platform path controller 30.

[0030] After receiving the firmware update command I1 and the firmware data D1, the baseboard management controller 10 responds to the firmware update command I1 by storing the firmware data D1 in the storage unit 12 (step S02). In some embodiments, the storage unit 12 may be, but is not limited to, a flash memory utilizing a serial peripheral interface (SPI).

[0031] In some embodiments, the baseboard management controller 10 further includes configuration software. The configuration software includes a reset type menu, which includes multiple reset type options. The firmware update command I1 is generated by the user selecting a reset type option in the reset type menu. For example, the reset type menu includes a cold reset option and a warm reset option. When the user wishes to perform a cold reset on the system 1, the user selects the cold reset option. In this case, the reset type information includes a cold reset. Similarly, when the user wishes to perform a warm reset on the system 1, the user selects the warm reset option. In this case, the reset type information includes a warm reset. In some embodiments, when neither the cold reset option nor the warm reset option is selected, the reset type information includes a cold reset. In some embodiments, the configuration software may be, but is not limited to, an embedded web service. In some embodiments, the configuration software further includes a graphical user interface (GUI), and the user can use the GUI to select a reset type option in the reset type menu.

[0032] In some embodiments, the firmware update command I1 is input by a user into the baseboard management controller 10 by typing on an external keyboard, pressing the power button, or via a local area network (LAN). In some embodiments, the firmware update command I1 is generated by inputting "reset-c" on an external keyboard or pressing the power button twice to perform a cold reboot of the system 1. In this case, the reset type information includes a cold reboot as the reset type. In some embodiments, the firmware update command I1 is generated by inputting "reset-w" or "Ctrl+Alt+Del" on an external keyboard to perform a warm reboot of the system 1. In this case, the reset type information includes a warm reboot as the reset type.

[0033] In some embodiments, the reset type information is included in a command I2 that is different from the firmware update command I1. The baseboard management controller 10 receives the command I2 containing the reset type information only after the firmware data D1 is stored in the storage unit 12. In some embodiments, the command I2 is input by a user into the baseboard management controller 10 by typing on an external keyboard, pressing the power button, or via a local area network (LAN). In some embodiments, the command I2 is input into the platform path controller 30 via an external input device such as a keyboard or mouse. In this case, the baseboard management controller 10 receives the command I2 indirectly through the platform path controller 30.

[0034] After step S02, the baseboard management controller 10 stores the update type value V1 in the storage unit 22 of the controller 20 based on the reset type information (step S03). In some embodiments, the baseboard management controller 10 stores the update type value V1 in the storage unit 22 via the system management bus (SMBus). In some embodiments, the storage unit 22 is a random access memory (RAM), but the present invention is not limited to this. The storage unit 22 can be a volatile storage medium, a non-volatile storage medium, or a combination thereof. A volatile storage medium is, for example, a random access memory (RAM), and a random access memory is, for example, a static random access memory (SRAM) or a dynamic random access memory (DRAM). Non-volatile storage media may include read-only memory (ROM), such as programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), one-time programmable read-only memory (OTPROM), or flash memory. In some embodiments, the update type value V1 may be, but is not limited to, 0x08.

[0035] After the baseboard management controller 10 stores the update type value V1 in the storage unit 22 of the controller 20 based on the reset type information, the processing unit 21 of the controller 20 reads the update type value V1 and executes the firmware update procedure 2 on the baseboard management controller 10 based on the update type value V1 (step S04). In some embodiments, the processing unit 21 supports platform firmware recovery (PFR). In some embodiments, the processing unit 21 can be, but is not limited to, a central processing unit (CPU).

[0036] See also Figure 3 . In some embodiments, first, the processing unit 21 provides a sleep signal S1 to the platform path controller 30, causing the platform path controller 30 to enter the sleep mode (step S21a). After the platform path controller 30 enters the sleep mode, the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1 (step S22a). After the baseboard management controller 10 completes the update according to the firmware data D1, the processing unit 21 provides a wake-up signal S2 to the platform path controller 30 to wake up the platform path controller 30 (step S23a). After the processing unit 21 wakes up the platform path controller 30, the platform path controller 30 stores the first check information CP1 to the storage unit 22 (step S24a), and the processing unit 21 then reads the first check information CP1 stored in the storage unit 22 to confirm whether the boot block 31 of the platform path controller 30 is operating normally (step S25a). After the processing unit 21 confirms whether the boot block 31 of the platform path controller 30 is operating normally, the platform path controller 30 stores the second check information CP2 in the storage unit 22 (step S26a). The processing unit 21 then reads the second check information CP2 stored in the storage unit 22 to confirm whether the verification code module 32 of the platform path controller 30 is operating normally (step S27a).

[0037] In some embodiments, the boot block 31 may be, but is not limited to, an OBB (OEM Boot Block). In some embodiments, the verification code module 32 may be, but is not limited to, an ACM (Authenticated Code Module). In some embodiments, the processing unit 21 may provide the sleep signal S1 to the platform path controller 30 by, but is not limited to, setting a signal received by the platform path controller 30 to a low level. The processing unit 21 may provide the wake-up signal S2 to the platform path controller 30 by, but is not limited to, setting the signal received by the platform path controller 30 to a high level.

[0038] In some embodiments, after the processing unit 21 reads the first inspection information CP1 stored in the storage unit 22, the processing unit 21 clears the data stored in the location of the first inspection information CP1 in the storage unit 22. In some embodiments, the first inspection information CP1 and the second inspection information CP2 are stored in the same location in the storage unit 22. In some embodiments, the values ​​of the first inspection information CP1 and the second inspection information CP2 can be, but are not limited to, 0x09.

[0039] In some embodiments, the controller 20 further includes a first timer. The platform path controller 30 is further configured to provide a reset signal S3 to the processing unit 21 to reset the platform path controller 30 before the processing unit 21 provides the sleep signal S1. In response to the reset signal S3, the processing unit 21 is further configured to reset the platform path controller 30 and activate the first timer. The processing unit 21 is further configured to deactivate the first timer after confirming that the boot block 31 and the verification code module 32 of the platform path controller 30 are functioning properly.

[0040] In some embodiments, the platform path controller 30 is further configured to store the first timer control value in the storage unit 22 of the controller 20 , and the processing unit 21 is further configured to start or stop the first timer according to the first timer control value stored in the storage unit 22 .

[0041] In some embodiments, after the baseboard management controller 10 completes the update based on the firmware data D1, the baseboard management controller 10 is further configured to store third check information CP3 in the storage unit 22. The processing unit 21 is further configured to read the third check information CP3 to confirm whether the baseboard management controller 10 is operating normally. In some embodiments, the value of the third check information CP3 may be, but is not limited to, 0x09. In some embodiments, the third check information CP3 is stored in a different location from the first check information CP1 and the second check information CP2 in the storage unit 22.

[0042] In some embodiments, the controller 20 further includes a second timer. When the baseboard management controller 10 completes the update according to the firmware data D1, the processing unit 21 starts the second timer. After confirming that the baseboard management controller 10 is operating normally, the processing unit 21 stops the second timer.

[0043] In some embodiments, the control unit 11 of the baseboard management controller 10 is further configured to store the second timer control value in the storage unit 22 of the controller 20 , and the processing unit 21 is further configured to enable or disable the second timer according to the second timer control value stored in the storage unit 22 .

[0044] See also Figure 4. At time point T1, the system 1 receives the firmware update command I1 (step S01) and the firmware data D1. At time point T2, the baseboard management controller 10 responds to the firmware update command I1 and stores the firmware data D1 in the storage unit 12 (step S02). At time point T3, the baseboard management controller 10 stores the update type value V1 in the storage unit 22 of the controller 20 according to the reset type information (step S03). At time point T4, the processing unit 21 of the controller 20 reads the update type value V1 and executes the firmware update program 2 on the baseboard management controller 10 according to the update type value V1 (step S04), the platform path controller 30 provides a reset signal S3 to the processing unit 21 to reset the platform path controller 30, and the processing unit 21 responds to the reset signal S3, resets the platform path controller 30 and starts the first timer. At time point T4 a , the processing unit 21 provides a sleep signal S1 to the platform path controller 30, causing the platform path controller 30 to enter the sleep mode (step S21a), and the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1 (step S22a). At time point T7, the baseboard management controller 10 completes the update according to the firmware data D1, and the processing unit 21 starts the second timer. In other words, at time point T4 a The time period P2 to the time point T7 is the time during which the baseboard management controller 10 is updated according to the firmware data D1 .

[0045] At time point T8, the processing unit 21 provides a wake-up signal S2 to the platform path controller 30 to wake up the platform path controller 30 (step S23a). The baseboard management controller 10 stores the third check information CP3 in the storage unit 22, and the processing unit 21 reads the third check information CP3 to confirm whether the baseboard management controller 10 is operating normally. After the processing unit 21 confirms that the baseboard management controller 10 is operating normally, the processing unit 21 stops the second timer. In other words, at time point T4 a The time period P3 to the time point T8 is the time when the platform path controller 30 is in the sleep mode.

[0046] At time T9, the platform path controller 30 stores the first check information CP1 in the storage unit 22 (step S24a). The processing unit 21 then reads the first check information CP1 stored in the storage unit 22 to confirm whether the boot block 31 of the platform path controller 30 is operating normally (step S25a). After the processing unit 21 confirms whether the boot block 31 of the platform path controller 30 is operating normally, the processing unit 21 clears the data stored in the location of the first check information CP1 in the storage unit 22. At time T11, the platform path controller 30 stores the second check information CP2 in the storage unit 22 (step S26a). The first check information CP1 and the second check information CP2 are stored in the same location in the storage unit 22. The processing unit 21 then reads the second check information CP2 stored in the storage unit 22 to confirm whether the verification code module 32 of the platform path controller 30 is operating normally (step S27a). After confirming that the boot block 31 and the verification code module 32 of the platform path controller 30 are operating normally, the processing unit 21 stops the first timer. In other words, the time period P4 from the time point T8 to the time point T11 is the time when the platform path controller 30 is not in the sleep mode (ie, the working mode).

[0047] See also Figures 4 to 6 . In the prior art, the FPGA of the system starts to update its baseboard management controller after receiving the reset signal S3 at time point T4. At time point T5, the platform path controller of the prior art stores the first check information CP1 in the storage unit of the FPGA. At time point T6, the platform path controller of the prior art stores the second check information CP2 in the storage unit of the FPGA. However, at time point T5 and time point T6, the FPGA of the prior art is busy because it is updating the baseboard management controller, so it cannot read the first check information CP1 and the second check information CP2. The FPGA of the prior art completes the update of the baseboard management controller at time point T7. In other words, the time segment P0 from time point T4 to time point T7 is the time when the baseboard management controller of the prior art is updated according to the firmware data D1.

[0048] When the prior art FPGA completes the baseboard management controller update and reads the first check information CP1 at time T9, because the first check information CP1 and the second check information CP2 are stored in the same location, the information read at this time actually overwrites the first check information CP1 with the second check information CP2. After reading this information, the prior art FPGA is unable to read the second check information at time T11, causing the prior art platform path controller to time out at time T10 and perform an unintended system recovery. In the prior art, during the time period P1 from time T4 to time T10, the prior art platform path controller is in operating mode.

[0049] Because the platform path controller 30 is in sleep mode during time period P3, the platform path controller 30 does not store the first inspection information CP1 and the second inspection information CP2 in the storage unit 22 at time points T5 and T6. Instead, the platform path controller 30 stores the first inspection information CP1 in the storage unit 22 at time point T9 and the second inspection information CP2 in the storage unit 22 at time point T11. Furthermore, because the processing unit 21 has completed updating the baseboard management controller 10 at time points T9 and T11, the processing unit 21 can read the first inspection information CP1 and the second inspection information CP2 in real time at time points T9 and T11, thereby preventing the first timer of the system 1 from timing out at time point T10, as in the prior art, causing the system 1 to perform an unexpected system recovery.

[0050] See also Figure 7 and Figure 9 . In some embodiments, first, the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1 (step S21b). When the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1, the platform path controller 30 stores the first check information CP1 to the first storage location 2221 of the storage unit 22 (step S22b) and stores the second check information CP2 to the second storage location 2222 of the storage unit 22 (step S23b). After the baseboard management controller 10 completes the update according to the firmware data D1, the processing unit 21 reads the first check information CP1 stored in the storage unit 22 to confirm whether the boot block 31 of the platform path controller 30 is operating normally (step S24b) and reads the second check information CP2 stored in the storage unit 22 to confirm whether the verification code module 32 of the platform path controller 30 is operating normally (step S25b).

[0051] In some embodiments, the platform path controller 30 is further configured to provide a reset signal S3 to the processing unit 21 to reset the platform path controller 30 before the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1. The processing unit 21 is further configured to respond to the reset signal S3 by resetting the platform path controller 30 and starting a first timer. The processing unit 21 is further configured to stop the first timer after confirming that the boot block 31 and the verification code module 32 of the platform path controller 30 are functioning properly.

[0052] In some embodiments, after the BMC 10 completes the update according to the firmware data D1, the BMC 10 further stores the third check information CP3 in the third storage location 2223 of the storage unit 22. The processing unit 21 further reads the third check information CP3 to confirm whether the BMC 10 operates normally.

[0053] See also Figure 8 . At time point T1, the system 1 receives a firmware update command I1 (step S01) and firmware data D1. At time point T2, the baseboard management controller 10 responds to the firmware update command I1 and stores the firmware data D1 in the storage unit 12 (step S02). At time point T3, the baseboard management controller 10 stores the update type value V1 in the storage unit 22 of the controller 20 according to the reset type information (step S03). At time point T4, the processing unit 21 of the controller 20 reads the update type value V1 and executes the firmware update program 2 on the baseboard management controller 10 according to the update type value V1 (step S04), the platform path controller 30 provides a reset signal S3 to the processing unit 21 to reset the platform path controller 30, and the processing unit 21 responds to the reset signal S3, resets the platform path controller 30 and starts the first timer, and the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1 (step S21b).

[0054] At time T5, the platform path controller 30 stores the first check information CP1 in the first storage location 2221 of the storage unit 22 (step S22b). At time T6, the platform path controller 30 stores the second check information CP2 in the second storage location 2222 of the storage unit 22 (step S23b). At time T7, the baseboard management controller 10 completes the update based on the firmware data D1, and the processing unit 21 starts the second timer. At time T8, the baseboard management controller 10 stores the third check information CP3 in the third storage location 2223 of the storage unit 22, and the processing unit 21 reads the third check information CP3 to confirm whether the baseboard management controller 10 is operating normally. After the processing unit 21 confirms that the baseboard management controller 10 is operating normally, the processing unit 21 stops the second timer. At time T9, the processing unit 21 reads the first check information CP1 stored in the first storage location 2221 of the storage unit 22 to confirm whether the boot block 31 of the platform path controller 30 is operating normally (step S24b). At time T11, the processing unit 21 reads the second check information CP2 stored in the second storage location 2222 of the storage unit 22 to confirm whether the verification code module 32 of the platform path controller 30 is operating normally (step S25b). After confirming that the boot block 31 and the verification code module 32 of the platform path controller 30 are operating normally, the processing unit 21 stops the first timer. During the time period P5 from time T4 to time T11, the platform path controller 30 is in the operating mode.

[0055] See also Figure 9In some embodiments, storage unit 22 includes multiple addresses 221 and multiple data locations 222. Multiple addresses 221 include a first address 2211, a second address 2212, and a third address 2213. Multiple data locations 222 include a first storage location 2221, a second storage location 2222, and a third storage location 2223. First address 2211 corresponds to first storage location 2221. Second address 2212 corresponds to second storage location 2222. Third address 2213 corresponds to third storage location 2223. First storage location 2221 is used to store first check information CP1. Second storage location 2222 is used to store second check information CP2. Third storage location 2223 is used to store third check information CP3. In some embodiments, multiple addresses 221 further include a fourth address 2214, and multiple data locations 222 further include a fourth storage location 2224. Fourth address 2214 corresponds to fourth storage location 2224. In some embodiments, fourth storage location 2224 is used to store update type value V1.

[0056] Since the first inspection information CP1 is stored in the first storage location 2221 of the storage unit 22 and the second inspection information CP2 is stored in the second storage location 2222 of the storage unit 22, the first inspection information CP1 and the second inspection information CP2 are stored in different locations of the storage unit 22. Therefore, the second inspection information CP2 will not overwrite the first inspection information CP1. The processing unit 21 can correctly read the second inspection information at time point T11, thereby preventing the first timer of the system 1 from timing out at time point T10, as in the prior art, causing the system 1 to perform an unintended system recovery.

[0057] See also Figure 10 . In some embodiments, first, the platform path controller 30 stores the first inspection information CP1 to the storage unit 22 (step S21c). After the platform path controller 30 stores the first inspection information CP1 to the storage unit 22, the processing unit 21 reads the first inspection information CP1 stored in the storage unit 22 to confirm whether the boot block 31 of the platform path controller 30 is operating normally (step S22c). Then, the platform path controller 30 stores the second inspection information CP2 to the storage unit 22 (step S23c). After the platform path controller 30 stores the second inspection information CP2 to the storage unit 22, the processing unit 21 reads the second inspection information CP2 stored in the storage unit 22 to confirm whether the verification code module 32 of the platform path controller 30 is operating normally (step S24c). After confirming that the boot block 31 and the verification code module 32 of the platform path controller 30 are operating normally, the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1 (step S25c).

[0058] In some embodiments, the platform path controller 30 is further configured to provide a reset signal S3 to the processing unit 21 to reset the platform path controller 30 before the platform path controller 30 stores the first check information CP1 in the storage unit 22. In response to the reset signal S3, the processing unit 21 is further configured to reset the platform path controller 30 and start a first timer. After confirming that the boot block 31 and the verification code module 32 of the platform path controller 30 are functioning properly, the processing unit 21 is further configured to stop the first timer.

[0059] See also Figure 11 . At time point T1, the system 1 receives a firmware update command I1 (step S01) and firmware data D1. At time point T2, the baseboard management controller 10 responds to the firmware update command I1 and stores the firmware data D1 in the storage unit 12 (step S02). At time point T3, the baseboard management controller 10 stores the update type value V1 in the storage unit 22 of the controller 20 according to the reset type information (step S03). At time point T4, the processing unit 21 of the controller 20 reads the update type value V1 and executes the firmware update program 2 on the baseboard management controller 10 according to the update type value V1 (step S04), the platform path controller 30 provides a reset signal S3 to the processing unit 21 to reset the platform path controller 30, and the processing unit 21 responds to the reset signal S3, resets the platform path controller 30 and starts the first timer.

[0060] At time T5, the platform path controller 30 stores the first check information CP1 in the storage unit 22 (step S21c). The processing unit 21 then reads the first check information CP1 stored in the storage unit 22 to confirm whether the boot block 31 of the platform path controller 30 is operating normally (step S22c). At time T6, the platform path controller 30 stores the second check information CP2 in the storage unit 22 (step S23c). The processing unit 21 then reads the second check information CP2 stored in the storage unit 22 to confirm whether the verification code module 32 of the platform path controller 30 is operating normally (step S24c). After confirming that the boot block 31 and verification code module 32 of the platform path controller 30 are operating normally, the processing unit 21 updates the baseboard management controller 10 according to the firmware data D1 (step S25c) and deactivates the first timer. At time T7, the baseboard management controller 10 completes the update according to the firmware data D1, and the processing unit 21 starts the second timer. At time T8, the baseboard management controller 10 stores the third check information CP3 in the storage unit 22, and the processing unit 21 reads the third check information CP3 to confirm whether the baseboard management controller 10 is operating normally. After the processing unit 21 confirms that the baseboard management controller 10 is operating normally, the processing unit 21 stops the second timer. The time period P6 from time T6 to time T7 is the time when the baseboard management controller 10 is updated according to the firmware data D1. During the time period P7 from time T4 to time T8, the platform path controller 30 is in the operating mode.

[0061] It is particularly noted that the time intervals between the time points T1 to T11 are not necessarily fixed. They are only used to indicate the time sequence of the actions, rather than limiting the actions corresponding to the time points to occur at fixed time points.

[0062] Because the platform path controller 30 updates the baseboard management controller 10 according to the firmware data D1 only after confirming that the boot block 31 and verification code module 32 of the platform path controller 30 are functioning properly, the processing unit 21 is not busy during the update of the baseboard management controller 10, preventing it from reading the first and second check information CP1 and CP2. The processing unit 21 can read the first and second check information CP1 and CP2 in real time at time points T5 and T6, thereby preventing the first timer of the system 1 from timing out at time point T10, as in the prior art, causing the system 1 to perform an unintended system recovery.

[0063] In summary, the system 1 of any embodiment can read the first inspection information CP1 and the second inspection information CP2 in real time and accurately, thereby preventing the first timer of the system 1 from timing out and causing the system 1 to perform unexpected system recovery.

[0064] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for updating firmware, characterized in that: Include: receiving a firmware update command including reset type information; In response to the firmware update instruction, storing firmware data in a storage unit of a baseboard management controller; After storing the firmware data in the storage unit of the baseboard management controller, an update type value is stored in a storage unit of a controller according to the reset type information; and The update type value is read, and a firmware update procedure is executed on the baseboard management controller according to the update type value.

2. The firmware update method according to claim 1, wherein: The firmware update process includes: providing a sleep signal to cause a platform path controller to enter a sleep mode; When the platform path controller enters the sleep mode, updating the baseboard management controller according to the firmware data; After the baseboard management controller completes the update according to the firmware data, it provides a wake-up signal to wake up the platform path controller; After waking up the platform path controller, the platform path controller stores first inspection information in a storage unit of the controller; Reading the first inspection information to confirm whether a boot block of the platform path controller operates normally; The platform path controller stores second inspection information in the storage unit of the controller; and The second inspection information is read to confirm whether a verification code module of the platform path controller operates normally.

3. The firmware update method according to claim 2, wherein: Also includes: Before providing the sleep signal, providing a reset signal to reset the platform path controller; In response to the reset signal, starting a first timer; and After confirming that the boot block and the verification code module of the platform path controller operate normally, the first timer is turned off.

4. The firmware update method according to claim 1, wherein: Also includes: When the baseboard management controller completes the update according to the firmware data, the baseboard management controller stores a third inspection information in the storage unit of the controller; and The third inspection information is read to confirm whether the baseboard management controller operates normally.

5. The firmware updating method according to claim 4, wherein: Also includes: When the baseboard management controller completes updating according to the firmware data, starting a second timer; and After confirming that the baseboard management controller operates normally, the second timer is turned off.

6. The firmware updating method according to claim 1, wherein: The firmware update process includes: updating the baseboard management controller according to the firmware data; When the baseboard management controller is updated according to the firmware data, a platform path controller stores first inspection information in a first storage location of a storage unit of the controller; The platform path controller stores a second inspection information in a second storage location of the storage unit of the controller; Reading the first inspection information to confirm whether a boot block of the platform path controller operates normally; and The second inspection information is read to confirm whether a verification code module of the platform path controller operates normally.

7. The firmware updating method according to claim 6, wherein: Also includes: Before updating the baseboard management controller according to the firmware data, providing a reset signal to reset the platform path controller; In response to the reset signal, starting a first timer; and After confirming that the boot block and the verification code module of the platform path controller operate normally, the first timer is turned off.

8. The firmware updating method according to claim 1, wherein: The firmware update process includes: A platform path controller stores first inspection information in a storage unit of the controller; Reading the first check information to confirm that a boot block of the platform path controller operates normally; The platform path controller stores second inspection information in the storage unit of the controller; Reading the second inspection information to confirm that a verification code module of the platform path controller is operating normally; and After confirming that the boot block and the verification code module of the platform path controller operate normally, the baseboard management controller is updated according to the firmware data.

9. The firmware updating method according to claim 8, wherein: Also includes: Before the platform path controller stores the first inspection information in the storage unit of the controller, providing a reset signal to reset the platform path controller; In response to the reset signal, starting a first timer; and After confirming that the boot block and the verification code module of the platform path controller operate normally, the first timer is turned off.

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