Memory operation instruction processing method, loading storage unit and processor system

Abstract

The embodiment of the invention provides a memory operation instruction processing method, a loading storage unit and a processor system, and relates to the technical field of micro-system structures. The method is applied to a loading storage unit LSU in a processor system, the processor system further comprises a processing unit PU and a memory subsystem MS, the processor system applies a memory mark extension MTE function, and the method comprises the steps that a memory operation instruction input by the PU is analyzed, operation instruction information is obtained and cached, a target cache line to which a target memory block belongs is determined, and the target cache line is used for storing the target memory block. If a target label set corresponding to a cached target cache line in the LSU is determined, an actual label of a target memory block is acquired from the target label set, if the actual label of the target memory block is determined to be the same as a target verification label, verification is determined to be successful, and when the MTE function is achieved, the cache line is taken as a unit, and when the LSU processes the first memory operation instruction, the verification is successful. And the tag set corresponding to the cache line is obtained from the MS and cached, so that delay caused by repeated interaction with the MS can be effectively reduced, and the performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of microarchitecture technology, and in particular, to a memory operation instruction processing method, a load storage unit, and a processor system. Background Art

[0002] Memory Tagging Extension (MTE) is a new feature added to the ARMv8.5-A architecture to alleviate memory safety issues. It detects and prevents memory errors such as buffer overflows and use-after-free by assigning tags to memory.

[0003] However, considering the application of the MTE function, each time the memory is accessed, a tag needs to be checked to verify whether the access is valid, which will increase the latency of the memory access and lead to performance degradation. Summary of the Invention

[0004] The embodiments of the present disclosure provide a memory operation instruction processing method, a load storage unit, and a processor system, which are used to solve the technical problem in the prior art that the application of the memory tag extension (MTE) function in the processor system may lead to performance degradation.

[0005] According to one aspect of an embodiment of the present disclosure, a method for processing memory operation instructions is provided. The method is applied to a load store unit (LSU) in a processor system. The processor system further includes a processing unit (PU) and a memory subsystem (MS). The processor system applies a memory tag extension (MTE) function. The method includes: Parse the memory operation instruction input by the PU, obtain and cache the operation instruction information, which includes the target physical address and the target check tag. The target check tag is the tag to be checked of the target memory block to which the target physical address belongs. Determine the target cache line to which the target memory block belongs. If it is determined that the target tag set corresponding to the target cache line has been cached in the LSU, obtain the actual tag of the target memory block from the target tag set. The target tag set is obtained and cached from the MS by the LSU when processing the first memory operation instruction corresponding to the target cache line. The MS includes multiple cache lines. The tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line. If it is determined that the actual tag of the target memory block is the same as the target verification tag, then the verification is determined to be successful.

[0006] According to another aspect of an embodiment of the present disclosure, a load storage unit is provided, including: The instruction processing module is used to parse the memory operation instructions input by the PU, obtain and cache the operation instruction information, which includes the target physical address and the target check tag. The target check tag is the tag to be checked of the target memory block to which the target physical address belongs; A data cache module is configured to determine a target cache line to which a target memory block belongs. If it is determined that a target tag set corresponding to the target cache line has been cached in the LSU, the module obtains the actual tag of the target memory block from the target tag set. The target tag set is obtained and cached from the MS by the LSU when processing the first memory operation instruction corresponding to the target cache line. The MS includes multiple cache lines, and the tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line. The tag verification module is used to determine that the verification is successful if it is determined that the actual tag of the target memory block is the same as the target verification tag.

[0007] According to another aspect of an embodiment of the present disclosure, there is provided a processor system, comprising: at least one load-store unit; The load storage unit implements the memory operation instruction processing method provided by any of the above embodiments when executing.

[0008] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory, and the processor executes the computer program to implement the memory operation instruction processing method provided in any of the above embodiments.

[0009] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the memory operation instruction processing method provided by any of the above embodiments is implemented.

[0010] According to one aspect of an embodiment of the present disclosure, a computer program product is provided, including a computer program, which implements the memory operation instruction processing method provided in any of the above embodiments when the computer program is executed by a processor.

[0011] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects: When implementing the MTE function, the LSU uses cache lines as units. When processing the first memory operation instruction, it obtains the corresponding tag set of the cache line from the MS and caches it locally. Compared with the method of obtaining the actual tag from the MS in units of memory blocks, it can effectively reduce the delay caused by repeated interaction with the MS, thereby improving performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for describing the embodiments of the present disclosure.

[0013] Figure 1 A schematic diagram of a processor system structure provided by an embodiment of the present disclosure; Figure 2 A flowchart of a method for processing memory operation instructions provided by an embodiment of the present disclosure; Figure 3 A flow chart of a method for processing a load instruction provided by an embodiment of the present disclosure; Figure 4 A flowchart of a storage instruction processing method provided by an embodiment of the present disclosure; Figure 5 A flowchart of a method for writing data to be stored provided in an embodiment of the present disclosure; Figure 6 A schematic structural diagram of a load storage unit provided in an embodiment of the present disclosure; Figure 7 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] The following describes the embodiments of the present application in conjunction with the drawings in this application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions used to explain the technical solutions of the embodiments of the present disclosure and do not constitute a limitation on the technical solutions of the embodiments of the present disclosure.

[0015] Those skilled in the art will understand that, unless otherwise stated, the singular forms "a", "an", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present disclosure mean that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements, and / or components, but do not exclude implementation as other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element, or it can refer to the connection relationship between the element and the other element established through an intermediate element. In addition, the "connection" or "coupling" used here can include wireless connection or wireless coupling. The term "and / or" used here indicates at least one of the items defined by the term, for example, "A and / or B" can be implemented as "A", or as "B", or as "A and B".

[0016] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0017] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present disclosure and the technical effects produced by the technical solutions of the present disclosure. It should be noted that the following embodiments can refer to, draw on, or combine with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0018] The following is an introduction and explanation of the relevant technologies involved in this application: Memory Tagging Extension (MTE) is a new feature added to the ARMv8.5-A architecture to detect memory safety violations and provide enhanced protection against attacks that exploit these violations.

[0019] The MTE function implements a lock and key access mechanism for memory, tracking memory usage by adding tags during memory allocation. Each 16-byte memory block is assigned a 4-bit metadata tag, which acts as the memory lock (the actual tag stored). When accessing memory, the corresponding key (the checksum tag carried in the memory operation instruction) is required to access the memory subsystem (MS) to find and obtain the corresponding lock for the memory block. If the key and lock match, the checksum is considered successful. If they do not match, the checksum fails, thereby detecting and preventing memory errors.

[0020] More specifically, the MTE function can be divided into precise MTE and imprecise MTE.

[0021] For inexact MTE, when memory access is performed and verification fails, an error is returned, but the next step is still processed without affecting data loading and storage.

[0022] Precise MTE can be configured to raise a synchronous exception, return an error, and not proceed to the next step when a memory access fails verification. Precise MTE is designed to provide the most information about the fault location, but it typically introduces additional latency to instruction execution, especially for store instructions. Therefore, enabling precise MTE will result in a certain degree of performance degradation.

[0023] Based on the technical problem of the above-mentioned precise MTE causing performance degradation due to additional delay, the embodiments of the present disclosure provide a memory operation instruction processing method to solve or partially solve the above-mentioned problem.

[0024] Figure 1 A schematic diagram of a processor system structure provided by an embodiment of the present disclosure is shown in FIG. Figure 1As shown, the processor system in the embodiment of the present disclosure includes a processing unit (PU), a memory subsystem (MS, also called a storage system) and a load store unit (LSU).

[0025] Among them, PU refers to the core component that performs calculations and logical operations, used to process data and execute programs, MS is responsible for storing and retrieving data, and LSU is the bridge between PU and MS. LSU is responsible for executing memory operation instructions sent by PU, reading data from MS or writing data in MS.

[0026] Specifically, memory operation instructions are used to transfer data between the PU's registers and the MS, including load instructions and store instructions. Load instructions are used to read data from the MS and load it into a register, while store instructions are used to write data from a register to a specific address in the MS.

[0027] It is understandable that from the perspective of microarchitecture chip design, the processor system can refer to a whole composed of a processor, memory, input and output devices, and various controllers and interfaces, such as SoC (System on Chip), AI (Artificial Intelligence) chip, etc.

[0028] The processor system can be a multi-core processor integrated by multiple processor cores, or a multi-processor integrated by multiple single-core processors or multi-core processors. Depending on the integration method of the processor system, the specific type of PU can be a processor core, a processor core cluster, and a processor.

[0029] The type of processor can be a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), an NPU, etc. If the processor system is integrated by multiple processors, the types of each processor can be different. The number of PUs and LSUs included in the corresponding processor system can be determined according to actual needs. The embodiments of the present disclosure do not limit this.

[0030] The memory operation instruction processing method provided by the embodiment of the present disclosure is executed by the load storage unit LSU in the processor system. The processor system also includes a processing unit PU and a memory subsystem MS, and the processor system applies the memory tag extension MTE function. When implementing the memory operation instruction processing method provided by the embodiment of the present disclosure, the specific hardware structure adopted by the processor system can be determined according to actual needs, and the embodiment of the present disclosure does not limit this.

[0031] Figure 2 A flow chart of a memory operation instruction processing method provided by an embodiment of the present disclosure is shown as follows: Figure 2 As shown, the method includes: Step S201 , parsing the memory operation instruction input by the PU, obtaining and caching the operation instruction information, where the operation instruction information includes a target physical address and a target check tag.

[0032] The target verification tag is a tag to be verified of the target memory block to which the target physical address belongs.

[0033] Specifically, in the embodiment of the present disclosure, the memory operation instruction may refer to a load instruction or a store instruction, and the method provided in this embodiment is applied to the memory operation instruction that requires tag verification when implementing the memory tag extension (MTE) function.

[0034] It should be noted that the specific method by which the LSU determines whether a memory operation instruction requires tag verification can be determined based on the actual requirements of the hardware architecture and operating system design.

[0035] Taking the processing unit sending any memory operation instruction as an example, the memory operation instruction processing method provided by the embodiment of the present disclosure is described in detail.

[0036] It is understandable that the memory operation instructions (including load instructions and store instructions) sent by the processing unit usually use virtual addresses (i.e. logical addresses), which is the address space used by applications and operating systems, and provides a continuous address range. After obtaining the memory operation instruction, the LSU needs to parse the virtual address and convert the virtual address into a physical address before it can access the actual physical memory.

[0037] In the embodiment of the present disclosure, in order to implement the MTE function, it is also necessary to obtain the check tag corresponding to the memory operation instruction. The method of determining the check tag includes but is not limited to being directly carried by the virtual address (such as certain bits in the virtual address are used to carry the tag, or containing metadata fields for carrying the tag, etc.), or being assisted by the memory management unit (Memory Management Unit, referred to as MMU) (such as the MMU contains relevant information for assisting in determining whether tag verification is required. In the process of converting the virtual address into the physical address, the MMU assists in determining whether the currently provided virtual address carries a valid check tag based on the relevant information), etc.

[0038] The PU sends a memory operation instruction to the LSU. In step S201, the LSU parses the memory operation instruction input by the PU, obtains the operation instruction information (including the target physical address and the target check tag), and caches the operation instruction information locally in the LSU.

[0039] Accordingly, the specific way in which the LSU parses the memory operation instruction is related to the way in which the label in the memory operation instruction is carried. The specific type depends on the specific hardware architecture and operating system design and can be determined according to actual needs. The embodiment of the present disclosure does not limit this.

[0040] The target verification tag is a tag to be verified of the target memory block to which the target physical address belongs.

[0041] It can be understood that each memory block corresponds to 16 bytes, and there may be more than one target memory block and more than one corresponding target cache line to which the target physical address corresponding to the memory operation instruction belongs. At this time, the number of target memory blocks is multiple, and the target verification tag is the tag to be verified corresponding to each target memory block. Accordingly, the method steps provided in the embodiment of the present disclosure are executed for each target cache line involved.

[0042] Step S202 : determining a target cache line to which the target memory block belongs. If it is determined that a target tag set corresponding to the target cache line has been cached in the LSU, obtaining an actual tag of the target memory block from the target tag set.

[0043] Among them, the target tag set is obtained and cached from the MS by the LSU when processing the first memory operation instruction corresponding to the target cache line. The MS includes multiple cache lines, and the tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line.

[0044] Specifically, a cache line is the smallest storage unit managed by the cache and can store 64 consecutive bytes. That is, one cache line maps to four memory blocks, and the data stored in the cache line includes the data stored in the corresponding physical address of each memory block included in the cache line.

[0045] The MS includes multiple cache lines, each cache line corresponds to four memory blocks, and each memory block corresponds to an actual tag for tag verification, that is, the tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line.

[0046] In step S202, the LSU determines the cache line to which the target memory block belongs as the target cache line based on the mapping relationship between the cache line and the memory block. It can be understood that when the target memory block refers to multiple memory blocks, the number of target cache lines to which the target memory block belongs can be one or more, and the specific number is determined according to the actual situation of the cache lines to which the multiple memory blocks indicated by the target cache line belong.

[0047] For example, when the target memory block indicates three memory blocks, if the three memory blocks all belong to the same cache line, the number of target cache lines is one; if the three memory blocks respectively belong to two cache lines, the number of target cache lines is two.

[0048] It will be appreciated that in the disclosed embodiments, for any cache line, when the LSU processes the first memory operation instruction corresponding to that cache line, it will retrieve the tag set corresponding to that cache line from the MS and cache the tag set locally in the LSU. The tag set includes the actual tags of each memory block included in the corresponding cache line. In other words, the target tag set is retrieved and cached by the LSU from the MS when processing the first memory operation instruction corresponding to the target cache line.

[0049] After the LSU determines the target cache line, for each target cache line, it searches the LSU local cache to see whether the target tag set corresponding to the target cache line has been cached. Based on whether the LSU has cached the target tag set corresponding to the target cache line locally, it can be determined whether the memory operation instruction currently processed by the LSU is the first memory operation instruction corresponding to the target cache line.

[0050] In the disclosed embodiments, the first memory operation instruction refers to the first memory operation instruction that instructs the execution of a read or write operation for a cache line when the LSU does not locally cache the corresponding tag set, including the first load instruction that instructs the execution of a read operation for the data corresponding to the corresponding physical address in the cache line, or the first store instruction that instructs the execution of a write operation for the corresponding physical address in the cache line. In other words, the first memory operation instruction may also refer to the first memory operation instruction that instructs the execution of a read or write operation for the corresponding data in the cache line after the previous round of cache data deletion.

[0051] In step S202, if it is determined that the target tag set corresponding to the target cache line is cached in the LSU, it can be determined that the memory operation instruction currently processed by the LSU is not the first memory operation instruction corresponding to the target cache line, then the actual tag of the target memory block is obtained from the target tag set locally cached by the LSU.

[0052] It should be noted that the memory subsystem MS usually includes multiple levels of cache (level 1 (L1) cache, level 2 (L2) cache, level 3 (L3) cache) and main memory. In modern processor architectures, especially high-performance processors, in order to reduce the latency of memory access and improve performance, the L1 cache will be implemented and utilized as much as possible.

[0053] In the disclosed embodiment, when the LSU obtains the target tag set from the MS, it adopts a certain sequential reading and reads data from the multi-level cache level by level (first L1 cache, then L3 cache). If the reading is unsuccessful, the data is finally read from the main memory.

[0054] That is, the L1 cache is checked first. If it is determined that the data is not in the L1 cache, the L2 cache is checked. If it is determined that the data is not in the L2 cache, the L3 cache is checked. If it is determined that the data is not in the L3 cache, the data is read from the main memory and loaded into the multi-level cache (L3 cache first, L1 cache last).

[0055] In the disclosed example, the LSU interacts directly with the PU to process memory operation instructions. The L1 cache is hierarchically divided into the memory subsystem and is not directly included in the LSU. The above hierarchical division does not directly affect the behavior of the L1 cache and LSU, facilitating a more accurate and clear description of the LSU's behavior.

[0056] It is understandable that since the LSU directly accesses the L1 cache and controls the read and write behavior of the L1 cache, for the sake of convenient maintenance and agile development, the L1 cache will be classified into the LSU in the hierarchical division of certain processor architectures. This hierarchical division method does not affect the functional implementation and performance of the processor, and does not affect the memory operation instruction processing method provided by the embodiment of the present disclosure.

[0057] Step S203: If it is determined that the actual tag of the target memory block is the same as the target verification tag, then it is determined that the verification is successful.

[0058] For each target memory block, after obtaining the actual tag of the target memory block, the actual tag of the target memory block is compared with the target verification tag to determine whether the tag verification is successful.

[0059] In step S203, if it is determined that the actual tag of the target memory block is the same as the target verification tag, the verification is determined to be successful, and accordingly, the instruction is executed according to the specific type of the target operation instruction and the corresponding operation instruction information.

[0060] It can be understood that in the technical solution of the embodiment of the present disclosure, for multiple memory operation instructions corresponding to each cache line, interaction with the MS is performed only when the LSU processes the first memory operation instruction corresponding to the cache line. When processing a non-first memory operation instruction, it is only necessary to obtain the target check tag of the target memory block corresponding to the cached memory operation instruction from the local LSU, and there is no need to interact with the MS again.

[0061] The technical solution provided by the embodiment of the present disclosure uses cache lines as units when implementing the MTE function. When the LSU processes the first memory operation instruction, it obtains the corresponding tag set of the cache line from the MS and caches it locally on the LSU. Compared with the method of obtaining the actual tag from the MS in units of memory blocks, it can effectively reduce the delay caused by repeated interactions with the MS, thereby improving performance.

[0062] In a possible implementation, after determining the target cache line to which the target memory block belongs, the following steps are included: If it is determined that the target tag set corresponding to the target cache line is not cached in the LSU, the target tag set is obtained from the MS and cached, and the actual tag of the target memory block is obtained from the target tag set; If it is determined that the actual tag of the target memory block is the same as the target verification tag, then the verification is determined to be successful.

[0063] Specifically, after the LSU determines the target cache line, for each target cache line, if it is determined that the target tag set corresponding to the target cache line is not cached in the LSU, and it can be determined that the memory operation instruction currently processed by the LSU is the first memory operation instruction corresponding to the target cache line, then the target tag set is obtained from the MS and cached.

[0064] And obtain the actual label of the target memory block from the target label set, compare the actual label of the target memory block with the target verification label to determine whether the label verification is successful, and accordingly, execute the instruction according to the specific type of the target operation instruction and the corresponding operation instruction information.

[0065] The technical solution provided by the disclosed embodiments implements the MTE function by acquiring and caching the target tag set corresponding to the target cache line from the MS only once, when processing the first memory operation instruction. This allows the LSU to subsequently acquire the cached actual tags locally from the LSU when processing non-first memory operation instructions, eliminating the need for further interaction with the MS. When multiple memory operation instructions access the same cache line, non-first load instructions no longer require additional delays, effectively reducing the delay caused by repeatedly acquiring actual tags and data per memory block, thereby improving performance.

[0066] It is understandable that when implementing the MTE function provided by the existing technology, when multiple storage instructions access the same cache line, each storage instruction needs to obtain the actual tag corresponding to the memory block from the MS. Each storage instruction has a latency of accessing the MS, which has a huge impact on performance, especially for typical functions such as MEMSET (a function in the C and C++ language standard libraries for memory initialization).

[0067] When implementing the MTE function, the memory operation instruction processing method provided by the embodiment of the present disclosure is adopted. When multiple storage instructions access the same cache line, it is only necessary to interact with the MS once, and obtain the tag set corresponding to the cache line from the MS. There is only one delay in accessing the MS. The more storage instructions are used to access the cache line, the greater the performance gain.

[0068] For example, when multiple store instruction handle tag checks are used, the total latency required using the prior art MTE function is:

[0069] When the MTE function provided by the embodiment of the present disclosure is used, the total delay required is:

[0070] In the formula, M is the number of store instructions; T0 is the inherent LSU pipeline delay; and T1 is the system latency for accessing memory.

[0071] It is understandable that when the type of memory operation instruction is a storage instruction, the above formula still holds true. The technical solution provided by the embodiment of the present disclosure can effectively reduce the latency in processing both types of memory operation instructions.

[0072] In one possible implementation, the memory operation instruction is a load instruction; After confirming that the verification is successful, it also includes: The data stored at the target physical address is obtained from the MS, and the data stored at the target physical address is transmitted to the PU.

[0073] Specifically, Figure 3 A flow chart of a method for processing a load instruction provided by an embodiment of the present disclosure is shown in FIG. Figure 3 As shown, in the step of LSU processing the memory operation instruction, if the type of the memory operation instruction is a load instruction, in the operation instruction information corresponding to the load instruction, the target physical address indicates the storage address corresponding to the data read by the load instruction target.

[0074] In the step of LSU processing the load instruction, after parsing the load instruction to obtain the target physical address and target check tag, the target cache line corresponding to the target memory block to which the target physical address belongs is determined, and it is determined whether the LSU has locally cached the target tag set corresponding to the target cache line.

[0075] If the target tag set corresponding to the target cache line is determined to be cached locally by the LSU, the actual tag of the target memory block is obtained from the cached target tag set; if the target tag set corresponding to the target cache line is determined to be not cached locally by the LSU, the target tag set is obtained and cached from the MS, and the actual tag of the target memory block is obtained from the target tag set.

[0076] The actual tag of the target memory block is compared with the target check tag to determine whether the actual tag and the target check tag are the same. This determines whether the tag verification is successful. If the verification is successful, the data stored at the target physical address is obtained from the MS and transmitted to the PU. If the verification fails, an error is reported to the PU.

[0077] The technical solution provided by the embodiment of the present disclosure, when implementing the MTE function, processes the load instruction only by obtaining and caching the target tag set corresponding to the target cache line from the MS once when the load instruction being processed is the first memory operation instruction. When the load instruction being processed is not the first memory operation instruction, the actual cached tag is obtained from the LSU locally. There is no need to interact with the MS again, and no additional delay is required. The tag verification can be quickly implemented, and the reading of the data indicated by the load instruction is completed, thereby reducing the delay in reading data and improving performance.

[0078] In one possible implementation, obtaining data stored at a target physical address from the MS includes: Obtain the data stored at the target physical address from the first-level cache of the MS, and cache the data stored at the target cache line in the first-level cache of the MS; The MS is further configured to: when the LSU obtains the target tag set from the MS, if it is determined that the data stored in the target cache line does not exist in the first-level cache, load the data stored in the target cache line into the first-level cache.

[0079] Specifically, in the embodiment of the present disclosure, when the LSU processes the first memory operation instruction, it obtains and caches the target tag set from the MS. In order to further improve the performance of the processor system using the embodiment of the present disclosure, on this basis, when the LSU obtains the target tag set from the MS, the MS is further configured to: if it is determined that the data stored in the target cache line does not exist in the first-level cache (i.e., L1 cache), then the data stored in the target cache line is loaded into the L1 cache.

[0080] That is, when the LSU obtains the target tag set from the MS, if the MS determines that the data stored in the target cache line is in the L1 cache, no additional operation is performed; if the MS determines that the data stored in the target cache line is not in the L1 cache, the data stored in the target cache line is loaded into the L1 cache.

[0081] It can be understood that when the load instruction processed by the LSU is not the first memory operation instruction, the above method can ensure that the data stored in the target cache line is cached in the MS's L1 cache. When the LSU obtains the data stored at the target physical address from the MS, it can directly obtain the data stored at the target physical address from the MS's L1 cache.

[0082] The technical solution provided by the embodiments of the present disclosure pre-loads the data stored in the target cache line that may be needed into the L1 cache of the MS when processing the first memory operation instruction. When the load instruction being processed is not the first memory operation instruction, if the data required to be read by the load instruction belongs to the target cache line, the data stored in the target physical address can be directly read from the L1 cache of the MS. Since the access speed of the L1 cache is higher than that of the L2 and L3 caches and much higher than that of the main memory, the access delay of the load instructions corresponding to the subsequent target cache lines in reading data can be significantly reduced, thereby effectively reducing the waiting time of the PU, improving the throughput of instruction execution, and improving the performance of the processor system.

[0083] In a possible implementation, the memory operation instruction is a storage instruction, and the operation instruction information further includes: target data to be stored; After confirming that the verification is successful, it also includes: Write the target data to be stored into the memory location specified by the target physical address in the MS.

[0084] Specifically, Figure 4 A flowchart of a storage instruction processing method provided by an embodiment of the present disclosure is shown in FIG. Figure 4 As shown, in the step of LSU processing the memory operation instruction, if the type of the memory operation instruction is a storage instruction, the operation instruction information corresponding to the storage instruction also includes target data to be stored, and the target physical address indicates that the storage instruction stores the target data to be stored in the memory location that needs to be written in the MS.

[0085] The difference between the storage instruction and the load instruction is that the storage instruction indicates the target data to be stored in the MS. Generally speaking, the storage instruction does not directly contain the target data to be stored, but instructs to read the data from the specified register. The LSU can obtain the target data to be stored from the corresponding register by parsing the storage instruction. The specific steps are not repeated here.

[0086] It is understandable that there may be a situation where the target physical address corresponding to the storage instruction belongs to more than one target memory block and more than one corresponding target cache line. In this case, the number of target memory blocks is multiple, and the target verification tag is the tag to be verified corresponding to each target memory block. Accordingly, the method steps provided in the embodiment of the present disclosure are executed for each target cache line involved.

[0087] In the step of LSU processing the storage instruction, after parsing the storage instruction to obtain the target physical address, the target data to be stored and the target check tag, the target cache line corresponding to the target memory block to which the target physical address belongs is determined, and it is determined whether the LSU has locally cached the target tag set corresponding to the target cache line.

[0088] If the target tag set corresponding to the target cache line is determined to be cached locally by the LSU, the actual tag of the target memory block is obtained from the cached target tag set; if the target tag set corresponding to the target cache line is determined to be not cached locally by the LSU, the target tag set is obtained and cached from the MS, and the actual tag of the target memory block is obtained from the target tag set.

[0089] The actual tag of the target memory block is compared with the target check tag to determine whether the actual tag and the target check tag are the same, thereby determining whether the tag verification is successful. If the verification is successful, the target data to be stored is written to the memory location specified by the target physical address in the MS. If the verification fails, an error is reported to the PU.

[0090] The technical solution provided by the embodiment of the present disclosure, when implementing the MTE function, for the processing of storage instructions, only needs to obtain and cache the target tag set corresponding to the target cache line from the MS once when the storage instruction being processed is the first memory operation instruction. When the storage instruction being processed is not the first memory operation instruction, the actual cached tag is obtained from the LSU locally. There is no need to interact with the MS again, and no additional delay is required. The tag verification can be quickly implemented, and the target data to be stored is written into the memory location specified by the target physical address in the MS as instructed by the storage instruction, thereby reducing the delay in storing data and improving performance.

[0091] In one possible implementation, for all data to be stored in the LSU and to be written into any cache line, all data to be stored is written into the MS in the following manner: Get the waiting time corresponding to the cache line. When the waiting time is greater than the time threshold, get all the data to be stored. For each piece of data to be stored among all the data to be stored, according to the physical address corresponding to the data to be stored, the data to be stored is written into a memory location specified by the corresponding physical address in the MS.

[0092] Specifically, Figure 5 A flowchart of a method for writing data to be stored provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, taking any cache line as an example, for the data to be stored corresponding to all physical addresses belonging to the cache line cached in the LSU, the specific steps of writing the data to be stored into the MS are described.

[0093] The embodiment of the present disclosure writes the data to be stored into the MS in a cache behavior unit manner. For each storage instruction, the corresponding data to be stored is first cached locally in the LSU, and the writing process of the data to be stored is batch processed in a cache behavior unit.

[0094] For any cache line, the LSU caches all data to be stored that are to be written into the cache line, and for the cache line, obtains the waiting time corresponding to the cache line.

[0095] Determine whether the waiting time is greater than a time threshold. When it is determined that the waiting time is not greater than the time threshold, continue to wait and monitor the updated waiting time.

[0096] If the waiting time is greater than the waiting time threshold, all the data to be stored that is locally cached by the LSU and belongs to the cache line are retrieved. For each of the data to be stored, the data is written to the memory location specified by the corresponding physical address in the MS according to the physical address of the data to be stored.

[0097] It can be understood that the data to be stored corresponding to all physical addresses belonging to the cache line may come from one or more storage instructions, and all memory blocks to which all the data to be stored belong may include one or more memory blocks.

[0098] For each memory block of all memory blocks to which the data to be stored belongs (i.e., the memory blocks in the cache line that contain the data to be stored), the data to be stored corresponding to the physical address included in the memory block is written into the memory location specified by the physical address included in the memory block in the MS.

[0099] It is understandable that when writing data to the MS, an attempt is usually made to write the data to the L1 cache first. The write operation may follow different write strategies, such as write-through or write-back. The specific write method can be determined based on the actual write strategy adopted, and the embodiments of the present disclosure do not limit this.

[0100] It is understood that after caching the data to be stored indicated by the store instruction, the LSU may record the length of time the data to be stored was cached in the LSU. The waiting time corresponding to the cache line is determined based on the length of time the data to be stored belonging to the cache line was cached in the LSU. Since a cache line can correspond to the data to be stored of one or more store instructions, the method for determining the waiting time corresponding to the cache line can be determined based on actual needs and is not limited in this embodiment of the present disclosure.

[0101] For example, the time during which the data to be stored of the first storage instruction corresponding to the cache line is cached in the LSU can be used as the waiting time; or, the average time during which the data to be stored of each storage instruction corresponding to the cache line is cached in the LSU can be used as the waiting time; or, each time the data to be stored of a new storage instruction is cached, the waiting time is reset to zero and recalculated, that is, the time during which the data to be stored of the last storage instruction is cached in the LSU is used as the waiting time, etc.

[0102] In addition, the duration threshold can be set to a fixed value or a dynamically updated value. The duration threshold can be set according to actual needs. The appropriate duration threshold can be determined based on factors such as processor performance, task complexity, system load and real-time requirements to ensure the efficiency and stability of the system. The embodiments of the present disclosure do not limit this.

[0103] For example, the duration threshold can be set to be related to information such as the number of storage instructions corresponding to the cache line, the amount of data to be stored corresponding to the cache line, and the number of all memory blocks related to the data to be stored corresponding to the cache line. By monitoring the usage of the cache line, the LSU can be helped to allocate local cache space more efficiently to avoid the cache space being occupied by inactive or unimportant data.

[0104] The technical solution provided by the embodiments of the present disclosure implements the MTE function. For storage instructions, the data to be stored is written to the MS in units of cache lines. For each storage instruction, the corresponding data to be stored is first cached locally in the LSU. A waiting mechanism is added to the data writing process in units of cache lines. When it is determined that the waiting data corresponding to a cache line is greater than a time threshold, the writing process of the data to be stored is processed in batches. All the data to be stored belonging to the cache line cached in the LSU is written to the MS at one time. This can reduce the number of interactions between the LSU and the MS to obtain the actual tag of the memory block while ensuring that the LSU's cache resources are not occupied for too long.

[0105] In one possible implementation, after writing the data to be stored into the memory location specified by the corresponding physical address in the MS, the following steps are included: Delete all cached data to be stored, all physical addresses, all check tags, and tag sets corresponding to the cache line.

[0106] Specifically, taking any cache line as an example, after all the to-be-stored data corresponding to the cache line is written to the memory location specified by the MS, the cached related data corresponding to the cache line in the local LSU (including the to-be-stored data, all physical addresses, all check tags and tag sets) is deleted.

[0107] It is understandable that the specific deletion strategy for deleting the cached related data corresponding to the cache line can be determined according to actual needs, including but not limited to designing that the cached data will become invalid upon being written into the MS, controlling deletion with hardware control or software instructions, setting a cache time threshold for related data to control deletion and cache replacement strategy, etc.

[0108] For example, the processing cycle of the cache line can be defined by setting a time threshold for caching related data. For any cache line, the time from the last deletion of the cached related data corresponding to the cache line to the next deletion of the cached related data corresponding to the cache line is regarded as a complete processing cycle. For each processing cycle, the first load instruction or store instruction corresponding to the cache line processed by the LSU is regarded as the first memory operation instruction.

[0109] It should be noted that the specific types of relevant data include data to be stored, physical addresses, check tags and tag sets. In actual application, a unified deletion strategy can be designed for all relevant data, or different deletion strategies can be designed for different types of relevant data. The specific method can be determined according to actual needs.

[0110] In the technical solution provided by the embodiments of the present disclosure, when implementing the MTE function, cache behavior is used as a processing unit, and lifecycle management of cached related data corresponding to a cache line in the LSU local cache is performed by setting a time threshold. When the waiting time corresponding to the cache line is greater than the time threshold, all to-be-stored data corresponding to the cache line is written to the memory location specified by the physical address included in the memory block in the MS, and then the cached related data corresponding to the cache line is cleared. This ensures data consistency between the LSU and the MS, frees up space for new data, and improves cache utilization.

[0111] In one possible implementation, the duration threshold is negatively correlated with the number of memory blocks to be written in the cache line, and the physical address range of the memory blocks to be written overlaps with the physical address corresponding to at least one data to be stored.

[0112] Specifically, the embodiment of the present disclosure sets the duration threshold corresponding to the cache line to a dynamically updated value, and the duration threshold is negatively correlated with the number of memory blocks to be written to the cache line, and the physical address range of the memory blocks to be written to the data overlaps with the physical address corresponding to at least one data to be stored.

[0113] That is, for each cache line, the more memory blocks that the LSU caches locally that contain data to be written corresponding to the cache line, the smaller the duration threshold, and the shorter the time that the data to be stored corresponding to the cache line can be cached locally in the LSU.

[0114] It is understandable that the specific relationship between the time threshold and the number of memory blocks to be written in the cache line can be determined according to actual needs, including but not limited to setting a fixed value, a functional relationship, and feedback control in combination with the LSU local remaining cache.

[0115] For example, a cache line corresponds to four memory blocks. For each cache line, when the number of memory blocks to be written to the cache line is 1-4, the corresponding setting time thresholds are 2048 clock cycles, 1024 clock cycles, 512 clock cycles, and 256 clock cycles, respectively. The clock cycle is determined by the frequency of the processing system, and the specific time corresponding to each clock cycle can be determined based on actual needs.

[0116] The length of time that the data to be stored of the first storage instruction corresponding to the cache line is cached in the LSU is used as the waiting time. For each cache line, when the physical address indicated by the first storage instruction belongs to only one memory block, the length threshold is 2048 clock cycles after the data to be stored indicated by the first storage instruction is cached.

[0117] During the waiting process, if there is no other storage instruction or the physical address indicated by the other storage instruction is still the same memory block, when the waiting time is longer than 2048 clock cycles, the data to be stored is written into the MS.

[0118] During the waiting process, if there is at least one other storage instruction and the physical address indicated by the storage instruction belongs to a different memory block, the duration threshold is updated according to the number of memory blocks to be written. When the waiting time is greater than the updated duration threshold, all the data to be stored corresponding to the cache line are written into the MS.

[0119] For each cache line, when the LSU caches more memory blocks of data to be written corresponding to the cache line locally, it means that the LSU has locally cached a large amount of relevant data for the cache line, and subsequent storage instructions from the same cache line may be less.

[0120] The technical solution provided by the embodiments of the present disclosure uses a dynamically updated duration threshold. For each cache line, the duration threshold is set to be negatively correlated with the number of memory blocks of data to be written corresponding to the cache line in the local LSU cache. This can dynamically adjust the cache strategy and shorten the duration that the relevant data corresponding to the cache line is retained in the local LSU, thereby freeing up space for more active data and reducing the pressure on the local cache.

[0121] In one possible implementation, for each memory block, after determining the actual tag and the check tag of the memory block, the method further includes: If it is determined that the actual tag and the verification tag are not the same, the verification is determined to have failed and an error is reported to the PU.

[0122] For details, see again Figure 3 and Figure 4 ,regardless of whether the type of memory operation instruction processed by LSU is a load instruction or a store instruction, ,it parses the memory operation instruction, obtains the target physical address and target ,check tag indicated by the instruction, and after determining the target memory block to which the ,target physical address belongs, obtains the actual tag corresponding to the target ,memory block from the MS or from the LSU local cache.

[0123] For each target memory block, the actual tag of the target memory block is compared with the target verification tag. If it is determined that the actual tag is different from the target verification tag, it is determined that the verification has failed and an error is reported to the PU.

[0124] It is understandable that for different types of memory operation instructions, the information carried when reporting an error to the PU may be different and may be determined according to actual needs.

[0125] The technical solution provided by the embodiment of the present disclosure, when implementing the MTE function to process each memory operation instruction, first determines the target memory block corresponding to the target physical address after obtaining the target physical address and target check tag indicated by the memory operation instruction. For each target memory block, the target check tag and the actual tag are compared to determine whether the verification is successful, and when it is determined that the verification fails, an error is reported to the PU.

[0126] That is, although the embodiment of the present disclosure uses cache lines as processing units, during tag verification, it still maintains a method of prioritizing data processing after verification in memory blocks. For the processing of storage instructions, although the data to be stored needs to be cached locally in the LSU and wait for all the data to be stored in the cache line to be processed together, the tag verification of all the memory blocks corresponding to the data to be stored has been completed in advance, and the tag verification results can be fed back to the PU in a timely manner, so that the PU can take corresponding processing measures for the error situation in a timely manner.

[0127] According to another aspect of an embodiment of the present disclosure, there is provided a processor system, comprising: at least one load-store unit; The load storage unit implements the memory operation instruction processing method provided by any of the above embodiments when executing.

[0128] Specifically, the processor system in the embodiment of the present disclosure may include at least one load storage unit LSU, which implements the memory operation instruction processing method provided by any of the above embodiments when executed. The specific implementation steps and effects are described above and are not limited here.

[0129] For example, see again Figure 1 The processor system includes a processing unit, a load-store unit and a memory subsystem. The load-store unit is used to receive memory operation instructions transmitted by the processing unit, and read or write data in the memory subsystem based on the type of memory operation instructions, and transmit the data corresponding to the load instruction to the processing unit.

[0130] It is understood that the processor system includes at least one processing unit, which can be a processor core, a processor core cluster, a processor, etc. The type and number of processing units in the processor system, as well as the specific number of load and store units, can be set according to the actual situation of the processor system.

[0131] When there are multiple processing units and multiple load storage units in the processor system, the quantity relationship between the processing units and the load storage units can be a one-to-one relationship, a many-to-one relationship, or a one-to-many relationship. The specific quantity relationship and mapping relationship can be designed according to actual needs.

[0132] Figure 6A schematic diagram of the structure of a load storage unit provided in an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the load storage unit 60 includes: The instruction processing module 601 is used to parse the memory operation instruction input by the PU, obtain and cache the operation instruction information, which includes the target physical address and the target check tag. The target check tag is the tag to be checked of the target memory block to which the target physical address belongs. The data cache module 602 is configured to determine a target cache line to which the target memory block belongs. If it is determined that the target tag set corresponding to the target cache line is already cached in the LSU, the actual tag of the target memory block is obtained from the target tag set. The target tag set is obtained and cached by the LSU from the MS when processing the first memory operation instruction corresponding to the target cache line. The MS includes multiple cache lines, and the tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line. The tag verification module 603 is configured to determine that the verification is successful if it is determined that the actual tag of the target memory block is the same as the target verification tag.

[0133] The technical solution provided in this embodiment uses cache lines as units when implementing the MTE function. When the LSU processes the first memory operation instruction, it obtains the corresponding tag set of the cache line from the MS and caches it locally on the LSU. Compared with the method of obtaining the actual tag from the MS in units of memory blocks, it can effectively reduce the delay caused by repeated interactions with the MS, thereby improving performance.

[0134] The device of the embodiment of the present disclosure can execute the method provided by the embodiment of the present disclosure, and its implementation principle is similar. The actions performed by each module in the device of each embodiment of the present application correspond to the steps in the method of each embodiment of the present application. For the detailed functional description of each module of the device, please refer to the description in the corresponding method shown in the previous text, and will not be repeated here.

[0135] In a possible implementation, after determining the target cache line to which the target memory block belongs, the following steps are included: If it is determined that the target tag set corresponding to the target cache line is not cached in the LSU, the target tag set is obtained from the MS and cached, and the actual tag of the target memory block is obtained from the target tag set; If it is determined that the actual tag of the target memory block is the same as the target verification tag, then the verification is determined to be successful.

[0136] In one possible implementation, the memory operation instruction is a load instruction; After confirming that the verification is successful, it also includes: The data stored at the target physical address is obtained from the MS, and the data stored at the target physical address is transmitted to the PU.

[0137] In one possible implementation, obtaining data stored at a target physical address from the MS includes: Obtain the data stored at the target physical address from the first-level cache of the MS, and cache the data stored at the target cache line in the first-level cache of the MS; The MS is further configured to: when the LSU obtains the target tag set from the MS, if it is determined that the data stored in the target cache line does not exist in the first-level cache, load the data stored in the target cache line into the first-level cache.

[0138] In a possible implementation, the memory operation instruction is a storage instruction, and the operation instruction information further includes: target data to be stored; After confirming that the verification is successful, it also includes: Write the target data to be stored into the memory location specified by the target physical address in the MS.

[0139] In one possible implementation, for all data to be stored in the LSU and to be written into any cache line, all data to be stored is written into the MS in the following manner: Get the waiting time corresponding to the cache line. When the waiting time is greater than the time threshold, get all the data to be stored. For each piece of data to be stored among all the data to be stored, according to the physical address corresponding to the data to be stored, the data to be stored is written into a memory location specified by the corresponding physical address in the MS.

[0140] In one possible implementation, after writing the data to be stored into the memory location specified by the corresponding physical address in the MS, the following steps are included: Delete all cached data to be stored, all physical addresses, all check tags, and tag sets corresponding to the cache line.

[0141] In one possible implementation, the duration threshold is negatively correlated with the number of memory blocks to be written in the cache line, and the physical address range of the memory blocks to be written overlaps with the physical address corresponding to at least one data to be stored.

[0142] In one possible implementation, for each memory block, after determining the actual tag and the check tag of the memory block, the method further includes: If it is determined that the actual tag and the verification tag are not the same, the verification is determined to have failed and an error is reported to the PU.

[0143] An embodiment of the present disclosure provides an electronic device (computer device / equipment / system), including a memory, a processor, and a computer program stored in the memory. The processor executes the above-mentioned computer program to implement the steps of the method provided in any optional embodiment of the present disclosure and achieve the corresponding technical effects.

[0144] In an alternative embodiment, an electronic device is provided, Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure is shown in FIG. Figure 7 As shown, electronic device 70 includes: a processor 701 and a memory 703. The processor 701 and the memory 703 are connected, for example, via a bus 702. Optionally, electronic device 700 may further include a transceiver 704, which may be used for data exchange between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the number of transceivers 704 is not limited to one, and the structure of electronic device 700 does not constitute a limitation on the embodiments of the present disclosure.

[0145] Processor 701 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the present disclosure. Processor 701 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0146] Bus 702 may include a path for transmitting information between the above components. Bus 702 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. Bus 702 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, Figure 7 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0147] The memory 703 may be a ROM (Read Only Memory) or other type of static storage device that can store static information and instructions, a RAM (Random Access Memory) or other type of dynamic storage device that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0148] The memory 703 is used to store the computer program for executing the embodiments of the present disclosure, and the execution is controlled by the processor 701. The processor 701 is used to execute the computer program stored in the memory 703 to implement the steps shown in the above method embodiments.

[0149] The electronic devices in the embodiments of the present disclosure may include but are not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable devices, etc., as well as fixed terminals such as digital TVs, desktop computers, etc.

[0150] An embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented.

[0151] The embodiments of the present disclosure further provide a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiments when executed by a processor.

[0152] It should be noted that the computer-readable storage medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or component, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0153] In this disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program for use by or in conjunction with an instruction execution system, apparatus, or device. Furthermore, in this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wire, fiber optic cable, RF (radio frequency), or any suitable combination thereof.

[0154] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including, but not limited to, object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0155] In the specification and claims of this application and the accompanying drawings, the terms "first," "second," "third," "fourth," "1," "2," and "target," etc. (if any) are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, such that the embodiments of the present application described herein can be practiced in an order other than that shown or described.

[0156] It should be understood that, although the flowcharts of the embodiments of the present disclosure indicate the various operation steps by arrows, the order of implementation of these steps is not limited to the order indicated by the arrows. Unless otherwise clearly stated herein, in some implementation scenarios of the embodiments of the present disclosure, the implementation steps in each flowchart can be performed in other orders as required. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on the actual implementation scenario. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage in these sub-steps or stages can also be executed at different times. In scenarios where the execution times are different, the order of execution of these sub-steps or stages can be flexibly configured as required, and the embodiments of the present disclosure do not limit this.

[0157] The above description is only an optional implementation method for some implementation scenarios of this application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of this application, other similar implementation methods based on the technical ideas of this application also fall within the protection scope of the embodiments of this disclosure.

Claims

1. A memory operation instruction processing method, characterized in that: The method is applied to a load store unit (LSU) in a processor system, wherein the processor system further includes a processing unit (PU) and a memory subsystem (MS). The processor system applies a memory tag extension (MTE) function. The method includes: Parsing the memory operation instruction input by the PU, obtaining and caching operation instruction information, wherein the operation instruction information includes a target physical address and a target check tag, wherein the target check tag is a to-be-checked tag of a target memory block to which the target physical address belongs; Determine a target cache line to which the target memory block belongs. If it is determined that a target tag set corresponding to the target cache line has been cached in the LSU, obtain an actual tag of the target memory block from the target tag set. The target tag set is obtained and cached by the LSU from the MS when processing the first memory operation instruction corresponding to the target cache line. The MS includes multiple cache lines, and the tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line. If it is determined that the actual tag of the target memory block is the same as the target verification tag, then the verification is determined to be successful.

2. The memory operation instruction processing method according to claim 1, characterized in that: After determining the target cache line to which the target memory block belongs, the method includes: If it is determined that the target tag set corresponding to the target cache line is not cached in the LSU, the target tag set is obtained from the MS and cached, and the actual tag of the target memory block is obtained from the target tag set; If it is determined that the actual tag of the target memory block is the same as the target verification tag, then the verification is determined to be successful.

3. The memory operation instruction processing method according to claim 1 or 2, characterized in that: The memory operation instruction is a load instruction; After the verification is confirmed to be successful, the method further includes: The data stored at the target physical address is acquired from the MS, and the data stored at the target physical address is transmitted to the PU.

4. The memory operation instruction processing method according to claim 3, wherein: The acquiring, from the MS, data stored at the target physical address, includes: Acquire the data stored in the target physical address from the first-level cache of the MS, the first-level cache of the MS caching the data stored in the target cache line; The MS is further configured to: when the LSU obtains the target tag set from the MS, if it is determined that the data stored in the target cache line does not exist in the first-level cache, load the data stored in the target cache line into the first-level cache.

5. The memory operation instruction processing method according to claim 1 or 2, characterized in that: The memory operation instruction is a storage instruction, and the operation instruction information further includes: target data to be stored; After the verification is confirmed to be successful, the method further includes: The target data to be stored is written into a memory location specified by the target physical address in the MS.

6. The memory operation instruction processing method according to claim 5, characterized in that: For all data to be stored in the LSU and to be written into any cache line, the data to be stored is written into the MS in the following manner: Obtaining a waiting time corresponding to the cache line, and when the waiting time is greater than a time threshold, obtaining all the data to be stored; For each piece of data to be stored among all the data to be stored, according to the physical address corresponding to the data to be stored, the data to be stored is written into a memory location specified by the corresponding physical address in the MS.

7. The memory operation instruction processing method according to claim 6, characterized in that: After writing the data to be stored into the memory location specified by the corresponding physical address in the MS, the method includes: Delete all cached data to be stored, all physical addresses, all check tags and tag sets corresponding to the cache line.

8. The memory operation instruction processing method according to claim 6, wherein: The time threshold is negatively correlated with the number of memory blocks to be written in the cache line, and the physical address range of the memory blocks to be written overlaps with the physical address corresponding to at least one data to be stored.

9. The memory operation instruction processing method according to claim 1, wherein: For each memory block, after determining the actual tag and the check tag of the memory block, the method further includes: If it is determined that the actual tag and the verification tag are not the same, it is determined that the verification has failed and an error is reported to the PU.

10. A load storage unit, characterized in that: include: An instruction processing module, configured to parse memory operation instructions input by the PU, obtain and cache operation instruction information, wherein the operation instruction information includes a target physical address and a target check tag, wherein the target check tag is a tag to be checked for the target memory block to which the target physical address belongs; a data cache module, configured to determine a target cache line to which the target memory block belongs, and if it is determined that a target tag set corresponding to the target cache line has been cached in the LSU, obtain an actual tag of the target memory block from the target tag set, wherein the target tag set is obtained and cached from the MS by the LSU when processing the first memory operation instruction corresponding to the target cache line, wherein the MS includes multiple cache lines, and the tag set corresponding to each cache line includes the actual tag of each memory block included in the corresponding cache line; The tag verification module is configured to determine that the verification is successful if it is determined that the actual tag of the target memory block is the same as the target verification tag.

11. A processor system, characterized in that: include: at least one load-store unit; When executed, the load storage unit implements the method according to any one of claims 1 to 9.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory, wherein: The processor executes the computer program to implement the method according to any one of claims 1 to 9.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.

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