Active maintenance method and device for cache consistency, electronic equipment and storage medium

Abstract

The embodiment of the invention relates to the technical field of processors, in particular to an active maintenance method and device for cache consistency, electronic equipment and a storage medium, and the method comprises the following steps: in response to the maintenance of the cache consistency, implementing invalidation operation on a copy of a first cache block of a target processor core, checking the consistency maintenance mode of the copy of the first cache block; under the condition that the consistency maintenance mode is an active maintenance mode, after invalidation operation is completed, an updating command is initiated to update the copy of the first cache block to the latest data content; after updating of the copy of the first cache block is completed, the copy of the first cache block is recovered to be in an effective state. According to the method, convenient and selective use of the active maintenance method is realized, and the hardware overhead of the active maintenance method is reduced by fully utilizing an existing hardware mechanism for consistent passive maintenance of the cache on the CPU.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of processor technology, and in particular to a method, device, electronic device, and storage medium for actively maintaining cache consistency. Background Art

[0002] To speed up access to memory data, each processor core on a modern multi-core CPU (central processing unit) includes a cache to increase data access speed and ensure ease of programming. When running a parallel program, multiple threads of the same process read and write data within the same shared memory area, potentially causing multiple cores to simultaneously store copies of the same cache line (typically 64 bytes). To ensure the correct execution of parallel programs, cache coherence is required between different cores on the same CPU, as well as between different CPUs within the same compute node. This ensures that the same data remains consistent across the caches of multiple cores within the same compute node.

[0003] The current method for maintaining cache coherence is passive. That is, when processor A invalidates a cache block copy on processor core B, B does not obtain the latest valid cache block copy. Instead, it must wait until B accesses the cache block again, at which point it can update its cache block copy as a cache miss. Although modern CPUs generally feature hardware data prefetching, it's possible that a cache block prefetched by one core may be invalidated by another core, resulting in a cache miss when it is actually used.

[0004] Therefore, when a processor core needs to access data produced by another processor core, it often incurs the cost of a cache miss and its significant overhead. This is especially true in producer-consumer parallel programming, where the consumer thread constantly queries the producer thread for computational tasks. This means the consumer thread constantly queries the signal data that the producer thread is constantly modifying. Regardless of whether the producer thread is ahead or behind, the consumer thread will experience a cache miss each time it obtains updated signal data. This means it must endure the synchronization overhead represented by cache misses to obtain new computational tasks. This increases the processor's dynamic power consumption and reduces the overall system throughput. Summary of the Invention

[0005] The purpose of the present invention is to at least provide an active maintenance method for cache consistency, which can at least solve the technical problem that passive maintenance of cache consistency leads to the update of cache block copies by processing cache misses, resulting in increased dynamic power consumption of the processor and decreased overall throughput of the system. It can at least achieve the effect of improving the synchronization overhead represented by cache miss overhead that needs to be endured in order to obtain new computing tasks.

[0006] To solve the above technical problems, at least one embodiment of the present application provides a method for actively maintaining cache consistency, including: In response to maintaining cache consistency, performing an invalidation operation on the copy of the first cache block of the target processor core, and checking a consistency maintenance mode of the copy of the first cache block of the target processor core, wherein the consistency maintenance mode includes an active maintenance mode; In a case where the consistency maintenance mode is an active maintenance mode, after completing the invalidation operation, issuing an update command to update the copy of the first cache block to the latest data content; and After the copy of the first cache block is updated, the copy of the first cache block is restored to a valid state.

[0007] In some optional embodiments, before checking the consistency maintenance mode of the copy of the first cache block, the method further includes: In response to receiving a maintenance setting instruction corresponding to the copy of the first cache block, checking consistency maintenance setting information of the maintenance setting instruction, wherein the consistency maintenance setting information is an active maintenance mode or a passive maintenance mode; A consistency maintenance mode for the copy of the first cache block is set according to the consistency maintenance setting information.

[0008] In some optional embodiments, setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information includes: The consistency maintenance setting information is stored in a preset storage space in the first cache block.

[0009] In some optional embodiments, setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information includes: Based on a directory protocol, the consistency maintenance setting information is stored in a table entry corresponding to the first cache block in a directory structure.

[0010] In some optional embodiments, after completing the invalidation operation, initiating an update command to update the copy of the first cache block to the latest data content includes: After the invalidation operation is completed and after a preset waiting time, an update command is initiated to update the copy of the first cache block to the latest data content.

[0011] In some optional embodiments, in the active maintenance mode, the size of the shared variable is set to be aligned with the first cache block size.

[0012] In some optional embodiments, after the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode, the active maintenance mode is always maintained unchanged.

[0013] At least one embodiment of the present application further provides a device for actively maintaining cache consistency, including: an invalidation operation module, configured to perform an invalidation operation on the copy of the first cache block of the target processor core in response to maintaining cache coherence; a maintenance mode checking module, configured to check a consistency maintenance mode of the copy of the first cache block in response to maintaining cache consistency, wherein the consistency maintenance mode includes an active maintenance mode; a cache block copy update module, configured to, when the consistency maintenance mode is an active maintenance mode, initiate an update command after completing the invalidation operation to update the copy of the first cache block to the latest data content; and A recovery module is configured to restore the copy of the first cache block to a valid state after the copy of the first cache block is updated.

[0014] At least one embodiment of the present application also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned active cache consistency maintenance method.

[0015] At least one embodiment of the present application further provides a computer-readable storage medium storing a computer program, which implements the above-mentioned active cache consistency maintenance method when executed by a processor.

[0016] The active maintenance method, device, electronic device and storage medium for cache consistency provided by the embodiments of the present application realize the convenient selective use of the active maintenance method by introducing the setting information of the consistency maintenance method. When a processor core immediately updates the content of the cache block copy of another processor core after invalidating the cache block copy of another processor core, if the invalidated cache block copy will not be used again in the future, it will increase the cache's additional access to the memory and increase the bandwidth pressure of the program accessing the memory. Therefore, the present application allows the processor core to choose to use active maintenance or passive maintenance according to specific needs, thereby reducing unnecessary additional memory access and bandwidth pressure.

[0017] Specifically, when a processor core performs a cache coherence maintenance operation (such as invalidating a cache block replica), it first checks the consistency maintenance mode setting for that cache block replica. If set to active maintenance mode, the processor core will proactively initiate a command to update the contents of the cache block replica after completing the invalidation operation, allowing it to immediately obtain the latest data and restore it to a valid state. If set to passive maintenance mode, only the invalidation operation is performed, and no update command is initiated. The processor core can choose to use active maintenance mode when it is necessary to ensure timely data updates and avoid cache miss overhead.

[0018] Furthermore, since modern CPUs typically already have hardware mechanisms to support reactive maintenance (such as cache coherence protocols and hardware data prefetching), this approach can leverage these existing mechanisms to reduce the hardware overhead of proactive maintenance. For example, during proactive maintenance, the processor core can leverage hardware prefetching to obtain the latest data in advance, reducing the latency associated with waiting for data updates. Furthermore, by carefully controlling the timing and conditions for switching between proactive and reactive maintenance, overall system performance and resource utilization can be further optimized.

[0019] To sum up, the method of this application realizes the convenient selective use of the active maintenance method by introducing the setting information of the consistency maintenance method and combining the active maintenance and passive maintenance methods, and makes full use of the existing hardware mechanism of cache consistency passive maintenance on the CPU to reduce the hardware overhead of the active maintenance method. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments are exemplarily described by the figures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments.

[0021] Figure 1 This is a flowchart of a method for actively maintaining cache consistency provided by an embodiment of the present application; Figure 2This is a schematic diagram of an active cache consistency maintenance device provided by another embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0023] To facilitate understanding of the embodiments of the present application, the following describes cache coherence.

[0024] Modern CPUs (central processing units) feature dozens or even hundreds of processor cores, providing immense computing power for accelerating program execution. This requires upgrading legacy serial programs to efficient parallel programs that can fully utilize the multi-core CPUs. Thread-level parallelism, which allows a single process to have multiple threads working simultaneously, is a fundamental approach to parallel program development. The collaborative work between threads often creates data dependencies, meaning one thread uses the results of another thread's computations. Because multiple threads within a process share the overall process memory, shared variables can be used to conveniently implement data dependencies.

[0025] To speed up access to memory data, each processor core on a modern multi-core CPU has a cache (i.e., a high-speed cache) to increase data access speed and ensure ease of program writing. When running a parallel program, multiple threads of the same process read and write data within the same shared memory area, resulting in multiple cores potentially holding copies of the same cache line (typically 64 bytes). To ensure the correct execution of parallel programs, cache coherence is required between different processor cores on the same CPU, as well as between different CPUs within the same compute node. This ensures that the same data remains consistent across the caches of multiple processor cores within the same compute node.

[0026] There are two main implementations of cache coherence protocols: snoop-based coherence protocols (snoop protocols) and directory-based coherence protocols (directory protocols). Snoop protocols rely on a bus or bus-like network connection; using this network, all requests from a single processor core's private cache are broadcast to the private caches of all other processor cores in the system. Access requests from all processors can also be sequenced on this bus, fulfilling the ordering requirements of the cache coherence model and the memory identity model. In the directory protocol, memory access requests from a processor core's private cache are first sent to the directory structure corresponding to the cache block. This directory structure records the sharing status of the current cache block. Based on the current cache block status, the directory structure controller chooses to respond to the request or forward it to the private caches of other corresponding processor cores. Both approaches have their advantages and disadvantages, and modern multi-core CPUs often use a hybrid of the two protocols.

[0027] To maintain cache consistency, when processor core A modifies a cache block for the first time, it will issue an invalidation command regarding the cache block to other processor cores. When processor core B has a valid copy of the cache block and receives the invalidation command, it will invalidate its copy of the cache block and then respond to A. When B wants to access the cache block again, a cache miss will occur, and then it will obtain the latest copy of the cache block from A or memory.

[0028] The above method for maintaining cache coherence can be called a passive approach. When processor A invalidates the cache block copy of processor core B, B does not obtain the latest valid cache block copy. Instead, it must wait until B accesses the cache block again before updating its cache block copy, which is handled as a cache miss. Although modern CPUs generally feature hardware data prefetching, it is possible that a cache block prefetched by one core is invalidated by another core, yet a cache miss still occurs when the block is actually used. Therefore, when a processor core attempts to access data produced by another processor core, it often incurs the cost of a cache miss and its significant overhead. In particular, in a producer-consumer parallel programming approach, the consumer thread constantly queries the producer thread for computational tasks. This means that the consumer thread constantly queries the signal data that the producer thread is constantly modifying. Regardless of whether the producer thread is ahead or behind, the consumer thread will incur a cache miss each time it obtains updated signal data. This means that it must endure synchronization overhead, represented by cache misses, to obtain new computational tasks.

[0029] In order to solve the technical problem that the above-mentioned passive maintenance of cache consistency leads to the update of cache block copies by processing cache misses, resulting in increased dynamic power consumption of the processor and decreased overall throughput of the system, the present invention proposes an active maintenance method for cache consistency. The implementation details of the active maintenance method for cache consistency of this embodiment are specifically described below. The following content is only the implementation details provided for easy understanding and is not necessary for the implementation of this solution.

[0030] Example 1: The active maintenance method for cache consistency of this embodiment can be applied to electronic devices with communication, computing and data storage capabilities. The specific process can be as follows: Figure 1 Shown, including: Step 110: In response to maintaining cache coherence, invalidate the copy of the first cache block of the target processor core, and check a coherence maintenance mode of the copy of the first cache block of the target processor core, where the coherence maintenance mode includes an active maintenance mode. Step 120: When the consistency maintenance mode is the active maintenance mode, after completing the invalidation operation, initiate an update command to update the copy of the first cache block to the latest data content; Step 130: After the copy of the first cache block is updated, the copy of the first cache block is restored to a valid state.

[0031] In this embodiment, when processor core A (the target processor core) has a valid copy of a cache block (i.e., a copy of the first cache block) and another processor core attempts to modify the data in that cache block, the cache coherence protocol initiates an operation to invalidate the copy of the first cache block on the target processor core, thereby initiating cache coherence maintenance. The system records the current coherence maintenance mode for each cache block copy on each processor core, i.e., either active or passive.

[0032] If it is determined that the copy of the first cache block is actively maintained, in addition to marking the copy of the first cache block as invalid, an update command can also be actively initiated to obtain the latest data content from the data source (which may be the cache of another processor core or the main memory).

[0033] Update commands can include information such as the specific address of the requested data, the request type (e.g., read or write), and the identity of the requester. These commands are sent via the system bus or a dedicated communication channel to the processor core or memory controller responsible for maintaining the latest data. Once the first cache block's copy has been successfully updated with the latest data, it is remarked as valid and ready for use by the processor core.

[0034] Cache coherence on modern multi-core CPUs is maintained passively, performing only invalidation operations. Active maintenance differs from passive maintenance in that after completing the invalidation operation, the cache block replica's contents are updated. This update can be implemented in a variety of ways. One readily conceivable approach is for the cache coherence protocol hardware to simultaneously send the latest data contents to a processor core's cache block replica while simultaneously initiating an invalidation operation. However, this approach is difficult to implement because the processor core that wants to write data must complete the invalidation operation on the corresponding cache block replicas in other processor cores and confirm sole ownership of the cache block before writing the data to the cache block. In other words, the invalidation operation and data update are performed sequentially and cannot be performed simultaneously.

[0035] Another more practical approach, adopted in this embodiment, is to have the target processor core initiate a command to update the copy of the first cache block after completing the invalidation operation on the target processor core. This update command can essentially be understood as a cache block data prefetch instruction. This implementation method can fully utilize the existing cache coherence capabilities of modern multi-core CPUs and therefore has promising application prospects.

[0036] In an optional embodiment, when the consistency maintenance mode is passive, only the invalidation operation is performed. If it is determined that the replica of the first cache block uses passive maintenance, then when the data of this replica is modified elsewhere, it is simply marked as invalid. In this way, when the processor core accesses the data again, a cache miss is triggered, and the latest data is retrieved from main memory or other caches.

[0037] The active maintenance method reduces the delay in data access and improves system performance by updating the cache in advance. However, the active maintenance method may increase the communication volume on the system bus, especially in high-concurrency access scenarios. Based on this, the active maintenance method should not be the default method or even the only method for maintaining cache consistency, because when the copy of the invalidated first cache block will not be used again, the active maintenance method will increase the additional access of the first cache block to the memory, increasing the bandwidth pressure of the program accessing the memory. Therefore, the active maintenance method of cache consistency in this embodiment focuses on solving the following two problems: 1) How to achieve convenient and selective use of proactive maintenance methods; 2) How to fully utilize the existing hardware mechanism for passive maintenance of cache coherence on the CPU to reduce the hardware overhead of active maintenance methods.

[0038] Specifically, this embodiment realizes the convenient selective use of active maintenance methods by introducing the setting information of the consistency maintenance mode, allowing the processor core to choose to use active maintenance or passive maintenance mode according to specific needs, thereby reducing unnecessary additional memory access and bandwidth pressure. When the processor core performs a maintenance operation on cache consistency (such as invalidating a cache block copy), it will first check the consistency maintenance mode setting of the cache block copy. If it is set to active maintenance mode, the processor core will actively initiate a command to update the content of the cache block copy after completing the invalidation operation, so that it can immediately obtain the latest data and restore it to a valid state. If it is set to passive maintenance mode, only the invalidation operation is performed, and no update command is initiated. Therefore, when it is necessary to ensure that data is updated in a timely manner and avoid cache miss overhead, the processor core can choose to use the active maintenance mode.

[0039] Furthermore, since modern CPUs typically already have hardware mechanisms supporting passive maintenance (such as cache coherence protocols and hardware data prefetching), this embodiment leverages these existing mechanisms to reduce the hardware overhead of active maintenance. For example, during active maintenance, a processor core can utilize hardware prefetching to pre-fetch the latest data (i.e., control the target processor core to initiate an update command), thereby reducing the delay caused by waiting for data updates. Furthermore, by carefully controlling the timing and conditions for switching between active and passive maintenance, the overall system performance and resource utilization can be further optimized.

[0040] To sum up, the active cache consistency maintenance method of this embodiment realizes the convenient selective use of the active maintenance method by introducing the setting information of the consistency maintenance method and combining the active maintenance and passive maintenance methods, and makes full use of the existing hardware mechanism of cache consistency passive maintenance on the CPU to reduce the hardware overhead of the active maintenance method.

[0041] In some optional embodiments, before checking the consistency maintenance mode of the copy of the first cache block, it also includes: in response to receiving a maintenance setting instruction corresponding to the copy of the first cache block, checking the consistency maintenance setting information of the maintenance setting instruction, wherein the consistency maintenance setting information is an active maintenance mode or a passive maintenance mode; and setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information.

[0042] In this embodiment, the target processor core checks the consistency maintenance setting information of the maintenance setting instruction in response to the execution of the maintenance setting instruction; if the consistency maintenance setting information is an active maintenance setting, the consistency maintenance mode of the cache block copy corresponding to the maintenance setting instruction (i.e., the copy of the first cache block) is set to the active maintenance mode; if the consistency maintenance setting information is a passive maintenance setting, the consistency maintenance mode of the cache block copy corresponding to the maintenance setting instruction is set to the passive maintenance mode.

[0043] In the context of modern multi-core CPUs employing a passive cache coherence maintenance approach, it can be assumed that the existing coherence maintenance settings during memory access instruction execution are all passive. Therefore, the problem to be solved in this embodiment is how to conveniently specify active maintenance settings while the passive maintenance settings are the default.

[0044] There are at least two ways to easily specify proactive maintenance settings: The first implementation method is to expand the various memory access instructions in the processor instruction set to include a mode for active maintenance settings. The specific method can be to add a status flag bit for active maintenance settings to the opcode of the existing memory access instruction (for example, the default is passive maintenance settings, and when marked, it is active maintenance settings). In other words, the maintenance setting instruction is a memory access instruction with a status flag bit, and the status flag bit contains consistency maintenance setting information. The essence of this method is to add new memory access instructions corresponding to active maintenance settings. Further support is provided in the programming language for the definition of shared variables with active maintenance settings, and the compiler uses memory access instructions in the active maintenance setting mode to implement access to shared variables with active maintenance settings. The first implementation method will cause major changes to the instruction set and decoding components, thereby incurring large hardware R&D costs.

[0045] The second implementation method is to add an instruction to change the current consistency maintenance setting information (i.e., a maintenance setting instruction). This instruction can change the current consistency maintenance setting information from a passive maintenance setting to an active maintenance setting, or vice versa. The second implementation method is the method adopted in this embodiment. Each maintenance setting instruction can query the current consistency maintenance setting information when it is executed. When the programming language supports the definition of shared variables with active maintenance settings, the compiler can add instructions to change the current consistency maintenance setting information before and after the maintenance setting instruction for the shared variables with active maintenance settings; when the programming language does not support the definition of shared variables with active maintenance settings, the programmer can also use embedded assembly to add instructions to change the current consistency maintenance setting information to the program. This implementation method is both easy to implement and does not incur large hardware R&D costs.

[0046] In some optional embodiments, setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information includes: storing the consistency maintenance setting information in a preset storage space in the first cache block.

[0047] In this embodiment, an additional bit is used in the first cache block to record the current consistency maintenance mode. This method has a hardware overhead of 1 / 512, where 512 represents the size of a cache block of 64 bytes, or 512 bits. This extremely low hardware overhead means that there is almost no burden on storage space, making it particularly suitable for resource-constrained environments. Due to this extremely low overhead, the method of this embodiment is highly cost-effective in implementing cache consistency maintenance, without significantly increasing hardware costs to store additional information.

[0048] In some optional embodiments, setting the consistency maintenance method of the copy of the first cache block according to the consistency maintenance setting information includes: based on the directory protocol, storing the consistency maintenance setting information in the table entry corresponding to the first cache block in the directory structure.

[0049] In this embodiment, in conjunction with the directory protocol, a bit is added to each entry in the directory structure to record the current consistency maintenance mode of the corresponding cache block. In this way, the directory protocol sends the current consistency maintenance mode of the cache block at the same time as issuing the invalidation operation.

[0050] By issuing the current consistency maintenance mode of the cache block through the directory protocol at the same time as the invalidation operation, the system can reduce additional communication overhead because the system does not need to query or confirm the maintenance mode again in subsequent operations, thereby enabling the system to respond to consistency maintenance requests more quickly, helping to reduce latency and improve overall system performance.

[0051] In some optional embodiments, after completing the invalidation operation, initiating an update command to update the copy of the first cache block to the latest data content, includes: after completing the invalidation operation and after a preset waiting time, initiating an update command to update the copy of the first cache block to the latest data content. In this embodiment, the update command can be initiated after completing the invalidation operation and waiting for a threshold number of CPU cycles to appropriately alleviate the working pressure of the cache consistency hardware. In some optional embodiments, the update command can also be initiated immediately upon completing the invalidation operation. The specific implementation method is selected based on actual needs and is not limited here.

[0052] In some optional embodiments, in the active maintenance mode, the size of the shared variable is set to be aligned with the first cache block size.

[0053] In this embodiment, when the consistency maintenance setting information of a memory access instruction is an active maintenance setting, the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode. If the consistency maintenance setting information of a memory access instruction is a passive maintenance setting, the consistency maintenance mode of the copy of the first cache block is set to the passive maintenance mode. An extreme situation may occur: two memory access instructions executed successively correspond to copies of the same first cache block, but their consistency maintenance setting information is different from each other, so that the current consistency maintenance mode of the copy of the first cache block is determined by the most recently executed instruction. This situation is likely to reduce the optimization effect of the cache consistency active maintenance method.

[0054] To solve the above problem, you can proactively maintain the size of shared variables aligned with the cache block size to avoid this situation as much as possible. The specific reasons are as follows: When the size of shared variables is aligned with the cache block size, the storage location of these variables in the cache will be more likely to occupy a cache line. Since the cache line is the basic storage unit of the cache and the processor accesses the cache in cache lines, alignment can ensure that different memory access instructions will not interfere with each other when maintaining the same cache block copy.

[0055] With alignment, even if two memory instructions access copies of the same cache block and their coherency maintenance settings are different, those settings will not overwrite each other in the same cache line. Because each setting is located in a separate cache line, the processor can correctly identify and perform the coherency maintenance operation required for each setting.

[0056] In summary, by aligning the size of the actively maintained shared variables with the cache block size, conflicts caused by different maintenance settings of the same cache block copy by different memory access instructions can be avoided as much as possible, thereby improving the efficiency and accuracy of cache consistency maintenance.

[0057] In actual use, due to the limited capacity of the first cache block, copies of the first cache block are frequently swapped in and out. A newly swapped-in copy of the first cache block is initialized to passive maintenance mode. Therefore, after the actively maintained copy of the first cache block is swapped out to memory, its active maintenance mode is lost. Nevertheless, the maintenance setting instruction for the active maintenance setting shared variable can cause the cache block copy that is swapped in again to return to active maintenance mode.

[0058] In some optional embodiments, after the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode, the active maintenance mode is always maintained unchanged.

[0059] In this embodiment, to address the issue of two consecutively executed memory access instructions corresponding to copies of the same first cache block but with different consistency maintenance settings, which reduces the optimization effect of the active cache coherence maintenance method, the active maintenance mode is given a higher priority. That is, after a cache block copy is set to active maintenance mode, it will no longer be set to passive maintenance mode.

[0060] Example 2: Another embodiment of the present application relates to an active cache consistency maintenance device. The implementation details of the active cache consistency maintenance device of this embodiment are specifically described below. The following content is only for the convenience of understanding the implementation details provided, and is not necessary for the implementation of this solution. The schematic diagram of the active cache consistency maintenance device of this embodiment can be as follows: Figure 2 As shown, it includes an invalidation operation module 210 , a maintenance mode viewing module 220 , a cache block copy update module 230 and a recovery module 240 .

[0061] an invalidation operation module 210 for performing an invalidation operation on the copy of the first cache block of the target processor core in response to maintaining cache coherence; A maintenance mode checking module 220 is configured to check a consistency maintenance mode of the copy of the first cache block in response to maintaining cache consistency, wherein the consistency maintenance mode includes an active maintenance mode; a cache block copy update module 230 configured to, when the consistency maintenance mode is active maintenance mode, initiate an update command after completing the invalidation operation to update the copy of the first cache block to the latest data content; and The recovery module 240 is configured to restore the copy of the first cache block to a valid state after the copy of the first cache block is updated.

[0062] It is worth mentioning that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovation of this application, this embodiment does not include units that are not closely related to solving the technical problem proposed by this application. However, this does not mean that other units do not exist in this embodiment.

[0063] In an optional embodiment, the method further includes: The maintenance mode checking module is further configured to check consistency maintenance setting information of the maintenance setting instruction in response to receiving the maintenance setting instruction corresponding to the copy of the first cache block, wherein the consistency maintenance setting information is an active maintenance mode or a passive maintenance mode; A maintenance mode setting module is used to set a consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information.

[0064] In some optional embodiments, the maintenance mode setting module includes: The first storage unit is configured to store the consistency maintenance setting information in a preset storage space in the first cache block.

[0065] In some optional embodiments, the maintenance mode setting module includes: The second storage unit is configured to store the consistency maintenance setting information in a table entry corresponding to the first cache block in a directory structure based on a directory protocol.

[0066] In some optional embodiments, the cache block copy update module includes: The first updating unit is configured to initiate an update command after completing the invalidation operation and after a preset waiting time to update the copy of the first cache block to the latest data content.

[0067] In some optional embodiments, the maintenance mode setting module is further configured to always keep the active maintenance mode unchanged after the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode.

[0068] Example 3: Another embodiment of the present application relates to an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the active cache consistency maintenance method in the above-mentioned embodiments.

[0069] The memory and processor are connected using a bus, which can include any number of interconnected buses and bridges. The bus connects various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over a wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to the processor.

[0070] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0071] Example 4: Another embodiment of the present application relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0072] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program. The program is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps in the methods described in the various embodiments of this application. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0073] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. A method for actively maintaining cache consistency, characterized in that: include: In response to maintaining cache consistency, performing an invalidation operation on the copy of the first cache block of the target processor core, and checking a consistency maintenance mode of the copy of the first cache block of the target processor core, wherein the consistency maintenance mode includes an active maintenance mode; In a case where the consistency maintenance mode is an active maintenance mode, after completing the invalidation operation, an update command is initiated to update the copy of the first cache block to the latest data content; as well as After the copy of the first cache block is updated, the copy of the first cache block is restored to a valid state.

2. The active cache consistency maintenance method according to claim 1, characterized in that: Before checking the consistency maintenance mode of the copy of the first cache block, the method further includes: In response to receiving a maintenance setting instruction corresponding to the copy of the first cache block, checking consistency maintenance setting information of the maintenance setting instruction, wherein the consistency maintenance setting information is an active maintenance mode or a passive maintenance mode; A consistency maintenance mode for the copy of the first cache block is set according to the consistency maintenance setting information.

3. The active cache consistency maintenance method according to claim 2, characterized in that: The step of setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information includes: The consistency maintenance setting information is stored in a preset storage space in the first cache block.

4. The active cache consistency maintenance method according to claim 2, characterized in that: The step of setting the consistency maintenance mode of the copy of the first cache block according to the consistency maintenance setting information includes: Based on a directory protocol, the consistency maintenance setting information is stored in a table entry corresponding to the first cache block in a directory structure.

5. The active cache consistency maintenance method according to any one of claims 1 to 4, characterized in that: After completing the invalidation operation, initiating an update command to update the copy of the first cache block to the latest data content, including: After the invalidation operation is completed and after a preset waiting time, an update command is initiated to update the copy of the first cache block to the latest data content.

6. The active cache consistency maintenance method according to any one of claims 1 to 4, characterized in that: In the active maintenance mode, the size of the shared variable is set to be aligned with the first cache block size.

7. The active cache consistency maintenance method according to any one of claims 1 to 4, characterized in that: When the consistency maintenance mode of the copy of the first cache block is set to the active maintenance mode, the active maintenance mode is always maintained unchanged.

8. An active cache consistency maintenance device, characterized in that: include: an invalidation operation module, configured to perform an invalidation operation on the copy of the first cache block of the target processor core in response to maintaining cache coherence; a maintenance mode checking module, configured to check a consistency maintenance mode of the copy of the first cache block in response to maintaining cache consistency, wherein the consistency maintenance mode includes an active maintenance mode; a cache block copy update module, configured to, when the consistency maintenance mode is an active maintenance mode, initiate an update command after completing the invalidation operation to update the copy of the first cache block to the latest data content; as well as A recovery module is configured to restore the copy of the first cache block to a valid state after the copy of the first cache block is updated.

9. An electronic device, characterized in that: include: at least one processor; as well as, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the active cache coherence maintenance method according to any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the active cache coherence maintenance method according to any one of claims 1 to 7 is implemented.

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