Quantum bit mapping method based on cross-graph attention mechanism and general compiler

Abstract

The application relates to a quantum bit mapping method and a general compiler based on a cross-graph attention mechanism, and a training method of a quantum bit mapping model based on a cross-graph attention mechanism, which comprises the following steps: performing an intra-graph adjacency aggregation operation according to hardware node information in a hardware topology graph to obtain an updated hardware node vector; performing an intra-graph adjacency aggregation operation according to logic node information in a quantum logic circuit to obtain an updated logic node vector; calculating the matching degree of the updated hardware node vector and the logic node vector and performing cross-graph attention updates on the logic node vector and the hardware node vector based on the matching degree; inputting the hardware node vector and the logic node vector after the pooling processing into a quantum bit mapping model to be trained to output a mapping quality prediction value; and constructing a loss function based on a mapping quality true value and the mapping quality prediction value, and training a graph neural network model by using a gradient descent method. The method can automatically select an optimal path combination to reduce the calculation complexity.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum computing, in particular to a training method of a quantum bit mapping model based on a cross-graph attention mechanism, a mapping method of a quantum bit based on a cross-graph attention mechanism, a device, a general compiler, an electronic device and a computer program product. BACKGROUND

[0002] Qubit mapping is one of the key steps in quantum compilation, which aims to map logical qubits in a quantum logic circuit to physical qubits reasonably under the physical topology constraints of a given quantum computing device, so as to reduce the number of required gate operations, reduce error rates and improve execution efficiency. Since the hardware topology structures of current mainstream quantum chips are different, and there are complex gate dependency relationships between logical qubits, it has become a research hotspot to construct an efficient and highly generalized qubit mapping strategy.

[0003] Existing qubit mapping methods mainly fall into two categories: optimization algorithms based on heuristic rules and mapping prediction models based on deep learning. The former relies on hand-designed rules and search strategies, which are highly interpretable but difficult to adapt to the development of hardware structures and complex quantum logic circuits. The latter attempts to automatically learn the mapping relationship between logical qubits and physical qubits by training neural network models, thereby improving mapping decision efficiency. However, existing neural network models usually use only one side of the logical circuit information as input, failing to fully model the interaction between the two, making it difficult to capture the structural matching features across graphs. SUMMARY

[0004] Therefore, the embodiments of the present application provide a training method of a quantum bit mapping model based on a cross-graph attention mechanism, a mapping method of a quantum bit based on a cross-graph attention mechanism, a device, a general compiler, an electronic device and a storage medium, which are used to solve at least one technical problem.

[0005] The embodiment of the application provides a training method of a quantum bit mapping model based on a cross-graph attention mechanism, a plurality of training samples are used to train a graph neural network model, each training sample comprises a hardware topology graph and a quantum logic circuit, wherein the training method comprises the following steps: performing an intra-graph adjacency aggregation operation of the graph neural network according to hardware node information of a hardware node to be updated in the hardware topology graph, to obtain an updated hardware node vector; performing the intra-graph adjacency aggregation operation of the graph neural network according to logic node information of a logic node to be updated in the quantum logic circuit, to obtain an updated logic node vector; calculating a matching degree of each updated hardware node vector and each logic node vector, and performing cross-graph attention update on the logic node vector and the hardware node vector based on the matching degree; performing pooling processing on the updated hardware node vector and the logic node vector respectively to obtain a hardware node graph-level vector and a logic node graph-level vector; inputting the hardware node graph-level vector and the logic node graph-level vector into a quantum bit mapping model to be trained, and outputting a mapping quality prediction value; constructing a loss function based on a mapping quality true value and the mapping quality prediction value, and cyclically training the graph neural network model by using a gradient descent method; and in response to a loss function value being less than a loss threshold, outputting a trained quantum bit mapping model.

[0006] According to the training method described above, the initial hardware edge vector and the initial hardware node vectors of all adjacent nodes thereof are determined according to the hardware node information of the hardware node to be updated in the hardware topology graph; and the neighbor information is calculated by using an aggregation function to perform weighted accumulation on the initial hardware edge vector and the initial hardware node vectors of all adjacent nodes thereof, to obtain the updated hardware node vector.

[0007] According to the training method described above, the intra-graph adjacency aggregation operation of the graph neural network is performed on the hardware node information of the hardware node to be updated, comprising the following steps: generating the initial hardware node vector and the initial hardware edge vector by performing normalization processing according to the relaxation time T1, the coherence time T2 and the quantum gate error rate in the hardware node information; calculating the initial hardware edge vector of the hardware node to be updated and the initial hardware node vectors of all adjacent nodes thereof by using a hardware weight matrix, to generate a hardware node aggregation vector; and calculating the initial hardware node vector of the node to be updated and the hardware node aggregation vector by using a nonlinear activation function, to obtain the updated hardware node vector.

[0008] According to the training method described above, the initial logic edge vector and the initial logic node vectors of all adjacent nodes thereof are determined according to the logic node information of the logic node to be updated in the quantum logic circuit; and the neighbor information is calculated by using an aggregation function to perform weighted accumulation on the initial logic edge vector and the initial logic node vectors of all adjacent nodes thereof, to obtain the updated logic node vector.

[0009] The method for training the graph neural network as described above, performing an intra-graph adjacency aggregation operation of the graph neural network on the logical node information of the logical node to be updated comprises: generating an initial logical node vector according to the gate type of a logical gate and the acting qubit position thereof in the logical node information; if there is an execution order between two logical gates and the acting bits overlap, generating an initial logical edge vector according to the execution distance and the bit overlap rate of the two logical gates in the logical node information; calculating the initial logical edge vector of the logical node to be updated and the initial logical node vectors of all adjacent nodes thereof by using a logical weight matrix to generate a logical node aggregation vector; and calculating the initial logical node vector and the logical node aggregation vector of the logical node to be updated by using a nonlinear activation function to obtain an updated logical node vector.

[0010] The method for training the graph neural network as described above, calculating the matching degree of each updated hardware node vector and each logical node vector and performing cross-graph attention update on the logical node vector and the hardware node vector based on the matching degree comprises: calculating the matching degree of each updated hardware node vector and each logical node vector and performing normalization processing on the matching degree to obtain an attention weight; performing weighted information fusion calculation on the updated logical node vector and the hardware node vector and the corresponding attention weight to obtain a cross-graph updated logical node vector; and performing weighted information fusion calculation on the updated hardware node vector and the logical node vector and the corresponding attention weight to obtain a cross-graph updated hardware node vector.

[0011] The method for training the graph neural network as described above, the hardware topology structure in the hardware topology graph is randomly generated based on preconfigured hardware node sampling information and a preset topology structure type.

[0012] The method for training the graph neural network as described above, the generation method of the hardware topology structure comprises: sampling hardware node information for each quantum bit node to be generated, the hardware node information comprising: a relaxation time T1, a coherence time T2 and a quantum gate error rate, the quantum gate error rate comprising: a single-bit gate error rate, a double-bit gate error rate and a readout error rate; generating a topology structure based on a generation rule of a preset topology structure type; and binding the sampled hardware node information and the topology structure to generate a hardware topology graph.

[0013] The method for training the graph neural network as described above, the migration adaptation method of a new chip comprises: obtaining a hardware topology graph of the new chip, inputting the relaxation time T1, the coherence time T2 and the quantum gate error rate data of the hardware topology graph into the quantum bit mapping model trained as described above to calculate a mapping quality prediction value; constructing a migration loss function with a regularization term according to a mapping quality true value and the mapping quality prediction value, and fine-tuning the parameters in the graph neural network model by using a gradient descent method; and in response to the loss function value being less than a loss threshold, outputting a quantum bit mapping model that is adapted for migration.

[0014] According to another aspect of the present application, a quantum bit mapping method based on a cross-graph attention mechanism is provided: a quantum logic circuit to be mapped is obtained, the quantum logic circuit comprising a plurality of logical bits and a logical gate sequence constructed based on the logical bits; the quantum logic circuit is encoded into a logical graph, wherein initial logical node features and logical edge features of each logical gate are included in the logical graph; the logical graph is input into a quantum bit mapping model trained by the above method, and a mapping quality score between the quantum logic circuit and each candidate hardware topology graph is calculated respectively by using a cross-graph attention mechanism; according to the mapping quality score, a hardware topology graph with the highest mapping quality is selected from the candidate hardware topology graphs, and an optimal mapping path of the logical bits to the physical bits in the hardware topology graph is output.

[0015] According to another aspect of the present application, a training device of a quantum bit mapping model based on a cross-graph attention mechanism is provided, comprising: a hardware node updating module configured to perform an intra-graph adjacency aggregation operation of a graph neural network according to hardware node information of a hardware node to be updated in the hardware topology graph, to obtain an updated hardware node vector; a logical node updating module configured to perform an intra-graph adjacency aggregation operation of a graph neural network according to logical node information of a logical node to be updated in the quantum logic circuit, to obtain an updated logical node vector; a cross-graph attention updating module configured to calculate a matching degree of each updated hardware node vector and each logical node vector and perform cross-graph attention updating of the logical node vector and the hardware node vector based on the matching degree; a pooling processing module configured to perform pooling processing on the updated hardware node vector and the logical node vector to obtain a hardware node graph-level vector and a logical node graph-level vector; a mapping quality prediction module configured to input the hardware node graph-level vector and the logical node graph-level vector into a quantum bit mapping model to be trained, and output a mapping quality prediction value; a model training module configured to construct a loss function based on a mapping quality real value and the mapping quality prediction value, and cyclically train the graph neural network model by using a gradient descent method; and a model output module configured to output the trained quantum bit mapping model in response to a loss function value being less than a loss threshold.

[0016] According to another aspect of the present application, a universal quantum compiler based on a cross-graph attention mechanism is provided, comprising: an acquisition module configured to acquire a quantum logic circuit to be mapped, the quantum logic circuit comprising a plurality of logical bits and a logical gate sequence constructed based on the logical bits; an encoding module configured to encode the quantum logic circuit into a logical graph, the logical graph comprising initial logical node features and logical edge features of each logical gate; a mapping quality calculation module configured to input the logical graph into a quantum bit mapping model trained by the method described above, and calculate a mapping quality score between the quantum logic circuit and each candidate hardware topology graph by using a cross-graph attention mechanism; and a mapping path output module configured to select a hardware topology graph with the highest mapping quality from the candidate hardware topology graphs according to the mapping quality scores, and output an optimal mapping path of the logical bits to the physical bits in the hardware topology graph.

[0017] According to another aspect of the present application, an electronic device is provided, comprising a processor and a memory, wherein the memory stores a computer program instruction set, and the processor executes the computer program instruction set on the memory to implement the training method of the quantum bit mapping model described above.

[0018] According to another aspect of the present application, a computer program product is provided, comprising a computer program instruction set, and the computer program instruction set is executed by a processor to implement the training method of the quantum bit mapping model described above.

[0019] The present method calculates the matching degree between each pair of "logical gate node-hardware node" by using a cross-graph attention mechanism, and determines the weight of information interaction based on the value. This structure can simulate "which hardware position is the most likely mapping for the current logical operation", thereby improving the mapping accuracy. The attention mechanism naturally has the ability of "weighted screening", and can automatically learn which physical path (bit connection) and which chip topology are optimal for the current circuit, thereby automatically selecting the optimal path combination from multiple candidate mapping schemes, avoiding exhaustive search, and reducing the computational complexity. BRIEF DESCRIPTION OF DRAWINGS

[0020] Hereinafter, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, in which:

[0021] Figure 1 is a flowchart of a training method of a quantum bit mapping model based on a cross-graph attention mechanism according to an embodiment of the present application.

[0022] Figure 2 is a flowchart of an intra-graph adjacency aggregation method of a graph neural network performed on the hardware node information of the hardware node to be updated in step S110.

[0023] Figure 3is a flowchart of the intra-graph adjacency aggregation method of the graph neural network performed on the hardware node information of the logical node to be updated in step S120.

[0024] Figure 4 is a flowchart of the cross-graph attention update method of the logical node vector and the hardware node vector according to the matching degree in step S130.

[0025] Figure 5 is a flowchart of the migration adaptation method of the new chip according to an embodiment of the present application.

[0026] Figure 6 is a flowchart of the quantum bit mapping method based on the cross-graph attention mechanism according to an embodiment of the present application.

[0027] Figure 7 is a flowchart of the hardware topology generation method according to an embodiment of the present application.

[0028] Figure 8 is a linear topology diagram of the hardware topology generation (HTG) according to an embodiment of the present application.

[0029] Figure 9 is a random topology diagram of the hardware topology generation (HTG) according to an embodiment of the present application.

[0030] Figure 10 is a mesh topology diagram of the hardware topology generation (HTG) according to an embodiment of the present application.

[0031] Figure 11 is a hexagonal topology diagram of the hardware topology generation (HTG) according to an embodiment of the present application.

[0032] Figure 12 is a hardware topology diagram according to an embodiment of the present application.

[0033] Figure 13 is a quantum logic circuit diagram according to an embodiment of the present application.

[0034] Figure 14 is a heat map of the matching degree of the logical gate node and the hardware node according to an embodiment of the present application.

[0035] Figure 15 is a loss function value curve diagram of the training process of the GNN general model according to an embodiment of the present application.

[0036] Figure 16 is a mapping quality prediction value distribution diagram of the training process of the GNN general model according to an embodiment of the present application.

[0037] Figure 17 isFigure 13 A quantum logic circuit graph in Figure 12 A mapping flowchart in a hardware topology graph.

[0038] Figure 18 A quantum logic circuit graph in Figure 13 An optimal mapping path in a hardware topology graph. Figure 12

[0039] Figure 19 A fine-tuning process of a GNN general model on a new chip Super Chip Alpha according to an embodiment of the present application.

[0040] Figure 20 A comparison chart of mean square errors of a general model GNN and a fine-tuned model on Super Chip Alpha data according to an embodiment of the present application.

[0041] Figure 21 An HTG-GNN technical module schematic diagram according to an embodiment of the present application.

[0042] Figure 22 A gate-level circuit graph output by a SABRE compiler according to an embodiment of the present application.

[0043] Figure 23 A gate-level circuit graph output by a dynamic routing quantum compiler according to an embodiment of the present application.

[0044] Figure 24 A comparison chart of measurement results obtained by respectively executing Figure 22 and Figure 23 circuit graphs.

[0045] Figure 25 A comparison chart of circuit depths and gate numbers of respectively executing Figure 22 and Figure 23 circuit graphs.

[0046] Figure 26 A comparison chart of compiling time and sampling time of respectively executing Figure 22 and Figure 23 circuit graphs.

[0047] Figure 27 A quantum qubit mapping model training device structure schematic diagram based on a cross-graph attention mechanism according to an embodiment of the present application.

[0048] Figure 28 A dynamic routing quantum compiler structure schematic diagram according to an embodiment of the present application.

[0049] Figure 29 A hardware structure principle schematic diagram of an electronic device according to an embodiment of the present application.​ DETAILED DESCRIPTION

[0050] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0051] In the following detailed description, reference can be made to the various drawings that form a part of the present disclosure and are used to illustrate specific embodiments of the present application. In the drawings, like numerals describe generally similar components throughout the several views. The various embodiments of the present application are described in sufficient detail to enable those of ordinary skill in the art to make and use the technical solutions of the present application. It should be understood that other embodiments can also be utilized or structural, logical or electrical changes can be made to the embodiments of the present application.

[0052] A graph neural network (GNN) is a neural network that operates directly on graph-structured data, which can capture dependencies in data by learning relationships between nodes and the topology of the graph, and can process data with irregular structures, such as social networks, knowledge graphs, and chemical molecular structures.

[0053] A hardware topology graph (HTG) is a visual structure diagram used to represent physical qubits and their physical connection relationships in a quantum computing chip. It displays the spatial layout and coupling mode of qubits in a graphical manner.

[0054] A quantum logic circuit is a basic framework for describing quantum algorithms in quantum computing, and is a directed acyclic graph composed of a series of quantum gates and qubits.

[0055] The quantum compiler of the present application is a mapping of abstract quantum circuits (logical gate sequences) to physical bits and connection topologies of specific quantum chips, and is a bridge between logical circuits and physical quantum chips.

[0056] Figure 1is a quantum bit mapping model training method flowchart based on a cross-graph attention mechanism according to an embodiment of the present application. The method is based on a graph neural network (GNN) structure and can realize automatic adaptation and mapping scoring between different logical quantum circuits and various hardware topologies. The method is based on a plurality of training sample pairs for modeling and training the graph neural network model. Each training sample pair includes a hardware topology graph and a quantum logic circuit. As shown in Figure 1 the training method includes:

[0057] S110, performing an intra-graph adjacency aggregation operation of the graph neural network according to hardware node information of a hardware node to be updated in the hardware topology graph to obtain an updated hardware node vector;

[0058] S120, performing an intra-graph adjacency aggregation operation of the graph neural network according to logical node information of a logical node to be updated in the quantum logic circuit to obtain an updated logical node vector;

[0059] S130, calculating a matching degree of each updated hardware node vector and each logical node vector and performing cross-graph attention update on the logical node vector and the hardware node vector based on the matching degree;

[0060] S140, performing pooling processing on the updated hardware node vector and the logical node vector to obtain a hardware node graph-level vector and a logical node graph-level vector;

[0061] S150, inputting the hardware node graph-level vector and the logical node graph-level vector into the quantum bit mapping model to be trained to output a mapping quality prediction value;

[0062] S160, constructing a loss function based on the mapping quality true value and the mapping quality prediction value, and using a gradient descent method to cyclically train the graph neural network model;

[0063] S170, in response to the loss function value being less than a loss threshold, outputting the trained quantum bit mapping model.

[0064] In step S110, for each hardware node (i.e., a physical quantum bit in the hardware topology graph) in the hardware topology graph, the hardware node information (i.e., initial edge information) and the initial information of the adjacent nodes are collected. The hardware node information is fused by using the intra-graph adjacency aggregation operation in the graph neural network to obtain an updated hardware node vector. This step is to mine the connection relationship and interaction characteristics between physical quantum bits, so that the model understands the connection structure of the chip and the performance of the physical gate. The hardware node information includes one or more of the relaxation time T1, the coherence time T2, and the quantum gate error rate, and the quantum gate error rate includes one or more of the single-bit gate error rate, the double-bit gate error rate, and the readout error rate.

[0065] In step S120, for each logical node in the quantum logic circuit (i.e., a quantum gate in the quantum logic circuit), logical node information is also collected, including the gate type of the logical gate and its acting qubit position, and the execution distance and bit coincidence rate of two logical gates. The logical node information is applied to an intra-graph adjacency aggregation operation similar to the hardware node update, to obtain an updated logical node vector. By sorting the execution order and mutual dependency between logical gates, such as the order arrangement of specific logical gate operations, whether the acting qubits overlap, and the like, the structural features of the quantum algorithm itself are extracted, facilitating the model to learn the general mapping rule between different circuits.

[0066] In step S130, the matching degree between the logical node vector and the hardware node vector is calculated, which can be realized by calculating the similarity of the information of the two. The matching degree refers to the similarity degree between the logical node and the hardware node in the feature space, which is used to measure the adaptation degree or "goodness of matching" of mapping a certain logical operation to a certain hardware position. Based on the calculated matching degree, the vectors of the logical node and the hardware node are updated and optimized, so that the logical circuit vector and the hardware structure vector can better correspond in the model, and it can be learned which logical gate is more suitable for being placed in which position of the hardware.

[0067] Traditional quantum bit mapping needs to traverse an exponential path, because when assigning logical bits to physical topology, both connectivity constraints (such as CX gates requiring adjacent physical bits) and dynamic routing decisions (such as inserting SWAP gates) must be met. For an n-bit circuit, there are O(n!) choices for the initial mapping, and each subsequent two-gate operation may trigger k swap paths, resulting in a total search space of O(n!·k^g) (g is the number of two-gate operations), which is an NP-Hard problem. The attention mechanism of the present application directly generates an n x n attention matrix through double-graph feature matching (calculation of the similarity between logical gates and physical bit vectors), replaces path enumeration with O(n2) matrix operations, and converts the problem into a polynomial complexity.

[0068] In step S140, the updated hardware node vector and the logical node vector are respectively summarized by pooling processing. Pooling processing is to aggregate the information of a large number of nodes into a whole graph-level information according to certain rules, so as to obtain a vector representing the whole hardware graph and a vector representing the whole logical graph. In this way, the adaptation of a specific circuit and a chip can be evaluated as a whole.

[0069] In step S150, the overall vector representing the logic graph and the overall vector representing the hardware graph are spliced together to form a comprehensive feature information, which is input into the quantum bit mapping model to be trained. The model outputs a mapping quality prediction value, which can be used to evaluate the mapping effect of the current circuit on the target hardware. According to the mapping quality prediction value, the optimal mapping path and the most suitable chip can be selected.

[0070] In step S160, a loss function is constructed to measure the gap between the mapping quality predicted by the model and the actual mapping quality. Using optimization algorithms such as gradient descent, the model's parameters are repeatedly adjusted and updated using real quantum operation data as training samples, gradually improving the prediction accuracy of the model.

[0071] In step S170, when the loss function value in the training process is less than the loss threshold, it is considered that the model has been trained and reaches a convergence state. At this time, the trained general quantum bit mapping model is output, which has good universality. In actual application, as long as the information of the logic circuit is input, the optimal mapping scheme in different chips or the most suitable target chip can be automatically found.

[0072] As can be seen from the above, compared with the traditional optimization algorithm based on heuristic rules, the method of the present application has a significant computational efficiency advantage. The traditional method usually relies on pre-designed search rules and a large number of traversal calculations, which has a large computational overhead and is not easy to adapt to changing hardware topologies. The present application, through bidirectional information fusion of quantum logic circuits and hardware topology graphs, uses graph neural networks to jointly encode both in the training phase, so that the mapping result can be quickly output in the inference phase, greatly reducing the demand for computing resources.

[0073] In addition, through the cross-graph attention mechanism, the model can simultaneously capture the timing dependence of the gate sequence in the logic graph and the performance parameters (such as T1, T2, and error rate, etc.) of the physical bits in the hardware graph, achieving high-precision matching between logical bits and physical bits. The matching degree obtained not only intuitively reflects the matching strength between each logical node and each candidate physical node, but also provides a reliable basis for the selection of subsequent mapping paths, and the final mapping path shows significant improvement over traditional methods in terms of circuit depth, gate number, and fidelity.

[0074] According to an embodiment of the present application, the initial hardware edge vector and the initial hardware node vector of all adjacent nodes of the hardware node to be updated in the hardware topology graph are determined according to the hardware node information of the hardware node; and the updated hardware node vector is obtained by performing weighted accumulation calculation on the neighbor information of the initial hardware edge vector and the initial hardware node vector of all adjacent nodes thereof through an aggregation function.

[0075] In the above embodiments, in order to achieve effective modeling of the hardware topology, the initial edge vector of the adjacent edge and the initial hardware node vector of all adjacent nodes of each hardware node need to be extracted, and the adjacent information is weighted and accumulated or nonlinearly combined through an aggregation function to generate the updated feature representation of the hardware node in the current propagation layer. Through the above aggregation mechanism, the hardware graph embedding constructed can not only accurately reflect the performance indicators of a single node, but also fully capture the global communication potential of the chip structure, thereby providing a reliable structural basis for high-quality mapping of the logic circuit. The aggregation function can include but is not limited to mean aggregation, weighted summation, maximum value selection, or a trainable multi-layer perceptron (MLP) structure.

[0076] For example, when a node is connected to multiple neighbor nodes with low error rate and high fidelity, the updated feature vector of the node will reflect the characteristics of the node having better communication capability in the hardware, which is helpful for subsequent matching of logic bits.

[0077] Figure 2 is a flowchart of the intra-graph aggregation method of the graph neural network performed on the hardware node information of the hardware node to be updated in step S110. As shown in Figure 2 , the method comprises:

[0078] S111, generating an initial hardware node vector and an initial hardware edge vector according to the relaxation time T1, the coherence time T2 and the quantum gate error rate in the hardware node information; wherein the initial hardware node vector and the initial hardware edge vector are represented by the following formula:

[0079]

[0080]

[0081] wherein, is the initial hardware node vector of node j in the hardware topology graph, is the relaxation time of node j, is the maximum theoretical value of the relaxation time for normalization processing, is the coherence time of node j, is the maximum theoretical value of the coherence time for normalization processing, is the single-bit gate error rate of node j, is the readout error rate of node j, is the feature vector of the hardware edge jk, is the two-bit gate error rate of edge jk, is the maximum value of the two-bit gate error rate for normalizing the error rate of the edge, is the relaxation time of node k.

[0082] S112, calculating an initial hardware edge vector of the hardware node to be updated and initial hardware node vectors of all adjacent nodes thereof using a hardware weight matrix to generate a hardware node aggregation vector; wherein the hardware node aggregation vector is represented by the following formula:

[0083]

[0084] wherein, is the hardware node aggregation vector to which node j is aggregated at the lth layer, is the hardware weight matrix of the lth layer, is the hardware node vector of neighbor node k at the (l-1)th layer, is the hardware edge vector of edge jk.

[0085] S113, calculating an initial hardware node vector of the node to be updated and the hardware node aggregation vector using a nonlinear activation function to obtain an updated hardware node vector. Wherein the hardware node vector is updated by the following formula:

[0086]

[0087] wherein, is the updated hardware node vector of node j at the lth layer, is the hardware node vector of node j at the (l-1)th layer, is the hardware update weight matrix of the lth layer, is the hardware node aggregation vector to which node j is aggregated at the lth layer, is the nonlinear activation function.

[0088] The above method not only retains the individualized physical characteristics of the node, but also introduces information about the topology position and connection environment of the node, so that the updated vector has both microscopic performance and macroscopic structural perception ability. In this way, a structure-sensitive and learnable hardware graph representation can be constructed, providing a solid foundation for subsequent logic gate mapping, path selection and quality scoring.

[0089] According to one embodiment of the present application, an initial logic edge vector and initial logic node vectors of all adjacent nodes thereof are determined according to logic node information of a logic node to be updated in a quantum logic circuit; and an updated logic node vector is calculated by weighting and accumulating neighbor information of the logic node to be updated using an aggregation function according to the initial logic edge vector and the initial logic node vectors of all adjacent nodes thereof.

[0090] The steps of updating the logic node vector are similar to the content of updating the hardware node vector, which will not be repeated here. Through the aggregation of the neighbor node information, the order dependence between the logic gates in the quantum circuit, the sharing bit relationship and other structural patterns can be automatically learned, providing a more rich and expressive logic graph representation basis for subsequent matching with the hardware topology graph.

[0091] Figure 3 is a flow chart of the intra-graph aggregation method of the graph neural network for the hardware node information of the logic node to be updated in step S120. As shown in Figure 3 , the method comprises:

[0092] S121, generating an initial logic node vector according to the gate type of the logic gate in the logic node information and the acting quantum bit position; wherein the initial logic node vector is represented by the following formula:

[0093]

[0094] wherein, is the initial logic node vector of node g in the quantum logic circuit, is the gate type, and the information is usually encoded as: one-hot, is the acting quantum bit position;

[0095] S122, if there is an execution order between two logic gates and the acting bits overlap, generating an initial logic edge vector according to the execution distance and the bit overlap rate of the two logic gates in the logic node information; wherein the initial logic edge vector is represented by the following formula:

[0096]

[0097] wherein, is the initial logic edge vector of the logic edge ij, is the execution distance of the logic gates i and j, is the bit overlap rate of the logic gates i and j.

[0098] S123, calculating the initial logic edge vector of the logic node to be updated and the initial logic node vectors of all adjacent nodes thereof by using a logic weight matrix to generate a logic node aggregation vector; wherein the logic node aggregation vector is represented by the following formula:

[0099]

[0100] wherein, is the logic node aggregation vector of node i obtained by aggregation at the lth layer, is the logic weight matrix at the lth layer, is a logical node vector of node i at the l-th layer, is a logical edge vector of edge ij.

[0101] S124, calculating an updated logical node vector by using a nonlinear activation function on the initial logical node vector of the logical node to be updated and the logical node aggregation vector. Wherein, the updated logical node vector is represented by the following formula:

[0102]

[0103] Wherein, is an updated logical node vector of node i at the l-th layer, is a logical node vector of node i at the l-1-th layer, is a logical update weight matrix of the l-th layer, is a logical node aggregation vector aggregated by node i at the l-th layer, is a nonlinear activation function.

[0104] In step S121, the gate type includes but is not limited to single-bit gate (such as H, X) and double-bit gate (such as CX), and the action bit information includes the number of control bits and target bits. The vector can represent the gate type in a fixed dimension embedding manner, and the action bit index is added as position coding (such as one hot coding), so that the model can distinguish the logical function and target quantum bit of different gates.

[0105] In step S122, the initial logical edge vector is used to represent the dependence strength, shared structure and timing distance between two gates, which is an important part of the logical graph structure, and helps the neural network to capture the structural pattern of "context-dependent gate".

[0106] Through the above method, the final logical node vector not only contains the information of the gate itself, but also integrates the execution structure characteristics of other gates in its context, providing a more recognizable logical graph representation for subsequent cross-graph matching.

[0107] Figure 4 is a flow chart of a cross-graph attention updating method for logical node vectors and hardware node vectors according to the matching degree in step S130. As shown in Figure 4 The method comprises the following steps:

[0108] S131, calculating the matching degree of each updated hardware node vector and each logical node vector and normalizing the matching degree to obtain an attention weight;

[0109] S132, performing weighted information fusion calculation on the updated logical node vector and the hardware node vector and the corresponding attention weight to obtain a cross-graph updated logical node vector;

[0110] S133, performing weighted information fusion calculation on the updated hardware node vector and the logical node vector and the corresponding attention weight to obtain a cross-graph updated hardware node vector.

[0111] In step S131, the matching degree can be evaluated by vector inner product, cosine similarity or a learning function in embedding space, for measuring whether a certain logical gate is suitable for mapping to a certain physical quantum bit. Then, all matching degree values are normalized by a Softmax function to obtain the attention weight. The attention weight represents the importance distribution of each node to the current logical node in all hardware nodes. The attention weight can be calculated by the following formula:

[0112]

[0113]

[0114] wherein, is the attention weight of the logical node i and the hardware node j, is the updated logical node vector of the node i at the Lth layer, is the updated hardware node vector of the node j at the Lth layer, is the attention weight matrix, d is the vector dimension, and is used for normalizing the similarity to prevent the vector dimension from expanding and affecting the stability of the model.

[0115] In step S132, calculating the cross-graph updated logical node vector is equivalent to letting the logical gate "perceive" all hardware bits and absorbing the structural information from the optimal mapping candidate to improve the adaptability of its embedding expression. The cross-graph updated logical node vector is calculated by the following formula:

[0116]

[0117] wherein, is the cross-graph updated logical node of the logical node i, is the updated logical node vector of the logical node i at the Lth layer, is the attention weight of the logical node i and the hardware node j, is the updated hardware node vector of the hardware node j at the Lth layer. is a projection matrix, which projects the hardware node feature dimension to the logical feature space .

[0118] In step S133, the cross-graph updated hardware node vector is calculated correspondingly, which enables the hardware node to perceive the structural load and gate sequence characteristics of the current quantum circuit, helps to form a "circuit-aware hardware node embedding", and thus reflects better structural selectivity in subsequent routing scoring. The cross-graph updated hardware node vector is calculated using the following formula:

[0119]

[0120] wherein, is the cross-graph updated logical node of hardware node j, is the updated logical node vector of hardware node j at the Lth layer, is the attention weight of logical node i and hardware node j, is the updated logical node vector of logical node i at the Lth layer. is a projection matrix that projects the features of logical gates from the logical node space to the hardware node space .

[0121] Through the above bidirectional interaction update mechanism, the model establishes an explicit semantic connection between the logical space and the physical space, not only enhancing the interpretability and structural perception ability of the model, but also significantly improving the generalization performance and robustness of the logical bit to physical bit mapping strategy.

[0122] Figure 5 is a flowchart of a migration adaptation method of a new chip according to an embodiment of the present application. As shown in Figure 5 , the method comprises:

[0123] S510, obtaining the hardware topology graph of the new chip, inputting its relaxation time T1, coherence time T2 and quantum gate error rate data into the quantum bit mapping model trained by the quantum bit mapping model training method to calculate a mapping quality prediction value;

[0124] S520, constructing a migration loss function with a regularization term according to the mapping quality true value and the mapping quality prediction value, and fine-tuning the parameters in the graph neural network model using the gradient descent method; wherein the loss function value is calculated using the following formula:

[0125]

[0126] wherein, is the loss function value, N is the number of samples on the new chip data, is the mapping quality true value of the i th sample, obtained from the actual quantum chip running result, is the model mapping quality prediction value of the i th sample, output by the current mapping model inference, a parameter set of a current model (e.g., attention layer, prediction layer weight, etc.), a parameter set of an original general model (trained on an old chip or global data), a regularization coefficient.

[0127] S530, in response to the loss function value being less than the loss threshold, outputting the quantum bit mapping model adapted by migration.

[0128] The mapping quality prediction value is used to measure the theoretical mapping effect of the current circuit on the new hardware structure as the initial benchmark for subsequent model optimization. The mapping quality real value can be obtained by the actual running result of the new chip, and the migration loss function including the regularization term is constructed accordingly. The regularization term is used to constrain the deviation between the model parameters after migration and the original general model parameters, so as to avoid overfitting or loss of original generalization ability of the model. Gradient descent method is used to update part of the parameters in the graph neural network during optimization.

[0129] To improve the fine-tuning efficiency and stability, the embodiment adopts a hierarchical fine-tuning strategy: the aggregation layer parameters of the bottom graph neural network are frozen, and only the cross-graph attention module and the final prediction network layer are optimized. This strategy can complete the adaptation of specific chip characteristics with less parameter change while maintaining the original model structure and knowledge migration ability.

[0130] Through the above migration mechanism, the present application can complete the mapping model optimization of the new chip in about 10 minutes on the premise of only about 50 quantum circuit samples and about 10 rounds of training, which significantly reduces the retraining cost required for heterogeneous hardware deployment, and has good practicability and engineering landing ability.

[0131] To enable the general quantum bit mapping model trained to efficiently adapt to the newly online target quantum chip, the present application further proposes a quantum bit mapping method based on the model. This method is especially suitable for quantum compilation tasks in a heterogeneous chip environment, which significantly reduces the debugging and deployment cost while ensuring the mapping quality. For ease of understanding, Figure 6 schematically shows the complete process of the quantum bit mapping method based on the cross-graph attention mechanism according to an embodiment of the present application.

[0132] Figure 6 is a flowchart of the quantum bit mapping method based on the cross-graph attention mechanism according to an embodiment of the present application. As shown in Figure 6 the method comprises:

[0133] S610, obtaining a quantum logic circuit to be mapped, the quantum logic circuit comprising a plurality of logic bits and a logic gate sequence constructed based on the logic bits;

[0134] S620, encode the quantum logic circuit as a logic graph, wherein initial logic node features and logic edge features of each logic gate are included in the logic graph;

[0135] S630, input the logic graph into a quantum bit mapping model trained by a quantum bit mapping model training method, and calculate mapping quality scores between the quantum logic circuit and each candidate hardware topology graph by using a cross-graph attention mechanism;

[0136] S640, select a hardware topology graph with the highest mapping quality from the candidate hardware topology graphs according to the mapping quality scores, and output an optimal mapping path of logical bits to physical bits in the hardware topology graph.

[0137] In step S620, in the logic graph, each logic gate is represented as a node in the graph and is assigned initial logic node features (including gate type, control / target bit position, etc.); the order-dependent relationship between gate sequences is represented as an edge in the graph, and logic edge features (such as gate spacing, bit overlap rate, etc.) are generated. This graph structure is used as model input to support structure-aware information processing.

[0138] In step S630, the constructed logic graph is input into the trained general quantum bit mapping model. At the same time, multiple candidate hardware topology graphs are loaded, and the matching relationship between the logic circuit and each candidate hardware graph is calculated by using a cross-graph attention mechanism. The mapping quality score of each combination is output to quantitatively represent the expected execution effect of mapping the circuit to the chip.

[0139] In step S640, the scoring results of all candidate hardware topology graphs are compared, and the target chip topology with the highest mapping quality score is selected as the recommended mapping chip for the circuit. At the same time, the attention matching relationship between the logic nodes and the hardware nodes generated inside the model is combined to automatically analyze and output the mapping path of the logical bits to the physical bits, i.e., to complete the final compilation result.

[0140] The method can efficiently predict the optimal mapping combination and routing scheme without enumerating all circuit-chip mapping paths, significantly reducing the compilation time and computational resource overhead. At the same time, thanks to the large amount of topology structure and circuit features absorbed by the model during the training phase, the scheme has good generalization ability and supports fast reasoning and intelligent screening of any new circuit on multiple chip platforms, which is suitable for general compiler design and deployment in a heterogeneous quantum chip environment.

[0141] In order to train a neural network model and realize mapping optimization of a specific hardware device, a large amount of labeled data needs to be collected for the hardware topology, which leads to high training cost, large amount of data labeling, and limits the generalization ability of the model among different quantum chips. In order to solve the technical problem, the present application proposes the following solutions:

[0142] The hardware topology structure in the hardware topology graph is randomly generated based on preconfigured hardware node sampling information and a preset topology structure type. In order to construct a large-scale and diversified quantum chip dataset that can be used to train a quantum bit mapping model, a hardware topology graph with different structure types and performance indicators is automatically constructed based on an HTG (Hardware Topology Graph) generation method.

[0143] Figure 7 is a hardware topology structure generation method flowchart according to an embodiment of the present application. As shown in Figure 7 , the method comprises:

[0144] S710, sampling hardware node information for each quantum bit node to be generated, the hardware node information comprising: relaxation time T1, coherence time T2 and quantum gate error rate, the quantum gate error rate comprising: single-bit gate error rate, double-bit gate error rate and readout error rate;

[0145] S720, generating a topology structure based on a generation rule of a preset topology structure type;

[0146] S730, binding the sampled hardware node information and the topology structure to generate a hardware topology graph.

[0147] In step S710, the specific parameters of the hardware node information can be statistically modeled from real chip samples, or sampled by referring to a typical distribution, so that the generated node features have a sense of reality and diversity in physical performance. By introducing physical level noise modeling, the breadth and difference of hardware features in the training sample are improved, and the model is avoided from being trained only on an ideal structure and lacking actual generalization ability. The present application uses a Monte Carlo sampling method to sample hardware nodes in multiple dimensions of information, and the specific content is as follows:

[0148] (1) Relaxation time T1 sampling

[0149] The relaxation time T1 is the time for the energy of a quantum bit to decay to the initial value, which determines the quantum state retention capability. The relaxation time T1 value is randomly generated within a given hardware upper and lower limit range, thereby providing diversified samples for different hardware characteristics, wherein the relaxation time T1 is sampled by using the following formula:

[0150]

[0151] wherein, is the relaxation time after the i-th sampling, and are the minimum and maximum values of the relaxation time, respectively, is a random variable uniformly distributed in the range [0, 1]

[0152] (2) Coherence time T2sampling

[0153] The coherence time T2is the phase retention time of a quantum state, which determines the length of time that information is preserved during quantum computing. Sampling the coherence time T2can ensure that the coherence times of different quantum hardware are modeled within a reasonable range to simulate the effects of different hardware on quantum state fidelity. The coherence time T2is sampled using the following equation:

[0154]

[0155] wherein, is the coherence time after the i-th sampling, and are the minimum and maximum values of the coherence time, respectively, is a random function uniformly distributed in the range [0, 1].

[0156] (3) Quantum gate error rate sampling

[0157] The quantum gate error rate reflects the accuracy of gate operations during quantum computing, including single-bit gate error rates, double-bit gate error rates, and readout error rates. This parameter is crucial for the execution accuracy and reliability of quantum circuits, wherein the single-bit gate error rate, double-bit gate error rate, and readout error rate are represented using the following equations:

[0158]

[0159]

[0160]

[0161] wherein, is the single-bit gate error rate after the i-th sampling, and are the minimum and maximum values of the single-bit gate error rate, respectively, is a random function uniformly distributed in the range [0, 1]; is the double-bit gate error rate after the i-th sampling, and are the minimum and maximum values of the double-bit gate error rate, respectively, is a random function uniformly distributed in the range [0, 1]; The readout error rate for the i-th sampling, and are the minimum and maximum values of the readout error rate, respectively, is a uniformly distributed random function, and the value range is [0, 1].

[0162] In step S720, the topology type can include but is not limited to linear chain (linear), regular grid (grid), random space (random-space), or heavy hexagonal lattice (heavy-hex), etc. The corresponding generation rule can be completed by using a fixed template, an adjacency matrix construction, or a graph generation algorithm. Generating multiple types of topology graphs can ensure that the generated topology graphs have representative structural characteristics to cover the layout characteristics of the current main flow sub-chip, so that the training model can adapt to multiple chip architectures.

[0163] The linear chain topology is connected by adjacent nodes to form a linear structure, and an edge is established between each node and its next adjacent node to form a linearly connected structure. The generation rule of the linear chain topology is represented by the following formula:

[0164]

[0165] wherein, is the edge set in the hardware topology graph, i is the node number, and the value is from 1 to N-1.

[0166] The grid topology is based on a two-dimensional grid structure, and uses nearest neighbor coupling to connect nodes, so that each node (except special positions such as boundaries) is connected to adjacent nodes above, below, left, and right, forming a chessboard-like topology structure. For example, for a 2x3 grid, there are 7 edges to connect the nodes. The generation rule of the grid topology is represented by the following formula:

[0167]

[0168] wherein, N is the total number of nodes, and based on the above rule, a two-dimensional structure of is approximately composed, and the edges in the grid graph are based on the orthogonal connection between the grid points.

[0169] The random sparse topology is a sparse structure generated according to predetermined parameters, and the generation method is usually to uniformly and randomly sample from all possible edges without repetition to form a sparse connected graph. The number of edges is represented by the formula:

[0170]

[0171] wherein, is the edge set in the hardware topology graph, d is the average degree, i.e., the average number of edges each node wants to connect, and N is the number of nodes.

[0172] Hexagonal topology is a hexagonal architecture simulated by IBM, including connections between a central node and peripheral hexagonal nodes. This topology structure is suitable for more complex quantum hardware design.

[0173] To ensure that the obtained parameter distribution tends to be a theoretical uniform distribution when the sampling scale increases, the present application uses the law of large numbers to verify the mathematical convergence of hardware parameter sampling. Specifically:

[0174] Each hardware topology node is sampled for key physical quantities including relaxation time T1, coherence time T2, and quantum gate error rate. By sampling a large number of samples, the mean value of multiple sample values is calculated;

[0175] By comparing the mean value of the sample value with the theoretical mean value, the relative error is calculated. If the relative error value is within the preset range, it means that the sample values of the relaxation time T1, the coherence time T2, and the gate error rate can converge to the theoretical mean value under a large number of samples, ensuring the accuracy of the model parameters.

[0176] For example, the present application sets the sampling scale At this time, the following table data is obtained:

[0177]

[0178] From the above table data, it can be seen that the sampling method of the present application can ensure that the distribution of hardware parameters meets the physical rationality, and at the same time ensure that the training data of the model can effectively cover all possible hardware conditions in actual application.

[0179] In step S730, the binding process includes assigning node features to each node in the topology graph, and determining edge attributes such as double-bit gate error rate or coupling distance according to the double-bit connection relationship.

[0180] Figure 8 is a linear topology structure diagram generated by a hardware topology structure (HTG) according to an embodiment of the present application. Figure 9 is a random topology structure diagram generated by a hardware topology structure (HTG) according to an embodiment of the present application. Figure 10 is a grid topology structure diagram generated by a hardware topology structure (HTG) according to an embodiment of the present application. Figure 11 is a hexagonal topology structure diagram generated by a hardware topology structure (HTG) according to an embodiment of the present application.

[0181] As Figures 8-11As shown, the HTG generates an instance of a specific topology, binds the sampled physical parameters to the topology, and forms a standardized graph structure representation (e.g., a 100-bit grid topology as shown in the figure). This structure can be used as the "hardware topology graph" part of the input graph neural network model, which is jointly trained with the quantum circuit graph to achieve bit mapping path optimization.

[0182] Through the hardware topology generation method, a large-scale, structurally diverse, and physically constrained quantum chip topology graph for training can be efficiently obtained. The sampled quantum chip topology graph is stored in a topology library, providing a stable and rich source of input samples for subsequent training of quantum bit mapping models.

[0183] In addition, in this application, the proposed HTG (Hardware Topology Generator) generation method can not only be used to automatically generate diversified quantum hardware topology graphs for quantum bit mapping optimization in the training phase, but also can be applied reversely in the structure design and architecture selection phase of quantum chips. Through this method, researchers can input multiple candidate hardware topology structures before the chip is taped out, and run multiple typical quantum circuits on them. By comparing and analyzing the impact of different architectures on the performance of actual circuits based on the mapping fidelity, gate number consumption, circuit depth, and other quality indicators output by the model, the influence of different architectures on the performance of actual circuits can be analyzed.

[0184] This method changes the previous "given chip to select mapping" mode to a new paradigm of "simulating mapping to deduce chip structure", which can effectively guide the structure selection and connection optimization in the early stage of chip design, improve the adaptability of hardware to high-frequency use circuits, and thus realize the coordinated optimization of computing efficiency and process cost at the system level. This "circuit-driven chip architecture co-design" capability significantly enhances the engineering landing potential of the model in chip design, simulation verification, and EDA process. The HTG generator can quickly simulate multiple topology schemes before the chip is taped out, realize "circuit-chip co-design", provide a new paradigm for EDA engineering, greatly reduce design cost, and speed up iteration.

[0185] The above describes the implementation of the embodiments of the present application and the advantages brought by the embodiments through multiple embodiments. The following describes the specific processing process of the training method of the general quantum bit mapping model of the present application in detail in combination with specific examples.

[0186] Suppose that the hardware topology generation method in Figure 7 is used to obtain a hardware topology graph with 4 nodes and 3 edges. The structure graph is shown in Figure 12 , and the parameters of the structure are shown in the following table:

[0187]

[0188] Randomly obtain a 3-qubit quantum logic circuit, and the quantum logic circuit diagram is as shown in Figure 13 The training process of a general quantum bit mapping model (also referred to as a GNN general model) is introduced by taking the hardware topology diagram in Figure 12 and the quantum logic circuit diagram in Figure 13 as examples.

[0189] 1. Perform an intra-graph adjacency aggregation operation of a graph neural network on hardware node information of a hardware node to be updated in the hardware topology structure in Figure 12 .

[0190] 1.1 Node feature normalization

[0191] Node 1: ;

[0192] Node 2: ;

[0193] Node 3: ;

[0194] Node 4: .

[0195] 1.2 Edge feature calculation )

[0196] Edge 1→2: ;

[0197] Edge 2→3: ;

[0198] Edge 3→4: .

[0199] 1.3 Neighbor aggregation (take node 2 as an example):

[0200]

[0201]

[0202] .

[0203] 1.4 Hardware node update (take node 2 as an example):

[0204] .

[0205] 2. Perform an intra-graph adjacency aggregation operation of a graph neural network on logic node information of a logic node to be updated in the quantum logic circuit diagram in Figure 13 .

[0206] 2.1 Logic node feature (gate type encoding: H=0, CX=1)

[0207] Gate 1 (H): / / single-bit gate, target bit = -1;

[0208] Gate 2 (CX): / / CX gate, control bit = 1, target bit = 2;

[0209] Gate 3 (CX): / / CX gate, control bit = 2, target bit = 3.

[0210] 2.2 Dependent edge features

[0211] Gate 1 -> Gate 2:

[0212] , ;

[0213] Gate 2 -> Gate 3:

[0214] , ;

[0215] Gate 1 -> Gate 3:

[0216] , .

[0217] 2.3 Neighbor aggregation (take Gate 2 as an example)

[0218]

[0219] 2.4 Logic node update (take Gate 2 as an example)

[0220] .

[0221] 3. Update the logical node vector and the hardware node vector respectively with cross-graph attention (double graph fusion and quality prediction).

[0222] 3.1 Calculate the matching degree between logical gate nodes and hardware nodes (take logical gate 2 (CXq1->q2) and hardware node 2 as an example)

[0223] Input features (output from steps 1 and 2):

[0224] (Features of logical gate 2)

[0225] (Features of hardware node 2)

[0226] Similarity calculation: Let It is the identity matrix. (Simplified calculation)

[0227]

[0228] Attention weight calculation: Assuming similarity with other nodes:

[0229] sim(gate2, node1) = 0.32

[0230] sim(gate2, node3) = 0.41

[0231] sim(gate2, node4) = 0.28

[0232]

[0233] By calculating the matching degree between each logic gate node and the hardware node, we can obtain the following: Figure 14 The heatmap shown is from... Figure 14 As can be seen, the horizontal axis represents 4 candidate physical bits (hardware nodes); the vertical axis represents 3 input logical bits (logical nodes); each colored square Aij represents the attention weight (matching degree) between logical bit Li and physical bit Qj, with a value range of [0,1]; the darker the color, the higher the degree of matching. The larger the value The higher the matching degree The fewer SWAP gates required, the more likely the model is to map the logical bit to the physical bit.

[0234] It should be noted that the attention heatmap reveals the model's matching preferences between different logical-physical bit pairs, which is used to explain the model's routing process. However, the final mapping path selection takes into account the coupling relationship between all logical bits and the overall graph structure. Therefore, the maximum value of the attention weight in the heatmap does not necessarily have to be strictly consistent with the final mapping path.

[0235] 3.2 Update Feature Vectors

[0236] Logic gate 2 fusion features:

[0237]

[0238]

[0239] Hardware Node 2 Fusion Features:

[0240]

[0241]

[0242] 3.4, Pooling the updated hardware node vector and logical node vector to get hardware node graph-level vector and logical node graph-level vector, respectively.

[0243] Logical graph-level features (MaxPool): Assume three gate fusion features:

[0244] Gate 1: [0.35, 0.28, 0.42];

[0245] Gate 2: [1.035, 0.962, 0.781, 0.011]; <- max value

[0246] Gate 3: [0.68, 0.75, 0.61];

[0247] .

[0248] Hardware graph-level features (MeanPool): Assume four node fusion features:

[0249] Node 1: [0.42, 0.38, 0.29, 0.03];

[0250] Node 2: [0.934, 0.4016, 0.2068, 0.041];

[0251] Node 3: [0.57, 0.48, 0.35, 0.02];

[0252] Node 4: [0.89, 0.31, 0.28, 0.04].

[0253]

[0254] .

[0255] 4, Map quality prediction

[0256] 4.1 Concatenate features:

[0257]

[0258] Predictive model (simplified calculation): Let

[0259] 4.2 Calculate linear transformation:

[0260]

[0261] 4.3 ReLU activation: ReLU(0.72249) = 0.72249

[0262] 4.3 Calculate the map quality prediction value:

[0263] .

[0264] 5. Loss function and optimization

[0265] Assume real mapping quality , regularization coefficient :

[0266]

[0267] Optimize parameters by gradient descent:

[0268] (1) Calculate the gradient of the loss function with respect to the parameters;

[0269] (2) Update parameters: ;

[0270] (3) Repeat until (loss threshold).

[0271] Figure 15 is a loss function value curve diagram of the training process of a GNN general model according to an embodiment of the present application. As shown in Figure 15 , the horizontal axis represents the training epoch (Epoch), and the vertical axis represents the prediction error (Mean Squared Error, MSE). Among them, the training error (blue line) and the test error (red line) decrease rapidly in a short time, and tend to be stable after about the 10th round, which indicates that the model has fully learned the matching rule between the hardware topology and the quantum circuit, and has good generalization ability.

[0272] Figure 16 is a mapping quality prediction value distribution diagram of the training process of a GNN general model according to an embodiment of the present application. As can be seen from Figure 16 , all data points are basically distributed along the ideal diagonal line, indicating that the prediction value output by the model is highly consistent with the real mapping effect, which reflects the high accuracy and high fidelity of the model in the prediction of the quality of quantum bit mapping.

[0273] 6. Output the trained model

[0274] After training, save the model parameters:

[0275] Attention weight matrix;

[0276] GNN weight matrix;

[0277] Prediction network weight.

[0278] Suppose that the quantum logic circuit in Figure 13 is mapped to Figure 12In the hardware topology in FIG. 1, the mapping process is as shown in the mapping flowchart in FIG. 2. After updating the features of both by extracting them respectively, the mapping quality value is obtained by double-graph fusion as 0.92, which is greater than the preset mapping threshold 0.9. Therefore, this mapping is adopted, otherwise, the hardware topology is replaced to recalculate. The best mapping path using the hardware topology is as shown in FIG. 3. Figure 17 Figure 18

[0279] In FIG. 4, the logical graph contains logical gates (such as H gates and CX gates) and their effects on logical bits q1-q3, and the hardware graph contains physical nodes 1-4 and their edge weights (including error rate, T1, T2, etc.). Figure 18

[0280] 7, Migration adaptation mechanism

[0281] The hardware data of the new chip Super Chip Alpha is shown in the following table:

[0282]

[0283] 7.1 Calculate the mapping quality prediction value

[0284] Use the model trained in step 6 to process the new chip

[0285] Normalize the node features:

[0286] ;

[0287] ;

[0288] .

[0289] Normalize the edge features :

[0290] ;

[0291] .

[0292] 7.2 Hardware node update

[0293] Use the trained to calculate the updated features:

[0294]

[0295] 7.3 Double-graph fusion and prediction

[0296] Calculate the attention weight (use the pre-trained ):

[0297] ​​​

[0298] Feature fusion:

[0299]

[0300] Predicted output:

[0301] 7.4 Transfer learning optimization

[0302] First, obtain the real mapping quality:

[0303] Test the real mapping quality by running the test on actual quantum hardware

[0304] Then, construct the transfer loss function:

[0305] Set the transfer regularization weight )

[0306] Finally, use gradient descent optimization:

[0307] Calculate the gradient:

[0308] Update the parameters: (Learning rate )

[0309] Iterate until convergence:

[0310]

[0311] Figure 19 is the fine-tuning process of the GNN general model according to an embodiment of the present application on the new chip Super Chip Alpha, as shown in Figure 19 The horizontal axis represents the number of training epochs (Epoch), and the vertical axis represents the mean square error (MSE). At Epoch 0, the mean square error (MSE) of the model is relatively high, about 0.012, which is the performance of the initial model on the Super Chip Alpha data. As the training progresses (Epoch 1-14), the mean square error of the model gradually decreases. After multiple Epoch training, the model's MSE stabilizes at about 0.0041 at Epoch 14, showing that the model's performance on the Super Chip Alpha data is continuously improving.

[0312] Output the adapted model:

[0313] When , stop, and finally , close to the true value 0.75, save the adapted parameters .

[0314] Figure 20 is a comparison chart of mean square error of general model GNN and fine-tuned model on Super Chip Alpha data according to an embodiment of the present application. As shown in Figure 20 , the mean square error of the general model is 0.0103, while the mean square error of the fine-tuned model is significantly reduced to 0.0002. It can be proved that the fine-tuning process effectively improves the fitting ability of the model on the specific chip (Super Chip Alpha) data. The fine-tuned model can better capture the characteristics of Super Chip Alpha, reduce the prediction error, and be suitable for accurate analysis and design optimization of the chip.

[0315] From the above, the new chip migration adaptation mechanism of the present application can constrain the migration process by introducing a regularization term. The model can still retain the understanding ability of the original general model for typical topological structures (such as chain connection) when adapting to new hardware parameters (such as coherence time improvement), realizing generalization learning and rapid migration across chip structures. In addition, compared with the general model which usually needs hundreds of rounds of training, the migration adaptation mechanism only needs about 15 rounds of iteration to complete the new chip adaptation, greatly reducing the model retraining cost, significantly improving the engineering deployment efficiency, and meeting the time constraints in the rapid iteration scene of the chip. Finally, in the actual adaptation experiment, the prediction error of the model mapping quality is controlled below 0.001, fully meeting the industrial-level precision requirements, and providing reliable protection for the stable and efficient operation of quantum circuits on new hardware.

[0316] Figure 21 is a schematic diagram of the HTG-GNN technology module according to an embodiment of the present application. As shown in Figure 21 , the quantum bit mapping system includes five functional modules, which are HTG topology generation engine, double graph attention training pool, quantum compiler adaptation center, deployment module, and collectively build an end-to-end efficient mapping and evaluation mechanism of quantum logic circuit to physical chip.

[0317] First, in the HTG topology generation engine, multiple basic hardware topology structure types are supported, including linear structure (Linear), random space structure (Random-Space), two-dimensional grid structure (Grid), and heavy hexagonal structure (Heavy-Hex), etc. By injecting physical-level parameters (such as relaxation time , coherence time and readout error), and supporting dynamic parameters such as controlling connection density, a representative set of hardware topology graphs can be constructed, and a total of thousands of topology samples of multiple types can be output for model training.

[0318] In the dual-graph attention training pool module, the gate sequence and dependency information are extracted from the quantum logic circuit, a logic graph is constructed, the connectivity and physical characteristics of the quantum chip are analyzed to construct a hardware graph, and the attention mechanism constructed by the graph neural network is fused. During the training process, the model aggregates the neighbor information of the logic nodes and the hardware nodes respectively, calculates the node matching degree (i.e. mapping tendency) between the two graphs, forms a cross-graph attention score, and predicts the execution cost (such as gate depth, SWAP gate introduction amount, etc.) of the logic gate under the current hardware topology. The model continuously adjusts its structure and parameters through the score feedback, and finally obtains a bit mapping network that can generalize different circuits and different topologies.

[0319] In order to further improve the generality and engineering deployment efficiency of the model, the quantum compiler adaptation center module supports multiple adaptation mechanisms. Among them, the "circuit-topology compression matrix" is constructed to evaluate the matching effect, and the target chip features are extracted for transfer learning training, realizing a fine-tuning mechanism that only requires a small amount of new samples. At the same time, this module can also output the mapping path and the optimized gate-level instruction sequence, which can be used to drive the actual quantum compiler.

[0320] In the deployment module, the present application supports multiple target quantum hardware platforms (such as superconducting quantum chips, ion trap chips, etc.). The model realizes dynamic readiness response and path adjustment according to the actual hardware feedback, has error avoidance capability, and ensures stable operation on the actual chip.

[0321] In summary, Figure 21 The HTG-GNN technology module in the above-mentioned figure shows the technical chain of the system in the whole process of "multi-topology generation-dual-graph learning-fine-tuning adaptation-industrial deployment", which significantly improves the compilation efficiency, mapping fidelity and automated deployment capability of quantum logic circuits on heterogeneous chips, and has good engineering landing performance.

[0322] To further verify the generality and superiority of the method in different quantum circuits and various hardware topologies, three specific embodiments are given below.

[0323] Embodiment 1: Grover search algorithm compilation

[0324] The test target of this embodiment is a 9-bit Grover search algorithm running in a random sparse topology. The physical parameters of this topology are set as follows: , and the error rate of the two-bit gate is 0.025±0.01. The effect of the dual-graph attention mechanism model in the present application and the traditional single-graph GNN model is compared, and the specific data is shown in the following table:

[0325]

[0326] The application can identify a low error rate connection in multiple candidate mapping paths by introducing a cross-graph attention mechanism , and preferentially map the oracle gate operation in Grover to a path with higher physical fidelity, thereby minimizing error propagation.

[0327] Embodiment 2: Multi-topology migration test

[0328] To verify the adaptation capability of the model of the application between heterogeneous chips, this embodiment selects a two-dimensional grid structure (16 quantum bits) as the source domain hardware, and the target domain is a superconducting chip Baihua-156 qubits with random sparse connection characteristics, and performs migration learning comparison test, and the results are as follows:

[0329] Indicator Direct prediction After fine-tuning Magnitude of improvement Initial MSE 6.2e-4 8.1e-5 86.9% Circuit depth 18.7% 5.3% 71.7% Adaptation time - 8 minutes 37 seconds -

[0330] The application adopts a transfer mechanism with regularization, freezes part of the bottom GNN parameters, and only fine-tunes the attention layer and prediction layer weights, which can realize rapid adaptation in 50 training samples and 15 iterations, and the model prediction error is less than 0.001, meeting the industrial deployment precision requirements.

[0331] Embodiment 3: Verification test of compilation effect based on HTG+GNN mapping optimization

[0332] This experiment takes a quantum logic circuit with 5 quantum bits as the object, and performs mapping optimization on a 5-node mesh structure. The experiment is divided into two groups:

[0333] Comparison group: use SABRE compiler to perform mapping;

[0334] This application group: use the dynamic routing quantum compiler of the application to perform mapping.

[0335] Input the quantum logic circuit with 5 quantum bits into the SABRE compiler and the dynamic routing quantum compiler of the application respectively, output the gate-level circuit diagram, and quantitatively compare the indicators (circuit sampling distribution consistency, circuit depth, gate number and compilation time.

[0336] Figure 22 is the gate-level circuit diagram (referred to as the first circuit) output by the SABRE compiler according to an embodiment of the application, Figure 23 is the gate-level circuit diagram (referred to as the second circuit) output by the dynamic routing quantum compiler according to an embodiment of the application. Reference Figure 22 , the mapping logic of the first circuit does not fully consider the hardware fidelity and connection cost, resulting in multiple SWAP gates being inserted between key gates, introducing redundant paths, and causing the overall circuit to be lengthened. Reference Figure 23 , the second circuit preferentially selects a path with lower physical error rate, Higher physical nodes, and automatically find the shortest connection path in the spatial topology, form a more compact gate sequence.

[0337] Figure 24 are respectively executed Figure 22 and Figure 23 The comparison chart of the measurement results obtained by the circuit diagrams in and. As shown in Figure 24 , the circuit of the compiler of the present application retains the logical structure of the original circuit, and after real hardware backend sampling test, it is found that the probability distribution of the two compiler outputs remains consistent in the main peak position, which indicates that no additional quantum state deviation is introduced in the optimization process, ensuring the correctness of the running results.

[0338] Figure 25 are respectively executed Figure 22 and Figure 23 The comparison chart of the circuit depth and the number of gates of the circuit diagrams. Referring to Figure 25 , it can be obviously observed that the circuit depth and the number of gates of the circuit diagram output by the compiler of the present application are significantly reduced, which indicates that the GNN can effectively avoid redundant SWAP gates in the mapping path selection, guide the gate sequence to be embedded in the topology structure more compactly, and improve the circuit execution efficiency.

[0339] Figure 26 are respectively executed Figure 22 and Figure 23 The comparison chart of the compilation time and the sampling time of the circuit diagrams. As shown in Figure 26 , the compiler of the present application has shorter processing time in both stages (compilation time and sampling time), especially in the compilation stage, which reflects the compression advantage of the GNN general model in path scoring on the search space, which helps to improve the system response speed when deploying large-scale circuits.

[0340] Corresponding to the method embodiment of the present application, the present application also provides a training device of a quantum bit mapping model based on a cross-graph attention mechanism, as shown in Figure 27 , the training device comprises:

[0341] The hardware node updating module 101 is configured to perform in-graph adjacency aggregation operation of the graph neural network according to the hardware node information of the hardware node to be updated in the hardware topology graph, and obtain the updated hardware node vector.

[0342] The logic node updating module 102 is configured to perform in-graph adjacency aggregation operation of the graph neural network according to the logic node information of the logic node to be updated in the quantum logic circuit, and obtain the updated logic node vector.

[0343] The cross-graph attention update module 103 is configured to calculate the matching degree of each updated hardware node vector and each updated logical node vector, and update the logical node vector and the hardware node vector based on the matching degree respectively through cross-graph attention;

[0344] The pooling processing module 104 is configured to perform pooling processing on the updated hardware node vector and the updated logical node vector respectively to obtain a hardware node graph-level vector and a logical node graph-level vector;

[0345] The mapping quality prediction module 105 is configured to input the hardware node graph-level vector and the logical node graph-level vector into a to-be-trained qubit mapping model, and output a mapping quality prediction value;

[0346] The model training module 106 is configured to construct a loss function based on the mapping quality true value and the mapping quality prediction value, and train the graph neural network model through gradient descent method;

[0347] The model output module 107 is configured to output the trained qubit mapping model in response to the loss function value being less than a loss threshold.

[0348] Corresponding to the method embodiments of the present application, the present application also provides a general quantum compiler based on the cross-graph attention mechanism, as shown in Figure 28 The general quantum compiler 200 includes:

[0349] The acquisition module 201 is configured to acquire a quantum logic circuit to be mapped, the quantum logic circuit including a plurality of logical qubits and a logical gate sequence constructed based on the logical qubits;

[0350] The encoding module 202 is configured to encode the quantum logic circuit into a logical graph, the logical graph including initial logical node features and logical edge features of each logical gate;

[0351] The mapping quality calculation module 203 is configured to input the logical graph into a qubit mapping model trained by the method described above, and calculate the mapping quality score between the quantum logic circuit and each candidate hardware topology graph through the cross-graph attention mechanism;

[0352] The mapping path output 204 is configured to select a hardware topology graph with the highest mapping quality from the candidate hardware topology graphs according to the mapping quality score, and output an optimal mapping path of the logical qubits to the physical qubits in the hardware topology graph.

[0353] Figure 29Fig. 1 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application. The electronic device can be implemented as a server or other various terminal devices, such as a desktop personal computer, a tablet computer, a laptop computer, a mobile phone, etc. The electronic device includes a processor 601 and a memory 602. The memory 602 stores a set of instructions. The set of instructions comprises functionality of training a quantum qubit mapping model based on a cross-graph attention mechanism and mapping a quantum qubit based on the trained quantum qubit mapping model, which are described above. The processor 601 executes the set of instructions stored in the memory 602.

[0354] In particular, the processor 601 can include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or can be configured to implement one or more integrated circuits configured to implement embodiments of the present application.

[0355] The memory 602 can include a mass storage, which can be used for storing data or instructions. As an example and not by way of limitation, the memory 602 can include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disc (e.g., a CD-ROM or DVD-ROM), a magneto-optical disc, a magnetic tape, or a Universal Serial Bus (USB) drive or a combination of two or more of these. Where appropriate, the memory 602 can include removable or non-removable (or fixed) media, where appropriate. Where appropriate, the memory 602 can be internal or external to the integrated gateway disaster recovery device. In a particular embodiment, the memory 602 is non-volatile, solid-state memory.

[0356] The memory can include read-only memory (ROM), random-access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, electrical, optical, or other physically tangible storage device. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software that, when executed (e.g., by one or more processors), is operable to perform the training a quantum qubit mapping model based on a cross-graph attention mechanism and mapping a quantum qubit based on the trained quantum qubit mapping model provided by the present application.

[0357] In one example, the electronic device can further include a communication interface 603 and a bus 604. The processor 601, the memory 602, and the communication interface 603 are connected through the bus 604 and complete communication with each other. The communication interface 603 is mainly used to realize the communication between various modules, devices, units, and / or equipment in the embodiments of the application. The bus 604 includes hardware, software, or both, which couples the components of the online data traffic billing device to each other. By way of example, and without limitation, the bus can include an accelerated graphics port (AGP) or other graphics bus, an enhanced industry standard architecture (EISA) bus, a frontside bus (FSB), a hypertransport (HT) interconnect, an industry standard architecture (ISA) bus, an infiniband interconnect, a low pin count (LPC) bus, a memory bus, a microchannel architecture (MCA) bus, a peripheral component interconnect (PCI) bus, a PCI-express (PCI-X) bus, a serial advanced technology attachment (SATA) bus, a video electronics standards association local (VLB) bus, or other suitable bus or combination of two or more of these. The bus 604 can include one or more buses, as appropriate. Although particular buses are described and illustrated in the embodiments of the application, the application contemplates any suitable bus or interconnect.

[0358] The application further provides a computer-readable storage medium having stored thereon computer program instructions, which, when executed by a processor, implement any of the foregoing embodiments of the training method and the quantum bit mapping method based on a cross-graph attention mechanism quantum bit mapping model. The computer-readable storage medium can be any medium that can tangibly contain or store computer-executable instructions for use by or in connection with an instruction execution system, apparatus, or device. The storage medium can be a transitory computer-readable storage medium or a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium can include, but is not limited to, a magnetic storage device, an optical storage device, and / or a semiconductor memory device. The corresponding embodiments of such storage devices include, for example, a magnetic disk, a CD, a DVD, or a Blu-ray disc based optical disk, and a persistent solid-state memory such as a flash memory, a solid-state drive, and the like.

[0359] The application further provides a computer program product including a set of computer program instructions, which, when executed by a processor, implement any of the foregoing embodiments of the training method and the quantum bit mapping method based on a cross-graph attention mechanism quantum bit mapping model. The computer program product includes, but is not limited to, an application installation package published in a website or an application store, an application plug-in, an applet that can run in some applications, and the like.

[0360] It is to be understood that the application is not limited to particular configurations and processes described herein and shown in the drawings, which can vary. For the sake of brevity and clarity, detailed descriptions of known methods will not be described herein in detail. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the application are not limited to the specific steps described and shown, and one of ordinary skill in the art can make various changes, modifications, and additions, or change the order of the steps, after understanding the spirit of the application.

[0361] The above embodiments are only used to illustrate the present application, but not to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application, and all equivalent technical solutions shall belong to the scope of the present application.

Claims

1. A method for training a quantum bit mapping model based on a cross-graph attention mechanism, characterized in that, The graph neural network model is trained using multiple training samples, each of which includes a hardware topology graph and a quantum logic circuit, wherein the training method comprises: performing an intra-graph adjacency aggregation operation of the graph neural network according to the hardware node information of the hardware node to be updated in the hardware topology graph to obtain an updated hardware node vector; performing an intra-graph adjacency aggregation operation of the graph neural network according to the logic node information of the logic node to be updated in the quantum logic circuit to obtain an updated logic node vector; calculating the matching degree of each updated hardware node vector and each logic node vector and performing cross-graph attention update on the logic node vector and the hardware node vector based on the matching degree; performing pooling processing on the updated hardware node vector and the logic node vector to obtain a hardware node graph-level vector and a logic node graph-level vector, respectively; inputting the hardware node graph-level vector and the logic node graph-level vector into the quantum bit mapping model to be trained to output a mapping quality prediction value; constructing a loss function based on the mapping quality true value and the mapping quality prediction value, and using the gradient descent method to train the graph neural network model in a loop; in response to the loss function value being less than a loss threshold, outputting the trained quantum bit mapping model.

2. The training method of claim 1, wherein, According to the hardware node information of the hardware node to be updated in the hardware topology graph, the initial hardware edge vector and the initial hardware node vector of all adjacent nodes are determined; and the neighbor information of the initial hardware edge vector and the initial hardware node vector of all adjacent nodes is calculated by an aggregation function to obtain an updated hardware node vector.

3. The training method of claim 1, wherein, The intra-graph adjacency aggregation operation of the graph neural network on the hardware node information of the hardware node to be updated comprises: normalizing the relaxation time T1, the coherence time T2 and the quantum gate error rate in the hardware node information to generate an initial hardware node vector and an initial hardware edge vector; calculating the initial hardware edge vector of the hardware node to be updated and the initial hardware node vector of all adjacent nodes using a hardware weight matrix to generate a hardware node aggregation vector; calculating the initial hardware node vector of the node to be updated and the hardware node aggregation vector using a nonlinear activation function to obtain an updated hardware node vector.

4. The training method of claim 1, wherein, According to the hardware node information of the hardware node to be updated in the hardware topology graph, the initial hardware edge vector and the initial hardware node vector of all adjacent nodes are determined; and the neighbor information of the initial hardware edge vector and the initial hardware node vector of all adjacent nodes is calculated by an aggregation function to obtain an updated hardware node vector.

5. The training method of claim 1, wherein, The intra-graph adjacency aggregation operation of the graph neural network on the hardware node information of the hardware node to be updated comprises: generating an initial logic node vector according to the gate type and the acting quantum bit position of the logic gate in the logic node information; if there is an execution order between two logic gates and the acting bits overlap, generating an initial logic edge vector according to the execution distance and the bit overlap rate of the two logic gates in the logic node information; calculating an initial logical edge vector of the to-be-updated logical node and initial logical node vectors of all adjacent nodes of the to-be-updated logical node by using a logical weight matrix to generate a logical node aggregation vector; calculating the initial logical node vector of the to-be-updated logical node and the logical node aggregation vector by using a nonlinear activation function to obtain an updated logical node vector.

6. The training method of claim 1, wherein, calculating the matching degree of each updated hardware node vector and each logical node vector and performing cross-graph attention update on the logical node vector and the hardware node vector based on the matching degree includes: calculating the matching degree of each updated hardware node vector and each logical node vector and performing normalization processing on the matching degree to obtain an attention weight; performing weighted information fusion calculation on the updated logical node vector and the hardware node vector and the corresponding attention weight to obtain a cross-graph updated logical node vector; performing weighted information fusion calculation on the updated hardware node vector and the logical node vector and the corresponding attention weight to obtain a cross-graph updated hardware node vector.

7. The training method of claim 1, wherein, The hardware topology structure in the hardware topology graph is randomly generated based on preconfigured hardware node sampling information and a preset topology structure type.

8. The training method of claim 7, wherein, The generation method of the hardware topology structure includes: sampling hardware node information for each to-be-generated quantum bit node, the hardware node information including: relaxation time T1, coherence time T2, and quantum gate error rate, the quantum gate error rate including: single-bit gate error rate, double-bit gate error rate, and readout error rate; generating a topology structure based on a generation rule of a preset topology structure type; binding the sampled hardware node information with the topology structure to generate a hardware topology graph.

9. A new chip migration adaptation method includes: obtaining the hardware topology graph of the new chip, inputting the relaxation time T1, the coherence time T2, and the quantum gate error rate data into the quantum bit mapping model trained by the training method of the quantum bit mapping model based on the cross-graph attention mechanism in any one of claims 1-8 to calculate a mapping quality prediction value; constructing a transfer loss function with a regularization term according to the mapping quality true value and the mapping quality prediction value, and fine-tuning the parameters in the graph neural network model by using the gradient descent method; in response to the loss function value being less than a loss threshold, outputting a quantum bit mapping model that is adapted for migration.

10. A quantum qubit mapping method based on cross-graph attention mechanism, characterized in that, The method includes: obtaining a quantum logic circuit to be mapped, the quantum logic circuit including a plurality of logical bits and a logical gate sequence constructed based on the logical bits; encoding the quantum logic circuit into a logical graph, the logical graph including initial logical node features and logical edge features of each logical gate; inputting the logical graph into the quantum bit mapping model trained by the method in any one of claims 1-8, and calculating the mapping quality score between the quantum logic circuit and each candidate hardware topology graph by using the cross-graph attention mechanism; selecting a hardware topology graph with the highest mapping quality from the candidate hardware topology graphs according to the mapping quality score, and outputting the best mapping path of the logical bits to the physical bits in the hardware topology graph.

11. A training device of a quantum bit mapping model based on a cross-graph attention mechanism, characterized in that, includes: The hardware node updating module is configured to perform an intra-graph adjacency aggregation operation of the graph neural network according to hardware node information of a hardware node to be updated in the hardware topology graph, to obtain an updated hardware node vector. The logic node updating module is configured to perform an intra-graph adjacency aggregation operation of the graph neural network according to logic node information of a logic node to be updated in the quantum logic circuit, to obtain an updated logic node vector. The cross-graph attention updating module is configured to calculate a matching degree of each updated hardware node vector and each logic node vector, and perform cross-graph attention updating on the logic node vectors and the hardware node vectors based on the matching degree. The pooling processing module is configured to perform pooling processing on the updated hardware node vectors and the logic node vectors, to obtain hardware node graph-level vectors and logic node graph-level vectors. The mapping quality prediction module is configured to input the hardware node graph-level vectors and the logic node graph-level vectors into the quantum bit mapping model to be trained, and output a mapping quality prediction value. The model training module is configured to construct a loss function based on the mapping quality true value and the mapping quality prediction value, and train the graph neural network model by using a gradient descent method. The model output module is configured to output the trained quantum bit mapping model in response to the loss function value being less than a loss threshold.

12. A general quantum compiler based on cross-graph attention mechanism, characterized in that, The obtaining module is configured to obtain a quantum logic circuit to be mapped, the quantum logic circuit including a plurality of logic bits and a logic gate sequence constructed based on the logic bits. The encoding module is configured to encode the quantum logic circuit into a logic graph, the logic graph including initial logic node features and logic edge features of each logic gate. The mapping quality calculation module is configured to input the logic graph into the quantum bit mapping model trained by the training method of the quantum bit mapping model based on the cross-graph attention mechanism of any one of claims 1-8, and calculate mapping quality scores between the quantum logic circuit and each candidate hardware topology graph by using the cross-graph attention mechanism. The mapping path output module is configured to select a hardware topology graph with the highest mapping quality from the candidate hardware topology graphs according to the mapping quality scores, and output a best mapping path of the logic bits to the physical bits in the hardware topology graph. The processor and the memory are included, and the memory stores a computer program instruction set, and the processor executes the computer program instruction set on the memory to implement the training method of the quantum bit mapping model based on the cross-graph attention mechanism of any one of claims 1-8.

13. An electronic device, comprising: The computer program instruction set is executed by the processor to implement the training method of the quantum bit mapping model based on the cross-graph attention mechanism of any one of claims 1-8.

14. A computer program product, characterised in that, ​

Images