2.5d substrate packaging method and packaging structure

Abstract

The application provides a 2.5D substrate packaging method and a packaging structure. The 2.5D substrate packaging method comprises the following steps: providing a base with a groove; wherein the groove is a stepped groove; the groove comprises a first groove and a second groove which are communicated; the depth of the first groove is greater than that of the second groove. A conductive column is formed in the base. The base is etched to expose the conductive column; a first insulating layer is formed on one side of the base where the conductive column is exposed by ion implantation; the first insulating layer covers the surface of the base and the end face and sidewall of the exposed part of the conductive column. The first insulating layer is polished to expose the end face of the conductive column. A dielectric layer with a wiring layer is formed on the side of the first insulating layer away from the base; the wiring layer is electrically connected with the conductive column. The adhesion between the conductive column and the base can be improved, the conductive column can be prevented from being broken or delaminated from the base during the polishing process, and the transmission performance of the conductive column is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a 2.5D substrate packaging method and packaging structure. BACKGROUND

[0002] With the rapid development of the semiconductor industry, chiplet technology adopts a new design method to package small chips with different functions together to form a heterogeneous integrated chip packaging structure. With the increasing input and output density of chips and the significant increase in the number of chips integrated in a single package, various 2.5D and 3D packaging technologies are used as multi-chip packaging solutions to connect adjacent chip pad lines in a single package. Therefore, a through silicon via technology is proposed to form a heterogeneous integrated packaging structure, thereby realizing multi-chip integration and reducing the packaging volume and the number of wiring layers.

[0003] At present, the through silicon via (TSV) technology on the substrate can realize the vertical interconnection between chips. In the conventional technology, the etching or laser drilling technology is usually used to form a through hole on the substrate in the through silicon via technology, and then a metal layer is deposited by electroplating to form a conductive column. The conductive column is exposed by grinding means, and the exposure height of the conductive column is usually microns. During the grinding of the conductive column surface, the conductive column is easily pulled apart by lateral stress, which causes poor adhesion between the conductive column and the inner wall of the substrate, especially in the area where the conductive column contacts the grinding surface during grinding. The poor adhesion between the conductive column and the inner wall of the substrate causes delamination and fracture, which affects the transmission performance of the conductive column. SUMMARY

[0004] The purpose of the present application is to provide a 2.5D substrate packaging method and packaging structure, which can prevent the conductive column from breaking during grinding, effectively protect the conductive column, and improve the transmission performance of the conductive column.

[0005] In a first aspect, the present application provides a 2.5D substrate packaging method, comprising:

[0006] A substrate with a groove is provided; wherein the groove is a stepped groove; the groove includes a first groove and a second groove in communication, and the depth of the first groove is greater than the depth of the second groove;

[0007] Forming a conductive column in the substrate;

[0008] Etching the substrate to expose the conductive column;

[0009] A first insulating layer is formed on the side of the substrate where the conductive column is exposed by ion implantation; the first insulating layer covers the surface of the substrate and the end face and side wall of the exposed part of the conductive column;

[0010] grinding the first insulating layer to expose end faces of the conductive pillars;

[0011] forming a dielectric layer with a wiring layer on a side of the first insulating layer away from the substrate; the wiring layer and the conductive pillars are electrically connected.

[0012] In an optional embodiment, in the step of etching the substrate to expose the conductive pillars, the substrate is etched to be flush with the bottom of the second groove.

[0013] In an optional embodiment, before or after the step of grinding the first insulating layer to expose end faces of the conductive pillars, further comprising:

[0014] forming a second insulating layer on a side of the first insulating layer away from the substrate;

[0015] grinding the second insulating layer to expose end faces of the conductive pillars;

[0016] in the step of forming a dielectric layer with a wiring layer on a side of the first insulating layer away from the substrate:

[0017] forming a first dielectric layer with a wiring layer on a side of the second insulating layer away from the substrate.

[0018] In an optional embodiment, further comprising forming a buffer layer in the first groove.

[0019] In an optional embodiment, the substrate comprises a first surface and a second surface arranged oppositely; the step of forming conductive pillars in the substrate comprises:

[0020] forming a seed layer on the first surface of the substrate;

[0021] attaching a first carrier on a side provided with the seed layer;

[0022] forming a through hole through the first surface and the second surface on the substrate;

[0023] electroplating metal in the through hole to form the conductive pillars; wherein the seed layer serves as an electroplating lead.

[0024] In an optional embodiment, before the step of forming a seed layer on the first surface of the substrate, further comprising:

[0025] forming the groove on the first surface;

[0026] forming the seed layer on the bottom and the walls of the groove and the first surface;

[0027] in the step of attaching a first carrier on a side provided with the seed layer:

[0028] The first carrier covers the groove of the slot to form a first cavity structure; the first cavity structure serves as a plating solution channel.

[0029] In an optional embodiment, the step of plating metal in the through hole to form the conductive column comprises:

[0030] A bottom metal layer is formed in the first cavity structure.

[0031] In an optional embodiment, after the step of plating metal in the through hole to form the conductive column, further comprising:

[0032] A communication hole is formed on the substrate, which is used to communicate the first groove on both sides of the substrate;

[0033] An edge metal column is formed in the communication hole.

[0034] In an optional embodiment, after the step of forming the conductive column in the substrate, further comprising:

[0035] A second carrier is attached to the second surface;

[0036] The first carrier and the seed layer are removed;

[0037] The substrate is etched from the first surface to expose the conductive column from the first surface;

[0038] A first insulating layer is formed on the first surface by ion implantation;

[0039] The first insulating layer is polished to expose the end surface of the conductive column.

[0040] In an optional embodiment, after the step of polishing the first insulating layer to expose the end surface of the conductive column, further comprising:

[0041] The electrical performance of the conductive column and the wiring layer is tested;

[0042] In which the negative electrode of the test probe is connected to the first insulating layer in the first groove, the positive electrode of the test probe is connected to the conductive column, a voltage is applied between the negative and positive electrodes of the test probe, and the current change is detected; each of the plurality of conductive columns is detected, and the Ohm's law formula R=U / I is used; since the resistance R is a constant value; according to the voltage and current change curve, it is judged whether the electrical performance of the conductive column and the wiring layer meets the requirements.

[0043] In an optional embodiment, further comprising:

[0044] A solder ball is formed on the surface of the medium layer and electrically connected to the wiring layer;

[0045] mounting an electronic component on the solder balls.

[0046] In an optional embodiment, further comprising:

[0047] cutting the substrate to separate into single products before or after the step of mounting an electronic component on the solder balls;

[0048] and / or, encapsulating the electronic component.

[0049] In a second aspect, the present application provides a packaging structure, comprising:

[0050] a substrate; the substrate comprises a first surface and a second surface arranged oppositely;

[0051] a plurality of conductive pillars are arranged on the substrate; each of the conductive pillars partially protrudes from the first surface and the second surface;

[0052] the first surface and the second surface of the substrate sequentially form a first insulating layer and a second insulating layer in a direction away from the substrate respectively; the first insulating layer protects the sidewall of the protruding part of the conductive pillar;

[0053] a first dielectric layer; arranged on a side of the second insulating layer away from the first insulating layer, the first dielectric layer has a wiring layer electrically connected with the conductive pillar;

[0054] a second dielectric layer; arranged on a side of the first dielectric layer away from the second insulating layer;

[0055] solder balls; the solder balls protrude from the second dielectric layer and are electrically connected with the wiring layer;

[0056] an electronic component, electrically connected with the solder balls;

[0057] an encapsulation body; the encapsulation body is arranged on the substrate and covers the electronic component.

[0058] In an optional embodiment, the encapsulation body exposes the surface of the electronic component away from the substrate.

[0059] In an optional embodiment, further comprising a circuit board and a metal ring; the solder balls on the substrate are electrically connected with the circuit board; the metal ring is connected with the circuit board and arranged around the outer periphery of the substrate.

[0060] In a third aspect, the present application provides a packaging structure, prepared by the 2.5D substrate packaging method of any one of the preceding embodiments.

[0061] The 2.5D substrate packaging method provided by the embodiment of the present application forms a first insulating layer on the side of the substrate where the conductive column is exposed by using an ion implantation method; the first insulating layer covers the surface of the substrate and the end face and sidewall of the exposed part of the conductive column. The first insulating layer can effectively protect the conductive column during subsequent grinding and prevent it from being broken. Moreover, the first insulating layer formed by ion implantation has better bonding force with the substrate and the conductive column, respectively, which is conducive to preventing the substrate and the conductive column from delaminating or cracking, and further improving the transmission performance of the conductive column. In addition, the substrate is provided with a stepped groove, which can be used to control the grinding depth and improve the grinding quality and efficiency.

[0062] The packaging structure provided by the embodiment of the present application is prepared by using the above-mentioned 2.5D substrate packaging method. The bonding force between the conductive column and the substrate can be improved, the conductive column can be prevented from being broken or delaminated from the substrate during the grinding process, and the transmission performance of the conductive column can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0063] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0064] Figure 1 The schematic diagram of forming a groove in the first surface of the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0065] Figure 2 The schematic diagram of forming a seed layer and attaching a first carrier in the 2.5D substrate packaging method provided by the embodiment of the present application; Figure 1 The local enlarged schematic diagram of A in the above figure;

[0066] Figure 3 The schematic diagram of forming a seed layer and attaching a first carrier in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0067] Figure 4 The schematic diagram of forming a groove in the second surface of the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0068] Figure 5 The process schematic diagram of forming a conductive column and an exposed part of the conductive column in the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0069] Figure 6 The schematic diagram of forming a buffer layer in the groove of the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0070] Figure 7A process schematic diagram of forming the first insulating layer and the second insulating layer on the substrate and grinding to expose the end face of the conductive column in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0071] Figure 8 A process schematic diagram of forming the first insulating layer and the second insulating layer on the substrate and grinding to expose the end face of the conductive column in the 2.5D substrate packaging method provided by the embodiment of the present application; Figure 7 A partial enlarged schematic view at B in FIG. 1;

[0072] Figure 9 A process schematic diagram of forming the first insulating layer and the second insulating layer on the substrate and grinding to expose the end face of the conductive column in the 2.5D substrate packaging method provided by the embodiment of the present application; Figure 7 A partial enlarged schematic view at C in FIG. 1;

[0073] Figure 10 A process schematic diagram of forming the first insulating layer and the second insulating layer on the substrate and grinding to expose the end face of the conductive column in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0074] Figure 11 A process schematic diagram of removing the seed layer on the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0075] Figure 12 A schematic diagram of completing the preparation of the first surface of the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0076] Figure 13 A process schematic diagram of cutting and separating into single products after mounting the chip in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0077] Figure 14 A process schematic diagram of mounting the chip after cutting and separating into single substrates in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0078] Figure 15 A process schematic diagram of plastic packaging and then cutting and separating into single products after mounting the chip in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0079] Figure 16 A distribution schematic diagram of the conductive column and the groove on the substrate in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0080] Figure 17 A schematic diagram of forming the second insulating layer and the second cavity structure by using the film covering method in the 2.5D substrate packaging method provided by the embodiment of the present application;

[0081] Figure 18 A first packaging structure schematic diagram provided by the embodiment of the present application;

[0082] Figure 19 A second packaging structure schematic diagram provided by the embodiment of the present application;

[0083] Figure 20A third packaging structure schematic diagram provided for the embodiment of the present application is shown in the figure;

[0084] Figure 21 A fourth packaging structure schematic diagram provided for the embodiment of the present application is shown in the figure.

[0085] Figure: 110 - substrate; 111 - first surface; 112 - second surface; 113 - groove; 114 - first groove; 115 - second groove; 116 - through hole; 117 - communication hole; 118 - buffer layer; 120 - conductive column; 121 - seed layer; 122 - first carrier; 123 - bonding glue; 124 - first cavity structure; 125 - bottom metal layer; 130 - edge metal column; 140 - first insulating layer; 141 - third groove; 142 - second insulating layer; 143 - second cavity structure; 151 - first dielectric layer; 152 - pattern layer opening; 153 - wiring layer; 154 - second dielectric layer; 155 - bump; 156 - solder ball; 161 - second carrier; 170 - chip; 171 - protective glue; 180 - plastic package; 210 - circuit board; 220 - metal ring; 230 - bottom glue. DETAILED DESCRIPTION

[0086] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme of the embodiments of the present application will be described clearly and completely below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0087] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0088] It should be noted that: similar labels and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0089] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings or the orientation or positional relationship commonly used when the product of the present application is used, and are merely for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0090] In addition, the terms "horizontal", "vertical", "overhanging" and the like do not mean that the components must be absolutely horizontal or overhanging, but can be slightly inclined. For example, "horizontal" only means that it is more horizontal relative to "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0091] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "arrangement", "installation", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0092] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0093] The 2.5D substrate packaging method proposed in the embodiment of the present application can improve the bonding force of the conductive column 120 and the substrate 110, prevent the conductive column 120 from breaking or delaminating from the substrate 110 during the grinding process, and further improve the transmission performance of the conductive column 120.

[0094] In combination Figure 1 And Figure 2 The 2.5D substrate packaging method generally comprises the following steps:

[0095] S1, providing a substrate 110 with a groove 113; wherein the groove 113 is a stepped groove; the groove 113 includes a first groove 114 and a second groove 115 in communication, the depth of the first groove 114 is greater than the depth of the second groove 115.

[0096] Optionally, the substrate 110 is a silicon-based or germanium-based substrate material, including but not limited to a silicon oxide, a phosphor-silicon glass, a fluorine-containing glass, or a glass. The thickness of the substrate 110 is 600 um to 1500 um.

[0097] The substrate 110 includes a first surface 111 and a second surface 112 oppositely arranged along the thickness direction thereof. The groove 113 can be formed in at least one of the first surface 111 and the second surface 112 by dry etching or chemical etching. In the embodiment, the groove 113 is first etched on the first surface 111. The groove 113 is step-shaped. The first groove 114 has a depth H1 and a width W1; the second groove 115 has a depth H2; and the sum of the widths of the first groove 114 and the second groove 115 is W2. Optionally, H1 is 21 um to 50 um; H2 is 2 um to 20 um; W1 is 50 um to 200 um; and W2 is 200 um to 600 um.

[0098] It can be understood that, in subsequent etching and polishing processes, the first groove 114 and the second groove 115 can also serve as depth control and positioning reference, so as to improve the preparation accuracy of the conductive pillar 120 and the height uniformity of the plurality of conductive pillars 120, and improve the yield of the packaging structure.

[0099] Please refer to Figure 3 S2, forming the conductive pillar 120 in the substrate 110. S2 includes steps S21 to S24.

[0100] S21, forming a seed layer 121 on the first surface 111.

[0101] Optionally, the seed layer 121 can be any conductive metal, such as copper or other metals. The thickness of the seed layer 121 is about 1 um to 5 um. The seed layer 121 can be formed by any one of the following processes: physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). The seed layer 121 can serve as an electroplating lead for subsequent formation of the conductive pillar 120. The seed layer 121 covers the first surface 111, the bottom and the wall of the groove 113, and the groove 113 can improve the adhesion of the electroplating lead edge, which is conducive to improving the uniformity and stability of the subsequent electroplating process.

[0102] S22, attaching a first carrier 122 to the side provided with the seed layer 121.

[0103] Optionally, the first carrier 122 is coated with a layer of bonding glue 123, which can be separated by irradiating ultraviolet light or laser. It can be understood that, due to the groove 113, the first carrier 122 covers the groove of the groove 113 to form a first cavity structure 124 at the groove 113; the first cavity structure 124 can be used as an electroplating solution channel, which is beneficial to improve the electroplating efficiency and quality.

[0104] S23, forming a through hole 116 through the first surface 111 and the second surface 112 on the substrate 110.

[0105] Please refer to Figure 4 Optionally, the second surface 112 is ground first to thin the thickness of the substrate 110. The grinding thickness can be set according to actual needs. In this embodiment, after grinding, the thickness of the substrate 110 is about 80um to 300um. The grinding process is beneficial to thin the thickness of the substrate 110 and reduce stress.

[0106] The groove 113 structure is formed on the second surface 112, and the groove 113 structure of the second surface 112 and the forming mode of the groove 113 are consistent with those of the first surface 111.

[0107] Please refer to Figure 5 The through hole 116 through the first surface 111 and the second surface 112 is formed on the substrate 110 by using a dry etching process. Of course, laser drilling or other methods can also be used to form the through hole 116.

[0108] Optionally, please refer to Figure 6 The buffer glue can be filled in the first groove 114 to form a buffer layer 118. The buffer glue is filled to a position flush with the groove bottom of the second groove 115. In this way, the buffer performance of the substrate 110 can be improved, and the warping deformation in the subsequent packaging process can be reduced. Of course, in some embodiments, the buffer layer 118 can also be omitted.

[0109] S24, electroplating metal in the through hole 116 to form a conductive pillar 120; wherein, the seed layer 121 is used as an electroplating lead.

[0110] It can be understood that the first cavity structure 124 is formed at the groove 113 of the first surface 111, which can be used as a flow channel of the electroplating solution in the electroplating process. The substrate 110 is hung in the electroplating solution, and the seed layer 121 is used as an electroplating lead to perform current electroplating. Since the electroplating solution directly contacts the seed layer 121 at the first cavity structure 124, and the seed layer 121 is in communication with each through hole 116, the uniformity and consistency of the height of the porous electroplated conductive pillar 120 can be improved. In addition, the seed layer 121 is used as an electroplating lead and is located at the bottom of the substrate 110. The electroplating current enters the through hole 116 from the side of the seed layer 121 to form the conductive pillar 120. This is conducive to improving the density of metal filling and preventing the occurrence of voids and the like in the electroplating process. The material of the conductive pillar 120 is copper or other metals.

[0111] It can be understood that when the conductive pillar 120 is formed by electroplating, the first cavity structure 124 can also be filled with metal by electroplating to form a bottom metal layer 125. The bottom metal layer 125 is conducive to improving the structural strength and edge support performance of the substrate 110 and improving the deformation of the substrate 110 in the subsequent grinding process.

[0112] Optionally, after the conductive pillar 120 is formed, a communication hole 117 is formed on the substrate 110 to communicate the groove 113 of the first surface 111 and the groove 113 of the second surface 112. The opening method can be laser opening or etching opening.

[0113] Optionally, an edge metal pillar 130 is formed in the communication hole 117 by electroplating. It should be noted that the conductive pillar 120 and the edge metal pillar 130 are formed by two electroplating processes. By controlling the current parameters in the electroplating process, the height of the edge metal pillar 130 is controlled, so that the groove 113 far from the seed layer 121 of the substrate 110 is not filled with electroplating.

[0114] It should be noted that the first cavity structure 124 can also be used as an electrical test point of the conductive pillar 120 and the wiring layer 153 in the subsequent process, so as to ensure that the electrical performance of the conductive pillar 120 and the wiring layer 153 meets the requirements and improve the transmission performance and quality of the conductive pillar 120 and the wiring layer 153. The formation of the edge metal pillar 130 is conducive to improving the support performance of the edge of the substrate 110, improving the strength of the substrate 110, preventing warping and deformation, and improving the heat dissipation performance of the packaging structure.

[0115] Of course, in some embodiments, the preparation of the communication hole 117 and the edge metal pillar 130 can be omitted, which is not limited here.

[0116] S3, etching the substrate 110 to expose the conductive pillar 120.

[0117] Optionally, the substrate 110 is etched at the second surface 112 to expose the conductive pillars 120 at the second surface 112. Optionally, the substrate 110 is etched to be flush with the bottom of the second recess 115. The etching thickness of the substrate 110 is equal to the depth of the second recess 115. The depth of the second recess 115 is used as a sacrificial layer for the etching process, which is beneficial to control the uniformity of the exposed height of the conductive pillars 120. In other words, the exposed height of the conductive pillars 120 is equal to the depth of the second recess 115.

[0118] It should be noted that in some embodiments, the substrate 110 is made of silicon. After forming the through holes 116 on the substrate 110, the substrate 110 can be placed in a high temperature environment. After high temperature oxidation of the silicon substrate, a silicon oxide film can be formed on the surface of the substrate 110 and the hole wall of the through holes 116. Then, the conductive pillars 120 are formed by electroplating, which is beneficial to improve the bonding force between the conductive pillars 120 and the substrate 110, and improve the insulation between the conductive pillars 120 and the substrate 110. In the step of etching the substrate 110 to expose the conductive pillars 120, the silicon oxide film on the surface of the substrate 110 away from the seed layer 121 is removed.

[0119] In combination with Figures 7 to 9 S4, a first insulating layer 140 is formed on the side of the substrate 110 exposing the conductive pillars 120 by ion implantation. The first insulating layer 140 covers the second surface 112 of the substrate 110 and the end surface and sidewall of the exposed part of the conductive pillars 120. The first insulating layer 140 has a third recess 141 formed thereon between adjacent conductive pillars 120.

[0120] Optionally, the atoms of the first insulating layer 140 are ionized by ion implantation process and implanted into the first surface 111 of the substrate 110 and the sidewall and end surface of the conductive pillars 120. Optionally, the thickness of the first insulating layer 140 is less than or equal to half of the exposed height H2 of the conductive pillars 120. By using the ion implantation process, the material on the surface of the substrate 110 and the material on the surface of the exposed part of the conductive pillars 120 can be changed to have better bonding force. The first insulating layer 140 can protect the sidewall of the conductive pillars 120 and improve the bonding force between the conductive pillars 120 and the substrate 110.

[0121] It is easy to understand that the thickness of the first insulating layer 140 can be designed according to actual needs. The surface of the first insulating layer 140 away from the substrate 110 can be a concave-convex structure, such as the surface between adjacent conductive pillars 120 being lower than the surface of the first insulating layer 140 at the head of the conductive pillars 120, or the surface of the first insulating layer 140 away from the substrate 110 can be a flat structure, which is not limited here.

[0122] It is worth noting that the conventional process is mostly roughened first, and then an insulating layer is formed on the second surface of the substrate by spin coating or vapor deposition. In this embodiment, the ion implantation process can save the surface roughening process, and the bonding force is better. Moreover, the ion implantation process can implant ions into the substrate 110, so that the overall thickness is smaller, the structure is thinner, the volume is smaller, and the structure is more compact.

[0123] In addition, the first groove 114 on the surface of the substrate 110 also helps to improve the bonding force between the first insulating layer 140 and the substrate 110.

[0124] S5, grinding the first insulating layer 140 to expose the end surface of the conductive column 120.

[0125] Optionally, the first insulating layer 140 covering the end surface of the conductive column 120 is removed by chemical grinding. In this process, the first groove 114 can be used as a positioning reference to grind the first insulating layer 140 on the surface of the conductive column 120 to the same level as the slot of the first groove 114. During the grinding process, the groove wall of the first groove 114 on the second surface 112 serves as a support to improve the edge support and prevent the edge from collapsing after grinding, which helps to improve the flatness of the second surface 112 after grinding. Moreover, the bottom metal layer 125 at the first cavity structure 124 and the edge metal column 130 further improve the edge support of the substrate 110 to prevent the edge of the substrate 110 from collapsing or deforming during the grinding process. In addition, the first insulating layer 140 protects the sidewall of the conductive column 120, preventing the conductive column 120 from breaking or separating from the substrate 110 due to grinding stress.

[0126] Optionally, chemical grinding is used to grind the second surface 112 of the substrate 110 by using a grinding liquid such as ammonia, hydrofluoric acid or citric acid under the action of the pressure of the polishing pad and the centrifugal force, to expose the head of the conductive column 120.

[0127] S6, forming a second insulating layer 142 on the side of the first insulating layer 140 away from the substrate 110; grinding the second insulating layer 142 to expose the end surface of the conductive column 120.

[0128] The second insulating layer 142 is formed on the first insulating layer 140 by spin coating or vapor deposition, and covers the first insulating layer 140 and the exposed end surface of the conductive column 120. It can be understood that the second insulating layer 142 fills the first groove 114 and the second groove 115, which can improve the bonding force between the first insulating layer 140 and the second insulating layer 142. It can be understood that if the second groove 115 is filled with a buffer layer 118 in advance, the second insulating layer 142 will fill the remaining space of the second groove 115.

[0129] The second insulating layer 142 covering the end surface of the conductive pillar 120 is removed by chemical grinding to expose the end surface of the conductive pillar 120. The second insulating layer 142 is ground to be flush with the slot of the first groove 114. In this way, the slot wall of the first groove 114 can realize the function of grinding depth control and edge support, improve the grinding precision, and improve the consistency of the exposed height of the conductive pillar 120. The top surface of the slot wall of the first groove 114 is flush with the end surface of the conductive pillar 120, which can share the stress of the conductive pillar 120 during grinding and protect the conductive pillar 120 from breaking.

[0130] It can be understood that the grinding can be performed after the formation of the first insulating layer 140 and the formation of the second insulating layer 142, that is, twice grinding, specifically: forming the first insulating layer 140, first grinding, forming the second insulating layer 142, and second grinding. Alternatively, the grinding after the formation of the first insulating layer 140 can be omitted, and after the formation of the first insulating layer 140 on the substrate 110, the second insulating layer 142 is formed, and then once grinding is performed to remove the second insulating layer 142 and the first insulating layer 140 on the end surface of the conductive pillar 120 to expose the end surface of the conductive pillar 120.

[0131] In combination with Figure 10 S7, a first dielectric layer 151 having a wiring layer 153 is formed on the side of the second insulating layer 142 away from the substrate 110.

[0132] Optionally, the first dielectric layer 151 is formed on the second insulating layer 142 by a spin coating process. A mask is covered on the first dielectric layer 151, and a pattern layer opening 152 is formed on the first dielectric layer 151 by an exposure and development process. The pattern layer opening 152 exposes the end surface of the conductive pillar 120. The wiring layer 153 is formed in the pattern layer opening 152 by electroplating process to realize the electrical connection between the wiring layer 153 and the conductive pillar 120. The process of forming the wiring layer 153 can also be sputtering, chemical plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD) or any process.

[0133] S8, a bump 155 connected with the wiring layer 153 is formed, and a ball is planted on the bump 155.

[0134] Optionally, a second dielectric layer 154 is formed on the side of the first dielectric layer 151 away from the substrate 110. The second dielectric layer 154 is formed in the same manner and from the same material as the first dielectric layer 151. An opening is formed in the first dielectric layer 151 by exposure and development, and the opening is filled with metal to form a bump 155. The bump 155 is formed by any one of the following processes, including but not limited to electroplating, sputtering, electroless plating, physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD).

[0135] A solder ball 156 is formed on the bump 155 by electroplating or printing.

[0136] In this embodiment, the first insulating layer 140 and the second insulating layer 142 are made of the same material, which can be at least one of silicon oxide, silicon dioxide, silicon nitride, aluminum oxide, silicon oxynitride, and organic dielectric material.

[0137] The first dielectric layer 151 and the second dielectric layer 154 are made of the same material, which can be any one or more of polyimide and benzocyclobutene.

[0138] In combination Figure 11 S9, a second carrier 161 is attached to the side of the substrate 110 on which the solder balls 156 are formed. The second carrier 161 is coated with a bonding agent 123, which can be separated by irradiation of ultraviolet light or laser.

[0139] The first carrier 122 on the first surface 111 is removed. The removal can be achieved by debonding.

[0140] S10, the seed layer 121 is etched away.

[0141] Optionally, the product is flipped over, with the first surface 111 facing upwards and the second carrier 161 underneath. The seed layer 121 is removed by micro-etching, including but not limited to dry etching or chemical etching. It should be noted that the seed layer 121 is removed together with the bottom metal layer 125 in the first cavity structure 124.

[0142] In combination Figure 12 The above steps S3 to S10 are repeated to complete the fabrication of the first surface 111 of the substrate 110.

[0143] The substrate 110 of the first surface 111 is etched away to expose the other end of the conductive pillar 120 from the first surface 111. The exposed height of the conductive pillar 120 can be set according to actual needs. In this embodiment, the exposed height of the conductive pillar 120 is equal to the depth of the second groove 115 on the first surface 111.

[0144] The first insulating layer 140 is formed by ion implantation on the first surface 111, and the second insulating layer 142 is formed. The second insulating layer 142 and the first insulating layer 140 are ground to expose the end surface of the conductive column 120. The first dielectric layer 151 is formed, the wiring layer 153 is formed, the second dielectric layer 154 is formed, the bump 155 is formed, and the solder ball 156 is formed.

[0145] In combination Figure 13 Optionally, the electronic component is attached on the first surface 111 side. The electronic component and the solder ball 156 are electrically connected. The electronic component includes at least one of the chip 170 and the component. In the embodiment, the chip 170 is attached on the first surface 111 side, and the pad on the chip 170 and the solder ball 156 on the bump 155 are soldered to achieve electrical connection. The protective glue 171 is drawn on the bottom of the chip 170. The second carrier 161 is debonded and removed. The cutting separates the product into single pieces.

[0146] Optionally, at least one of the chip 170 and the component can also be attached on the second surface 112 side to improve the integration level.

[0147] It can be understood that after the chip 170 or the component is attached, the chip 170 or the component can be selectively encapsulated to form a plastic package 180.

[0148] In combination Figure 14 Optionally, after the solder ball 156 on both sides of the substrate 110 is completed, the substrate 110 can be cut and separated first while the second carrier 161 is retained. The cutting depth is cut to the second carrier 161, and the second carrier 161 is not cut. In this way, the second carrier 161 plays a supporting role and can prevent the substrate 110 from deforming during cutting. Then the chip 170 or the component can be attached on the single substrate 110. In this way, the cutting process is completed before the chip 170 is attached, and the soldering structure of the chip 170 and the solder ball 156 can be prevented from being affected by the cutting stress and cracking.

[0149] In combination Figure 15 Optionally, if the chip 170 is to be plastic-encapsulated, the chip 170 can be plastic-encapsulated to form a plastic package 180 after being attached, the second carrier 161 is removed, and the product is cut and separated into single pieces.

[0150] Optionally, in the embodiment, after the second surface 112 side of the substrate 110 is completed, the product is flipped to remove the seed layer 121. After the first insulating layer 140 is formed by ion implantation on the first surface 111, the conductive column 120 and the wiring layer 153 on the second surface 112 side can be tested for electrical performance. The testing principle is as follows:

[0151] The negative pole of the test probe is connected to the first insulating layer 140 at the groove 113, the positive pole of the test probe is connected to the conductive column 120, a voltage is applied between the positive pole and the negative pole, and the current change is detected. Each conductive column 120 is detected in turn, and the conductivity of the conductive column 120 and the wiring layer 153 is tested according to the Ohm's law formula R=U / I, and whether the electrical performance of the conductive column 120 and the wiring layer 153 meets the requirements is determined according to the voltage-current change curve.

[0152] The first insulating layer 140 can also play a role in improving the insulation performance and preventing electric leakage in the electrical test. In the test process or the subsequent use process, the conductive column 120 and the like will generate heat, and the edge metal column 130 can also play a good heat dissipation role.

[0153] It should be noted that the electrical test can also be performed after the second insulating layer 142 is ground, at this time, the negative pole of the test probe is connected to the second insulating layer 142 at the first groove 114, and has similar technical effects. Alternatively, if the first insulating layer 140 and the second insulating layer 142 are ground twice, the electrical test can be performed after each grinding.

[0154] In combination Figure 16 On the substrate 110, a plurality of conductive columns 120 are formed, and the grooves 113 structures are arranged at the outer periphery of the conductive columns 120 respectively, the groove 113 structure is used as an electrical test point, and the electrical performance of the conductive column 120 and the wiring layer 153 can be detected in time.

[0155] In combination Figure 17 Optionally, in some embodiments, in the step of forming the second insulating layer 142, the second insulating layer 142 can be formed by a film coating method, so that the second insulating layer 142 covers the slot of the groove 113, and a second cavity structure 143 is formed between the second insulating layer 142 and the first insulating layer 140. Optionally, in the subsequent process, the second cavity structure 143 is filled with a filling material through a micro channel design. The filling material can be the same material as the second insulating layer 142. In this way, the support and heat dissipation can be improved, and the filling material has a certain buffering effect, which can reduce the plastic sealing stress and reduce the warping deformation.

[0156] The embodiment of the application also provides a packaging structure prepared by the above method.

[0157] In combination Figure 18The packaging structure comprises a substrate 110 and a conductive column 120 penetrating through the substrate 110. A first surface 111 and a second surface 112 of the substrate 110 are sequentially provided with a first insulating layer 140, a second insulating layer 142, a first dielectric layer 151 with a wiring layer 153, a second dielectric layer 154, and a solder ball 156 in a direction away from the substrate 110. The first insulating layer 140 protects the sidewall of the exposed substrate 110 part of the conductive column 120. Optionally, a third groove 141 is arranged on the first insulating layer 140, and the sidewall of the third groove 141 protects the sidewall of the exposed substrate 110 part of the conductive column 120. The second insulating layer 142 fills the third groove 141. The substrate 110 is attached with a chip 170 on one side or both sides; or the chip 170 is attached on one side and a component is attached on the other side; or the chip 170 and the component are arranged on the same side, which is not limited here.

[0158] Optionally, the chip 170 is a flip chip, and the solder pad of the chip 170 is soldered with the solder ball 156 of the substrate 110 and protected by a protective glue 171.

[0159] In combination Figure 19 The chip 170 is molded to form a molded body 180.

[0160] In combination Figure 20 When the substrate 110 is cut and separated into single substrates 110, the groove 113 structure of the first surface 111 and the second surface 112 is retained in the single substrate 110. After the chip 170 is attached, the chip 170 is molded to form a molded body 180. The molded body 180 fills the groove 113 on the same side as the chip 170, which can improve the bonding force of the molded body 180 and the substrate 110. It can be understood that in this embodiment, the first wiring layer 153 and the second wiring layer 153 are formed while avoiding the groove 113 on the side of the substrate 110 for attaching the chip 170.

[0161] In combination Figure 21 Optionally, the molded body 180 can be thinned to expose the surface of the chip 170 to improve heat dissipation.

[0162] Optionally, the packaging structure further comprises a circuit board 210 and a metal ring 220. The solder ball 156 on the substrate 110 is electrically connected to the circuit board 210, and the metal ring 220 is connected to the circuit board 210 and arranged around the outer periphery of the substrate 110. Specifically, the solder ball 156 on the substrate 110 is soldered with the circuit board 210, and the bottom glue 230 is used to fix and protect the solder ball 156. The metal ring 220 is fixedly connected to the circuit board 210, and the metal ring 220 plays a role in heat dissipation and anti-warping.

[0163] In some embodiments, the groove 113 structure on both sides of the substrate 110 can be removed when the substrate 110 is cut and separated into single substrates 110 or single products.

[0164] It should be noted that the first insulating layer 140 and the second insulating layer 142 are arranged between the surface of the substrate 110 and the second wiring layer 153 in the embodiment, the first insulating layer 140 can protect the conductive column 120, and the first insulating layer 140 and the second insulating layer 142 can also prevent electromigration.

[0165] The 2.5D substrate packaging method and packaging structure provided by the embodiment have the following beneficial effects:

[0166] By arranging the groove 113, the positioning, the edge support, the edge bonding force, the protection of the conductive column 120 by the first insulating layer 140 and the second insulating layer 142, the stress reduction in the grinding process, the prevention of the fracture or separation of the conductive column 120 from the substrate 110, the improvement of the insulation performance, and the prevention of the electric leakage in the electric property test process can be achieved. By arranging the seed layer 121 on one side, the seed layer 121 can be used as a plating lead wire, the uniformity of the plating of the conductive column 120 can be improved, the groove 113 structure can be used as a plating liquid channel and an electric property test point, and the packaging quality and the packaging efficiency can be improved. The first insulating layer 140 is formed by using the ion implantation process, the process can be simplified, the bonding force can be improved, the material surface performance can be changed, and the insulation performance is better.

[0167] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the above embodiments, or make equivalent replacement for part or all of the technical features; any modification, equivalent replacement, improvement, etc. should be included in the protection scope of the present application.

Claims

1. A 2.5D substrate packaging method, characterized in that, The method comprises the following steps: providing a substrate with a groove; wherein the groove is a stepped groove; the groove comprises a first groove and a second groove which are communicated; the depth of the first groove is greater than that of the second groove; forming a conductive column in the substrate; wherein the substrate comprises a first surface and a second surface which are oppositely arranged; forming a through hole which penetrates the first surface and the second surface in the substrate; forming the conductive column by electroplating metal in the through hole; forming a communicating hole in the substrate, which is used for communicating the first groove on both sides of the substrate; forming an edge metal column in the communicating hole; etching the substrate to expose the conductive column; forming a first insulating layer on the side of the substrate where the conductive column is exposed by ion implantation; the first insulating layer covers the surface of the substrate and the end face and sidewall of the exposed part of the conductive column; polishing the first insulating layer to expose the end face of the conductive column; forming a dielectric layer with a wiring layer on the side of the first insulating layer away from the substrate; the wiring layer is electrically connected with the conductive column.

2. The 2.5D substrate packaging method of claim 1, wherein, In the step of etching the substrate to expose the conductive column, the substrate is etched to be flush with the bottom of the second groove.

3. The 2.5D substrate packaging method of claim 1, wherein, Before or after the step of polishing the first insulating layer to expose the end face of the conductive column, the method further comprises the following steps: forming a second insulating layer on the side of the first insulating layer away from the substrate; polishing the second insulating layer to expose the end face of the conductive column; in the step of forming a dielectric layer with a wiring layer on the side of the first insulating layer away from the substrate: forming a first dielectric layer with a wiring layer on the side of the second insulating layer away from the substrate.

4. The 2.5D substrate packaging method of claim 1, wherein, The method further comprises the following step:

5. The 2.5D substrate packaging method of claim 1, wherein, forming a buffer layer in the first groove. Before the step of forming a through hole which penetrates the first surface and the second surface in the substrate, the method further comprises the following steps: forming a seed layer on the first surface of the substrate; 6. The 2.5D substrate packaging method of claim 5, wherein, attaching a first carrier on the side provided with the seed layer; wherein the seed layer serves as an electroplating lead. Before the step of forming a seed layer on the first surface of the substrate, the method further comprises the following steps: forming the groove on the first surface; forming the seed layer on the bottom and sidewall of the groove and the first surface; in the step of attaching a first carrier on the side provided with the seed layer:

7. The 2.5D substrate packaging method of claim 6, wherein, the first carrier covers the notch of the groove to form a first cavity structure; the first cavity structure serves as a plating solution channel. The step of forming the conductive column by electroplating metal in the through hole comprises the following steps:

8. The 2.5D substrate packaging method of claim 6, wherein, forming a bottom metal layer in the first cavity structure. After the step of forming a conductive column in the substrate, the method further comprises the following steps: attaching a second carrier on the second surface; removing the first carrier and the seed layer; etching the substrate from the first surface to expose the conductive column from the first surface; forming a first insulating layer on the first surface by ion implantation; 9. The 2.5D substrate packaging method of claim 8, wherein, polishing the first insulating layer to expose the end face of the conductive column. After the step of polishing the first insulating layer to expose the end face of the conductive column, the method further comprises the following steps: testing the electrical performance of the conductive column and the wiring layer; Wherein, the negative electrode of the test probe is connected to the first insulating layer in the first groove, the positive electrode of the test probe is connected to the conductive column, a voltage is applied between the negative electrode and the positive electrode of the test probe, and a current change is detected; each of the plurality of conductive columns is detected, and the Ohm's law formula R=U / I is used; since the resistance R is a constant value; according to the voltage and current change curve, it is judged whether the electrical performance of the conductive column and the wiring layer produced meets the requirements.

10. The 2.5D substrate packaging method according to any one of claims 1-9, wherein, Further comprising: forming a solder ball on the surface of the medium layer and electrically connected to the wiring layer; mounting an electronic component on the solder ball.

11. The 2.5D substrate packaging method of claim 10, wherein, Further comprising: cutting the substrate to separate into single products before or after the step of mounting the electronic component on the solder ball; and / or, plastic packaging the electronic component.

12. A package structure, characterized by, The packaging structure is made by the 2.5D substrate packaging method according to any one of claims 1 to 11, and the packaging structure comprises: a substrate; the substrate comprises a first surface and a second surface arranged oppositely; a plurality of conductive columns are arranged on the substrate; each of the conductive columns partially protrudes from the first surface and the second surface; the first surface and the second surface of the substrate are sequentially formed with a first insulating layer and a second insulating layer respectively in a direction away from the substrate; the first insulating layer protects the sidewall of the protruding part of the conductive column; a first medium layer; the first medium layer is arranged on the side of the second insulating layer away from the first insulating layer, and the first medium layer has a wiring layer electrically connected to the conductive column; a second medium layer; the second medium layer is arranged on the side of the first medium layer away from the second insulating layer; a solder ball; the solder ball protrudes from the second medium layer and is electrically connected to the wiring layer; an electronic component, electrically connected to the solder ball; a plastic package; the plastic package is arranged on the substrate and covers the electronic component.

13. The package structure of claim 12, wherein, The plastic package exposes the surface of the electronic component away from the substrate.

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