Switching control circuit, DC-DC converter, and chip

Abstract

The invention provides a switch control circuit, a DC-DC converter and a chip. According to the switch control circuit, one end of a first switch module is connected with a first voltage; a second voltage is connected between one end of the second switch module and the other end of the first switch module, and the other end is grounded; a first end of the detection module is connected with a second voltage and is used for detecting the second voltage at a falling edge of the first control voltage and providing an adjusting signal based on the second voltage; the second end of the detection module is connected between the first end of the control module and the control end of the first switch module and used for providing first control voltage, the second end of the control module is connected with the control end of the second switch module and used for providing second control voltage, and the third end of the control module is connected with the third end of the detection module and used for providing second control voltage. And the adjusting module is used for adjusting the first control voltage and the second control voltage based on the adjusting signal, so that the time when the first switch module and the second switch module are turned off is within a preset range. Thus, power consumption can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electrical and electronic technology, and in particular to a switch control circuit, a DC-DC converter, and a chip. Background Art

[0002] When the switch control circuit is operating, a short circuit will occur if both switch modules are turned on at the same time. To prevent the two switch modules from turning on simultaneously, a time period during which both switch modules are turned off can be set as a transition between the two switching modules. This prevents a situation where one switch module is not fully turned off while the other switch module is turned on due to a turn-off delay.

[0003] In the related art, the time during which both switch modules are turned off is usually fixed. However, a fixed time that is too long or too short usually increases power consumption and reduces the working efficiency of the switch control circuit. Summary of the Invention

[0004] In view of this, the present application provides a switch control circuit, a DC-DC converter, and a chip, which can reduce power consumption and improve the working efficiency of the switch control circuit.

[0005] In a first aspect, the present application provides a switch control circuit, comprising: a first switch module, wherein one end of the first switch module is connected to a first voltage; a second switch module, wherein one end of the second switch module is connected to the other end of the first switch module, and the other end is grounded; a detection module, wherein the first end of the detection module is connected to the second voltage, and is used to detect the second voltage at a falling edge of the first control voltage, and provide an adjustment signal based on the second voltage; a control module, wherein the second end of the detection module is connected between the first end of the control module and the control end of the first switch module, and is used to provide the first control voltage, the second end of the control module is connected to the control end of the second switch module, and is used to provide the second control voltage, the third end of the control module is connected to the third end of the detection module, and is used to adjust the first control voltage and the second control voltage based on the adjustment signal, so that the time when the first switch module and the second switch module are both turned off is within a preset range; wherein the first voltage is one of the output voltage and the input voltage, and the second voltage is the other of the output voltage and the input voltage.

[0006] In a second aspect, the present application provides a direct current to direct current (DC-DC) converter, which includes the switch control circuit described in the first aspect.

[0007] In a third aspect, the present application provides a chip, wherein the DC-DC converter includes the DC-DC converter described in the second aspect.

[0008] The present application provides a switch control circuit, a DC-DC converter, and a chip. By detecting a second voltage at the falling edge of a first control voltage and generating an adjustment signal based on the second voltage, the adjustment signal is used to control the time when both the first switch module and the second switch module are turned off to be within a preset range, thereby reducing power consumption and improving the working efficiency of the switch control circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0010] Figure 1 It is a structural diagram of a switch control circuit;

[0011] Figure 2 It is a schematic diagram of the waveforms of the voltages in a switch control circuit;

[0012] Figure 3 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 1 ;

[0013] Figure 4 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 2 ;

[0014] Figure 5 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 3 ;

[0015] Figure 6 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 4 ;

[0016] Figure 7 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 5 ;

[0017] Figure 8 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 6 ;

[0018] Figure 9 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 7 ;

[0019] Figure 10 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 8 ;

[0020] Figure 11 1 is a schematic diagram of waveforms of various voltages in a switch control circuit provided in an embodiment of the present application;

[0021] Figure 12 1 is a schematic structural diagram of a DC-DC converter provided in an embodiment of the present application;

[0022] Figure 13 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and in detail described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the embodiments of the present application.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0025] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] It should also be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0027] In addition, the term "and / or" in the embodiments of this application is merely a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0028] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following relevant technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all fall within the protection scope of the embodiments of the present application.

[0029] When the switch control circuit is operating, the two switch modules alternately turn on. In practice, both switch modules may be turned on simultaneously. This can cause leakage from the power supply to ground, increasing power consumption and reducing the efficiency of the switch control circuit. To prevent the two switch modules from turning on simultaneously, a time period during which both switch modules are turned off can be set as a transition between the alternating turns on. This prevents a situation where one switch module is not fully turned off while the other is turned on due to a shutdown delay.

[0030] For example, taking the boost circuit as an example, Figure 1 It is a structural diagram of a switch control circuit. Figure 1 As shown, the switch control circuit 100 may include a control module 101, a driving module 102, a PMOS transistor M1, an NMOS transistor M2, an inductor L1, a resistor R1, a resistor R2, an error amplifier 103, and a comparator 104. The connection relationship between the components is as follows:

[0031] The first end of the control module 101 is connected to the first end of the driving module 102, the second end of the control module 101 is connected to the second end of the driving module 102, and the third end of the control module 101 is connected to the output end of the comparator 104; the third end of the driving module 102 is connected to the gate of the PMOS transistor M1, and the fourth end of the driving module 102 is connected to the gate of the NMOS transistor M2; the source of the PMOS transistor M1 is connected to the output voltage V OUT , connect the inductor L1 in series between the drain of the PMOS tube M1 and the drain of the NMOS tube M2, and then connect the input voltage V IN , the source of NMOS tube M2 is grounded; one end of resistor R1 is connected between the source of PMOS tube M1 and the output voltage V OUT The other end is connected to the negative end of the error amplifier 103, and the other end of the resistor R2 is grounded; the positive end of the error amplifier 103 is connected to the reference voltage V REF The output of the error amplifier 103 is connected to the negative terminal of the comparator 104; the positive terminal of the comparator 104 is connected to the slope voltage V slope .

[0032] Output voltage V OUT The voltage V at the negative terminal of the error amplifier 103 is obtained through the feedback resistor network composed of resistors R1 and R2. OUT_FB , and then amplified by the error amplifier 103 and the reference voltage V REFThe deviation of the output voltage V of the error amplifier 103 is obtained. EA , and V EA As the voltage of the negative terminal of the comparator 104, V EA It is V REF With V OUT_FB The multiple of the difference. V EA With the slope voltage V slope After comparison by the comparator 104, the digital signal V is output. PWM_OUT , the control module 101 passes the digital signal V PWM_OUT Provide control voltage V PDRV_PRE and control voltage V NDRV_PRE , control voltage V PDRV_PRE and control voltage V NDRV_PRE After passing through the driving module 102, the delayed and / or driving capability-enhanced control voltage V PDRV and control voltage V NDRV , to pass V PDRV and V NDRV Control the on / off of the PMOS tube M1 and the NMOS tube M2 to adjust the output voltage V OUT For example, in V OUT_FB Greater than V REF When V EA will become low, V PWM_OUT will become high, and the control module 101 will then PDRV_PRE and V NDRV_PRE are pulled low, V PDRV_PRE and V NDRV_PRE After passing through the driving module 102, the NMOS transistor M2 is turned off and the PMOS transistor M1 is turned on, thereby increasing the output voltage V OUT Charge.

[0033] Due to the existence of non-ideal effects, the switching of PMOS tube M1 and NMOS tube M2 requires a certain amount of time, so there may be a situation where PMOS tube M1 and NMOS tube M2 are turned on at the same time. At this time, the output voltage V OUT The short circuit leakage to ground increases power consumption and reduces the working efficiency of the switch control circuit. Therefore, by setting the time when both the PMOS transistor M1 and the NMOS transistor M2 are turned off, the PMOS transistor M1 is turned on after the NMOS transistor M2 is completely turned off, thereby avoiding the situation where the PMOS transistor M1 and the NMOS transistor M2 are turned on at the same time.

[0034] Exemplarily, the control module 101 may be a pulse width modulation (PWM) logic module.

[0035] Exemplarily, the comparator 104 may be a PWM comparator.

[0036] Figure 2 It is a waveform diagram of each voltage in a switch control circuit. Figure 2 As shown, the current flowing through the inductor L1 is recorded as I L , the voltage between the drain of the PMOS tube M1 and the drain of the NMOS tube M2 is recorded as V SW , we can get I L 、V SW 、V PDRV and V NDRV waveform.

[0037] I understand. Figure 2 Can be Figure 1 The waveforms of the voltages in the switch control circuit shown.

[0038] Understandably, in V PDRV and V NDRV When both are high level, the PMOS tube M1 is turned off and the NMOS tube M2 is turned on. L The direction is positive, V SW Equal to 0; at V NDRV Low level, V PDRV When the level is high, both the NMOS tube M2 and the PMOS tube M1 are turned off. L The direction is negative, V SW Equal to V OUT and the body diode voltage in the PMOS tube M1; NDRV and V PDRV When both are at low level, NMOS tube M2 is turned off and PMOS tube M1 is turned on. L The direction is negative, V SW Equal to V OUT .

[0039] In the related art, when the switch control circuit is working, the time when both switch modules are turned off is usually fixed, for example, Figure 2 As shown, the time when both the PMOS tube M1 and the NMOS tube M2 are turned off is recorded as the dead time. It can be seen that Figure 2 The dead time shown is a fixed time. However, a fixed time that is too long or too short will usually increase power consumption and reduce the operating efficiency of the switch control circuit.

[0040] Based on this, an embodiment of the present application provides a switch control circuit, which detects a second voltage at the falling edge of a first control voltage and generates an adjustment signal based on the second voltage, so as to control the time when the first switch module and the second switch module are both turned off to be within a preset range through the adjustment signal, thereby reducing power consumption and improving the working efficiency of the switch control circuit.

[0041] To facilitate understanding of the technical solutions of the embodiments of the present application, the technical solutions of the present application are described in detail below through specific embodiments. The above related technologies can be combined with the technical solutions of the embodiments of the present application as optional solutions, and they all fall within the scope of protection of the embodiments of the present application. The embodiments of the present application include at least part of the following contents.

[0042] Figure 3 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 1 ,like Figure 3 As shown, the switch control circuit 300 may include:

[0043] A first switch module 301, wherein one end of the first switch module 301 is connected to a first voltage V1; a second switch module 302, wherein one end of the second switch module 302 is connected to the other end of the first switch module 301 and the second voltage V2 is connected, and the other end is grounded; a detection module 303, wherein a first end of the detection module 303 is connected to the second voltage V2, and is configured to detect the second voltage V2 at a falling edge of the first control voltage and provide an adjustment signal based on the second voltage V2; a control module 304, wherein a first end of the control module 304 is connected to a second end of the detection module 303 between a control end of the first switch module 301 and the second end of the detection module 303 is configured to provide the first control voltage, a second end of the control module 304 is connected to a control end of the second switch module 302 and the second control voltage, and a third end of the control module 304 is connected to a third end of the detection module 303 and is configured to adjust the first control voltage and the second control voltage based on the adjustment signal so that the time when the first switch module 301 and the second switch module 302 are both turned off is within a preset range.

[0044] The first voltage V1 is one of the output voltage and the input voltage, and the second voltage V2 is the other of the output voltage and the input voltage.

[0045] It should be noted that when the first voltage V1 is the output voltage and the second voltage V2 is the input voltage, the switch control circuit can be a Boost circuit; when the first voltage V1 is the input voltage and the second voltage V2 is the output voltage, the switch control circuit can be a Buck circuit.

[0046] It should also be noted that the preset range can be set by those skilled in the art based on experience, or can be set in other ways, and the embodiments of the present application are not limited to this.

[0047] For example, the control module 304 may be the control module 101 in the aforementioned embodiment, or may be another control module, which is not limited in the embodiment of the present application.

[0048] It should be understood that providing an adjustment signal based on the second voltage V2 can be understood as judging whether the time when both switch modules (i.e., the first switch module 301 and the second switch module 302) are turned off in the current cycle is too long or too short based on the level of the second voltage V2 in the current cycle, and generating an adjustment signal based on the judgment result to adjust the time when both switch modules are turned off in the next cycle through the adjustment signal.

[0049] Furthermore, the third end of the control module 304 is used to reduce the time when the first switch module 301 and the second switch module 302 are both turned off in the next cycle based on the adjustment signal in the current cycle when the second voltage V2 in the current cycle is at a high level; or, when the second voltage V2 in the current cycle is at a low level, increase the time when the first switch module 301 and the second switch module 302 are both turned off in the next cycle based on the adjustment signal in the current cycle.

[0050] It can be understood that when the second voltage V2 in the current cycle is at a high level, it means that the time when both the first switch module 301 and the second switch module 302 are turned off in the current cycle is too long. In this case, the time when both the first switch module 301 and the second switch module 302 are turned off in the next cycle can be reduced by adjusting the signal. When the second voltage V2 in the current cycle is at a low level, it means that the time when both the first switch module 301 and the second switch module 302 are turned off in the current cycle is too short. In this case, the time when both the first switch module 301 and the second switch module 302 are turned off in the next cycle can be increased by adjusting the signal. In this way, the time when both switch modules are turned off can be dynamically adjusted, thereby improving the operating efficiency of the switch control circuit.

[0051] Based on the above technical solution, by detecting the second voltage at the falling edge of the first control voltage and generating an adjustment signal based on the second voltage, the time when the first switch module and the second switch module are both turned off is controlled by the adjustment signal to be within a preset range, thereby reducing power consumption and improving the working efficiency of the switch control circuit.

[0052] In some embodiments, Figure 3 The switch control circuit 300 shown is based on Figure 4 As shown, the first switch module 301 may include a PMOS transistor M3, the source of the PMOS transistor M3 is connected to the first voltage V1, the gate of the PMOS transistor M3 is connected to the first end of the control module 304, and the second end of the detection module 303 is connected between the gate and the first end of the control module 304, and the drain of the PMOS transistor M3 is connected to one end of the second switch module 302. The second voltage V2 is connected.

[0053] It should be noted that the first switch module 301 may include one PMOS transistor (such as the PMOS transistor M3 ), or may include multiple PMOS transistors, which is not limited in the embodiment of the present application.

[0054] It should also be noted that, in addition to being a PMOS tube, the first switch module 301 may also be a thyristor, a transistor, an insulated-gate bipolar transistor (IGBT), etc., which is not limited in the embodiment of the present application.

[0055] It should be understood that the first control voltage and the first voltage V1 can control the conduction or shutdown of the PMOS transistor M3. Furthermore, when the first control voltage is at a high level, the difference between the first voltage V1 and the first control voltage is less than the threshold voltage of the PMOS transistor M3, thereby controlling the PMOS transistor M3 to be turned off; when the first control voltage is at a low level, the difference between the first voltage V1 and the first control voltage is greater than or equal to the threshold voltage of the PMOS transistor M3, thereby controlling the PMOS transistor M3 to be turned on.

[0056] Based on the above technical solution, the conduction or shutdown of the PMOS tube M3 is controlled by the first control voltage and the first voltage, so that there is no path from the first voltage to the ground under different first voltages, thereby reducing the risk of leakage and improving the stability of the circuit.

[0057] In some embodiments, Figure 3 The switch control circuit 300 shown is based on Figure 5 As shown, the second switch module 302 may include an NMOS transistor M4, the source of the NMOS transistor M4 is grounded, the gate of the NMOS transistor M4 is connected to the second end of the control module 304, and the drain of the NMOS transistor M4 and the drain of the PMOS transistor M3 are connected to the second voltage V2.

[0058] It should be noted that the second switch module 302 may include one NMOS transistor (such as the NMOS transistor M4 ), or may include multiple NMOS transistors, which is not limited in the embodiment of the present application.

[0059] It should also be noted that, in addition to being an NMOS tube, the second switch module 302 may also be a thyristor, a transistor, an IGBT, etc., which is not limited in the embodiment of the present application.

[0060] It should be understood that the ground voltage and the second control voltage can control the conduction or shutdown of the NMOS transistor M4. Furthermore, when the second control voltage is at a high level, the difference between the second control voltage and the ground voltage is greater than or equal to the threshold voltage of the NMOS transistor M4, thereby controlling the NMOS transistor M4 to be turned on; when the second control voltage is at a low level, the difference between the second control voltage and the ground voltage is less than the threshold voltage of the NMOS transistor M4, thereby controlling the NMOS transistor M4 to be turned off.

[0061] Based on the above technical solution, the NMOS tube M4 is turned on or off by controlling the ground voltage and the second control voltage, so that there is no path from the first voltage to the ground under different first voltages, thereby reducing the risk of leakage and improving the stability of the circuit.

[0062] In some embodiments, Figure 3 The switch control circuit 300 shown is based on Figure 6 As shown, the detection module 303 may include a sampling module 601, a D-type flip-flop 602, an inverter 603, and an up-down counter 604, wherein: one end of the sampling module 601 is connected to the second voltage V2, and the other end is connected to the first end of the D-type flip-flop 602; the second end of the D-type flip-flop 602 is connected to one end of the inverter 603; the other end of the inverter 603 is connected between the first end of the control module 304 and the gate of the PMOS transistor M3; one end of the up-down counter 604 is connected to the third end of the D-type flip-flop 602, and the other end is connected to the third end of the control module 304.

[0063] It should be noted that the other end of the inverter 603 is used to detect the first control voltage. One end of the sampling module 601 is used to detect the second voltage V2 at the falling edge of the first control voltage. The third end of the D flip-flop 602 is used to output a high level or a low level based on the level of the second voltage V2. Furthermore, when the second voltage V2 is at a high level, the third end of the D flip-flop 602 outputs a high level, and when the second voltage V2 is at a low level, the third end of the D flip-flop 602 outputs a low level. The up-down counter 604 is used to: when the third end of the D flip-flop 602 outputs a high level in the current cycle, perform a subtraction operation, thereby outputting an adjustment signal through the other end of the up-down counter 604 to reduce the time during which both the first switch module 301 and the second switch module 302 are off in the next cycle; and when the third end of the D flip-flop 602 outputs a low level in the current cycle, perform a addition operation, thereby outputting an adjustment signal through the other end of the up-down counter 604 to increase the time during which both the first switch module 301 and the second switch module 302 are off in the next cycle.

[0064] Based on the above technical solution, by detecting the second voltage at the falling edge of the first control voltage and controlling the add-subtract counter to add and subtract according to the level of the second voltage, the time when the first switch module and the second switch module are both turned off can be adaptively changed, avoiding the time when the first switch module and the second switch module are both turned off being too long or too short, thereby reducing power consumption and improving the working efficiency of the switch control circuit.

[0065] In some embodiments, Figure 3 The switch control circuit 300 shown is based on Figure 7 As shown, the switch control circuit may further include a driving module 701, wherein a first end of the driving module 701 is connected to the other end of the inverter 603 between the first end of the control module 304, a second end of the driving module 701 is connected to the second end of the control module 304, a third end of the driving module 701 is connected to the gate of the PMOS transistor M3, and a fourth end of the driving module 701 is connected to the gate of the NMOS transistor M4, for delaying the first control voltage and the second control voltage, and / or enhancing the driving capability of the first control voltage and the second control voltage.

[0066] It should be noted that the driving module 701 is used to delay the first control voltage and the second control voltage. It can be understood that the third terminal of the driving module 701 is used to delay the first control voltage, and the fourth terminal of the driving module 701 is used to delay the second control voltage.

[0067] It should also be noted that the PMOS tube M3 can be controlled to be turned on or off by the delayed and / or driven-capability-enhanced first control voltage and the first voltage V1; and the NMOS tube M4 can be controlled to be turned on or off by the delayed and / or driven-capability-enhanced second control voltage and the ground voltage.

[0068] Furthermore, Figure 3 and Figure 7 In comparison, Figure 3 As shown, before the first control voltage and the second control voltage are delayed, the detection module 303 can generate an adjustment signal according to the level of the second voltage V2 in the current cycle, and the control module 304 can adjust the first control voltage and the second control voltage according to the adjustment signal, so as to adjust the time when both switch modules are turned off in the next cycle according to the adjusted first control voltage and the second control voltage; as shown in FIG. Figure 4As shown, after the first control voltage and the second control voltage are delayed, the detection module 303 can generate an adjustment signal according to the level of the second voltage V2 in the current cycle, and the control module 304 can adjust the first control voltage and the second control voltage according to the adjustment signal. After the first control voltage and the second control voltage are delayed by the driving module 701, the delayed first control voltage and the delayed second control voltage have been adjusted, so that the time when both switch modules are turned off in the current cycle can be adjusted by the delayed first control voltage and the delayed second control voltage.

[0069] It can be understood that the first control voltage with enhanced driving capability has a stronger control capability on the PMOS transistor M3, thereby accelerating the speed of turning on or off the PMOS transistor M3; the second control voltage with enhanced driving capability has a stronger control capability on the NMOS transistor M4, thereby accelerating the speed of turning on or off the NMOS transistor M4.

[0070] Based on the above technical solution, the first control voltage with enhanced driving capability and / or the second control voltage with enhanced driving capability have stronger control capabilities over the PMOS transistor M3 and the NMOS transistor M4, thereby improving the response efficiency of the switch control circuit; the delayed first control voltage and the second control voltage can adjust the time when both switch modules are turned off in the current cycle, thereby further reducing power consumption and improving the working efficiency of the switch control circuit.

[0071] In some embodiments, Figure 3 The switch control circuit 300 shown is based on Figure 8 As shown, the switch control circuit may further include a first resistor R3, a second resistor R4, an error amplifier 801, and a comparator 802, wherein: one end of the first resistor R3 is connected between one end of the first switch module 301 and the first voltage V1, and the other end is connected to the negative terminal of the error amplifier 801 between the first end and one end of the second resistor R4, and the other end of the second resistor R4 is grounded; the positive terminal of the error amplifier 801 is connected to the reference voltage, and the output terminal of the error amplifier 801 is connected to the negative terminal of the comparator 802; the positive terminal of the comparator 802 is connected to the slope voltage, and the output terminal of the comparator 802 is connected to the fourth terminal of the control module 304 for outputting the digital signal V PWM_OUT1 , so that the control module 304 passes the digital signal V PWM_OUT1 A first control voltage and a second control voltage are provided.

[0072] For example, the error amplifier 801 may be the error amplifier 103 in the aforementioned embodiment, or may be another error amplifier, which is not limited in the embodiment of the present application.

[0073] Exemplarily, the comparator 802 may be the comparator 104 in the aforementioned embodiment, or may be other comparators, which is not limited in the embodiment of the present application.

[0074] It should be noted that the first voltage V1 passes through the feedback resistor network composed of the first resistor R3 and the second resistor R4 to obtain the voltage V at the negative terminal of the error amplifier 801. OUT_FB1 , and then amplified by the error amplifier 801 and the reference voltage V REF1 The deviation of the error amplifier 801 is obtained by the output voltage V EA1 , and V EA1 As the voltage of the negative terminal of the comparator 802, where V EA1 It is V REF1 With V OUT_FB1 The multiple of the difference. V EA1 With the slope voltage V slope1 After comparison by comparator 802, the digital signal V is output PWM_OUT1 , the control module 304 passes the digital signal V PWM_OUT1 Provide a first control voltage and a second control voltage to control the first switch module 301 and the second switch module 302 to be turned on or off by the first control voltage and the second control voltage, so as to adjust the first voltage V1. OUT_FB1 Greater than V REF1 When V EA1 will become low, V PWM_OUT1 will become high, and at this time the control module 304 will lower both the first control voltage and the second control voltage, thereby turning off the second switch module 302 and turning on the first switch module 301 to realize charging of the first voltage V1.

[0075] Based on the above technical solution, the control module can provide the first control voltage and the second control voltage through digital signals, and subsequently control the conduction or shutdown of the two switch modules based on the first control voltage and the second control voltage, so that there will be no path from the first voltage to the ground under different first voltages, thereby reducing the risk of leakage and improving the stability of the circuit.

[0076] In some embodiments, Figure 3 The switch control circuit 300 shown is based on Figure 9 As shown, the switch control circuit may further include a first inductor L2, one end of the first inductor L2 is connected to the other end of the first switch module 301, one end of the second switch module 302 and the first end of the detection module 303, and the other end is connected to the second voltage V2. The detection module 303 is used to detect the node voltage V at the falling edge of the first control voltage. SW1 , and based on the node voltage V SW1 Provides a regulation signal; wherein the node voltage V SW1is the voltage between the first switch module 301 and the second switch module 302 .

[0077] It should be understood that based on the node voltage V SW1 Providing a regulation signal can be understood as based on the node voltage V in the current cycle SW1 The level of is used to judge whether the time when both switch modules are turned off in the current cycle is too long or too short, and an adjustment signal is generated based on the judgment result to adjust the time when both switch modules are turned off in the next cycle through the adjustment signal.

[0078] Furthermore, the third terminal of the control module 304 is used to control the node voltage V SW1 When the node voltage V SW1 When it is at a low level, based on the adjustment signal in the current cycle, the time when both the first switch module 301 and the second switch module 302 are turned off in the next cycle is increased.

[0079] It can be understood that the node voltage V SW1 When the node voltage V SW1 If the signal is low, it indicates that the time during which both the first switch module 301 and the second switch module 302 are turned off is too short in the current cycle. In this case, the signal can be adjusted to increase the time during which both the first switch module 301 and the second switch module 302 are turned off in the next cycle. This allows the time during which both switch modules are turned off to be dynamically adjustable, thereby increasing the operating efficiency of the switch control circuit.

[0080] Based on the above technical solution, by detecting the node voltage at the falling edge of the first control voltage and generating an adjustment signal based on the node voltage, the time when the first switch module and the second switch module are both turned off is controlled by the adjustment signal to be within a preset range, thereby reducing power consumption and improving the working efficiency of the switch control circuit.

[0081] The switch control circuit provided in the above embodiment is described in detail below in conjunction with specific application scenarios.

[0082] exist Figure 3 The switch control circuit 300 shown is based on Figure 10 This is a schematic diagram of the structure of a switch control circuit provided in an embodiment of the present application. Figure 8The connection relationship between the various components can be referred to the description in the aforementioned embodiment and will not be repeated here.

[0083] like Figure 10 As shown, if the node voltage V sampled by the sampling module 601 in the current cycle is SW1 If the voltage is high, it means that the time when the PMOS tube M3 and the NMOS tube M4 are both turned off in the current cycle is too long. At this time, the up-down counter 604 performs a subtraction operation, thereby outputting an adjustment signal through the other end of the up-down counter 604. The control module 304 can adjust the first control voltage and the second control voltage according to the adjustment signal. After the driving module 701 delays the first control voltage and the second control voltage, the delayed first control voltage and the second control voltage have been adjusted, thereby reducing the time when the PMOS tube M3 and the NMOS tube M4 are both turned off in the current cycle through the delayed first control voltage and the second control voltage.

[0084] If the node voltage V sampled by the sampling module 601 in the current cycle SW1 If the level is low, it means that the time when the PMOS tube M3 and the NMOS tube M4 are both turned off in the current cycle is too short. At this time, the up-down counter 604 performs an increment operation, thereby outputting an adjustment signal through the other end of the up-down counter 604. The control module 304 can adjust the first control voltage and the second control voltage according to the adjustment signal. After the driving module 701 delays the first control voltage and the second control voltage, the delayed first control voltage and the second control voltage have been adjusted, thereby increasing the time when the PMOS tube M3 and the NMOS tube M4 are both turned off in the current cycle according to the delayed first control voltage and the second control voltage.

[0085] Figure 11 Schematic diagram of the waveforms of the voltages in a switch control circuit provided by an embodiment of the present application. Figure 11 As shown, the current flowing through the inductor L2 is recorded as I L1 , the first control voltage is recorded as V PDRV_PRE1 , the second control voltage is recorded as V NDRV_PRE1 , the first control voltage after delay is recorded as V PDRV1 The second control voltage after delay is recorded as V NDRV1 , we can get I L1 、V SW1 、V PDRV_PRE1 、V NDRV_PRE1 , V after delay PDRV1 、V NDRV1 waveform.

[0086] I understand. Figure 11 Can be Figure 10 The waveforms of the voltages in the switch control circuit shown.

[0087] Understandably, in V PDRV1 and V NDRV1 When both are high level, the PMOS tube M3 is turned off and the NMOS tube M4 is turned on. L1 The direction is positive, V SW1 Equal to 0; at V NDRV1 Low level, V PDRV1 When the level is high, both the NMOS tube M4 and the PMOS tube M3 are turned off. L1 The direction is negative, V SW1 Equal to the sum of V1 and the body diode voltage in PMOS tube M3; NDRV1 and V PDRV1 When both are at low level, NMOS tube M4 is turned off and PMOS tube M3 is turned on. L1 The direction is negative, V SW1 Equal to V1.

[0088] like Figure 11 As shown, the first to fifth dead times are the times when both the PMOS transistor M3 and the NMOS transistor M4 are turned off. It can be seen that in the regulation phase, the first to third dead times do not show periodic changes, while in the steady-state phase, the fourth and fifth dead times, as well as the dead times after the fifth dead time, show periodic changes. At this time, the up-down counter 604 adds 1 in the previous cycle and subtracts 1 in the next cycle, corresponding to an increase in the dead time of the previous cycle and a decrease in the dead time of the next cycle. This cycle repeats to control the time when both the PMOS transistor M3 and the NMOS transistor M4 are turned off to be within a preset range.

[0089] It can be understood that since V is detected in the first cycle SW1 is high, so the second dead time needs to be reduced based on the first dead time; since V is detected in the second cycle SW1 is high, so the third dead time needs to be reduced based on the second dead time; since V is detected in the third cycle SW1 is low, so the fourth dead time needs to be increased based on the third dead time; since V is detected in the fourth cycle SW1 is high level, so the fifth dead time needs to be reduced based on the fourth dead time.

[0090] It can also be understood that due to the existence of the driving module 701, through V NDRV1 and V PDRV1 The time when both the PMOS tube M3 and the NMOS tube M4 are turned off in the current cycle can be adjusted. For example, taking the first dead time and the second dead time as an example, VSW1 is high, so it is necessary to reduce the first dead time by adjusting the signal to V PDRV_PRE1 and V NDRV_PRE1 After adjustment, the first dead time (i.e., the second dead time) can be reduced; the driving module 701 controls V PDRV_PRE1 and V NDRV_PRE1 After the delay, the obtained V NDRV1 and V PDRV1 has been regulated, so through V NDRV1 and V PDRV1 It can be obtained that the time during which both the PMOS tube M3 and the NMOS tube M4 are turned off in the first cycle is the second dead time.

[0091] Based on the above technical solution, by detecting the node voltage at the falling edge of the first control voltage and generating an adjustment signal based on the node voltage, the adjustment signal is used to control the time when both the PMOS transistor M3 and the NMOS transistor M4 are turned off to be within a preset range, thereby reducing power consumption and improving the working efficiency of the switch control circuit.

[0092] The preferred embodiments of the present application are described in detail above in conjunction with the accompanying drawings. However, the present application is not limited to the specific details in the above embodiments. Within the technical concept of the present application, the technical solution of the present application can be subjected to a variety of simple modifications, and these simple modifications all fall within the scope of protection of the present application. For example, the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present application will not further describe the various possible combinations. For another example, the various different embodiments of the present application can also be arbitrarily combined, as long as they do not violate the ideas of the present application, they should also be regarded as the contents disclosed in the present application. For another example, under the premise of no conflict, the various embodiments and / or the technical features in each embodiment described in the present application can be arbitrarily combined with the relevant technologies, and the technical solution obtained after the combination should also fall within the scope of protection of the present application.

[0093] Figure 12 This is a schematic diagram of the structure of a DC-DC converter provided in an embodiment of the present application. Figure 12 As shown, the DC-DC converter 1200 may include the switch control circuit 300 in the above embodiment, and has the beneficial effects of the switch control circuit in the above embodiment, which will not be described in detail here.

[0094] Figure 13 This is a schematic diagram of the structure of a chip provided in an embodiment of the present application. Figure 13 As shown, the chip 1300 may include the DC-DC converter 1200 in the above embodiment.

[0095] It should be noted that, in this application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, article, or device comprising the element.

[0096] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0097] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0098] The above implementation methods are only used to illustrate the embodiments of the present application, and are not intended to limit the embodiments of the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the embodiments of the present application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present application, and the scope of patent protection of the embodiments of the present application should be defined by the claims.

Claims

1. A switch control circuit, characterized in that: include: a first switch module, one end of which is connected to a first voltage; a second switch module, wherein one end of the second switch module is connected to a second voltage with the other end of the first switch module, and the other end is grounded; a detection module, wherein a first terminal of the detection module is connected to the second voltage, and is configured to detect the second voltage at a falling edge of the first control voltage, and provide an adjustment signal based on the second voltage; a control module, wherein a first terminal of the control module is connected to the second terminal of the detection module between the first terminal of the control module and the control terminal of the first switch module, and is used to provide the first control voltage; a second terminal of the control module is connected to the control terminal of the second switch module and is used to provide the second control voltage; a third terminal of the control module is connected to the third terminal of the detection module and is used to adjust the first control voltage and the second control voltage based on the adjustment signal so that the time when the first switch module and the second switch module are both turned off is within a preset range; The first voltage is one of the output voltage and the input voltage, and the second voltage is the other of the output voltage and the input voltage.

2. The switch control circuit according to claim 1, wherein: The first switch module includes a PMOS tube, the source of the PMOS tube is connected to the first voltage, the gate of the PMOS tube is connected to the first end of the control module to the second end of the detection module, and the drain of the PMOS tube is connected to one end of the second switch module to the second voltage.

3. The switch control circuit according to claim 2, wherein: The second switch module includes an NMOS tube, the source of the NMOS tube is grounded, the gate of the NMOS tube is connected to the second end of the control module, and the drain of the NMOS tube and the drain of the PMOS tube are connected to the second voltage.

4. The switch control circuit according to claim 3, wherein: The detection module includes a sampling module, a D trigger, an inverter and an up-down counter, wherein: One end of the sampling module is connected to the second voltage, and the other end is connected to the first end of the D flip-flop, the second end of the D flip-flop is connected to one end of the inverter, and the other end of the inverter is connected between the first end of the control module and the gate of the PMOS tube; One end of the up-down counter is connected to the third end of the D flip-flop, and the other end is connected to the third end of the control module.

5. The switch control circuit according to claim 4, characterized in that: The switch control circuit also includes a driving module, wherein a first end of the driving module is connected to the other end of the inverter between the first end of the control module, a second end of the driving module is connected to the second end of the control module, a third end of the driving module is connected to the gate of the PMOS transistor, and a fourth end of the driving module is connected to the gate of the NMOS transistor, for delaying the first control voltage and the second control voltage, and / or enhancing the driving capability of the first control voltage and the second control voltage.

6. The switch control circuit according to any one of claims 1 to 5, characterized in that: The switch control circuit further includes a first resistor, a second resistor, an error amplifier and a comparator, wherein: One end of the first resistor is connected between one end of the first switch module and the first voltage, the other end of the first resistor is connected to the negative terminal of the error amplifier between the other end and one end of the second resistor, and the other end of the second resistor is grounded; The positive terminal of the error amplifier is connected to the reference voltage, and the output terminal of the error amplifier is connected to the negative terminal of the comparator; The positive terminal of the comparator is connected to the slope voltage, and the output terminal of the comparator is connected to the fourth terminal of the control module for outputting a digital signal so that the control module provides the first control voltage and the second control voltage through the digital signal.

7. The switch control circuit according to any one of claims 1 to 5, characterized in that: The switch control circuit also includes a first inductor, one end of which is connected to the other end of the first switch module, one end of the second switch module, and the first end of the detection module, and the other end is connected to the second voltage. The detection module is used to detect a node voltage at a falling edge of the first control voltage and provide the adjustment signal based on the node voltage; wherein the node voltage is the voltage between the first switch module and the second switch module.

8. The switch control circuit according to any one of claims 1 to 5, characterized in that: The third end of the control module is used to reduce the time when the first switch module and the second switch module are both turned off in the next cycle based on the adjustment signal in the current cycle when the second voltage in the current cycle is at a high level; or to increase the time when the first switch module and the second switch module are both turned off in the next cycle based on the adjustment signal in the current cycle when the second voltage in the current cycle is at a low level.

9. A DC-DC converter, characterized in that: The DC-DC converter includes at least the switch control circuit according to any one of claims 1 to 8.

10. A chip, characterized in that: comprising the DC-DC converter as claimed in claim 9.

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