Soft start circuit and DC-DC converter

Abstract

The invention relates to a soft start circuit and a DC-DC converter. The soft start circuit can suppress overshoot of an output voltage when recovering from an abnormal state in which the output voltage is reduced. The DC power supply device includes: an error amplifier circuit that inputs a feedback voltage corresponding to an output voltage and a predetermined voltage; a driving switching element provided between a voltage input terminal and a voltage output terminal; and a control circuit that controls the driving switching element in accordance with the output of the error amplifier circuit. The soft start circuit of the DC power supply device generates a soft start voltage for controlling the ON of the driving switching element when the voltage of the voltage input terminal rises, and is provided with: a state detection means capable of detecting a state in which the output voltage of the error amplification circuit exceeds a predetermined potential; the soft start voltage is generated on the basis of the condition that a state detection unit detects that the output voltage of the error amplification circuit recovers from a state in which the output voltage exceeds a predetermined potential.

Description

Technical Field

[0001] The present invention relates to a soft start circuit and a DC-DC converter of a DC power supply device, and, for example, to a technology that is effective when applied to a switching regulator type DC-DC converter. Background Art

[0002] As a power supply device that supplies a DC power supply voltage, there is a switching regulator type DC-DC converter. Among switching regulator type DC-DC converters, there are DC-DC converters that control the output voltage using a PWM control method (e.g., Patent Document 1). Furthermore, some DC-DC converters include a soft-start circuit that suppresses inrush current during startup and prevents overshoot of the output voltage (e.g., Patent Document 2).

[0003] Some DC-DC converters are equipped with an output low voltage protection circuit that detects when the output voltage drops below a predetermined potential and stops the output.

[0004] Prior art literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2002-044938

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2009-100497 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] In automotive electronic control systems equipped with battery-powered DC-DC converters, the input voltage sometimes drops below the DC-DC converter's output voltage during startup. DC-DC converters equipped with low-voltage protection circuits are required to maintain output even in such situations. However, this presents the following problems.

[0009] Figure 6 This is a timing diagram showing the changes in the main voltages and signals of a general PWM-controlled DC-DC converter as the input voltage decreases. VIN is the input voltage, VOUT is the output voltage, COMP is the output of the error amplifier (amplifier circuit), RAMP is the waveform signal (triangle wave) compared with the error amplifier output, and PWM is the drive signal waveform (drive pulse) of the switching element.

[0010] like Figure 6As shown in the figure, when the DC-DC converter's input voltage VIN decreases, the output voltage VOUT also decreases, and the COMP voltage rises above the RAMP maximum voltage. Subsequently, when the input voltage VIN begins to rise at timing t1, the output voltage VOUT follows the input voltage VIN and rises accordingly. When the output voltage VOUT reaches the set voltage at timing t2, the COMP voltage begins to decrease. However, the duty cycle control signal for the drive pulse corresponding to the input-output voltage difference cannot be immediately output, so VOUT continues to rise above the set voltage.

[0011] Then, when the COMP voltage drops to a voltage at which the duty ratio can be controlled, the output voltage VOUT stops rising, and the output of the converter is controlled to the set voltage.

[0012] As described above, conventional PWM controlled DC-DC converters have a problem in which the output voltage VOUT overshoots when the output voltage VOUT recovers from a state where the output voltage VOUT cannot be controlled to the set voltage. Figure 6 In the embodiment, the high-level period of the PWM pulse is controlled to turn on the driving switch transistor (M1 in the figure). Therefore, in the period T1 where the COMP voltage is higher than the maximum voltage of RAMP, the driving switch M1 is turned on for a longer time.

[0013] In order to solve the problem of overshoot, the present inventors have thought of and studied Figure 7 The circuit structure shown.

[0014] exist Figure 7 In the circuit shown, VO is the terminal to which the output voltage VOUT is applied, AMP is the error amplifier that amplifies the potential difference between the voltage VFB obtained by resistor-dividing VOUT and the reference voltage VREF, CLP1 is the clamping circuit that clamps the potential at terminal SS, and CLP2 is the clamping circuit that clamps the voltage COMP supplied from the error amplifier AMP to the subsequent-stage PWM comparator.

[0015] SS clamp circuit CLP1 creates an offset between the input terminals. When voltage VFB decreases due to a decrease in output voltage VOUT, the potential at terminal SS is clamped to a level close to voltage VFB. This suppresses abrupt changes in the output of error amplifier AMP when input voltage VIN rises, thereby providing a soft-start function that prevents overshoot of output voltage VOUT. Additionally, although not shown, an output low-voltage protection circuit is provided that detects a low-voltage state in output voltage VOUT and halts output.

[0016] but, Figure 7In the circuit shown, if the output voltage VOUT drops and enters an abnormal state where the SS pin voltage is clamped, and if the VO pin voltage drops below the detection voltage VLVP of the output low-voltage protection circuit, even if the VO pin voltage rises due to soft-start operation, output may be stopped due to the detection of the output low-voltage state, provided that the abnormal state is recovered within the low-voltage detection delay time (TDLY).

[0017] Here, assuming the soft-start time is Tss, the condition for output not to be stopped by the output undervoltage protection circuit is Tss < TDLY. Furthermore, if the delay time TDLY is extended, if an output abnormality (overcurrent due to a short circuit) occurs, the time until the abnormality is detected and output is stopped becomes longer. This can cause current to continue flowing through the drive switching transistor, potentially heating the IC and damaging it. Therefore, it is not advisable to extend the delay time TDLY too long.

[0018] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a soft start circuit capable of suppressing an overshoot of an output voltage when recovering from an abnormal state in which the output voltage drops.

[0019] Another object of the present invention is to provide a DC-DC converter that recovers from an abnormal state of output voltage drop within a detection delay time of the output low voltage and does not stop output due to detection of the output low voltage state.

[0020] Means for solving problems

[0021] To achieve the above-mentioned object, the present invention provides a soft start circuit in a DC power supply device, the DC power supply device comprising: an error amplifier circuit that receives a feedback voltage corresponding to an output voltage and a predetermined first reference voltage as input; a drive switching element disposed between a voltage input terminal and a voltage output terminal; and a control circuit that controls the drive switching element based on the output of the error amplifier circuit. The soft start circuit generates a soft start voltage for controlling the drive switching element to turn on when the voltage at the voltage input terminal rises, wherein:

[0022] The soft start circuit includes a state detection unit capable of detecting a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential.

[0023] The soft start circuit generates the soft start voltage in response to the state detection unit detecting that the output voltage of the error amplifier circuit has recovered from a state exceeding a predetermined potential.

[0024] The soft-start circuit having the above-described configuration generates a soft-start voltage upon detecting that the output voltage of the error amplifier circuit has recovered from a state exceeding a predetermined potential. This soft-start voltage is used to control the conduction of the drive switching element, thereby gradually increasing the output voltage. This prevents overshoot of the output voltage when recovering from an abnormal state in which the output voltage has dropped.

[0025] Effects of the Invention

[0026] The soft-start circuit of the present invention can suppress output voltage overshoot when recovering from an abnormal output voltage drop. Furthermore, the DC-DC converter of the present invention has the following advantages: if the output voltage drops within the output low voltage detection delay time, output will not be stopped due to the detection of a low output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a circuit configuration diagram showing an embodiment in which the present invention is applied to a switching regulator type DC-DC converter.

[0028] Figure 2 This is a circuit configuration diagram showing a configuration example of a recovery circuit constituting a DC-DC converter according to an embodiment.

[0029] Figure 3 This is a timing chart showing changes in signals and potentials of various components when the FB voltage drops to a potential slightly higher than the low voltage detection level in the DC-DC converter according to the embodiment.

[0030] Figure 4 This is a timing chart showing changes in signals and potentials of various components when the FB voltage drops to a potential lower than the low voltage detection level in the DC-DC converter according to the embodiment.

[0031] Figure 5 This figure shows the relationship between the error amplifier output and the waveform signal (triangular wave), as well as the change in the PWM drive pulse, when the FB voltage in the DC-DC converter of the embodiment drops to a potential lower than the low-voltage detection level and then recovers. (A) is a timing diagram when the output current capability of the error amplifier is temporarily increased, and (B) is a timing diagram when the output current capability of the error amplifier is not temporarily increased.

[0032] Figure 6 This is a timing chart showing changes in signals and potentials of various components when the output voltage drops due to a temporary drop in input voltage in a conventional switching regulator-type DC-DC converter.

[0033] Figure 7This is a circuit diagram showing the structure of a DC-DC converter studied before the present invention, which has a function of preventing an output voltage overshoot after recovery from an output drop state. DETAILED DESCRIPTION

[0034] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0035] Figure 1 One embodiment of a DC-DC converter using a switching regulator method according to the present invention is shown.

[0036] This embodiment of the DC-DC converter includes: a coil L1 serving as an inductor; a driving switching transistor M1 comprised of an N-channel MOSFET (insulated gate field effect transistor), connected between a voltage input terminal IN, to which a DC input voltage VIN is applied, and one terminal of the coil L1, for supplying a driving current to the coil L1; and a rectifying switching transistor M2 comprised of an N-channel MOSFET, connected between one terminal of the coil L1 and a ground point. Furthermore, a smoothing capacitor C1 is connected between the other terminal of the coil L1 (output terminal OUT) and the ground point, and a stabilizing capacitor C0 is connected between the voltage input terminal IN and the ground point.

[0037] In addition, the DC-DC converter has: a switching control circuit 10, which generates a signal for controlling the on / off of the switching transistors M1 and M2; drive circuits DRV1 and DRV2, which drive the switching transistors M1 and M2 to be on / off according to the switching control signal generated by the control circuit 10; and an internal power supply circuit 20, which generates an operating voltage for the internal circuit according to the input voltage VIN.

[0038] Although not particularly limited, in this embodiment, the components constituting the switch control circuit 10 and the drive circuits DRV1 and DRV2, as well as the switching transistors M1 and M2, are formed on a single semiconductor chip to form a semiconductor integrated circuit (power supply control IC). Furthermore, the coil L1, capacitor C0, and smoothing capacitor C1 are connected as external components to external terminals provided on the power supply control IC.

[0039] In this embodiment of the DC-DC converter, drive circuits DRV1 and DRV2 generate drive pulses that complementarily turn switching transistors M1 and M2 on and off, applying them to the gate terminals of M1 and M2. In normal operation, when drive transistor M1 is on, a DC input voltage VIN is applied to coil L1, causing current to flow toward output terminal OUT and charging smoothing capacitor C1. Furthermore, when switching transistor M1 is off, rectifying switching transistor M2 is on, allowing current to flow toward coil L1 through the on-state transistor M2. Consequently, an output voltage VOUT of a predetermined potential is output from output terminal OUT.

[0040] The switching control circuit 10 includes: a voltage divider circuit 11, which is composed of resistors R1 and R2 connected in series between a terminal VO and a ground point, and the terminal VO is applied with a voltage VOUT output from the output terminal OUT; and an error amplifier 12, which receives a voltage VFB generated by the voltage divider circuit 11 and a reference voltage VREF1 as inputs and outputs a voltage corresponding to the potential difference between VFB and VREF1.

[0041] In addition, the switching control circuit 10 includes: a waveform generating circuit 13, which generates a waveform signal of a specified frequency such as a triangular wave; a PWM comparator 14, which compares the generated triangular wave with the output of the above-mentioned error amplifier 12 to generate a control pulse; and a logic circuit 15, which generates a signal for driving and controlling the above-mentioned drive circuits DRV1 and DRV2 based on the generated control pulse.

[0042] The switching control circuit 10 also includes a low-voltage protection circuit 16 that detects a low-voltage state (when the output voltage VOUT drops below a predetermined potential VLVP) based on the voltage VFB generated by the voltage divider circuit 11 and stops output; and a recovery circuit 17 that provides a soft-start function to prevent output overshoot and increase the output voltage VOUT when the output recovers from a low-voltage state. Furthermore, VLVP < VREF1. When the low-voltage protection circuit 16 detects a low-voltage state, it supplies a shutdown signal SD to the logic circuit 15, which then stops output by maintaining the drive switching transistor M1 and the rectifier transistor M2 in the off state.

[0043] The error amplifier 12 uses an amplifier having one inverting input terminal (-) and two non-inverting input terminals (+). The voltage VFB generated by the voltage divider circuit 11 is input to the inverting input terminal (-), the reference voltage VREF1 is applied to one non-inverting input terminal (+), and the other non-inverting input terminal (+) is connected to the recovery circuit 17.

[0044] The DC-DC converter power supply control IC of this embodiment includes an external terminal SS connected to an external capacitor C5 for setting the soft-start time. The recovery circuit 17 is connected to this terminal SS. Furthermore, capacitor C2 and resistor R3, connected in series between the output terminal of error amplifier 12 and ground, form a phase compensation circuit.

[0045] exist Figure 2 , a circuit configuration example of a specific example of the above-mentioned recovery circuit 17 is shown together with the error amplifier 12. Figure 2 In the illustrated structure, the circuit excluding the voltage divider circuit 11 and the error amplifier 12 is the recovery circuit 17 .

[0046] like Figure 2 As shown, the recovery circuit 17 includes an amplifier AMP1 for soft start and an amplifier AMP2 that forms a clamping circuit for clamping the output voltage of the error amplifier 12. The output of the error amplifier 12 is input to the non-inverting input terminal (+) of the amplifier AMP2, and a constant voltage VCLP that provides a clamping level is input to the inverting input terminal (-).

[0047] Furthermore, a MOS transistor M4 is connected between the output terminal of the error amplifier 12 and the ground point, and the output voltage of the amplifier AMP2 is applied to the gate terminal of M4. Consequently, when the output voltage of the error amplifier 12 exceeds the voltage VCLP, the amplifier AMP2 turns on the transistor M4, thereby clamping the voltage COMP supplied from the error amplifier 12 to the subsequent PWM comparator to the voltage VCLP. Thus, the amplifier AMP2 and the transistor M4 form a clamping circuit (referred to herein as the COMP clamping circuit) that clamps the output voltage of the error amplifier 12. Furthermore, VCLP > VREF1.

[0048] In addition, amplifier AMP2 also functions as a comparator that compares the output voltage of error amplifier 12 with voltage VCLP. When the output voltage of error amplifier 12 reaches voltage VCLP, the output signal of amplifier AMP2 rises, and this signal is fed back to error amplifier 12 and amplifier AMP1, turning the amplifier on and off.

[0049] To turn the error amplifier 12 on and off, a one-shot pulse generation circuit 18 is provided, which receives the output signal of the amplifier AMP2 as input. This circuit generates a one-shot pulse OSP with a predetermined pulse width in synchronization with the falling edge of the output signal of the amplifier AMP2. This pulse signal temporarily increases the output current capability of the error amplifier 12. This function can be achieved, for example, by providing two current sources for flowing the operating current of the error amplifier 12. In normal operation, only one current source is turned on, and when the one-shot pulse OSP is generated, the other current source is also turned on.

[0050] The soft-start amplifier AMP1 has one non-inverting input terminal (+) and two inverting input terminals (-). The non-inverting input terminal (+) is connected to the external terminal SS. The voltage VFB generated by the voltage divider circuit 11 is input to one inverting input terminal (-). The reference voltage VREF2 is applied to the other inverting input terminal (-). Furthermore, VLVP < VREF2 < VREF1.

[0051] Furthermore, a constant current source CC0 and a MOS transistor M3 are connected in series between the internal power supply voltage terminal VDD and the ground point, and a connection node N1 between the constant current source CC0 and the transistor M3 is connected to the external terminal SS.

[0052] Thus, when VFB < VREF2, amplifier AMP1 activates transistor M3 so that the voltage VSS at terminal SS matches VREF2, fixing VSS to VREF2. Furthermore, when VFB > VREF2, amplifier AMP1 activates transistor M3 so that the voltage VSS at terminal SS matches the output feedback voltage VFB, fixing VSS to VFB. Consequently, constant current source CC0, transistor M3, and amplifier AMP1 form a clamp circuit (referred to herein as the SS clamp circuit). Furthermore, the voltage VSS at terminal SS serves as a soft-start voltage for slowly increasing the output voltage when power is turned on.

[0053] Furthermore, the output signal of amplifier AMP2 of the COMP clamp circuit is supplied to amplifier AMP1 as an on / off control signal. Amplifier AMP1 operates only while the output signal of amplifier AMP2 is at a high level and the COMP clamp circuit is clamping the output of error amplifier 12. Thus, the SS clamp circuit and amplifier AMP2 of the COMP clamp circuit, which controls its operation, form a soft-start circuit. Furthermore, amplifier AMP2 functions as a state detection unit capable of detecting when the output voltage exceeds a predetermined potential.

[0054] On the other hand, the error amplifier 12 inputs the voltage VFB generated by the voltage divider circuit 11 to its inverting input terminal (-), inputs the voltage VSS of the external terminal SS to one of its two non-inverting input terminals (+), and applies the reference voltage VREF1 to the other non-inverting input terminal (+).

[0055] Thus, the error amplifier 12 operates to output a voltage corresponding to the potential difference between VFB and VREF1 when VSS>VREF1, and to output a voltage corresponding to the potential difference between VFB and VSS when VSS<VREF1.

[0056] In addition, Figure 2 In the circuit, the capacitor C3 is connected between the output terminal of the amplifier AMP1 and the ground point, and the capacitor C4 is connected between the output terminal of the amplifier AMP2 and the ground point.

[0057] Next, use Figures 3 to 5 The timing chart of FIG. 1 illustrates the operation of the recovery circuit 17 when an abnormal state occurs in which the output voltage VOUT decreases and VOUT recovers thereafter.

[0058] also, Figure 3 1 shows changes in signals and potentials of various components when the FB voltage drops to a potential slightly higher than the reference voltage VREF2 in the DC-DC converter of this embodiment. Figure 4 The diagram shows changes in signals and potentials of various components when the FB voltage drops to a potential lower than the low voltage detection level VLVP.

[0059] In the PWM DC-DC converter, as described above, when the output voltage VOUT drops significantly, the output voltage COMP of the error amplifier 12 rises above the maximum voltage of the triangular wave signal RAMP, and the output voltage cannot be controlled. Figure 2 ), when the COMP voltage rises above the clamp voltage VCLP of the amplifier AMP2, the mode is entered in which the voltage VSS of the SS terminal is controlled according to the voltage VFB obtained by dividing the output voltage VOUT.

[0060] At this time, if VREF2 ≤ VFB < VREF1, the voltage VSS of the SS terminal is controlled by the amplifier AMP1 of the SS clamp circuit so that VSS = VFB. On the other hand, if VFB < VREF2, the voltage VSS is controlled so that VSS = VREF2 voltage.

[0061] like Figure 3As shown, when the FB voltage VFB drops to a reference voltage VREF2 (e.g., 0.8V) or slightly higher, the output voltage COMP of the error amplifier 12 rises as VFB decreases. When COMP rises to the clamp voltage VCLP (e.g., 1.6V) (timing: t1), amplifier AMP2 of the COMP clamp circuit clamps COMP to COMP = VCLP. Furthermore, at this time, the output (ON / OFF) of amplifier AMP2 goes high, activating amplifier AMP1 of the SS clamp circuit. Transistor M3 turns on, draining charge from capacitor C5 and rapidly dropping the voltage VSS at the SS terminal to VSS = VFB.

[0062] Then, when the abnormal condition (low output voltage) is resolved and FB voltage VFB begins to rise, error amplifier 12 outputs a voltage corresponding to the potential difference between VFB and VSS. This causes COMP to fall, and the subsequent PWM comparator begins generating duty-cycle-controlled pulses, causing output voltages VOUT and VFB to rise. Consequently, the output (ON / OFF) of amplifier AMP2 in the COMP clamp circuit changes to a low level, and amplifier AMP1 in the SS clamp circuit ceases operation (timing: t2).

[0063] As a result, transistor M3 is turned off, and external capacitor C5 at the SS terminal is charged, causing voltage VSS to rise. Furthermore, after VFB begins to rise, VFB temporarily rises above VSS because voltage COMP decreases, preventing the immediate output of a signal for controlling the duty cycle of the drive pulse corresponding to the input-output voltage difference.

[0064] Then, when VFB gradually rises and reaches VREF1 (e.g., 1.2V), the error amplifier 12 outputs a voltage corresponding to the potential difference between VFB and VREF1, thereby controlling the output voltage VOUT to a predetermined set voltage. Furthermore, after timing t3, when the output voltage VOUT reaches the predetermined voltage, the operation of the amplifier AMP1 also ceases, and the transistor M3 turns off. Therefore, the voltage VSS at the SS terminal continues to rise. At timing t4, when the external capacitor C5 at the SS terminal is fully charged, the voltage is then maintained constant.

[0065] like Figure 4As shown, when voltage VFB drops below low voltage detection level VLVP (e.g., 0.4V) and then recovers, the output voltage COMP of error amplifier 12 rises as FB voltage VFB decreases. Amplifier AMP2 of the COMP clamp circuit clamps COMP to COMP = VCLP (timing: t1). Furthermore, at this time, the output of amplifier AMP2 goes high, activating amplifier AMP1 of the SS clamp circuit. Transistor M3 turns on, draining charge from capacitor C5 and rapidly decreasing voltage VSS at the SS terminal, clamping it to VSS = VREF2.

[0066] After that, at timing t2, when the abnormal state (low voltage state of the output) is eliminated and the system recovers, VFB temporarily rises until the output voltage reaches VFB>VSS, and then Figure 3 In the same manner as in the case of , VFB rises slowly. At this time, if the rise of VFB takes time, the low voltage protection circuit 16 may detect a low voltage state and stop outputting.

[0067] Here, regarding the condition under which the low-voltage protection circuit 16 fails to detect the low-voltage state, if the period between timing t1 and t2 is set to T1 and the delay time of the low-voltage protection circuit 16 is set to TDLY (e.g., 1.0 ms), T1 < TDLY. Therefore, in the DC-DC converter of this embodiment, VFB is temporarily increased to VREF2 after the low-voltage state is released, thereby failing to detect the low-voltage state.

[0068] This shortens T1, preventing the low-voltage protection circuit 16 from detecting a low-voltage state, and allows normal operation to resume without stopping output. Furthermore, by temporarily increasing the output current capability of the error amplifier 12, the time it takes for the error amplifier 12 output COMP to drop to a level capable of controlling the output voltage (a level lower than the maximum value of the triangular wave signal input to the PWM comparator) can be shortened. This improves the responsiveness of the PWM comparator's duty cycle control and prevents overshoot of the output voltage.

[0069] Figure 5 (A) shows the relationship between the output COMP of the error amplifier 12 and the waveform signal (triangular wave) RAMP, and the change in the PWM drive pulse when the FB voltage proportional to the output voltage VOUT drops to a potential lower than the low voltage detection level VLVP and then recovers in the DC-DC converter of this embodiment. In addition, Figure 5 (B) shows the relationship between the output COMP of the error amplifier 12 and the waveform signal (triangular wave) RAMP and the change of the PWM drive pulse when the output current capability of the error amplifier 12 is not temporarily increased after the low voltage state is released. Figure 5Comparing (A) and (B), it can be seen that in the DC-DC converter of this embodiment in which the output current capability of the error amplifier 12 is temporarily increased, the time T2 required for the output COMP of the error amplifier 12 to drop to a level that enables appropriate duty cycle control can be shortened.

[0070] While the invention developed by the present inventors has been specifically described above based on embodiments, the present invention is not limited to the aforementioned embodiments. For example, in the aforementioned embodiments, the output of amplifier AMP1, which constitutes the SS clamp circuit, is input to the gate terminal of transistor M3, which is connected in series with constant current source CC0, which constitutes the soft-start circuit. However, if the IC has an external terminal (chip enable terminal) for inputting an enable signal for activating the IC, a signal that is a logical sum of the output of amplifier AMP1 and the signal at the enable terminal may be input to the gate terminal of transistor M3.

[0071] In the above embodiment, the low voltage protection circuit 16 detects the low voltage state of the output voltage based on the feedback voltage VFB. However, the low voltage state of the output voltage may be detected by directly monitoring the output voltage.

[0072] In the above embodiment, the transistors M1 and M2 are on-chip elements, but they may be configured as external elements in an IC.

[0073] Furthermore, in the description of the above-mentioned embodiment, an example of applying the present invention to a step-down DC-DC converter is described, but the present invention is not limited to this. The soft start circuit, etc. can also be applied to a step-up type or an inverter type DC-DC converter that generates a negative voltage, as well as a linear regulator, etc.

[0074] Explanation of symbols

[0075] 10…Switch control circuit, 11…Voltage divider circuit, 12…Error amplifier, 13…Waveform generation circuit, 14…PWM comparator (state detection unit), 15…Logic circuit, 16…Low voltage protection circuit, 17…Recovery circuit, 18…One-shot pulse generation circuit, DRV1, DRV2…Drive circuit, M1…Drive switching transistor (Drive switching element), M2…Synchronous rectification switching transistor (Rectification switching element), AMP1…Amplifier constituting the soft-start circuit, AMP2…Amplifier constituting the clamp circuit.

Claims

1. A soft start circuit in a DC power supply device, the DC power supply device comprising: an error amplifier circuit receiving a feedback voltage corresponding to an output voltage and a predetermined first reference voltage as input; a drive switching element disposed between a voltage input terminal and a voltage output terminal; and a control circuit controlling the drive switching element based on the output of the error amplifier circuit, wherein the soft start circuit generates a soft start voltage for controlling the drive switching element to turn on when the voltage at the voltage input terminal rises, wherein: The soft start circuit includes a state detection unit capable of detecting a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential. The soft start circuit generates the soft start voltage in response to the state detection unit detecting that the output voltage of the error amplifier circuit has recovered from a state exceeding a predetermined potential.

2. The soft start circuit according to claim 1, characterized in that: The state detection unit is a clamp circuit that clamps the output voltage of the error amplifier circuit to a predetermined potential when the output voltage of the error amplifier circuit reaches a predetermined potential.

3. The soft start circuit according to claim 2, characterized in that: The soft start circuit comprises: a constant current source; a capacitor charged by the current of the constant current source; a transistor for discharging the charge of the capacitor; and a differential amplifier circuit having as inputs the charging voltage of the capacitor, the feedback voltage, and a second reference voltage lower than the first reference voltage, The charging voltage of the capacitor is input to the error amplifier circuit. The differential amplifier circuit is configured to control the transistor so that the charging voltage of the capacitor is consistent with the feedback voltage when the feedback voltage drops to near the second reference voltage, and to control the transistor so that the charging voltage of the capacitor is consistent with the second reference voltage when the feedback voltage drops below the second reference voltage.

4. A DC-DC converter comprising: an error amplifier circuit having a feedback voltage corresponding to an output voltage and a predetermined first reference voltage as inputs; a drive switching element disposed between a voltage input terminal and a voltage output terminal; a control circuit for controlling the drive switching element based on the output of the error amplifier circuit; and a soft-start circuit for generating a soft-start voltage for controlling the drive switching element to turn on when the voltage at the voltage input terminal rises, wherein: The DC-DC converter includes a state detection unit capable of detecting a state in which the output voltage of the error amplifier circuit exceeds a predetermined potential, and the soft start circuit generates the soft start voltage in response to the state detection unit detecting that the output voltage of the error amplifier circuit has recovered from a state in which the output voltage has exceeded the predetermined potential.

5. The DC-DC converter according to claim 4, wherein: The state detection unit is a clamp circuit that clamps the output voltage of the error amplifier circuit to a predetermined potential when the output voltage of the error amplifier circuit reaches a predetermined potential.

6. The DC-DC converter according to claim 5, wherein: The soft start circuit comprises: a constant current source; a capacitor charged by the current of the constant current source; and a transistor for discharging the charge of the capacitor. and a differential amplifier circuit having as inputs the charging voltage of the capacitor, the feedback voltage, and a second reference voltage lower than the first reference voltage, The charging voltage of the capacitor is input to the error amplifier circuit. The differential amplifier circuit is configured such that when the feedback voltage drops to near the second reference voltage, the transistor is controlled so that the charging voltage of the capacitor is consistent with the feedback voltage; and when the feedback voltage drops below the second reference voltage, the transistor is controlled so that the charging voltage of the capacitor is consistent with the second reference voltage.

7. The DC-DC converter according to claim 6, wherein: The differential amplifier circuit is configured to operate only while the output voltage of the error amplifier circuit reaches a predetermined potential and the state detection unit fixes the output voltage of the error amplifier circuit at the predetermined potential.

8. The DC-DC converter according to claim 7, wherein: The error amplifier circuit is configured to take the charging voltage of the capacitor, the feedback voltage, and the first reference voltage as inputs, and output a voltage corresponding to the difference between the feedback voltage and the first reference voltage when the feedback voltage is higher than the first reference voltage, and output a voltage corresponding to the difference between the feedback voltage and the charging voltage of the capacitor when the feedback voltage is lower than the first reference voltage.

9. The DC-DC converter according to claim 8, wherein: The state detection unit is configured to temporarily increase the output current capability of the error amplifier circuit after the output voltage of the error amplifier circuit reaches a predetermined potential and fixes the output voltage of the error amplifier circuit at the predetermined potential, and after the output voltage of the error amplifier circuit falls below the predetermined potential.

10. The DC-DC converter according to any one of claims 4 to 9, characterized in that: The control circuit includes a PWM comparator that compares the output voltage of the error amplifier circuit with a waveform signal of a predetermined period and generates a duty-controlled pulse signal for turning on and off the driving switching element. and a low voltage detection circuit that detects a low voltage state in which the output voltage is lower than a specified voltage based on the feedback voltage or the output voltage. The control circuit is configured to fix the driving switching element in an off state and stop the output based on the low voltage state detected by the low voltage detection circuit.

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