Broadband signal parallel column path real-time processing method realized based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a broadband signal parallel column path real-time processing method based on an FPGA (Field Programmable Gate Array), belongs to the field of digital signal processing, and comprehensively considers an ADC (Analog to Digital Converter) system which is based on JESD204B, JESD204C and RFSoC architectures and has a sampling rate up to several GHz. In order to solve the difficult problem of speed reduction processing of high-speed and high-throughput data in an FPGA, the difficult problem of real-time processing of high-speed multi-column data and the difficult problem of effective acquisition of broadband signals, broadband real-time spectrum processing is carried out by adopting an adaptive mixed base optimization method, three parallel FFT processing structures of radix-2 parallel FFT, radix-4 parallel FFT and radix-8 parallel FFT are adopted, and the real-time acquisition of the broadband signals is realized by adopting three parallel FFT processing structures of the radix-2 parallel FFT, the radix-4 parallel FFT and the radix-8 parallel FFT. The method is suitable for efficient calculation under FPGA optimal resources under different processing lengths, has the advantages of being low in delay, high in throughput, customizable and the like, and effectively meets the requirement for broadband signal real-time spectrum processing.

Description

Technical Field

[0001] The invention belongs to the field of digital signal processing, and in particular relates to a broadband signal parallel column real-time processing method based on FPGA. Background Art

[0002] In the application field of broadband signal monitoring, when the real-time processing bandwidth reaches above 2 GHz, the signal sampling rate often reaches above 4 GHz. The amount of digital signal data obtained by high-speed sampling can reach nearly 100 Gbps. How to receive, effectively process and reasonably analyze such a large amount of data in real time is a difficult problem faced by broadband high-speed systems.

[0003] Existing solutions include some that focus on signal processing system hardware design, such as the ADC+FPGA+DSP multi-processor hardware system design method. While these approaches involve broadband signal processing, they are based on hardware architectures and lack the ability for flexible multi-path parallel processing, making them incapable of adapting to high-speed processing requirements exceeding GHz. Other solutions focus on signal processing flows or algorithms, including those involving FPGA processing, ARM processing, DSP processing, or host computer software processing. These algorithms are single-flow and lack the concept of parallel multi-path processing of broadband signals. Their architecture is simplistic and incapable of addressing the real-time processing of high-speed, high-throughput data. Current solutions fail to address the challenges of FPGA processing speed reduction and real-time processing of high-speed, high-throughput data during high-speed acquisition. Summary of the Invention

[0004] In view of the above problems existing in the prior art, the present invention proposes a real-time processing method for parallel columns of broadband signals based on FPGA, which has a reasonable design, solves the shortcomings of the prior art and has good effects.

[0005] The method for real-time processing of broadband signal parallel columns based on FPGA includes the following steps:

[0006] Step 1: For an acquisition system with an ADC sampling rate of fs and a sampling accuracy of b bits, after receiving the sampled data, the FPGA performs parallel column data reorganization and mapping based on the ADC architecture and ADC output data protocol, and then proceeds to step 2.

[0007] Step 2: Based on the ADC architecture and ADC output data protocol, determine the number of multi-link parallel output data samples N1 and the data synchronization rate f1, and proceed to step 3;

[0008] Step 3: Configure the dual-port RAM so that port A of the dual-port RAM is the data write port and port B is the data read port. The data bandwidth of port A is B1, and the data clock of port A is f1; the data width of port B is B2, the data rate is f2, and the number of single output samples is N. Go to step 4.

[0009] Step 4: Implement adaptive optimization judgment. Assume that the number of points for implementing FFT of the real-time spectrum of the broadband signal within the sampling frequency range of fs is L, and the number of points for implementing parallel FFT of the nth parallel column is L. n , n=1,…,N; when implementing radix-8 parallel FFT, proceed to step 5; when implementing radix-4 parallel FFT, proceed to step 10; when implementing radix-2 parallel FFT, proceed to step 15;

[0010] Step 5: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 6;

[0011] Step 6: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 7;

[0012] Step 7: Based on the adaptive optimization judgment, N=8 m The value of m is: let m1 = m. When m1 > 1, multi-level radix-8 disk operations are required. Let N2 = N for the number of parallel disk paths, and go to step 8.

[0013] Step 8: Set X0, X 1, ,…,X N2-1 Divide the sequence into N2 / 8 subsequence groups using N2 mod 8, and perform N2 / 8 radix-8 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 8, and proceed to step 9.

[0014] Step 9: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 8 to perform N2-way N / N2-point reduced radix-8 disk operations. If m1 is equal to 1, complete one-way N-point radix-8 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 5 and perform the next operation until the process stops and returns to step 1.

[0015] Step 10: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 11;

[0016] Step 11: Real-time parallel calculation of N L nDFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 12;

[0017] Step 12: Based on the adaptive optimization judgment, N=4 m Where m is the value of the disk operation. Let m1 = m. When m1 > 1, multi-stage radix-4 disk operation is required. Let N2 = N for the number of parallel disk operations. Then go to step 13.

[0018] Step 13: Set X0, X 1, ,…,X N2-1 Divide the sequence into N2 / 4 subsequences using N2 mod 4, and perform N2 / 4 radix-4 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 4, and proceed to step 14.

[0019] Step 14: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 13 to perform N2-way N / N2-point reduced radix-4 disk operations. If m1 is equal to 1, complete one-way N-point radix-4 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 10 and perform the next operation until the process stops and returns to step 1.

[0020] Step 15: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 16;

[0021] Step 16: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 17;

[0022] Step 17: Based on the adaptive optimization decision, N=2 m Where m is the value of the disk operation. Let m1 = m. When m1 > 1, multiple radix-2 disk operations are required. Let N2 = N for the number of parallel disk operations. Then go to step 18.

[0023] Step 18: Set X0, X 1, ,…,X N2-1 Divide the sequence into N2 / 2 subsequences using N2 mod 2, and perform N2 / 2 radix-2 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 2, and proceed to step 19.

[0024] Step 19: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 18 to perform N2-way, N / N2-point, degraded radix-2 disk operations. If m1 is equal to 1, complete one-way, N-point radix-2 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 15 and perform the next operation until the process stops and returns to step 1.

[0025] Furthermore, in step 1, the parallel column data reorganization mapping is to rearrange and map the multi-link data according to the protocol agreement, using the assignment method to re-arrange the N1 point sampling data in step 2 from low to high according to the data width B1 in step 3 and the sampling order.

[0026] Furthermore, in step 2, the data synchronization rate The number N1 of data sample points outputted in parallel by multiple columns is determined by the specific ADC used according to the ADC architecture system and the specific form of the ADC output data protocol.

[0027] Furthermore, in step 3, the data bandwidth of port A is B1=b×N1, the data bandwidth of port B is B2=b×N, and the RAM output data rate is

[0028] Furthermore, in step 4, the number of points L of the FFT of the broadband signal real-time spectrum is determined according to the signal resolution index, and the signal resolution is equal to

[0029] The number of points for parallel FFT in each column L n The length of is associated and implemented according to the determination of N in the adaptive optimization judgment.

[0030] Furthermore, in step 4, the adaptive optimization judgment is specifically as follows: when N=8 m When N=4, radix-8 parallel FFT is implemented. m When N=2, a radix-4 parallel FFT is implemented. m When N=8, implement radix-2 parallel FFT, m is a positive integer; m N = 4 m 、N=2 m When all conditions are met, or two of them are met, the one with the higher cardinality is preferred, and the broadband signal spectrum operation is preferably performed with the highest computational efficiency.

[0031] Furthermore, the radix-8 butterfly operation in steps 5 to 9 has the following operation rules:

[0032]

[0033] Among them, a,…,g are the power coefficients of the 8th root of unity, and the rotation factors

[0034] Furthermore, the radix-4 butterfly operation in steps 10 to 14 has the following operation rules:

[0035]

[0036] Among them, the rotation factor

[0037] Furthermore, the radix-2 butterfly operation in steps 15 to 19 has the following operation rules:

[0038]

[0039] Among them, the rotation factor

[0040] Furthermore, the sampling accuracy in step 1 is b bits, and in the case of IQ complex numbers, the bit width is doubled.

[0041] Beneficial technical effects brought about by the present invention:

[0042] The present invention proposes a method for parallel processing of broadband signals suitable for high-speed ADC sampling. This method effectively addresses the difficulty of slowing down high-speed data sampled at several GHz in FPGAs. The method is compatible with a variety of high-speed ADC systems and adapts to different transmission protocols, providing a path for real-time processing of broadband signals. The parallel column path utilizes an adaptive hybrid basis optimization method to optimize FPGA resource allocation, load balancing, and effectively improve computational efficiency. This FPGA-based parallel column path processing method offers low latency, high throughput, and customizability, effectively addressing the need for real-time broadband signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 This is the functional block diagram of the JESD204B and JESD204C system ADC;

[0044] Figure 2 This is a functional diagram of the RF-ADC Tile;

[0045] Figure 3 This is a timing diagram of the ADC data stream;

[0046] Figure 4 Schematic diagram of the parallel column real-time processing method of the present invention;

[0047] Figure 5 This is a diagram of the JESD204 protocol packet data reassembly and mapping process;

[0048] Figure 6Schematic diagram of the RFSoC protocol packet data reassembly and mapping process;

[0049] Figure 7 This is a diagram of the Block RAM configuration interface; DETAILED DESCRIPTION

[0050] The specific implementation of the present invention will be further described below with reference to specific embodiments:

[0051] This FPGA-based real-time parallel column processing method for broadband signals takes into account the current mainstream ADC systems with sampling rates up to several GHz based on JESD204B, JESD204C, and RFSoC architectures. It aims to address the challenges of processing high-speed, high-throughput data at reduced speeds in FPGAs, the real-time processing of high-speed, multi-column data, and the effective capture of broadband signals. The method includes the following steps:

[0052] Step 1: For an acquisition system with an ADC sampling rate of fs and a sampling accuracy of b bits, after receiving the sampled data, the FPGA performs parallel column data reorganization and mapping based on the ADC architecture and ADC output data protocol, and then proceeds to step 2.

[0053] Step 2: Based on the ADC architecture and ADC output data protocol, determine the number of multi-link parallel output data samples N1 and the data synchronization rate f1, and proceed to step 3;

[0054] Step 3: Configure the dual-port RAM so that port A of the dual-port RAM is the data write port and port B is the data read port. The data bandwidth of port A is B1, and the data clock of port A is f1; the data width of port B is B2, the data rate is f2, and the number of single output samples is N. Go to step 4.

[0055] Step 4: Implement adaptive optimization judgment. Assume that the number of points for implementing FFT of the real-time spectrum of the broadband signal within the sampling frequency range of fs is L, and the number of points for implementing parallel FFT of the nth parallel column is L. n , n=1,…,N; when implementing radix-8 parallel FFT, proceed to step 5; when implementing radix-4 parallel FFT, proceed to step 10; when implementing radix-2 parallel FFT, proceed to step 15;

[0056] Step 5: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 6;

[0057] Step 6: Real-time parallel calculation of N L nDFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 7;

[0058] Step 7: Based on the adaptive optimization judgment, N=8 m The value of m is: let m1 = m. When m1 > 1, multi-level radix-8 disk operations are required. Let N2 = N for the number of parallel disk paths, and go to step 8.

[0059] Step 8: Set X0, X 1, ,…,X N2-1 Divide into N2 / 8 subsequence groups by N2 mod 8, that is, first X0,X 1, ,…,X N2-1 Divide the sequence into 8 groups in sequence, take the jth subsequence from each group to form the jth subsequence group, and finally obtain N2 / 8 subsequence groups; calculate N2 / 8 radix-8 butterfly operations in parallel, set m1=m1-1, N2=N2 / 8, and go to step 9;

[0060] Step 9: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 8 to perform N2-way N / N2-point reduced radix-8 disk operations. If m1 is equal to 1, complete one-way N-point radix-8 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 5 and perform the next operation until the process stops and returns to step 1.

[0061] Step 10: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 11;

[0062] Step 11: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 12;

[0063] Step 12: Based on the adaptive optimization judgment, N=4 m Where m is the value of the disk operation. Let m1 = m. When m1 > 1, multi-stage radix-4 disk operation is required. Let N2 = N for the number of parallel disk operations. Then go to step 13.

[0064] Step 13: Set X0, X 1, ,…,X N2-1Divide the sequence into N2 / 4 subsequences using N2 mod 4, and perform N2 / 4 radix-4 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 4, and proceed to step 14.

[0065] Step 14: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 13 to perform N2-way N / N2-point reduced radix-4 disk operations. If m1 is equal to 1, complete one-way N-point radix-4 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 10 and perform the next operation until the process stops and returns to step 1.

[0066] Step 15: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 16;

[0067] Step 16: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 17;

[0068] Step 17: Based on the adaptive optimization decision, N=2 m Where m is the value of the disk operation. Let m1 = m. When m1 > 1, multiple radix-2 disk operations are required. Let N2 = N for the number of parallel disk operations. Then go to step 18.

[0069] Step 18: Set X0, X 1, ,…,X N2-1 Divide the sequence into N2 / 2 subsequences using N2 mod 2, and perform N2 / 2 radix-2 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 2, and proceed to step 19.

[0070] Step 19: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 18 to perform N2-way, N / N2-point, degraded radix-2 disk operations. If m1 is equal to 1, complete one-way, N-point radix-2 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 15 and perform the next operation until the process stops and returns to step 1.

[0071] In step 1, parallel column data reorganization and mapping is to re-arrange and map the multi-link data according to the protocol agreement, using the assignment method to re-arrange the N1 point sampling data in step 2 according to the data width B1 in step 3 and the sampling order from low to high.

[0072] In step 2, the data synchronization rate The number N1 of data sample points outputted in parallel by multiple columns is determined by the specific ADC used according to the ADC architecture system and the specific form of the ADC output data protocol.

[0073] In step 3, the data bandwidth of port A is B1=b×N1, the data width of port B is B2=b×N, and the RAM output data rate is

[0074] In step 4, the number of points L for performing FFT on the real-time spectrum of the broadband signal is determined based on the signal resolution index, which is equal to

[0075] The number of points for parallel FFT in each column L n The length of is associated and implemented according to the determination of N in the adaptive optimization judgment.

[0076] In step 4, the adaptive optimization judgment is specifically as follows: when N=8 m When N=4, radix-8 parallel FFT is implemented. m When N=2, a radix-4 parallel FFT is implemented. m When N=8, implement radix-2 parallel FFT, m is a positive integer; m N = 4 m 、N=2 m When all conditions are met, or two of them are met, the one with the higher cardinality is preferred, and the broadband signal spectrum operation is preferably performed with the highest computational efficiency.

[0077] The radix-8 butterfly operation in steps 5 to 9 has the following operation rules:

[0078]

[0079] Among them, a,…,g are the power coefficients of the 8th root of unity, and the rotation factors

[0080] The radix-4 butterfly operation in steps 10 to 14 has the following operation rules:

[0081]

[0082] Among them, the rotation factor

[0083] The radix-2 butterfly operation in steps 15 to 19 has the following operation rules:

[0084]

[0085] Among them, the rotation factor

[0086] The sampling accuracy described in step 1 is b bits. In the case of IQ complex numbers, the bit width is doubled.

[0087] Example

[0088] Currently, the mainstream high-speed ADCs operating above several GHz are based on JESD204B, JESD204C, or RFSoC architectures. JESD204B and JESD204C ADCs are traditional ADCs, transmitting up to tens of Gbps of sampled data via the JESD204B or JESD204C architecture protocols to an FPGA for processing. RFSoC ADCs, on the other hand, are a new hardware-based architecture that integrates the ADC IP core into the SoC, directly transmitting up to tens of Gbps of sampled data via a parallel port to the FPGA logic. Regardless of the ADC architecture, to transmit tens of Gbps of data to back-end processing, multiple columns of parallel outputs are used to reduce the data speed. The specific implementation is described below.

[0089] JESD204B and JESD204C ADCs and FPGAs are independent hardware units. The JESD204B and JESD204C architecture protocols are used to transmit sampled data between the ADC and FPGA. Figure 1 As shown in the figure, it is the ADC functional block diagram. After the broadband analog signal is sampled by the high-speed ADC, it is encapsulated inside the ADC using the JESD204B or JESD204C protocol and output to the FPGA via a x8 or x16 link.

[0090] Table 1 shows the format of link data packets encapsulated within the ADC using the JESD204B and JESD204C protocols. This is a x8 link, using 8B / 10B encoding. With a sampling accuracy of 12 bits, each link is encapsulated at 64 bits. Through parallel transmission and processing over the x8 links, data processing can be reduced by a factor of 40.

[0091] Table 1

[0092]

[0093] Table 2 shows the format of link data packets encapsulated within the ADC using the JESD204B and JESD204C protocols. This format uses a x16 link with 8B / 10B encoding. With a sampling accuracy of 12 bits, each link is encapsulated at 64 bits. Parallel transmission over the x16 links reduces data processing speed by a factor of 80.

[0094] Table 2

[0095]

[0096] In RFSoC architecture devices, ADC is integrated into SoC as a dedicated module RF-ADC. It uses dedicated banks and dedicated pins to interconnect with external analog signals and clock signals, such as Figure 2 As shown, RFSoC has 8-channel ADC acquisition function. Inside the RF-ADC IP, the ADC core is organized in the form of tiles. According to the bank division, each dedicated bank is divided into a tile. Each tile includes the configuration management of 2 ADC channels. For each tile, it shares a sampling input clock. When the tile output clock matches, theoretically, the two ADC cores in a tile can be configured with different functions separately. However, in actual use, RF-ADC is generally used in multi-channel parallel acquisition, so in general, the two ADC cores in each tile are configured consistently. The tile function of RF-ADC is shown in the figure below. Figure 2 shown.

[0097] Since the ADC core unit and FPGA are integrated into a SoC, the ADC high-speed sampling data can be transmitted to the FPGA in a parallel link through the onboard AXI Stream Data bus. Figure 3 The output format is RF-ADC data stream, and its output data is 128 bits wide. It can output ADC data or IQ data separately, each data is 16 bits. After 128-bit parallel transmission processing, the data processing speed can be reduced by 8 times.

[0098] The idea of ​​the method of the present invention is to implement parallel column data reorganization mapping in FPGA after ADC sampling data is acquired, in order to adapt to the mechanism of multi-link transmission of high-speed ADC sampling data. First, the data reorganization mapping of high-speed sampling encoded according to the transmission mode is converted into data suitable for the back-end rate matching and the parallel processing sequence requirements for adaptive hybrid base optimization implementation. The FPGA large-capacity dual-port RAM is used to complete the caching of high-speed sampling data and the reading of data for back-end adaptive processing. The RAM cache input data rate and data width can be flexibly configured according to the front-end ADC transmission protocol mode and the data stream encoding arrangement mode. The adaptive data reading rate and data bandwidth can be flexibly configured according to the back-end adaptive optimization processing requirements. Parallel column data reorganization mapping and data caching processing effectively solve the problem of high-speed data sampled up to several GHz in FPGA for speed reduction processing and matching of back-end processing, such as Figure 4 shown.

[0099] Parallel column data reorganization and mapping is to rearrange and map the sampled data in the protocol packet from low to high according to the protocol agreement using the assignment method. Assuming the sampling accuracy is b, and the sample point data of a protocol packet is N1, the data width after parallel column data reorganization and mapping is B1 = b × N1. The JESD204B and JESD204C architecture ADC JMODE 0 protocol packet mapping is as follows: Figure 5 As shown, the mapping process of other packets is similar.

[0100] For RFSoC architecture ADC protocol packet mapping Figure 6 As shown, its output is IQ format data. The real data is similar to the JESD204 protocol mapping process above. IQ format data can combine I-channel and Q-channel data into one piece and double the bit width. The mapping process of other packets is similar.

[0101] In FPGA, the present invention uses dual-port RAM to implement sampling data caching and matching between the front-end data rate of acquisition and the back-end parallel processing data rate. Taking Xilinx Ultrascale Ku series FPGA as an example, the maximum configurable data port width of its Block RAM is 4608 bits, which far exceeds the width requirement of the application in the present invention and meets the use requirements of the method of the present invention. Its IP configuration interface is as follows: Figure 7 After the high-speed parallel column sampling data is reorganized and mapped, the dual-port RAM can be configured so that port A of the dual-port RAM is the data write port and port B is the data read port. The data bandwidth of port A is B1, which is the total data width after the sampling data is reorganized and mapped. The data clock of port A is f1, which is at the sampling rate fs.

[0102] Assume that the data width of the dual-port RAM data readout port B is B2, the data rate is f2, and the number of single output samples is N, then B2=N×b, N is also the number of parallel columns processed in the backend. Assume that the number of points for implementing FFT on the real-time spectrum of the broadband signal within the sampling frequency range of fs is L, then the number of points for implementing parallel FFT on each of the N parallel columns is The back-end uses an adaptive hybrid radix optimization method to process broadband real-time spectrum, using three parallel FFT processing structures: radix-2 parallel FFT, radix-4 parallel FFT, and radix-8 parallel FFT. It adapts to efficient calculations under FPGA optimal resources under different processing lengths, has the characteristics of low latency, high throughput, and customizability, and effectively solves the needs of broadband signal real-time spectrum processing. The basis and method of adaptive optimization judgment are: preferably, when N=8 m When N=4, implement radix-8 parallel FFT; when N=4 m When N=2, implement radix-4 parallel FFT;m When N=8, implement radix-2 parallel FFT; when N=8 m N = 4 m 、N=2 m When all of them are satisfied, or two of them are satisfied, the one with the higher cardinality is preferred, and the broadband signal spectrum operation is preferably performed with the highest computational efficiency; in the above equation, m is a positive integer; here, when m is greater than 1, it is necessary to complete m-level disk operations, and finally the results are combined and output.

[0103] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by technicians in this technical field within the essential scope of the present invention should also fall within the scope of protection of the present invention.

Claims

1. A real-time processing method for parallel column paths of broadband signals based on FPGA, characterized in that: The following steps are involved: Step 1: For an acquisition system with an ADC sampling rate of fs and a sampling accuracy of b bits, after receiving the sampled data, the FPGA performs parallel column data reorganization and mapping based on the ADC architecture and ADC output data protocol, and then proceeds to step 2. Step 2: Based on the ADC architecture and ADC output data protocol, determine the number of multi-link parallel output data samples N1 and the data synchronization rate f1, and proceed to step 3; Step 3: Configure the dual-port RAM so that port A of the dual-port RAM is the data write port and port B is the data read port. The data bandwidth of port A is B1, and the data clock of port A is f1; the data width of port B is B2, the data rate is f2, and the number of single output samples is N. Go to step 4. Step 4: Implement adaptive optimization judgment. Assume that the number of points for implementing FFT of the real-time spectrum of the broadband signal within the sampling frequency range of fs is L, and the number of points for implementing parallel FFT of the nth parallel column is L. n , n=1,…,N; when implementing radix-8 parallel FFT, proceed to step 5; when implementing radix-4 parallel FFT, proceed to step 10; when implementing radix-2 parallel FFT, proceed to step 15; Step 5: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 6; Step 6: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 7; Step 7: Based on the adaptive optimization judgment, N=8 m The value of m is: let m1 = m. When m1 > 1, multi-level radix-8 disk operations are required. Let N2 = N for the number of parallel disk paths, and go to step 8. Step 8: Set X0, X 1, ,…,X N2-1 Divide the sequence into N2 / 8 subsequence groups using N2 mod 8, and perform N2 / 8 radix-8 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 8, and proceed to step 9. Step 9: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 8 to perform N2-way N / N2-point reduced radix-8 disk operations. If m1 is equal to 1, complete one-way N-point radix-8 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 5 and perform the next operation until the process stops and returns to step 1. Step 10: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 11; Step 11: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 12; Step 12: Based on the adaptive optimization judgment, N=4 m The value of m is set as m1 = m. When m1 > 1, multi-level radix-4 disk operations are required. Set the number of parallel disk paths N2 = N and proceed to step 13. Step 13: Set X0, X 1, ,…,X N2-1 Divide the sequence into N2 / 4 subsequences using N2 mod 4, and perform N2 / 4 radix-4 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 4, and proceed to step 14. Step 14: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 13 to perform N2-way N / N2-point reduced radix-4 disk operations. If m1 is equal to 1, complete one-way N-point radix-4 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 10 and perform the next operation until the process stops and returns to step 1. Step 15: Divide the N columns of sample data stream output at data rate f2 into N subsequences: x0[k], x1[k], …, x N-1 [k], k=0,1,…,L n -1, go to step 16; Step 16: Real-time parallel calculation of N L n DFT of a point: X0 = FFT(x0), X1 = FFT(x1), ..., X N-1 =FFT(x N-1 ), go to step 17; Step 17: Based on the adaptive optimization decision, N=2 m Where m is the value of the disk operation. Let m1 = m. When m1 > 1, multiple radix-2 disk operations are required. Let N2 = N for the number of parallel disk operations. Then go to step 18. Step 18: Set X0, X1,,…, X N2-1 Divide the sequence into N2 / 2 subsequences using N2 mod 2, and perform N2 / 2 radix-2 butterfly operations in parallel on each subsequence. Set m1 = m1-1, N2 = N2 / 2, and proceed to step 19. Step 19: Determine the number of disk operations m1. If m1 is greater than 1, use the previous calculation result as input and return to step 18 to perform N2-way, N / N2-point, degraded radix-2 disk operations. If m1 is equal to 1, complete one-way, N-point radix-2 disk operation and output the N-point calculation results to the backend for broadband spectrum processing. Return to step 15 and perform the next operation until the process stops and returns to step 1.

2. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: In step 1, the parallel column data reorganization mapping is to rearrange and map the multi-link data according to the protocol agreement, using the assignment method to re-arrange the N1 point sampling data in step 2 from low to high according to the data width B1 in step 3 and the sampling order.

3. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: In step 2, the data synchronization rate The number N1 of data sample points outputted in parallel by multiple columns is determined by the specific ADC used according to the ADC architecture system and the specific form of the ADC output data protocol.

4. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: In step 3, the data bandwidth of port A is B1=b×N1, the data width of port B is B2=b×N, and the RAM output data rate is 5. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: In step 4, the number of points L of the FFT of the broadband signal real-time spectrum is determined according to the signal resolution index, and the signal resolution is equal to The number of points for parallel FFT in each column L n The length of is associated and implemented according to the determination of N in the adaptive optimization judgment.

6. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: In step 4, the adaptive optimization judgment is specifically as follows: when N=8 m When N=4, radix-8 parallel FFT is implemented. m When N=2, a radix-4 parallel FFT is implemented. m When N=8, implement radix-2 parallel FFT, m is a positive integer; m N = 4 m 、N=2 m When all conditions are met, or two of them are met, the one with the higher cardinality is preferred, and the broadband signal spectrum operation is preferably performed with the highest computational efficiency.

7. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: The radix-8 butterfly operation in steps 5 to 9 has the following operation rules: Among them, a,…,g are the power coefficients of the 8th root of unity, and the rotation factors 8. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: The radix-4 butterfly operation in steps 10 to 14 has the following operation rules: Among them, the rotation factor 9. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: The radix-2 butterfly operation in steps 15 to 19 has the following operation rules: Among them, the rotation factor 10. The method for real-time processing of broadband signals in parallel columns based on FPGA according to claim 1, characterized in that: The sampling accuracy described in step 1 is b bits. In the case of IQ complex numbers, the bit width is doubled.

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