Memory, preparation method thereof and electronic equipment

Abstract

A preparation method of a memory comprises the following steps: providing a substrate to form a laminated structure; etching the laminated structure to form a channel hole penetrating through the laminated structure in the direction vertical to the substrate; depositing a charge storage layer in the channel hole, wherein the charge storage layer is located on the surface of the side wall of the channel hole; depositing a first metal layer on the surface, far away from the substrate, of the laminated structure and in the channel hole; removing the first metal layer, and forming silicide on the surface of the substrate exposed out of the channel hole through a silicification annealing process; a first amorphous silicon layer is formed in the channel hole, the charge storage layer surrounds the first amorphous silicon layer, and one end, close to the substrate, of the first amorphous silicon layer is in contact with the silicide; and utilizing silicide to perform induced crystallization on the first amorphous silicon layer along the direction of the first amorphous silicon layer away from the substrate, so that the first amorphous silicon layer is crystallized to form a monocrystalline silicon layer.

Description

Technical Field

[0001] This article relates to the field of semiconductor technology, in particular to a memory and its preparation method, and electronic equipment. Background Art

[0002] With the advancement of integrated circuit technology, device critical dimensions are shrinking, and the variety and number of devices contained in a single chip are increasing. Consequently, even the slightest variation in process production can affect device performance. To minimize product costs, the goal is to create as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] Embodiments of the present disclosure provide a memory, a method for manufacturing the same, and an electronic device.

[0005] On the one hand, this embodiment provides a method for preparing a memory, comprising: providing a substrate, alternately depositing multiple isolation layers and multiple sacrificial layers on the substrate to form a stacked structure; etching the stacked structure to form a channel hole penetrating the stacked structure in a direction perpendicular to the substrate, the channel hole exposing the surface of the substrate; depositing a charge storage layer in the channel hole, the charge storage layer being located on the sidewall surface of the channel hole; depositing a first metal layer on the surface of the stacked structure away from the substrate and in the channel hole; removing the first metal layer, and forming a silicide on the substrate surface exposed by the channel hole through a silicidation annealing process; forming a first amorphous silicon layer in the channel hole, the charge storage layer surrounding the first amorphous silicon layer, and the first amorphous silicon layer being in contact with the silicide at one end close to the substrate; using the silicide to induce crystallization of the first amorphous silicon layer along the direction of the first amorphous silicon layer away from the substrate, so that the first amorphous silicon layer is crystallized to form a single crystal silicon layer.

[0006] In some exemplary embodiments, the preparation method further includes: depositing an auxiliary layer and a second amorphous silicon layer in sequence on the side of the stacked structure away from the substrate; sucking out residual materials in the single crystal silicon layer into the second amorphous silicon layer through a transfer annealing process, the residual materials including at least one of the following: materials of the first metal layer, silicide; and removing the auxiliary layer and the second amorphous silicon layer.

[0007] In some exemplary embodiments, the transfer annealing process has an annealing temperature of 500 degrees Celsius to 550 degrees Celsius and an annealing time of 1 hour to 24 hours.

[0008] In some exemplary embodiments, the auxiliary layer includes silicon dioxide, and the thickness of the auxiliary layer is in a range from 1 nanometer to 3 nanometers.

[0009] In some exemplary embodiments, after removing the auxiliary layer and the second amorphous silicon layer, the preparation method further includes: forming a drain electrode on a side of the stacked structure away from the substrate, the drain electrode contacting an end of the single crystal silicon layer away from the substrate, and the substrate contacted by the single crystal silicon layer serving as a source electrode.

[0010] In some exemplary embodiments, before forming the channel hole, the fabrication method further comprises: etching the stacked structure to form a stepped structure, wherein the channel hole is located on one side of the stepped structure. After forming the drain electrode, the fabrication method further comprises: removing the sacrificial layer of the stacked structure, and forming a plurality of word lines spaced apart and arranged perpendicular to the substrate in the position of the sacrificial layer; forming a first connecting line, a plurality of second connecting lines, and a third connecting line extending perpendicular to the substrate, wherein the first connecting line is connected to the drain electrode, the plurality of second connecting lines and the third connecting lines correspond one-to-one to the plurality of steps of the first stepped structure, the plurality of second connecting lines are connected one-to-one to the plurality of word lines, and the third connecting line is connected to the source electrode.

[0011] In some exemplary embodiments, the silicidation annealing process has an annealing temperature of 450 degrees Celsius to 550 degrees Celsius and an annealing time of 25 seconds to 35 seconds.

[0012] In some exemplary embodiments, removing the first metal layer includes removing the first metal layer by selective metal etching.

[0013] In some exemplary embodiments, the material of the first metal layer is nickel, and the silicide is nickel disilicide (NiSi 2 ).

[0014] On the other hand, this embodiment provides a memory, comprising: a substrate, a single crystal silicon layer extending in a direction perpendicular to the substrate, and a plurality of transistors stacked in a direction perpendicular to the substrate; the transistors comprising: a channel layer extending in a direction perpendicular to the substrate, a gate arranged around the channel layer, and a charge storage layer located between the gate and the channel layer, an isolation layer being arranged between the gates of adjacent transistors; the channel layer being part of the single crystal silicon layer; an end of the single crystal silicon layer away from the substrate being connected to a drain electrode, and the substrate contacted by the single crystal silicon layer serving as a source electrode.

[0015] In some exemplary embodiments, the charge storage layer includes a blocking layer, a charge trapping layer, and a tunneling layer sequentially arranged from the gate toward the channel layer.

[0016] In some exemplary embodiments, the drain electrode is connected to a first connection line extending in a direction perpendicular to the substrate, and the source electrode is connected to a third connection line extending in a direction perpendicular to the substrate.

[0017] In some exemplary embodiments, the memory further includes: a plurality of word lines stacked along a direction perpendicular to the substrate, the gate of the transistor being part of the word line, the plurality of word lines being distributed in a stepped manner on one side of the plurality of transistors, and each word line being connected to a second connection line extending along a direction perpendicular to the substrate.

[0018] On the other hand, this embodiment provides an electronic device including the memory as described above.

[0019] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0021] Figure 1 is a schematic cross-sectional view of a memory according to at least one embodiment of the present disclosure;

[0022] Figure 2 is a schematic cross-sectional view of a stacked structure according to at least one embodiment of the present disclosure;

[0023] Figure 3 is a schematic cross-sectional view of a stacked structure after a step structure is formed in at least one embodiment of the present disclosure;

[0024] Figure 4 is a schematic cross-sectional view of a stacked structure after forming a channel hole in at least one embodiment of the present disclosure;

[0025] Figure 5 is a schematic cross-sectional view of a stacked structure after a charge storage layer is formed in at least one embodiment of the present disclosure;

[0026] Figure 6 is a schematic cross-sectional view of the stacked structure after the first metal layer is formed in at least one embodiment of the present disclosure;

[0027] Figure 7 is a schematic cross-sectional view of a stacked structure after silicide is formed in at least one embodiment of the present disclosure;

[0028] Figure 8This is a schematic cross-sectional view of a stacked structure after forming a first amorphous silicon layer and a spacer layer in at least one embodiment of the present disclosure.

[0029] Figure 9 is a schematic cross-sectional view of a stacked structure after a single crystal silicon layer is formed in at least one embodiment of the present disclosure;

[0030] Figure 10 is a schematic cross-sectional view of the stacked structure after forming the second amorphous silicon layer in at least one embodiment of the present disclosure;

[0031] Figure 11 A schematic cross-sectional view of at least one embodiment of the present invention showing that residual material is absorbed into the second amorphous silicon layer;

[0032] Figure 12 A schematic diagram of a process for sucking out residual materials according to at least one embodiment of the present disclosure;

[0033] Figure 13 is a schematic cross-sectional view of the stacked structure after the auxiliary layer and the second amorphous silicon layer are removed in at least one embodiment of the present disclosure;

[0034] Figure 14 is a schematic cross-sectional view of the stacked structure after forming a drain electrode in at least one embodiment of the present disclosure;

[0035] Figure 15 FIG. 4 is a schematic cross-sectional view of a stacked structure after forming a plurality of word lines in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] This application describes multiple embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described herein. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0037] The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive solution. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the appended claims and their equivalents, the embodiments are not subject to other limitations. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0038] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0039] In this specification, a transistor may include a gate (also referred to as a gate electrode), a channel, a first electrode, and a second electrode. The first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, and the second electrode may be a drain electrode. The source electrode may also be referred to as a source electrode terminal, a source region, or a source electrode, and the drain electrode may also be referred to as a drain electrode terminal, a drain region, or a drain electrode. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the “source electrode” and the “drain electrode” are sometimes interchanged.

[0040] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0041] The terms “approximately” and “substantially” in this application refer to values ​​that are not strictly limited and allow for process and measurement errors.

[0042] The phrase "A and B disposed in the same layer" in this disclosure encompasses layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer from the same material and then undergoing the same patterning process or different patterning processes. A and B disposed in the same layer can be located on the same horizontal plane, but not necessarily on the same film layer, or in different regions of the same film layer, but not necessarily on the same horizontal plane.

[0043] In the embodiments of the present disclosure, "A and B are interconnected integral structures" may include a film layer patterned to form a connection as an integral structure. For example, A and B are formed using the same material in a single film layer and are formed simultaneously through the same patterning process to form a connected structure.

[0044] After research, the inventors found that polysilicon has grain boundary scattering, which will affect the driving current and reliability of transistors using polysilicon as the channel. Current memory transistors usually use polysilicon channels, which will limit the miniaturization and stacking of the memory, thereby affecting the storage density of the memory.

[0045] This embodiment provides a memory and a preparation method thereof, and an electronic device. By reducing metal contamination through an induced amorphous crystallization process, the driving current and reliability of transistors can be improved, thereby increasing the storage density of the memory.

[0046] Figure 1 FIG. 4 is a schematic cross-sectional view of a memory according to at least one embodiment of the present disclosure. Figure 1 The figure shows a cross section of the memory perpendicular to the plane of the substrate. In this example, the first direction D1 may be parallel to the plane of the substrate and parallel to the direction in which the word lines extend, and the second direction D2 may be perpendicular to the plane of the substrate.

[0047] In some examples, such as Figure 1 As shown, the memory may include: a substrate 100, a single crystal silicon layer 23 extending in a direction perpendicular to the substrate (i.e., a second direction D2), and multiple transistors stacked in the direction perpendicular to the substrate. The transistor may include: a channel layer extending in the direction perpendicular to the substrate, a gate disposed around the channel layer, and a charge storage layer 21 located between the gate and the channel layer. The charge storage layer 21 may also be referred to as an ONO (Oxide-Nitride-Oxide) charging layer. The gate of the transistor may be part of a word line 25. Multiple word lines 25 may be stacked in a direction perpendicular to the substrate. An isolation layer 111 may be provided between adjacent word lines 25. The channel layer of the transistor is part of the single crystal silicon layer 23. The end of the single crystal silicon layer 23 away from the substrate 100 may be connected to a drain electrode 24, and the substrate 100 contacted by the single crystal silicon layer 23 serves as a source electrode.

[0048] In some examples, the plurality of word lines 25 may be distributed in a stepped manner on one side of the stacked plurality of transistors, and each word line 25 may be connected to a second connection line 262 extending in a direction perpendicular to the substrate (ie, the second direction D2 ).

[0049] In some examples, the drain electrode 24 can contact a surface of the single crystal silicon layer 23 at one end away from the substrate 100 and be connected to a first connection line 261 extending in a direction perpendicular to the substrate. The drain electrode 24 can be part of a bit line. The substrate 100 serving as a source electrode can be connected to a third connection line 263 extending in a direction perpendicular to the substrate. The third connection line 263 can be located on a side of the plurality of second connection lines 262 away from the first connection lines 261.

[0050] The technical solution of this embodiment is further explained below through the preparation process of the memory of this embodiment. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc., coating can adopt known coating processes, and etching can adopt known methods, which are not limited here.

[0051] In some examples, the memory preparation process may include the following steps.

[0052] (1) Multiple isolation layers 111 and multiple sacrificial layers 112 are alternately deposited on a substrate to form a stacked structure 10. Figure 2 Schematic cross-sectional view of a stacked structure according to at least one embodiment of the present disclosure.

[0053] In some examples, substrate 100 may be a semiconductor substrate, such as a silicon substrate. In other examples, substrate 100 may be made of single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI); or may be other materials, such as Group III-V compounds such as gallium arsenide.

[0054] In some examples, such as Figure 2 As shown, the stacked structure 10 may include a plurality of sacrificial layers 112 and a plurality of isolation layers 111 that are alternately stacked. For example, the stacked structure 10 may include: three sacrificial layers 112 and four isolation layers 111 that are alternately stacked. This example does not limit the number of sacrificial layers 112 and isolation layers 111 included in the stacked structure 10. The alternating stacking described in this example means that after forming an isolation layer, a sacrificial layer is formed on the surface of the isolation layer, and then the steps of forming the isolation layer and the sacrificial layer located on the isolation layer are cyclically performed. In this example, the bottom layer (i.e., the film layer closest to the substrate) of the stacked structure 10 is an isolation layer, and the top layer (i.e., the film layer farthest from the substrate) is also an isolation layer.

[0055] In some examples, the number of layers in the stacked structure 10 (referring to the number of sacrificial layers in the stacked structure) can be determined based on the number of transistors required to be formed in the vertical direction. For example, the number of layers can be 3, 4, or 6. The greater the number of layers, the higher the integration density. This example uses a stacked structure 10 with 3 layers as an example.

[0056] In some examples, the materials of the sacrificial layer 112 and the isolation layer 111 may be different. When the sacrificial layer 112 is subsequently removed, the sacrificial layer 112 can have a high etching selectivity relative to the isolation layer 111. This allows the isolation layer 111 to be etched with a small or negligible amount during the removal of the sacrificial layer 111, thereby ensuring the flatness of the isolation layer 111.

[0057] In some examples, the material of isolation layer 111 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride, and the material of sacrificial layer 112 may be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. In this example, the material of isolation layer 111 may be silicon oxide, and the material of sacrificial layer 112 may be silicon nitride (e.g., Si3N4). Isolation layer 111 and sacrificial layer 112 may be formed using a chemical vapor deposition process.

[0058] In some examples, the isolation layer 111 and the sacrificial layer 112 may cover the substrate 100. The orthographic projection of the isolation layer 111 on the substrate 100 may coincide with the orthographic projection of the sacrificial layer 112 on the substrate 100. For example, the orthographic projections of the isolation layer 111 and the sacrificial layer 112 may both be rectangular. The orthographic projection of the isolation layer 111 on the substrate 100 may coincide with the substrate 100.

[0059] (2) A step structure 11 is formed on the substrate 100 and the stacked structure 10. Figure 3 Schematic diagram of a cross-section of a stacked structure after forming a stepped structure in at least one embodiment of the present disclosure.

[0060] In some examples, such as Figure 3As shown, one end of the stacked structure 10 in the first direction D1 is etched to form a step structure 11. The step structure 11 may include a plurality of steps that are gradually raised in a step-like manner. For example, the four isolation layers 111 and the three sacrificial layers 112 of the stacked structure 10 may be sequentially recorded as follows along the direction away from the substrate 100: the first isolation layer, the first sacrificial layer, the second isolation layer, the second sacrificial layer, the third isolation layer, the third sacrificial layer, and the fourth isolation layer. Parts of the first isolation layer and the first sacrificial layer may be removed to form a first step exposing the surface of the substrate 100; parts of the second isolation layer and the second sacrificial layer may be removed to form a second step exposing the surface of the first sacrificial layer; parts of the third isolation layer, the third sacrificial layer, and the fourth isolation layer may be removed to form a third step exposing the surface of the second sacrificial layer.

[0061] (3) Forming a channel hole in the stacked structure 10. Figure 4 Schematic diagram of a cross-section of a stacked structure after forming a channel hole in at least one embodiment of the present disclosure.

[0062] In some examples, such as Figure 4 As shown, after forming the stepped structure 11, a first planarization layer 113 may be formed to planarize the stepped structure 11. The surface of the first planarization layer 113 away from the substrate 100 may be flush with the surface of the stacked structure 10 away from the substrate 100. In some examples, the material of the first planarization layer 113 may be the same as that of the isolation layer 111. For example, the material of the first planarization layer 113 may be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0063] In some examples, such as Figure 4 As shown, the stacked structure 10 is etched to form a channel hole K1. The channel hole K1 can be located on one side of the step structure 11 in the first direction D1, and the orthographic projection of the channel hole K1 on the substrate 100 does not overlap with the orthographic projection of the step structure 11 on the substrate 100. The multiple (e.g., three) sacrificial layers 112 and the multiple (e.g., four) isolation layers 111 within the channel hole K1 can be removed to expose the surface of the substrate 100. For example, the orthographic projection of the channel hole K1 on the substrate 100 can be circular or rectangular. This embodiment is not limited to this.

[0064] (4) A charge storage layer is formed in the channel hole. Figure 5 FIG. 4 is a schematic cross-sectional view of a stacked structure after a charge storage layer is formed in at least one embodiment of the present disclosure.

[0065] In some examples, the charge storage layer 21 may also be referred to as an ONO (Oxide-Nitride-Oxide) charging layer. Figure 5As shown, the charge storage layer 21 may include a blocking layer 211 located on the sidewall surface of the channel hole, a charge trapping layer 212 located on the sidewall surface of the blocking layer 211, and a tunneling layer 213 located on the sidewall surface of the charge trapping layer 212. The blocking layer 211, the charge trapping layer 212, and the tunneling layer 213 may be sequentially arranged around the channel hole in a direction from the periphery to the center.

[0066] In some examples, the material of the blocking layer 211 and the tunneling layer 213 may be an oxide, such as silicon oxide, and the material of the charge trapping layer 212 may be a nitride, such as silicon nitride. The blocking layer 211, the charge trapping layer 212, and the tunneling layer 213 may be sequentially deposited using a chemical vapor deposition process.

[0067] (5) Forming a first metal layer. Figure 6 Schematic diagram of a cross-section of a stacked structure after forming a first metal layer in at least one embodiment of the present disclosure.

[0068] In some examples, such as Figure 6 As shown, the first metal layer 21 can cover the first planar layer 113 and the surface of the stacked structure away from the substrate 100, and fill the channel hole K1. The first metal layer 21 can cover the sidewalls of the charge storage layer 21 and the exposed surface of the substrate 100 in the channel hole K1. For example, the first metal layer 12 can be formed using atomic layer deposition (ALD).

[0069] In some examples, the material of the first metal layer 12 can be one or more of nickel (Ni), cobalt, titanium, and tantalum. The thickness of the first metal layer 12 can be, for example, 9 to 11 nanometers (nm). In this example, the material of the first metal layer 12 can be nickel, and the thickness can be approximately 10 nm.

[0070] (6) removing the first metal layer and forming silicide on the substrate surface exposed in the channel hole through a silicide annealing process. Figure 7 FIG. 4 is a schematic cross-sectional view of a stacked structure after silicide is formed in at least one embodiment of the present disclosure.

[0071] In some examples, the first metal layer can be removed by selective metal etching. For example, the first metal layer can be removed by etching with sulfuric acid (H2SO4). A silicidation annealing process is then performed to form an ultra-thin silicide 13. Silicide 13 can be formed at the contact point between the first metal layer and the substrate 100, such as on the surface of the substrate 100 exposed within the trench hole.

[0072] In some examples, the annealing temperature of the silicidation annealing process can be 450 degrees Celsius to 550 degrees Celsius, such as about 500 degrees Celsius, and the annealing time can be 25 seconds to 35 seconds, such as about 30 seconds. The material of the first metal layer is Ni, and the silicide 13 formed is NiSi2. The thickness of NiSi2 can be about 26 angstroms. During the nickel deposition process, nickel diffuses into the amorphous silicon layer. During the selective etching process, the nickel diffused into the amorphous silicon layer cannot be removed. However, the amount of nickel diffused into the amorphous silicon layer during the nickel deposition process is limited. Therefore, the silicide (such as NiSi2) formed by the annealing process in this example has self-limiting properties and a smooth interface with silicon, which greatly reduces Ni contamination.

[0073] (7) Forming a first amorphous silicon layer and a spacer layer in the channel hole. Figure 8 Schematic diagram of a cross-section of a stacked structure after forming a first amorphous silicon layer and a spacer layer in at least one embodiment of the present disclosure.

[0074] In some examples, such as Figure 8 As shown, after forming the silicide 13, an amorphous silicon (a-Si) material and a spacer filler can be filled into the channel hole to form a first amorphous silicon layer 22 and a spacer layer 114. The surface of the first amorphous silicon layer 22 on the side of the channel hole away from the substrate 100 is exposed by etching back. In some examples, the material of the spacer layer 114 can be silicon dioxide (SiO2).

[0075] In some examples, the first amorphous silicon layer 22 may be located on the sidewall surface of the tunneling layer 213 of the charge storage layer 21 and may contact the silicide 13 located at the bottom of the channel hole. The spacer layer 114 may be located on the sidewall surface of the first amorphous silicon layer 22. The spacer layer 114, the first amorphous silicon layer 22, the tunneling layer 213 of the charge storage layer 21, the charge trapping layer 212, and the blocking layer 211 are sequentially arranged in the channel hole from the center to the periphery.

[0076] (8) Performing an induced crystallization annealing process on the first amorphous silicon layer to form a single crystal silicon layer. Figure 9 FIG. 4 is a schematic cross-sectional view of a stacked structure after a single crystal silicon layer is formed in at least one embodiment of the present disclosure.

[0077] In some examples, the temperature of the induced crystallization annealing process may be 500°C to 550°C and the duration may be 1 hour to 24 hours. Figure 9As shown, during the induced crystallization annealing process, silicide (for example, NiSi2) can diffuse to the bottom along the amorphous silicon nanowire, that is, diffuse from the end of the first amorphous silicon layer close to the substrate 100 along the extension direction of the first amorphous silicon layer to the end away from the substrate 100. This example can carry out silicide-induced amorphous crystallization from bottom to top. Among them, amorphous silicon will crystallize into single crystal silicon (c-Si) with the NiSi2 crystal phase as the motherboard, so that the first amorphous silicon layer is crystallized into a single crystal silicon layer 23. Since NiSi2 has a face-centered cubic structure (FCC), which is very close to the single crystal silicon lattice structure, and the lattice mismatch is only 0.4%, it can be considered that the amorphous silicon crystallizes into single crystal silicon.

[0078] In some examples, residual material 14 may exist on the top of the single crystal silicon layer 23 (ie, the end away from the substrate 100 ). For example, the residual material 14 may include nickel, or NiSi 2 , or nickel and NiSi 2 .

[0079] (9) Depositing an auxiliary layer and a second amorphous silicon layer on the side of the stacked structure away from the substrate. Figure 10 FIG. 4 is a schematic cross-sectional view of a stacked structure after forming a second amorphous silicon layer in at least one embodiment of the present disclosure.

[0080] In some examples, such as Figure 10 As shown, an auxiliary layer 115 and a second amorphous silicon layer 116 may be sequentially deposited on a surface of the stacked structure away from the substrate 100. The orthographic projections of the auxiliary layer 115 and the second amorphous silicon layer 116 on the substrate 100 may cover the orthographic projections of the step structure and the channel hole on the substrate 100. The material of the auxiliary layer 115 may include SiO2, for example, and the thickness of the auxiliary layer 115 may range from 1 nm to 3 nm.

[0081] (10) The residual material in the single crystal silicon layer is sucked out to the second amorphous silicon layer through a transport annealing process. Figure 11 A schematic cross-sectional view of residual material being absorbed into the second amorphous silicon layer in at least one embodiment is disclosed. Figure 12 Schematic diagram of the residual material suction process according to at least one embodiment of the present disclosure.

[0082] In some examples, the annealing temperature of the transfer annealing process may be 500 degrees Celsius to 550 degrees Celsius, and the annealing time may be 1 hour to 24 hours. Figure 11 and Figure 12 As shown, during the transfer annealing process, the residual material 14 in the single crystal silicon layer 23 can be sucked out into the second amorphous silicon layer 116. This example can further reduce metal residue and contamination by sucking out the residual material (such as metal Ni or NiSi2) on the top of the single crystal silicon layer.

[0083] (11) Remove the auxiliary layer and the second amorphous silicon layer. Figure 13 Schematic diagram of the cross section of the stacked structure after removing the auxiliary layer and the second amorphous silicon layer in at least one embodiment of the present disclosure. Figure 13 As shown, after the auxiliary layer and the second amorphous silicon layer are removed, the single crystal silicon layer 23 in the channel hole can be exposed away from the surface of the substrate 100 .

[0084] (12) Forming a drain electrode. Figure 14 FIG. 1 is a schematic cross-sectional view of a stacked structure after forming a drain electrode in at least one embodiment of the present disclosure. Figure 14 As shown, a second metal layer is deposited on the surface of the stacked structure away from the substrate 100, forming a drain electrode 24 located at the top of the stacked structure. The drain electrode 24 can also be called a top drain. The orthographic projection of the drain electrode 24 on the substrate 100 can cover the orthographic projection of the channel hole on the substrate 100 and may not overlap with the orthographic projection of the step structure on the substrate 100. The drain electrode 24 can contact the surface of the charge storage layer 21, the single crystal silicon layer 23, and the spacer layer 114 in the channel hole away from the substrate 100. The drain electrode 24 can be connected to a bit line or serve as part of a bit line.

[0085] (13) forming a plurality of word lines. Figure 15 FIG. 1 is a cross-sectional view of a stacked structure after forming a plurality of word lines in at least one embodiment of the present disclosure. Figure 15 As shown, the sacrificial layer in the stacked structure can be removed to form a cavity, and multiple word lines 25 arranged along a direction perpendicular to the substrate are formed at the location where the sacrificial layer was removed. The isolation layer 111 can serve as electrical isolation between word lines in different layers and between word lines and other devices. The word lines 25 can also serve as the gates of the transistors.

[0086] In some examples, the material of word line 25 may be TiN or tungsten (W).

[0087] In some examples, after forming the plurality of word lines, a second planarization layer 117 can be formed to cover the stepped structure and the drain electrode 24. In some examples, the material of the second planarization layer 117 can be the same as that of the isolation layer 111. For example, the material of the second planarization layer 117 can be one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.

[0088] (14) forming multiple connection lines. In some examples, such as Figure 1As shown, multiple vias can be provided in the second planar layer 117, for example, including: a first via exposing the surface of the drain electrode 24, a second via exposing the surface of the word line 25, and a third via exposing the surface of the substrate 100. Multiple connecting lines are formed by depositing a third metal layer. The multiple connecting lines may include: a first connecting line 261, a second connecting line 262, and a third connecting line 263. The multiple connecting lines may extend along the second direction D2. The first connecting line 261 may be provided in the first via and electrically connected to the drain electrode 24 through the first via. The second connecting line 262 may be provided in the second via and electrically connected to the corresponding word line 25 through the second via. The third connecting line 263 may be provided in the third via and connected to the substrate 100 through the third via. In this example, the substrate 100 may serve as the source of the bottom transistor. The multiple second and third connecting lines may be arranged sequentially along the stepped structure, distributed on the multiple steps of the stepped structure.

[0089] In some examples, such as Figure 1 As shown, multiple (e.g., three) transistors stacked along the second direction D2 can be connected in series. The single crystal silicon layer 23 can serve as the channel layer of the series-connected transistors. One end of the single crystal silicon layer 23 away from the substrate 100 is connected to the drain electrode 24, and the other end is in contact with the substrate 100. The substrate 100 contacted by the single crystal silicon layer 23 can be formed into a source electrode through a doping process.

[0090] In the preparation method of this example, after the first metal layer is deposited, the first metal layer is directly removed by selective metal etching, and then a silicidation annealing process is performed to form an ultra-thin silicide (such as NiSi2), followed by silicidation-induced amorphous crystallization from the bottom up. The silicide (such as NiSi2) formed by the method of this example has self-limiting properties, which can greatly reduce the residue and contamination of metals (such as Ni). Moreover, the use of an auxiliary layer and a second amorphous silicon layer to absorb the residual materials (such as Ni, NiSi2) in the single crystal silicon layer can further improve the metal residue and contamination. This example uses a metal-induced amorphous crystallization method with low metal contamination, which is beneficial to improving the device driving current and reliability, thereby increasing the storage density of the memory.

[0091] This embodiment also provides a method for preparing a memory device, comprising: providing a substrate, alternately depositing multiple isolation layers and multiple sacrificial layers on the substrate to form a stacked structure; etching the stacked structure to form a channel hole extending perpendicularly through the stacked structure, the channel hole exposing the substrate surface; depositing a charge storage layer within the channel hole, the charge storage layer being located on the sidewall surface of the channel hole; depositing a first metal layer on the surface of the stacked structure away from the substrate and within the channel hole; removing the first metal layer and forming a silicide on the substrate surface exposed by the channel hole through a silicidation annealing process; forming a first amorphous silicon layer within the channel hole, the charge storage layer surrounding the first amorphous silicon layer, the first amorphous silicon layer being in contact with the silicide at one end thereof proximal to the substrate; and inducing crystallization of the first amorphous silicon layer using the silicide along a direction away from the substrate, such that the first amorphous silicon layer crystallizes to form a single crystalline silicon layer. In some examples, the first metal layer is made of nickel, and the silicide is nickel disilicide (NiSi2).

[0092] In some exemplary embodiments, the preparation method of this example may further include: depositing an auxiliary layer and a second amorphous silicon layer in sequence on the side of the stacked structure away from the substrate; sucking out the residual material in the single crystal silicon layer into the second amorphous silicon layer through a transfer annealing process, wherein the residual material includes at least one of the following: the material of the first metal layer, silicide; and removing the auxiliary layer and the second amorphous silicon layer.

[0093] In some exemplary embodiments, after removing the auxiliary layer and the second amorphous silicon layer, the preparation method of this example may further include: forming a drain electrode on the side of the stacked structure away from the substrate, the drain electrode contacts the end of the single crystal silicon layer away from the substrate, and the substrate contacted by the single crystal silicon layer serves as a source electrode.

[0094] In some exemplary embodiments, before forming the channel hole, the fabrication method of this example may further include: etching the stacked structure to form a stepped structure, wherein the channel hole is located on one side of the stepped structure. After forming the drain electrode, the fabrication method of this example may further include: removing the sacrificial layer of the stacked structure, and forming a plurality of word lines spaced apart and arranged perpendicular to the substrate in the position of the sacrificial layer; forming a first connecting line, a plurality of second connecting lines, and a third connecting line extending perpendicular to the substrate, wherein the first connecting line is connected to the drain electrode, the plurality of second connecting lines and the third connecting lines correspond one-to-one to the plurality of steps of the first stepped structure, the plurality of second connecting lines are connected one-to-one to the plurality of word lines, and the third connecting line is connected to the source electrode.

[0095] The description of the method for preparing the memory of this embodiment can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0096] This embodiment further provides an electronic device including the memory described in the preceding embodiment. The electronic device may include a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or a smart mobile terminal. The storage device may include, for example, computer memory, but this embodiment is not limited thereto.

[0097] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0098] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or to implicitly specify the quantity of the technical features being referred to. Thus, a feature defined as "first," "second," etc. may explicitly or implicitly include at least one of the features.

[0099] In the description of the present application, “a plurality of” means at least two, for example, two, three, etc., unless explicitly defined otherwise.

[0100] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can mean mechanical connection or electrical connection; it can mean direct connection or indirect connection through an intermediate medium; it can mean internal communication between two elements or interaction between two elements, unless otherwise specified. For those skilled in the art, the meanings of the above terms in this application can be understood according to the circumstances.

[0101] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it can mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it can mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it can mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0102] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0103] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A method for preparing a memory, characterized in that: include: Providing a substrate, and alternately depositing multiple isolation layers and multiple sacrificial layers on the substrate to form a stacked structure; Etching the stacked structure to form a channel hole penetrating the stacked structure in a direction perpendicular to the substrate, wherein the channel hole exposes the surface of the substrate; Depositing a charge storage layer in the channel hole, wherein the charge storage layer is located on a sidewall surface of the channel hole; Depositing a first metal layer on a surface of the stacked structure away from the substrate and in the channel hole; removing the first metal layer and forming silicide on the substrate surface exposed by the channel hole through a silicidation annealing process; forming a first amorphous silicon layer in the channel hole, wherein the charge storage layer surrounds the first amorphous silicon layer, and an end of the first amorphous silicon layer close to the substrate contacts the silicide; The silicide is used to induce crystallization of the first amorphous silicon layer along a direction in which the first amorphous silicon layer is away from the substrate, so that the first amorphous silicon layer is crystallized to form a single crystal silicon layer.

2. The preparation method according to claim 1, characterized in that The preparation method further comprises: Depositing an auxiliary layer and a second amorphous silicon layer in sequence on a side of the stacked structure away from the substrate; sucking out residual material in the single crystal silicon layer into the second amorphous silicon layer through a transfer annealing process, the residual material comprising at least one of the following: a material of the first metal layer, and silicide; The auxiliary layer and the second amorphous silicon layer are removed.

3. The preparation method according to claim 2, characterized in that The annealing temperature of the transfer annealing process is 500 degrees Celsius to 550 degrees Celsius, and the annealing time is 1 hour to 24 hours.

4. The preparation method according to claim 2, characterized in that The auxiliary layer is made of silicon dioxide, and the thickness of the auxiliary layer is in a range of 1 nanometer to 3 nanometers.

5. The preparation method according to claim 2, characterized in that After removing the auxiliary layer and the second amorphous silicon layer, the preparation method further includes: forming a drain electrode on the side of the stacked structure away from the substrate, the drain electrode contacts the end of the single crystal silicon layer away from the substrate, and the substrate contacted by the single crystal silicon layer serves as a source electrode.

6. The preparation method according to claim 5, characterized in that Before forming the channel hole, the preparation method further comprises: etching the stacked structure to form a step structure, wherein the channel hole is located on one side of the step structure; After forming the drain electrode, the preparation method further includes: removing the sacrificial layer of the stacked structure, and forming a plurality of word lines arranged at intervals along a direction perpendicular to the substrate at the position of the sacrificial layer; forming a first connecting line, a plurality of second connecting lines and a third connecting line extending along a direction perpendicular to the substrate, the first connecting line is connected to the drain electrode, the plurality of second connecting lines and the third connecting lines correspond one-to-one to the plurality of steps of the step structure, the plurality of second connecting lines are connected one-to-one to the plurality of word lines, and the third connecting line is connected to the source electrode.

7. The preparation method according to claim 1, characterized in that The annealing temperature of the silicidation annealing process is 450 degrees Celsius to 550 degrees Celsius, and the annealing time is 25 seconds to 35 seconds.

8. The preparation method according to claim 1, characterized in that The removing of the first metal layer includes: removing the first metal layer by selective metal etching.

9. The preparation method according to any one of claims 1 to 8, characterized in that The material of the first metal layer is nickel, and the silicide is nickel disilicide NiSi2.

10. A memory, characterized in that: include: A substrate, a single crystal silicon layer extending in a direction perpendicular to the substrate, and a plurality of transistors stacked in a direction perpendicular to the substrate; the transistors comprising: a channel layer extending in a direction perpendicular to the substrate, a gate disposed around the channel layer, and a charge storage layer located between the gate and the channel layer, wherein an isolation layer is disposed between the gates of adjacent transistors; The channel layer is a part of the single crystal silicon layer; one end of the single crystal silicon layer away from the substrate is connected to the drain electrode, and the substrate contacted by the single crystal silicon layer serves as a source electrode.

11. The memory according to claim 10, wherein: The charge storage layer includes a blocking layer, a charge trapping layer, and a tunneling layer which are sequentially arranged from the gate to the channel layer.

12. The memory according to claim 10, wherein: The drain electrode is connected to a first connection line extending in a direction perpendicular to the substrate, and the source electrode is connected to a third connection line extending in a direction perpendicular to the substrate.

13. The memory according to claim 10, wherein: The memory also includes: a plurality of word lines stacked along a direction perpendicular to the substrate, the gate of the transistor is part of the word line, the plurality of word lines are distributed in a step-like manner on one side of the plurality of transistors, and each word line is connected to a second connection line extending along a direction perpendicular to the substrate.

14. An electronic device, characterized in that: Comprising the memory according to any one of claims 10 to 13.

Images