Solar cell, preparation method therefor and use thereof

Abstract

The present disclosure relates to the technical field of solar cells. Disclosed are a solar cell, a preparation method therefor and a use thereof. A P-type doped region and an N-type doped region are alternately arranged on the back surface of a crystalline silicon substrate; a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially formed in the P-type doped region; and a phosphorus-doped silicon oxide layer, a phosphorus-doped polycrystalline silicon layer, a second passivation layer and a second anti-reflection layer are sequentially formed on the surface of the crystalline silicon substrate in the N-type doped region. The P regions of traditional TBC cells mostly adopt a two-step process of depositing intrinsic amorphous silicon and performing boron diffusion to form a polycrystalline silicon layer. However, the P region of the present disclosure does not contain a polycrystalline silicon layer, and can be prepared by a one-step boron diffusion process, which can reduce the process steps and shorten the process time. The interaction between laser and the polycrystalline silicon in the P region is also avoided, the difficulty of cell patterning is reduced, and the production yield of cells can be greatly improved.

Description

Solar cell and preparation method and application thereof

[0001] Cross-reference to Related Applications

[0002] The present disclosure claims priority to the Chinese patent application No. 2024110804493, filed on August 7, 2024, entitled "Solar cell and preparation method and application thereof", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of solar cells, in particular to a solar cell and a preparation method and application thereof. BACKGROUND

[0004] TBC cells are a combination of TOPCon and BC technologies, with no metal electrode on the front side to block light, and the PN region on the back side is passivated by a tunneling layer + poly layer structure. Compared with conventional PERC cells and TOPCon cells, TBC cells have higher efficiency and better appearance on the front side, and are more suitable for distributed photovoltaic scenarios.

[0005] Currently, the existing commercial TBC cells all use tunneling oxide passivation contact technology, that is, a doped polysilicon film is deposited in the PN region, which can significantly reduce metal recombination of the cell and improve the open-circuit voltage (Voc) and photoelectric conversion efficiency of the cell. However, the preparation process of TBC cells is relatively complex, and the doping concentration and crystallization rate of the doped polysilicon will change after being subjected to high-energy density laser, increasing the difficulty of wet alkali etching and patterning, and making it easy to have patterning defects during the preparation process, affecting the yield of TBC cells.

[0006] Therefore, there is an urgent need to improve the structure and preparation process of TBC cells to reduce the patterning difficulty of TBC cells and improve the production yield of TBC cells.

[0007] In view of this, the present disclosure is proposed. SUMMARY

[0008] The present disclosure aims to provide a solar cell and a preparation method and application thereof, which aims to reduce the patterning difficulty of the cell and improve the production yield of the cell.

[0009] The present disclosure is implemented as follows:

[0010] In a first aspect, the present disclosure provides a solar cell, comprising: a crystalline silicon substrate, the crystalline silicon substrate having a front side and a back side opposite to the front side;

[0011] The P-type doped region and the N-type doped region are alternately and spacedly arranged on the back side of the crystalline silicon substrate;

[0012] In the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate;

[0013] The P-type doped region takes the boron diffusion doped layer as a PN junction, has a sheet resistance of 200Ω / sq-1000Ω / sq, a doping concentration of 7E17cm -3 -7E18cm -3 , and a junction depth of 0.3μm-1.0μm;

[0014] In the N-type doped region, an N-type doped layer, a second passivation layer and a second anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; the N-type doped layer of the N-type doped region comprises a phosphorus-doped silicon oxide layer and a phosphorus-doped polysilicon layer which are sequentially arranged, and the phosphorus-doped polysilicon layer is located between the phosphorus-doped silicon oxide layer and the second passivation layer.

[0015] In an optional embodiment, the PN junction of the P-type doped region has a sheet resistance of 300Ω / sq-800Ω / sq, a doping concentration of 1E18cm -3 -5E18cm -3 , and a junction depth of 0.5μm-0.8μm;

[0016] Optionally, the P-type doped region is further provided with a first metal electrode, and the N-type doped region is further provided with a second metal electrode; the first metal electrode is in contact with the boron diffusion doped layer, and the contact surface of the first metal electrode with the boron diffusion doped layer has a hole and a conductive structure; the conductive structure comprises a silver-silicon eutectic layer close to the boron diffusion doped layer and a conductive crystalline body extending from the silver-silicon eutectic layer towards the hole; the silver-silicon eutectic layer comprises a eutectic body formed by silver elements and silicon elements, and the conductive crystalline body comprises a crystalline body formed by crystallization of silver elements;

[0017] More optionally, the conductive crystalline body comprises a main chain and a side chain extending from the main chain in a direction different from the growth direction of the main chain.

[0018] In an optional embodiment, an isolation trench is arranged between the adjacent P-type doped region and N-type doped region;

[0019] In the region where the isolation trench is located, a third passivation layer and a third anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate;

[0020] Optionally, the distance between the phosphorus-doped silicon oxide layer and the front surface of the crystalline silicon substrate is less than the distance between the boron diffusion doped layer and the front surface of the crystalline silicon substrate, and the distance between the second anti-reflection layer and the front surface of the crystalline silicon substrate is less than the distance between the first anti-reflection layer and the front surface of the crystalline silicon substrate, so that the P-type doped region and the N-type doped region have a height difference at the end away from the front surface of the crystalline silicon substrate; more optionally, the height difference is 0.5μm-5.0μm;

[0021] Optionally, the boron-diffused doped layer of the P-type doped region has a junction depth of 0.3-1.0 μm, the phosphorus-doped silicon oxide layer has a thickness of 0.5-3.0 nm, and the phosphorus-doped polysilicon layer has a thickness of 50-300 nm.

[0022] In an optional embodiment, the crystalline silicon substrate is an N-type single-crystal silicon, the N-type doped region and the crystalline silicon substrate form a high-low junction, the high-low junction has a sheet resistance of 10-100 Ω / sq and a doping concentration of 1E20 cm -3 -9E20 cm -3 , a junction depth of 0.07-0.5 μm, and an internal diffusion depth of 0.02-0.1 μm under the silicon substrate.

[0023] Optionally, the high-low junction of the N-type doped region has a sheet resistance of 10-50 Ω / sq and a doping concentration of 2-6E20 cm -3 , a junction depth of 0.1-0.4 μm, and an internal diffusion depth of 0.03-0.08 μm under the silicon substrate.

[0024] In an optional embodiment, the P-type doped region has a width of 200-1000 μm, and the N-type doped region has a width of 200-1000 μm.

[0025] Optionally, the area ratio of the P-type doped region to the N-type doped region is (0.5-2.0) : 1, preferably (0.8-1.2) : 1.

[0026] Optionally, the isolation trench has a width of 50-200 μm and a depth of 0.5-5.0 μm.

[0027] Optionally, the distance between two adjacent N-type doped regions is 0.5-2.0 mm.

[0028] Optionally, the silicon substrate corresponding to the P-type doped region, the N-type doped region, and the isolation trench has a planar structure or a textured structure, and the textured structure has a pyramid base size of 1-5 μm and a tower height of 0.5-2.0 μm.

[0029] In an optional embodiment, the first metal electrode of the P-type doped region includes a plurality of first sub-gate electrodes and a first main gate electrode configured to connect the plurality of first sub-gate electrodes, and the second metal electrode on the N-type doped region includes a plurality of second sub-gate electrodes and a second main gate electrode configured to connect the plurality of second sub-gate electrodes.

[0030] Optionally, each first sub-gate electrode perpendicularly intersects the first main gate electrode and is connected through the first main gate electrode, and each second sub-gate electrode perpendicularly intersects the second main gate electrode and is connected through the second main gate electrode.

[0031] In an optional embodiment, on the front surface of the crystalline silicon substrate, a front passivation layer and a front anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate.

[0032] Optionally, the material of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer is independently selected from at least one of Al2O3 and SiO2.

[0033] Optionally, the material of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer is independently selected from at least one of SiNx and SiO x N y .

[0034] Optionally, the thickness of the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer is independently 2 nm-5 nm.

[0035] Optionally, the thickness of the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer is independently 70 nm-100 nm.

[0036] Optionally, the thickness of the crystalline silicon substrate is 100 μm-150 nm.

[0037] In a second aspect, the present disclosure provides a preparation method of the solar cell in any one of the foregoing embodiments, comprising:

[0038] providing a crystalline silicon substrate, the crystalline silicon substrate having a front surface and a back surface opposite to the front surface;

[0039] forming P-type doped regions and N-type doped regions alternately arranged on the back surface of the crystalline silicon substrate; and on the P-type doped regions, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate, the P-type doped regions take the boron diffusion doped layer as a PN junction, the sheet resistance is 200 Ω / sq-1000 Ω / sq, the doping concentration is 7E17 cm -3 -7E18 cm -3 , and the junction depth is 0.3 μm-1.0 μm;

[0040] on the N-type doped regions, a phosphorus-doped silicon oxide layer, a phosphorus-doped polysilicon layer, a second passivation layer and a second anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate.

[0041] In an optional embodiment, the method comprises: forming an isolation trench on the back surface of the crystalline silicon substrate, separating the back surface of the crystalline silicon substrate into P-type doped regions and N-type doped regions alternately arranged by the isolation trench, and forming functional layers on each region of the back surface of the crystalline silicon substrate and the front surface of the crystalline silicon substrate to obtain an intermediate film layer with the functional layers;

[0042] The first plurality of sub-gate electrodes and the at least one first main gate electrode are formed on the P-type doped region of the intermediate film layer, and the second plurality of sub-gate electrodes and the at least one second main gate electrode are formed on the N-type doped region, and the laser-induced sintering is performed after forming the complete cell structure;

[0043] Optionally, the laser-induced sintering process comprises: applying a reverse bias on the main gate electrodes of the cell to form a loop, and then performing laser scanning on at least the P-type doped region; the reverse bias is controlled to be 10V-50V, the applied laser power is 20W-120W, and the laser scanning rate is 50mm / s-500mm / s.

[0044] In the optional embodiment, the first probe array is used to press on each first main gate electrode on the P-type doped region, the second probe array is used to press on each second main gate electrode on the N-type doped region, and the first probe array and the second probe array are used to apply a reverse bias on each main gate electrode to form a loop, and the laser-induced sintering is performed on at least the P-type doped region.

[0045] In the optional embodiment, the third passivation layer and the third anti-reflection layer are sequentially arranged on the surface of the crystalline silicon substrate in the region where the isolation groove is located.

[0046] The preparation process of the intermediate film layer comprises:

[0047] The boron diffusion doped layer, the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer are formed on the back surface of the crystalline silicon substrate, and meanwhile, the intermediate protective layer is formed, and the local film opening is removed, so that the P-type doped region only retains the boron diffusion doped layer, the N-type doped region only retains the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer, and the hollow groove region is formed between the P-type doped region and the N-type doped region.

[0048] The passivation layer and the anti-reflection layer corresponding to each region are formed on the P-type doped region, the N-type doped region and the hollow groove region of the back surface of the crystalline silicon substrate, and the front passivation layer and the front anti-reflection layer are formed on the front surface of the crystalline silicon substrate.

[0049] In the optional embodiment, the process of forming the hollow groove region comprises: pre-treating the back surface of the crystalline silicon substrate, sequentially forming the boron diffusion doped layer and the boron-silicon glass layer on the back surface of the crystalline silicon substrate, locally opening the film using laser, removing the local boron-silicon glass layer using laser, removing the boron diffusion doped layer in the laser region by alkali etching, and making the width of the film opening equal to the sum of one N-type doped region and two isolation groove regions, and making the etching depth reach the crystalline silicon substrate.

[0050] The phosphorus-doped silicon oxide layer, the phosphorus-doped polysilicon layer and the phosphorus-silicon glass layer are sequentially formed on the entire back surface of the crystalline silicon substrate.

[0051] The phosphosilicate glass layer on the P-type doped region is removed by local film opening with a laser, and the opening width is greater than the width of the P-type doped region, and the difference between the opening width and the width of the P-type doped region is 50-200 μm;

[0052] The front surface of the crystalline silicon substrate is subjected to acid etching and groove texturing, so that the area protected by the borosilicate glass layer and the phosphosilicate glass layer is not etched, and then all the borosilicate glass layer and the phosphosilicate glass layer on the back surface are removed by etching, so that the P-type doped region only retains the boron diffusion doped layer, the N-type doped region only retains the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer, and a hollow groove region is formed between the P-type doped region and the N-type doped region, and the width of the hollow groove region is 50-200 μm;

[0053] Optionally, the pre-treatment is polishing or texturing.

[0054] Optionally, the crystalline silicon substrate is subjected to single-side boron doping by high-temperature boron diffusion, and the diffusion temperature is controlled to be 980-1050 °C to form a boron diffusion doped layer.

[0055] Optionally, the thickness of the formed borosilicate glass layer is 20-100 nm, and the thickness of the formed phosphosilicate glass layer is 20-80 nm.

[0056] Optionally, the process of forming the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer includes: forming a tunneling silicon oxide layer with a thickness of 1-3 nm and an intrinsic amorphous silicon film with a thickness of 50-300 nm by chemical vapor deposition, and then performing high-temperature phosphorus diffusion with a diffusion temperature of 800-900 °C.

[0057] Optionally, the phosphorus-doped polysilicon layer is formed by plasma-enhanced chemical vapor deposition and annealing.

[0058] In an optional embodiment, the first sub-grid electrode, the second sub-grid electrode, the first main grid electrode, and the second main grid electrode are prepared by screen printing.

[0059] Optionally, the process of preparing the sub-grid electrode and the main grid electrode includes:

[0060] The first sub-grid paste, the second sub-grid paste, the first main grid paste, and the second main grid paste are prepared.

[0061] The first sub-grid paste, the second sub-grid paste, the first main grid paste, and the second main grid paste are printed on the intermediate film layer, respectively.

[0062] The cell piece with the printed paste is subjected to sintering and light injection, and the sintering temperature is controlled to be 700-800 °C.

[0063] In a third aspect, the present disclosure provides a photovoltaic module comprising the solar cell of any one of the preceding embodiments or the solar cell prepared by the preparation method of any one of the preceding embodiments.

[0064] The present disclosure has the following beneficial effects: the P-type doped region and the N-type doped region are alternately arranged on the back surface of the crystalline silicon substrate, the boron diffusion doped layer, the first passivation layer and the first anti-reflection layer are sequentially arranged in the P-type doped region, and the phosphorus-doped silicon oxide layer, the phosphorus-doped polysilicon layer, the second passivation layer and the second anti-reflection layer are sequentially arranged in the N-type doped region from the surface of the crystalline silicon substrate. In the conventional TBC cell, the P region is more likely to use a two-step process of depositing intrinsic amorphous silicon + boron diffusion to form a polysilicon layer, while the P region of the present disclosure does not contain a polysilicon layer and can be prepared by a one-step boron diffusion process, which can reduce the process steps and process time. It also avoids the action of laser and P region polysilicon, reduces the patterning difficulty of the cell, and can greatly improve the production yield of the cell.

[0065] It should be noted that the sheet resistance of the boron diffusion doped layer of the conventional BC cell is small, and the boron diffusion doped layer of the P-type doped region in the present disclosure has a large difference in sheet resistance from the boron diffusion doped layer of the conventional BC cell. Generally speaking, the conventional BC cell directly boron diffuses on the silicon substrate, which often has a high doping concentration and a deep diffusion junction depth, which will change the arrangement of crystalline silicon, cause lattice distortion defects, and the recombination of carriers is large, thereby affecting the performance of the cell. The present disclosure optimizes the preparation process of the P region of the TBC cell, directly boron diffuses on the crystalline silicon substrate to form a PN junction and cooperates with the laser-induced sintering process (LIF), without high doping concentration and deep diffusion junction depth, avoiding the problem of high doping concentration of the P region non-metallic region causing silicon lattice distortion and disordered arrangement, while ensuring the metal contact performance of the P region, effectively reducing the carrier recombination of the P region non-metallic region, and being conducive to improving the photoelectric conversion efficiency of the cell. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0067] FIG. 1 is a structural schematic diagram of a solar cell provided by an embodiment of the present disclosure;

[0068] FIG. 2 is a schematic diagram of a conductive structure generated at the contact between the first metal electrode and the boron diffusion doped layer in FIG. 1;

[0069] FIG. 3 is an enlarged view of the conductive structure in FIG. 2;

[0070] Fig. 4 is a schematic diagram of a crystalline silicon substrate according to an embodiment of the present disclosure;

[0071] Fig. 5 is a schematic diagram of a crystalline silicon substrate after forming a boron diffusion doped layer and a borosilicate glass layer thereon according to an embodiment of the present disclosure;

[0072] Fig. 6 is a schematic diagram of a crystalline silicon substrate after removing a part of the boron diffusion doped layer and the borosilicate glass layer by laser ablation according to an embodiment of the present disclosure;

[0073] Fig. 7 is a schematic diagram of a crystalline silicon substrate after forming a phosphorus doped silicon oxide layer, a phosphorus doped polysilicon layer and a phosphosilicate glass layer thereon according to an embodiment of the present disclosure;

[0074] Fig. 8 is a schematic diagram of a crystalline silicon substrate after removing the phosphosilicate glass layer on the P-type doped region by laser ablation according to an embodiment of the present disclosure;

[0075] Fig. 9 is a schematic diagram of a crystalline silicon substrate after acid etching and slot texturing according to an embodiment of the present disclosure;

[0076] Fig. 10 is a schematic diagram of a crystalline silicon substrate after forming a passivation layer and an anti-reflective layer thereon according to an embodiment of the present disclosure;

[0077] Fig. 11 is a schematic diagram of a crystalline silicon substrate after forming a main grid electrode and a sub-grid electrode thereon according to an embodiment of the present disclosure;

[0078] Fig. 12 is a schematic diagram of a crystalline silicon substrate after laser induced sintering according to an embodiment of the present disclosure.

[0079] Main element symbol explanation: 1-crystalline silicon substrate; 2-boron diffusion doped layer; 3-borosilicate glass layer; 4-phosphorus doped silicon oxide layer; 5-phosphorus doped polysilicon layer; 6-phosphosilicate glass layer; 7-passivation layer; 8-anti-reflective layer; 9-first sub-grid electrode; 10-second sub-grid electrode; 11-first main grid electrode; 12-second main grid electrode; 13-first probe row; 14-second probe row; 15-hole; 16-conductive structure; 161-silver silicon eutectic layer; 162-conductive crystalline; 1621-crystalline main chain; 1622-crystalline side chain. DETAILED DESCRIPTION

[0080] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below. If specific conditions are not specified in the embodiments, conventional conditions or manufacturer recommended conditions are used. If the manufacturers of the reagents or instruments are not specified, they are all conventional products that can be purchased in the market.

[0081] The P region of the existing TBC cell is formed by a two-step process of depositing intrinsic amorphous silicon and boron diffusion to form a polysilicon layer, which has a complex preparation process. After the doped polysilicon is subjected to high-energy density laser, the doping concentration and crystallization rate will change, which increases the difficulty of wet alkali etching and patterning, and the preparation process is prone to pattern defects, which affects the yield of the TBC cell.

[0082] To solve the above technical problems, the inventors optimize the structure and preparation process of the P region of the TBC cell, and directly prepare a boron diffusion doped layer on the crystalline silicon substrate to form a PN junction, which avoids the action of laser on the polysilicon in the P region, reduces the patterning difficulty of the cell, and can greatly improve the production yield of the cell.

[0083] As shown in FIG. 1, the present disclosure provides a solar cell, which comprises a crystalline silicon substrate 1 having a front surface and a back surface opposite to the front surface; a P-type doped region (P region) and an N-type doped region (N region) are alternately and spacedly arranged on the back surface of the crystalline silicon substrate 1, and an isolation trench is arranged between adjacent P-type doped region and N-type doped region.

[0084] In the P-type doped region, a boron diffusion doped layer 2, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged from the surface of the crystalline silicon substrate 1. Compared with the traditional P region, the P-type doped region does not contain a polysilicon layer, which not only reduces the process steps, but also avoids the action of laser on the polysilicon in the P region, reduces the patterning difficulty of the cell, and can greatly improve the production yield of the cell. Specifically, the passivation layer 7 of the P-type doped region is also referred to as a first passivation layer, and the anti-reflection layer 8 is also referred to as a first anti-reflection layer.

[0085] In some embodiments, in the N-type doped region, an N-type doped layer, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged from the surface of the crystalline silicon substrate 1. Specifically, the N-type doped layer is doped with phosphorus, and the specific structure can refer to the existing N region structure. The passivation layer 7 of the N-type doped region is also referred to as a second passivation layer, and the anti-reflection layer 8 is also referred to as a second anti-reflection layer. In some embodiments, the N-type doped layer of the N-type doped region comprises a phosphorus-doped silicon oxide layer 4 and a phosphorus-doped polysilicon layer 5 arranged in sequence, and the phosphorus-doped polysilicon layer 5 is located between the phosphorus-doped silicon oxide layer 4 and the second passivation layer 7.

[0086] In some embodiments, in the region where the isolation trench is located, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged from the surface of the crystalline silicon substrate 1. The passivation layer 7 at the isolation trench is also referred to as a third passivation layer, and the anti-reflection layer 8 at the isolation trench is also referred to as a third anti-reflection layer.

[0087] In some embodiments, on the front surface of the crystalline silicon substrate 1, a passivation layer 7 and an anti-reflection layer 8 are sequentially arranged from the surface of the crystalline silicon substrate 1, and the passivation layer 7 on the front surface is also referred to as a front passivation layer, and the anti-reflection layer 8 on the front surface is also referred to as a front anti-reflection layer.

[0088] In some embodiments, the width of the P-type doped region is 200 μm-1000 μm, such as 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, etc. The width of the N-type doped region is 200 μm-1000 μm, such as 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm, etc. Specifically, the width direction and length direction of the P-type doped region can refer to the width and length direction of the crystalline silicon substrate 1, such as the width direction and thickness direction shown in FIG. 1, and the length direction is not shown.

[0089] Optionally, the area ratio of the P-type doped region and the N-type doped region is (0.5-2.0):1, such as 0.5:1, 0.8:1, 1.0:1, 1.2:1, 1.5:1, 1.8:1, 2.0:1, etc., preferably (0.8-1.2):1. The area ratio of the P-type doped region and the N-type doped region can be controlled within the above range, and the area ratio of the two can be controlled according to the process requirements, and both can be prepared into high-efficiency solar cells. Specifically, the area of the P-type doped region and the N-type doped region is calculated by the product of the length and the width.

[0090] Optionally, the width of the isolation trench is 50 μm-200 μm, such as 50 μm, 100 μm, 150 μm, 200 μm, etc.; the depth of the isolation trench is 0.5 μm-5.0 μm, such as 0.5 μm, 1.0 μm, 2.0 μm, 3.0 μm, 4.0 μm, 5.0 μm, etc. The horizontal direction of FIG. 1 can be the width direction, which is consistent with the width direction of the P-type doped region and the N-type doped region; the depth of the isolation trench refers to the height difference of the isolation trench and the N-type doped region at the end away from the front surface of the crystalline silicon substrate 1. The pitch between the two adjacent N-type doped regions is 0.5 mm-2.0 mm, such as 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, etc. The P-type doped region and the N-type doped region are distributed at equal intervals on the cell, and the pitch can be 0.5 mm-2.0 mm.

[0091] In some embodiments, the P-type doped region uses the boron diffusion doped layer 2 as the PN junction, the sheet resistance is 200 Ω / sq-1000 Ω / sq, the doping concentration is 7E17 cm -3 -7E18 cm -3 , and the junction depth is 0.3 μm-1.0 μm; optionally, the PN junction sheet resistance of the P-type doped region is 300 Ω / sq-800 Ω / sq, the doping concentration is 1E18 cm -3 -5E18 cm -3, and the junction depth is 0.5-0.8 μm, and the sheet resistance, the doping concentration and the junction depth are optimized, which is beneficial to further reduce the surface recombination of the non-metal region of the P region and improve the efficiency of the battery.

[0092] Specifically, the sheet resistance of the PN junction of the P-type doped region can be 200 Ω / sq, 300 Ω / sq, 400 Ω / sq, 600 Ω / sq, 800 Ω / sq, 1000 Ω / sq, etc.; and the junction depth can be 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, etc.

[0093] In some embodiments, the crystalline silicon substrate 1 is an N-type single crystal silicon, and the N-type doped region and the crystalline silicon substrate 1 are doped with different concentrations of phosphorus to form a high-low junction, the sheet resistance of the high-low junction is 10-100 Ω / sq, the doping concentration is 1E20 cm -3 -9E20 cm -3 , the junction depth is 0.07-0.5 μm, and the internal diffusion depth under the silicon substrate is 0.02-0.1 μm; optionally, the sheet resistance of the high-low junction of the N-type doped region is 10-50 Ω / sq, the doping concentration is 2E20 cm -3 -6E20 cm -3 , the junction depth is 0.1-0.4 μm, and the internal diffusion depth under the silicon substrate is 0.03-0.08 μm. By optimizing the sheet resistance, the doping concentration, the junction depth, the internal diffusion depth and other parameters of the high-low junction of the N-type doped region, the field passivation of the non-metal region of the N region is further improved, the metal recombination of the metal region of the N region is reduced, and the efficiency of the battery is improved.

[0094] Specifically, the sheet resistance of the high-low junction of the N-type doped region can be 10 Ω / sq, 30 Ω / sq, 50 Ω / sq, 80 Ω / sq, 100 Ω / sq, etc.; the doping concentration can be 1E20 cm -3 , 2E20 cm -3 , 5E20 cm -3 , 6E20 cm -3 , 9E20 cm -3 , etc.; the junction depth can be 0.07 μm, 0.10 μm, 0.20 μm, 0.30 μm, 0.40 μm, 0.50 μm, etc.; and the internal diffusion depth under the silicon substrate can be 0.02 μm, 0.03 μm, 0.05 μm, 0.08 μm, 0.10 μm, etc.

[0095] As shown in Fig. 1, in some embodiments, the distance between the phosphorus-doped silicon oxide layer 4 and the front surface of the crystalline silicon substrate 1 is less than the distance between the boron-diffusion-doped layer 2 and the front surface of the crystalline silicon substrate 1, and the distance between the second anti-reflective layer and the front surface of the crystalline silicon substrate 1 is less than the distance between the first anti-reflective layer and the front surface of the crystalline silicon substrate 1, so that the P-type doped region and the N-type doped region have a height difference at the end away from the front surface of the crystalline silicon substrate 1, which is caused by the complete removal of the boron-doped layer by wet etching after laser patterning and the laser damage process. In preferred embodiments, the height difference is 0.5 μm-5.0 μm, such as 0.5 μm, 1.0 μm, 2.0 μm, 3.0 μm, 4.0 μm, 5.0 μm, etc.

[0096] Optionally, the thickness of the crystalline silicon substrate 1 is 100 μm-150 μm (such as 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, etc.), the junction depth of the boron-diffusion-doped layer 2 is 0.3 μm-1 μm (such as 0.3 μm, 0.5 μm, 0.8 μm, 1.0 μm, etc.), the thickness of the phosphorus-doped silicon oxide layer 4 is 0.5 nm-3.0 nm (such as 0.5 nm, 1.0 nm, 2.0 nm, 3.0 nm, etc.), and the thickness of the phosphorus-doped polysilicon layer 5 is 50 nm-300 nm (such as 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc.).

[0097] Optionally, the thickness of the front passivation layer, the first passivation layer, the second passivation layer, and the third passivation layer is independently 2 nm-5 nm (such as 2 nm, 3 nm, 4 nm, 5 nm, etc.), and the thickness of the passivation layers in different regions can be the same or different. Similarly, the thickness of the front anti-reflective layer, the first anti-reflective layer, the second anti-reflective layer, and the third anti-reflective layer is independently 70 nm-100 nm (such as 70 nm, 80 nm, 90 nm, 100 nm, etc.), and the thickness of the anti-reflective layers in different regions can be the same or different.

[0098] Optionally, the material of the passivation layer 7 in each region is independently selected from at least one of Al2O3 and SiO2, and the material of the passivation layer 7 in different regions can be the same or different, preferably the same material, prepared by the same process.

[0099] Optionally, the material of the anti-reflective layer 8 in each region is independently selected from at least one of SiN x and SiO x N y , and the material of the anti-reflective layer 8 in different regions can be the same or different, preferably the same material, prepared by the same process.

[0100] It should be noted that the P-type doped region can be a planar structure or a textured structure, wherein the textured structure has a pyramid base size of 1-5 μm and a pyramid height of 0.5-2 μm; the N-type doped region can be a planar structure or a textured structure, wherein the textured structure has a pyramid base size of 1-5 μm and a pyramid height of 0.5-2 μm; and the isolation trench region can be a planar structure or a textured structure, wherein the textured structure has a pyramid base size of 1-5 μm and a pyramid height of 0.5-2 μm.

[0101] In some embodiments, the solar cell further comprises a first metal electrode disposed on the first type doped region and a second metal electrode disposed on the N-type doped region. The first metal electrode and the second metal electrode can be silver electrodes, and the details thereof can be found in the description of the preparation method.

[0102] In some embodiments, the first metal electrode and the second metal electrode each comprise a main grid electrode and a sub-grid electrode, and FIG. 1 only shows the first sub-grid electrode 9 and the second sub-grid electrode 10.

[0103] As shown in FIG. 2, the first metal electrode is in contact with the boron diffusion doped layer 2, and the contact surface of the first metal electrode and the boron diffusion doped layer 2 has a hole 15 and a conductive structure 16. The conductive structure 16 comprises a silver-silicon eutectic layer 161 close to the boron diffusion doped layer and a conductive crystalline body 162 extending from the silver-silicon eutectic layer 161 toward the hole 15.

[0104] Specifically, since the silver-silicon eutectic layer 161 comprises a eutectic body formed by a metal element (e.g., silver) in the metal electrode and a semiconductor element (Si), it not only facilitates the transportation of carriers from the substrate of the solar cell to the boron diffusion doped layer 2, but also has a lower contact resistance than the non-eutectic contact between metal particles and semiconductor materials. Since the silver-silicon eutectic layer is a eutectic body formed by silver and silicon elements, it has a lower resistivity and better conductivity than the direct contact between nano-silver powder and a silicon layer, i.e., a non-eutectic contact. The contact resistivity of the silver-silicon eutectic layer 161 is 0.1-2 mΩ·cm 2 (e.g., 0.1 Ω·cm 2 , 0.5 Ω·cm 2 , 1.0 Ω·cm 2 , 1.5 Ω·cm 2 , 2.0 Ω·cm 2 , etc.). The present disclosure forms a silver-silicon alloy layer with a low contact resistivity between the doped layer and the metal electrode under the condition of laser-induced sintering and reverse bias voltage loading.

[0105] It should be noted that the principle of forming the silver-silicon eutectic layer 161 by the laser-induced sintering process is as follows: the laser irradiation generates photo-generated carriers, which are gathered at the position of the fine grid under the action of the reverse bias, and the carriers are transported along the path with the highest conductivity, and a point with a diameter of about 300 nm-500 nm appears on the fine grid, and the instantaneous temperature can reach above 1000℃ (exceeding the melting point of silicon material), and the silver atoms in the slurry are melted at high temperature, and then diffuse into the crystalline silicon material to form a silver-silicon alloy, and the formed silver-silicon alloy has very high electrical conductivity.

[0106] Meanwhile, the conductive crystal 162 grown from the silver-silicon eutectic layer 161 towards the hole 15 includes a crystal formed by crystallization of a metal element (such as silver), which has a higher purity than the structure in which metal particles are in contact with a semiconductor material, and also has a lower resistivity and a better carrier transport capability. The conductive crystal 162 with high purity in the hole 15 can further reduce the loss of carriers transported from the silver-silicon eutectic layer 161 to the first metal electrode, thereby optimizing the contact performance of the first metal electrode and the boron diffusion doped layer 2 through the cooperation of the silver-silicon eutectic layer 161 and the conductive crystal 162 in the hole 15, and further improving the performance indicators such as the series resistance, short-circuit current and photoelectric conversion efficiency of the solar cell.

[0107] Optionally, as shown in FIGS. 2 and 3, the conductive crystal 162 includes a crystal main chain 1621 and a crystal side chain 1622 extending from the crystal main chain 1621 in a direction different from the growth direction of the crystal main chain 1621. In the embodiment of the present disclosure, the crystal main chain 1621 and the crystal side chain 1622 laterally grown from the crystal main chain 1621 make the conductive crystal 162 as a whole in a dendritic structure. Compared with the conductive crystal 162 (such as a rod-shaped conductive crystal 162) grown only in a single direction, the dendritic conductive crystal 162 can provide more transport channels for the carriers from the boron diffusion doped layer 2, and since the conductive crystal 162 is usually composed of higher-purity silver particle crystals, it has higher conductivity and is more conducive to reducing the transport loss of carriers.

[0108] The embodiment of the present disclosure provides a preparation method of a solar cell, including the following steps:

[0109] S1, providing a crystalline silicon substrate 1

[0110] As shown in FIG. 4, a crystalline silicon substrate 1 is provided, which has a front surface and a back surface opposite to the front surface, and the back surface is configured to prepare a PN region. The crystalline silicon substrate 1 can be an N-type single crystal silicon, and the silicon sheet resistivity is greater than 2Ω.cm.

[0111] In some embodiments, the crystalline silicon substrate 1 is pre-processed to prepare a polished surface. Specifically, the silicon wafer can be polished by using an alkaline solution.

[0112] In another embodiment, the crystalline silicon substrate 1 is pre-processed to prepare a textured surface. Specifically, the silicon wafer can be textured by using an additive to make the P-type doped region textured. The textured surface has a pyramid base size of 1-5 μm (e.g., 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, etc.) and a pyramid height of 0.5-2.0 μm (e.g., 0.5 μm, 1.0 μm, 1.5 μm, 2.0 μm, etc.).

[0113] It should be noted that the P-type doped region can also have a textured surface in addition to the polished surface, which can improve the double-sided rate of the solar cell.

[0114] S2, preparing an intermediate film layer with functional layers

[0115] The P-type doped region and the N-type doped region are alternately formed on the back surface of the crystalline silicon substrate 1, and an isolation trench is formed between adjacent P-type doped regions and N-type doped regions. Functional layers are formed on each region of the back surface of the crystalline silicon substrate 1 and the front surface of the crystalline silicon substrate 1 to obtain an intermediate film layer with functional layers.

[0116] As shown in FIG. 1, in the P-type doped region, a boron diffusion doped layer 2, a passivation layer 7 and an anti-reflection layer 8 are sequentially formed on the surface of the crystalline silicon substrate 1; in the N-type doped region, an N-type doped layer, a passivation layer 7 and an anti-reflection layer 8 are sequentially formed on the surface of the crystalline silicon substrate 1; and in the region where the isolation trench is located, a passivation layer 7 and an anti-reflection layer 8 are sequentially formed on the surface of the crystalline silicon substrate 1. The N-type doped layer of the N-type doped region includes a phosphorus-doped silicon oxide layer 4 and a phosphorus-doped polysilicon layer 5, which are sequentially arranged, and the phosphorus-doped polysilicon layer 5 is located between the silicon oxide layer and the second passivation layer 7. The thickness and parameters of each functional layer can refer to the description of the solar cell in the specification, which will not be repeated here.

[0117] The preparation process of the intermediate film layer includes: as shown in FIGS. 4-10, forming a boron diffusion doped layer 2, a phosphorus-doped silicon oxide layer 4 and a phosphorus-doped polysilicon layer 5 on the back surface of the crystalline silicon substrate 1, and at the same time, forming an intermediate protective layer and removing the film in a local manner to make the P-type doped region only retain the boron diffusion doped layer 2, the N-type doped region only retain the phosphorus-doped silicon oxide layer 4 and the phosphorus-doped polysilicon layer 5, and form a hollow groove region between the P-type doped region and the N-type doped region (structure as shown in FIG. 9). As shown in FIG. 10, the passivation layer 7 and the anti-reflection layer 8 corresponding to each region are formed on the P-type doped region, the N-type doped region and the hollow groove region of the back surface of the crystalline silicon substrate 1; and the passivation layer 7 and the anti-reflection layer 8 are formed on the front surface of the crystalline silicon substrate 1.

[0118] FIGS. 4-10 show the process of preparing the intermediate film layer, which specifically includes the following steps:

[0119] (1) As shown in FIG. 5, a boron diffusion doped layer 2 and a boron silicon glass layer 3 (BSG) are sequentially formed on the back surface of the crystalline silicon substrate 1, and the boron silicon glass layer 3 is configured as a subsequent protective layer. The boron diffusion doped layer 2 can be prepared by single-sided boron doping of the crystalline silicon substrate 1 through high-temperature boron diffusion, and the diffusion temperature is controlled to be 980-1050°C, such as 980°C, 1000°C, 1020°C, 1050°C, etc. The boron silicon glass layer 3 can be prepared by diffusion, and the thickness of the boron silicon glass layer 3 is controlled to be 20-100 nm, such as 20 nm, 50 nm, 80 nm, 100 nm, etc.

[0120] It should be noted that the P region in the cell adopts high sheet resistance and low recombination boron diffusion instead of LPCVD + boron doping, which reduces the process steps and time, thereby reducing the cost; the P region adopts high sheet resistance boron diffusion, which has better matching with laser and wet process than boron doping, thereby avoiding the problem that the polysilicon in the P region is difficult to remove by alkali etching due to the action of laser, and the patterning difficulty is greatly reduced.

[0121] (2) As shown in FIG. 6, laser is used for local film opening, and the opening width is 200-1000 μm, which is equal to the sum of one N-type doped region and two isolation trench regions, and the etching depth is deep into the crystalline silicon substrate 1, and the opening width is specifically obtained according to the width of the P region and the N region. The laser can be a picosecond (ps) or nanosecond (ns) pulse laser, which aims to remove the local BSG; then a slot wet alkali etching is used to remove the boron diffusion doped layer 2 in the laser region, and the silicon wafer is cleaned.

[0122] (3) As shown in FIG. 7, a phosphorus-doped silicon oxide layer 4, a phosphorus-doped polysilicon layer 5 and a phosphorus silicon glass layer 6 are sequentially formed on the entire back surface of the crystalline silicon substrate 1. In actual operation, low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) can be used to sequentially generate 1-3 nm of tunneling silicon oxide (SiO2) and 50-300 nm of intrinsic amorphous silicon film on the boron doped plane, and then high-temperature phosphorus diffusion is used for phosphorus doping of the silicon wafer, and the diffusion temperature is 800-900°C. Subsequently, a phosphorus silicon glass layer 6 (PSG) is formed on the surface, and the thickness of the PSG is 20-80 nm.

[0123] Specifically, the thickness of the tunneling silicon oxide (SiO2) can be 1 nm, 2 nm, 3 nm, etc., the thickness of the intrinsic amorphous silicon thin film can be 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc., and the phosphorus diffusion temperature can be 800°C, 850°C, 900°C, etc. The preparation method of the phosphosilicate glass layer 6 (PSG) is not limited, and can be an existing preparation method, such as a diffusion method to generate PSG, and the PSG thickness can be controlled to be 20 nm, 40 nm, 60 nm, 80 nm, etc.

[0124] In a preferred embodiment, the phosphorus-doped polysilicon layer 5 can be formed by plasma-enhanced chemical vapor deposition and annealing, which is simpler than low-pressure chemical vapor deposition operation.

[0125] (4) As shown in FIG. 8, local film opening is performed by laser to remove the phosphosilicate glass layer 6 on the P-type doped region, and the film opening width is greater than the width of the P-type doped region, and the difference between the film opening width and the width of the P-type doped region is 50 μm-200 μm, such as 50 μm, 100 μm, 150 μm, 200 μm, etc.

[0126] That is, the film opening width is 50 μm-200 μm wider than the P region, and the film opening process needs to leave the width of the isolation groove on both sides. The size of the film opening is determined according to the width of the two preset doped regions, so that the area ratio range of the first type of doped region and the N-type doped region is 0.5-2, and preferably 0.8-1.2.

[0127] Specifically, the laser can be a picosecond (ps) or nanosecond (ns) pulsed laser, and the purpose is to remove the excess PSG thin film above the P region.

[0128] (5) As shown in FIG. 9, chain acid etching and groove texturing treatment are performed on the front surface of the crystalline silicon substrate 1, and the back surface P-type doped region and the N-type doped region are respectively protected by BSG and PSG and will not be etched, while the n-poly layer of the region in the middle of the P and N junction regions without PSG protection is etched to form a region containing only a silicon substrate, and the width of the region is 50 μm-200 μm; then all the BSG and PSG on the back surface are removed by using groove HF solution, and the silicon wafer is cleaned. The P-type doped region only retains the boron diffusion doped layer 2, and the N-type doped region only retains the phosphorus-doped silicon oxide layer 4 and the phosphorus-doped polysilicon layer 5, and a hollow groove region is formed between the P-type doped region and the N-type doped region, and the width of the hollow groove region is 50 μm-200 μm.

[0129] (6) As shown in FIG. 10, the passivation layer 7 (including the first passivation layer, the second passivation layer and the third passivation layer) and the anti-reflection layer 8 (including the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer) corresponding to the P-type doped region, the N-type doped region and the hollow groove region on the back surface of the crystalline silicon substrate 1 are formed; the passivation layer 7 (front surface passivation layer) and the anti-reflection layer 8 (front surface anti-reflection layer) are also formed on the front surface of the crystalline silicon substrate 1.

[0130] Specifically, the passivation layer 7 can be an aluminum oxide (Al Ox) thin film, and the anti-reflection layer 8 can be a silicon nitride (SiNx) thin film, but is not limited thereto.

[0131] S3, preparing the main grid electrode and the auxiliary grid electrode

[0132] As shown in FIGS. 11 and 12, the main grid electrode and the auxiliary grid electrode are prepared on the intermediate film layer, and a complete cell structure is formed.

[0133] In some embodiments, a plurality of first auxiliary grid electrodes 9 and at least one first main grid electrode 11 are prepared on the P-type doped region of the intermediate film layer, and one first auxiliary grid electrode 9 is arranged corresponding to each P-type doped region, and the number of the first main grid electrode 11 is not limited. A plurality of second auxiliary grid electrodes 10 and at least one second main grid electrode 12 are prepared on the N-type doped region, and one second auxiliary grid electrode 10 is arranged corresponding to each N-type doped region, and the number of the second main grid electrode 12 is not limited.

[0134] Specifically, the first main grid electrode 11 is configured to connect a plurality of first auxiliary grid electrodes 9, each first auxiliary grid electrode 9 perpendicularly intersects the first main grid electrode 11 and is connected through the first main grid electrode 11. The second main grid electrode 12 is configured to connect a plurality of second auxiliary grid electrodes 10, each second auxiliary grid electrode 10 perpendicularly intersects the second main grid electrode 12 and is connected through the second main grid electrode 12.

[0135] Optionally, the first auxiliary grid electrode 9, the second auxiliary grid electrode 10, the first main grid electrode 11 and the second main grid electrode 12 can be prepared by screen printing, but are not limited thereto. When prepared by screen printing, the following steps are included: preparing first auxiliary grid paste, second auxiliary grid paste, first main grid paste and second main grid paste; printing the first auxiliary grid paste, the second auxiliary grid paste, the first main grid paste and the second main grid paste on the intermediate film layer respectively; sintering and light injection are performed on the cell piece after printing the paste, and the first auxiliary grid paste, the second auxiliary grid paste, the first main grid paste and the second main grid paste are simultaneously sintered, and the sintering temperature is controlled to be 700-800°C. Specifically, the sintering process is performed in a sintering furnace, and the sintering temperature can be 700°C, 730°C, 750°C, 780°C, 800°C, etc.

[0136] It should be noted that the vice-grid paste printing method is a step-by-step printing, and the order is to print the first vice-grid electrode 9 first and then print the second vice-grid electrode 10, or to print the second vice-grid electrode 10 first and then print the first vice-grid electrode 9; the first main grid paste and the second main grid paste are prepared by a single printing method.

[0137] S4, laser-induced sintering

[0138] After the complete cell piece structure is formed in step S3, laser-induced sintering is performed, and the P-type doped region is subjected to laser-induced sintering process (LIF), which can greatly reduce metal recombination and improve the open-circuit voltage of the cell, thereby improving the photoelectric conversion efficiency. Specifically, by using a laser to form a microstructure on the surface of the cell, an ohmic contact between the metal and the semiconductor is formed, thereby optimizing the contact structure of the cell, reducing the recombination loss of the electron-hole pairs in the metal region, and improving the efficiency of the cell.

[0139] In some embodiments, as shown in FIG. 12, the process of laser-induced sintering includes: applying a reverse bias to the main grid of the cell piece to form a loop, and then at least laser scanning the P-type doped region. The laser can scan the back surface of each cell piece or only scan the P-type doped region by controlling the precision of the laser. The reverse bias is controlled to be 10V-50V, the applied laser power is 20W-120W, and the laser scanning rate is 50mm / s-500mm / s. By further controlling the operation parameters of the laser, the contact performance of the P-type doped region can be further improved, and the metal recombination can be reduced.

[0140] Specifically, the reverse bias applied to the main grid of the cell piece can be 10V, 20V, 30V, 40V, 50V, etc., the applied laser power can be 20W, 50W, 80W, 100W, 120W, etc., and the laser scanning rate can be 50mm / s, 100mm / s, 150mm / s, 200mm / s, 300mm / s, 400mm / s, 500mm / s, etc.

[0141] Alternatively, the specific operation is as follows: the second probe row 14 is pressed on each first main grid electrode 11 on the P-type doped region, the second probe row 14 is pressed on each second main grid electrode 12 on the N-type doped region, and a certain constant reverse bias is applied to each main grid by the first probe row 13 and the second probe row 14 to form a loop, and laser scanning processing is performed at the same time.

[0142] It should be noted that the embodiment of the present disclosure adopts one-step boron diffusion in the P region to replace the conventional LPCVD deposition of intrinsic amorphous silicon + boron doping, forms a diffusion layer with high sheet resistance and low recombination in the non-metal region of the P region, and cooperates with the laser-assisted sintering technology to reduce the metal recombination of the metal region of the P region and improve the contact performance of the metal region of the P region. Not only can the process steps be reduced and the process time be saved, but also the effect of laser on the P region polycrystalline silicon is avoided, the patterning difficulty of the battery is reduced, and the production yield of the battery can be greatly improved.

[0143] The embodiment of the present disclosure also provides a photovoltaic module comprising the above-mentioned solar cell, which can be prepared by using the traditional back contact cell module interconnection method. Due to the improvement of the structure and process of the solar cell, the production yield and photoelectric conversion performance of the photovoltaic module are improved.

[0144] The features and performances of the present disclosure are further described in detail below in combination with embodiments.

[0145] Embodiment 1

[0146] The embodiment of the present disclosure provides a preparation method of a solar cell, as shown in FIGS. 4-12, comprising the following steps:

[0147] (1) As shown in FIG. 4, an N-type monocrystalline silicon wafer with a thickness of 145 μm (length and width are 210 μm and 182 μm, respectively) is provided, and a 5% (mass fraction, the same below) sodium hydroxide aqueous solution is used to polish and remove damage and clean the silicon wafer.

[0148] (2) As shown in FIG. 5, a single-side boron doping is performed on the silicon wafer by using a high-temperature boron diffusion method, the diffusion temperature is 1000°C, the boron raw material is BCl3, and a boron diffusion doping layer 2 with a junction depth of 0.5 μm is formed. A boron-silicon glass layer 3 (BSG) is formed on the surface of the boron diffusion doping layer 2 by using the diffusion method, and the thickness of the BSG is 45 nm. The prepared P-type doped region takes the boron diffusion doping layer 2 as the PN junction, the sheet resistance is 300 Ω / sq, the doping concentration is 3E18 cm -3 , and the junction depth is 0.5 μm.

[0149] (3) As shown in FIG. 6, a picosecond (ps) laser is used to locally open a film on the boron-doped surface, the opening width is 500 μm, and the local BSG is removed; then a slot wet alkali etching (the alkali is a 5% KOH aqueous solution) is used to remove the boron diffusion doping layer 2 in the laser area, and the silicon wafer is cleaned.

[0150] (4) As shown in Fig. 7, a low pressure chemical vapor deposition (LPCVD) is used to sequentially form a 1.5 nm tunneling silicon oxide (SiO2) and a 200 nm intrinsic amorphous silicon film; then a high temperature phosphorus diffusion is used to dope the silicon wafer with phosphorus, with a diffusion temperature of 850°C, to form a phosphorus-doped silicon oxide layer 4 and a phosphorus-doped polysilicon layer 5. A diffusion method is used to form a phosphosilicate glass layer 6 (PSG) on the surface, with a PSG thickness of 50 nm. The prepared N-type doped region and the crystalline silicon substrate 1 are doped with different concentrations of phosphorus, to form a high-low junction, with a sheet resistance of the high-low junction of 20 Ω / sq, a doping concentration of 3E20 cm -3 , and a junction depth of 0.27 μm.

[0151] (5) As shown in Fig. 8, a picosecond (ps) laser is used to locally open a film on a boron-doped plane, to remove the excess PSG film above the P region, and the opening width is slightly larger than that of the P region, with an opening width of 100 μm more than that of the P region. The width of the formed P-type doped region is 500 μm, the width of the N-type doped region is 400 μm, the width of the isolation trench is 100 μm, the distance between two adjacent N-type doped regions is 1 mm, and the area ratio of the first type of doped region to the N-type doped region is in a range of 1.25:1.

[0152] (6) As shown in Fig. 9, a chain acid etching (using a mixed solution of HF, HNO3 and H2SO4, with a total acid mass fraction of 10% in the mixed solution, and a volume ratio of HF:HNO3:H2SO4 of 1:3:1) and a tank-type texturing process are performed on the front surface of the silicon wafer, while the back surface P-type doped region and the N-type doped region are respectively protected by BSG and PSG and thus are not etched, while the n-poly layer in the region between the P and N junction regions without PSG protection is etched, to form a region containing only a silicon substrate, with a width of 50 μm; then a tank-type HF solution is used to remove all the BSG and PSG on the back surface, and the silicon wafer is cleaned.

[0153] (7) As shown in Fig. 10, an aluminum oxide (AlOx) film with a thickness of 4 nm and a silicon nitride (SiNx) anti-reflective film with a thickness of 75 nm are respectively deposited on the front and back surfaces of the silicon wafer. The aluminum oxide (AlOx) film deposition process is as follows: TMA (trimethylaluminum) and H2O are used as deposition raw materials, and an ALD method is used to deposit at 250°C. The silicon nitride (SiNx) anti-reflective film deposition process is as follows: NH3 and SiH4 are used as deposition raw materials, and a PECVD method is used to deposit at 500°C.

[0154] (8) As shown in Fig. 11, a first sub-gate electrode 9, a second sub-gate electrode 10, a first main-gate electrode 11 and a second main-gate electrode 12 are prepared, with the electrodes being silver paste, and the specific steps are as follows:

[0155] The first sub-grid paste, the second sub-grid paste, the first main-grid paste and the second main-grid paste are printed by screen printing, all the first sub-grid electrodes 9 perpendicularly intersect with the first main-grid electrodes 11 and are connected through the first main-grid electrodes 11, and all the second sub-grid electrodes 10 perpendicularly intersect with the second main-grid electrodes 12 and are connected through the second main-grid electrodes 12. The battery piece printed with the paste is sintered and light-injected, and the paste is simultaneously sintered, the sintering temperature is controlled at 750°C, and the sintering time is 100s.

[0156] (9) As shown in Fig. 12, each first main-grid electrode 11 on the P-type doped region is pressed by the first probe row 13, each second main-grid electrode 12 on the N-type doped region is pressed by the second probe row 14, and a certain constant reverse bias is applied to each main-grid by the first probe row 13 and the second probe row 14 to form a loop, and laser scanning processing is simultaneously performed. The reverse bias applied to the main-grid of the battery piece is 30V, the laser power is 100W, and the laser scanning speed is 100mm / s.

[0157] Example 2

[0158] The difference from Example 1 is that in step (9), the reverse bias applied to the main-grid of the battery piece is 35V, the laser power is 80W, and the laser scanning speed is 80mm / s.

[0159] Example 3

[0160] The difference from Example 1 is that in step (9), the reverse bias applied to the main-grid of the battery piece is 20V, the laser power is 150W, and the laser scanning speed is 120mm / s.

[0161] Example 4

[0162] The difference from Example 1 is that in step (2), the boron diffusion sheet resistance is 500Ω / sq, the doping concentration is 1E18cm -3 , and the junction depth is 0.4μm; in step (9), the reverse bias applied to the main-grid of the battery piece is 33V, the laser power is 120W, and the laser scanning speed is 100mm / s.

[0163] Comparative Example 1

[0164] The difference from Example 1 is that the boron diffusion doped layer 2 is not arranged in the P-type doped region, and a conventional LPCVD deposition of intrinsic amorphous silicon + boron diffusion is adopted, which is prepared as follows: in step (2), 1.8nm of tunneling silicon oxide layer and 300nm of intrinsic amorphous silicon layer are first deposited by LPCVD, and then boron diffusion is performed at a temperature of 950°C to form boron-doped polysilicon, the sheet resistance is 120Ω / sq, the doping concentration is 5E18cm -3The junction depth is 0.4 μm, i.e. the P region is composed of a tunneling oxide silicon and a boron-doped polysilicon.

[0165] Comparative Example 2

[0166] The difference from Example 1 is that step (9) is not performed.

[0167] Test Example 1

[0168] The solar cells prepared in the test examples and comparative examples were tested for photoelectric conversion efficiency Eta, open circuit voltage Voc, short circuit current density Jsc and fill factor FF, and the results are shown in Table 1.

[0169] Table 1 Comparison of properties of solar cells prepared in examples and comparative examples

[0170] As can be seen from Table 1, the solar cells prepared in the examples of the present disclosure have higher photoelectric conversion efficiency.

[0171] The above only is the preferred embodiment of the present disclosure, and is not used to limit the present disclosure, and the present disclosure can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure. Industrial applicability

[0172] The P-type doped region and the N-type doped region are alternately arranged on the back surface of the crystalline silicon substrate, the boron diffusion doped layer, the first passivation layer and the first anti-reflection layer are sequentially arranged in the P-type doped region, and the phosphorus-doped silicon oxide layer, the phosphorus-doped polysilicon layer, the second passivation layer and the second anti-reflection layer are sequentially arranged in the N-type doped region from the surface of the crystalline silicon substrate. The P region of the conventional TBC cell is more likely to use a two-step process of depositing intrinsic amorphous silicon + boron diffusion to form a polysilicon layer, and the P region of the present disclosure does not contain a polysilicon layer, which can be prepared by one-step boron diffusion process, thereby reducing the process steps and process time; also avoids the action of laser and P region polysilicon, reduces the patterning difficulty of the cell, and can greatly improve the production yield of the cell.

Claims

1. A solar cell, characterized by, The application relates to a solar cell, which comprises: a crystalline silicon substrate having a front surface and a back surface opposite to the front surface; a P-type doped region and an N-type doped region are alternately and spacedly arranged on the back surface of the crystalline silicon substrate; on the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; The P-type doped region takes the boron diffusion doped layer as a PN junction, has a sheet resistance of 200 Ω / sq-1000 Ω / sq, a doping concentration of 7E17 cm -3 -7E18 cm -3 , and a junction depth of 0.3 μm-1.0 μm; on the N-type doped region, an N-type doped layer, a second passivation layer and a second anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate, the N-type doped layer of the N-type doped region comprises a phosphorus-doped silicon oxide layer and a phosphorus-doped polysilicon layer which are sequentially arranged, and the phosphorus-doped polysilicon layer is located between the phosphorus-doped silicon oxide layer and the second passivation layer.

2. The solar cell according to claim 1, characterized in that, The PN junction sheet resistance of the P-type doped region is 300 Ω / sq-800 Ω / sq, the doping concentration is 1E18 cm -3 -5E18 cm -3 , and the junction depth is 0.5 μm-0.8 μm; Optionally, the P-type doped region is further provided with a first metal electrode, the N-type doped region is further provided with a second metal electrode, the first metal electrode is in contact with the boron diffusion doped layer, the contact surface of the first metal electrode and the boron diffusion doped layer has a hole and a conductive structure, the conductive structure comprises a silver-silicon eutectic layer close to the boron diffusion doped layer and a conductive crystalline body extending from the silver-silicon eutectic layer towards the hole, the silver-silicon eutectic layer comprises a eutectic body formed by silver elements and silicon elements, and the conductive crystalline body comprises a crystalline body formed by crystallization of silver elements. More optionally, the conductive crystalline body comprises a crystalline main chain and a crystalline side chain extending from the crystalline main chain towards a growth direction different from the crystalline main chain.

3. The solar cell of claim 1, wherein An isolation groove is arranged between adjacent P-type doped regions and N-type doped regions; on the region where the isolation groove is located, a third passivation layer and a third anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate; Optionally, the distance between the phosphorus-doped silicon oxide layer and the front surface of the crystalline silicon substrate is smaller than the distance between the boron diffusion doped layer and the front surface of the crystalline silicon substrate, and the distance between the second anti-reflection layer and the front surface of the crystalline silicon substrate is smaller than the distance between the first anti-reflection layer and the front surface of the crystalline silicon substrate, so that the P-type doped region and the N-type doped region have a height difference at the end far from the front surface of the crystalline silicon substrate; more optionally, the height difference is 0.5-5.0 mu m.

4. The solar cell according to claim 3, characterized in that, The depth of the boron diffusion doped layer of the P-type doped region is 0.3-1.0 mu m, the thickness of the phosphorus-doped silicon oxide layer is 0.5-3.0 nm, and the thickness of the phosphorus-doped polysilicon layer is 50-300 nm.

5. The solar cell of claim 3, wherein The crystalline silicon substrate is N-type monocrystalline silicon, the N-type doped region and the crystalline silicon substrate form a high-low junction, the square resistance of the high-low junction is 10Ω / sq-100Ω / sq, the doping concentration is 1E20cm -3 -9E20cm -3 , the junction depth is 0.07μm-0.5μm, and the internal diffusion depth under the silicon substrate is 0.02μm-0.1μm; Optionally, the N-type doped region has a high-low junction sheet resistance of 10 Ω / sq-50 Ω / sq, a doping concentration of 2-6E20 cm, a junction depth of 0.1 μm-0.4 μm, and an internal extension depth under the silicon substrate of 0.03 μm-0.08 μm. -3 , a junction depth of 0.1 μm-0.4 μm, and an internal extension depth under the silicon substrate of 0.03 μm-0.08 μm.

6. Solar cell according to any of claims 3-5, characterized in that, The width of the P-type doped region is 200-1000 mu m, and the width of the N-type doped region is 200-1000 mu m; Optionally, the area ratio of the P-type doped region and the N-type doped region is (0.5-2.0):1, preferably (0.8-1.2):1; Optionally, the width of the isolation groove is 50-200 mu m, and the depth of the isolation groove is 0.5-5.0 mu m; Optionally, the distance between two adjacent N-type doped regions is 0.5-2.0 mm. Optionally, the P-type doped region, the N-type doped region and the isolation trench correspond to the silicon substrate in a planar structure or a textured structure, and the textured structure has a pyramid base size of 1-5 μm and a tower height of 0.5-2.0 μm.

7. Solar cell according to any of claims 2-6, characterized in that, The first metal electrode of the P-type doped region comprises a plurality of first sub-gate electrodes and a first main gate electrode configured to connect the plurality of first sub-gate electrodes, and the second metal electrode on the N-type doped region comprises a plurality of second sub-gate electrodes and a second main gate electrode configured to connect the plurality of second sub-gate electrodes. Optionally, each of the first sub-gate electrodes perpendicularly intersects with the first main gate electrode and is connected through the first main gate electrode, and each of the second sub-gate electrodes perpendicularly intersects with the second main gate electrode and is connected through the second main gate electrode.

8. The solar cell of claim 3, wherein, On the front surface of the crystalline silicon substrate, a front passivation layer and a front anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate. Optionally, the front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer are independently selected from at least one of Al2O3 and SiO2. Optionally, the material of the front anti-reflective layer, the first anti-reflective layer, the second anti-reflective layer and the third anti-reflective layer are independently selected from at least one of SiN x and SiO x N y .

9. The solar cell of claim 3, wherein, The front passivation layer, the first passivation layer, the second passivation layer and the third passivation layer independently have a thickness of 2-5 nm. Optionally, the front anti-reflection layer, the first anti-reflection layer, the second anti-reflection layer and the third anti-reflection layer independently have a thickness of 70-100 nm. Optionally, the crystalline silicon substrate has a thickness of 100-150 μm.

10. A method of producing the solar cell according to any one of claims 1 to 9, characterized by, The method comprises: providing the crystalline silicon substrate having a front surface and a back surface opposite to the front surface; forming the P-type doped region and the N-type doped region alternately arranged on the back surface of the crystalline silicon substrate; and in the P-type doped region, a boron diffusion doped layer, a first passivation layer and a first anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate, the P-type doped region takes the boron diffusion doped layer as a PN junction, the sheet resistance is controlled to be 200Ω / sq-1000Ω / sq, the doping concentration is 7E17cm -3 -7E18cm -3 , and the junction depth is 0.3μm-1.0μm; on the N-type doped region, a phosphorus-doped silicon oxide layer, a phosphorus-doped polysilicon layer, a second passivation layer and a second anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate.

11. The production method according to claim 10, characterized by, The method comprises: forming an isolation trench on the back surface of the crystalline silicon substrate, and separating the back surface of the crystalline silicon substrate into the P-type doped region and the N-type doped region alternately arranged by using the isolation trench, and forming a functional layer on each region of the back surface of the crystalline silicon substrate and the front surface of the crystalline silicon substrate to obtain an intermediate film layer having a functional layer; preparing a plurality of first sub-gate electrodes and at least one first main gate electrode on the P-type doped region of the intermediate film layer, and preparing a plurality of second sub-gate electrodes and at least one second main gate electrode on the N-type doped region, and performing laser-induced sintering after forming a complete cell structure; Optionally, the process of laser-induced sintering comprises: forming a loop by applying a reverse bias on the cell main gate, and then performing laser scanning on at least the P-type doped region; the reverse bias is controlled to be 10-50 V, the applied laser power is 20-120 W, and the laser scanning rate is 50-500 mm / s.

12. The method of claim 11, wherein, At least laser-induced sintering is performed on the P-type doped region by using a first probe array to press on each of the first main grid electrodes on the P-type doped region, using a second probe array to press on each of the second main grid electrodes on the N-type doped region, and forming a loop by applying reverse bias to each main grid electrode by using the first probe array and the second probe array.

13. The preparation method according to claim 11, characterized in that, In the region where the isolation groove is located, a third passivation layer and a third anti-reflection layer are sequentially arranged from the surface of the crystalline silicon substrate. The preparation process of the intermediate film layer comprises: The boron diffusion doped layer, the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer are formed on the back surface of the crystalline silicon substrate, and meanwhile, the P-type doped region is only left with the boron diffusion doped layer, the N-type doped region is only left with the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer, and a hollow groove region is formed between the P-type doped region and the N-type doped region by means of forming an intermediate protection layer and locally opening the film to remove the intermediate protection layer; A passivation layer and an anti-reflection layer corresponding to each region are formed on the P-type doped region, the N-type doped region and the hollow groove region on the back surface of the crystalline silicon substrate; a front passivation layer and a front anti-reflection layer are formed on the front surface of the crystalline silicon substrate.

14. The method of claim 13, wherein, The process of forming the hollow groove region comprises: pre-treating the back surface of the crystalline silicon substrate, sequentially forming the boron diffusion doped layer and a borosilicate glass layer on the back surface of the crystalline silicon substrate, locally opening the film by using a laser, removing the borosilicate glass layer in the local area by using the laser, removing the boron diffusion doped layer in the laser area by using an alkali etching method, the width of the film opening is equal to the sum of one N-type doped region and two isolation groove regions, and the etching depth is deep into the crystalline silicon substrate; The phosphorus-doped silicon oxide layer, the phosphorus-doped polysilicon layer and a phosphosilicate glass layer are sequentially formed on the entire back surface of the crystalline silicon substrate; The phosphosilicate glass layer on the P-type doped region is removed by locally opening the film by using a laser, and the film opening width is greater than the width of the P-type doped region, and the difference between the film opening width and the width of the P-type doped region is 50-200 μm; The front surface of the crystalline silicon substrate is subjected to acid etching and groove texturing treatment, so that the regions protected by the borosilicate glass layer and the phosphosilicate glass layer are not etched, and then all the borosilicate glass layers and the phosphosilicate glass layers on the back surface are removed by etching, so that the P-type doped region is only left with the boron diffusion doped layer, the N-type doped region is only left with the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer, and a hollow groove region is formed between the P-type doped region and the N-type doped region, and the width of the hollow groove region is 50-200 μm; Optionally, the pre-treatment is to prepare a polished surface or a textured surface. Optionally, the crystalline silicon substrate is subjected to single-side boron doping by means of high-temperature boron diffusion, and the diffusion temperature is controlled to be 980-1050 °C, so as to form the boron diffusion doped layer. Optionally, the thickness of the borosilicate glass layer is 20-100 nm, and the thickness of the phosphosilicate glass layer is 20-80 nm. Optionally, the process of forming the phosphorus-doped silicon oxide layer and the phosphorus-doped polysilicon layer comprises: forming a tunneling silicon oxide layer with a thickness of 1-3 nm and an intrinsic amorphous silicon film with a thickness of 50-300 nm by chemical vapor deposition, and then performing high-temperature phosphorus diffusion at a temperature of 800-900 °C. Optionally, the phosphorus-doped polysilicon layer is formed by plasma-enhanced chemical vapor deposition and annealing.

15. The method of any one of claims 10-14, wherein, The first sub-grid electrode, the second sub-grid electrode, the first main-grid electrode and the second main-grid electrode are prepared by screen printing.

16. The method of claim 15, wherein, The process of preparing the sub-grid electrodes and the main-grid electrodes comprises: preparing a first sub-grid paste, a second sub-grid paste, a first main-grid paste and a second main-grid paste; printing the first sub-grid paste, the second sub-grid paste, the first main-grid paste and the second main-grid paste on the intermediate film layer, respectively; sintering and light injection are performed on the cell with the printed paste, and the sintering temperature is controlled at 700-800 °C.

17. A photovoltaic module, characterized by The photovoltaic module comprises the solar cell prepared by the method of any one of claims 1-9 or any one of claims 10-16.

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