A silicon carbide trench power device and method of manufacturing the same

Abstract

The application provides a silicon carbide trench power device and a manufacturing method thereof, and belongs to the technical field of semiconductor power devices. Aiming at the problems of high specific on-resistance, contradiction between gate oxide reliability and conductive channel and the like of a traditional silicon carbide trench MOSFET, a new structure and a manufacturing process are provided. The device comprises a semiconductor drain region, a drift region and a second conductive type semiconductor well region, a carrier diffusion layer is arranged at a first trench corner, the Z direction of the carrier diffusion layer passes through a semiconductor shielding region lead-out end, meanwhile, the semiconductor shielding region lead-out end of a side edge of the first trench is in stage distribution in the Z direction, the semiconductor shielding region directly below the first trench is in continuous distribution, and a second trench formed by over-etching silicon carbide is arranged in an interlayer dielectric layer. The carrier diffusion layer sacrifices the conductive channel which is not shielded by the lead-out end, and the second trench increases the ohmic contact area; by arranging a series of structures in the application, the specific on-resistance of the device can be significantly optimized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor power devices, and more particularly relates to a silicon carbide trench power device and a manufacturing method thereof. BACKGROUND

[0002] In recent years, silicon carbide trench MOSFET power devices have been vigorously developed by researchers due to their smaller cell size and higher channel density, among which silicon carbide trench MOSFET represented by Infineon has been mass-produced. However, the structure of the silicon carbide trench MOSFET sacrifices half of the conductive channel to ensure the reliability of the gate oxide, so the specific on-resistance is not significantly reduced compared with the silicon carbide planar MOSFET.

[0003] The carrier diffusion layer formed by the semiconductor region at the first trench corner can make the electrons on the semiconductor shielding zone extraction side flow to the semiconductor drain zone from the Z direction without the semiconductor shielding zone extraction region when the device is in forward conduction, so the semiconductor shielding zone extraction end does not sacrifice the conductive channel. Further, the second trench is prepared on the basis of the first contact hole, and as the depth of the second trench increases and the width decreases, the surface area of the second trench increases, thereby increasing the ohmic contact area of the device. By setting a series of structures in the present application, the specific on-resistance of the device can be significantly optimized. SUMMARY

[0004] To solve the above technical problems, the present application provides a silicon carbide trench power device and a manufacturing method thereof to solve the above problems.

[0005] A silicon carbide trench power device, comprising:

[0006] Semiconductor drain region: a heavily doped first conductive type semiconductor material;

[0007] Semiconductor buffer region: a first conductive type semiconductor material with a doping concentration only second to the semiconductor drain region;

[0008] Semiconductor drift region: a lightly doped first conductive type semiconductor material located above the semiconductor buffer region;

[0009] Second conductive type semiconductor well region: a doping concentration higher than the semiconductor drift region, located at the top of the semiconductor drift region;

[0010] First conductive type semiconductor source region: heavily doped, located at the middle position of the top of the semiconductor well region;

[0011] Second conductive type semiconductor body contact region: located at the top of the semiconductor well region and away from the middle position;

[0012] Second-conductivity-type semiconductor shield region lead-out end -: arranged in the middle of the upper part of the semiconductor drift region in the Z direction;

[0013] First trench: located in the middle of the top of the semiconductor drift region, extending from the semiconductor source region to the inside of the semiconductor drift region;

[0014] First-conductivity-type semiconductor carrier diffusion layer: located next to the corner of the first trench;

[0015] Second-conductivity-type semiconductor shield region: located directly below the first trench;

[0016] Gate dielectric layer: covering the inner wall of the first trench;

[0017] Gate electrode: located on the gate dielectric layer;

[0018] Interlayer dielectric layer: covering the gate electrode;

[0019] Contact hole: arranged in the interlayer dielectric layer, with the bottom over-etching silicon carbide to form a second trench;

[0020] Source metal electrode: forming ohmic contact with the semiconductor source region and the semiconductor body contact region through the second trench;

[0021] Drain metal electrode: located below the semiconductor drain region and forming ohmic contact.

[0022] Preferably, the second-conductivity-type semiconductor shield region lead-out end is distributed in stages in the Z direction, with a thickness T1 that is at least 5% greater than the depth of the first trench, and a width W1 that is at least 80% wider than the first trench. The depth of the second-conductivity-type semiconductor shield region is determined by the energy of high-energy ion implantation, and the depth is T2.

[0023] Preferably, the initial depth T3 of the first trench is less than the depth of the second-conductivity-type semiconductor well region.

[0024] Preferably, the first trench is formed by the following steps:

[0025] Covering the initial first trench with a thickness of T3 with a hard mask HM2;

[0026] Etching the hard mask HM2 to expose the silicon carbide at the bottom of the trench, and after thermal oxidation, removing the oxidation layer by wet etching to remove the amorphous region at the bottom of the trench, and finally making the depth of the first trench exceed the depth of the second-conductivity-type semiconductor well region by more than 0.1 μm.

[0027] Preferably, the first-conductivity-type semiconductor carrier diffusion layer is formed by oblique-angle ion implantation in the semiconductor region at the corner of the first trench, with a net impurity doping concentration of 5×10 15 cm 3 ~5×10 17cm-2 3 .

[0028] Preferably, the depth T4 of the second groove can be 0.15 μm, and the width W4 can be 0.1 μm, and the surface area increases with the increase of T4 and the decrease of W4, so as to reduce the ohmic contact resistance.

[0029] Another technical problem to be solved by the present application is to provide a manufacturing method of a silicon carbide trench power device, comprising the following steps:

[0030] S1 layer stack preparation:

[0031] Semiconductor buffer region (2): a first conductive type semiconductor layer is epitaxially grown above the heavily doped first conductive type (N type) semiconductor drain region (1), the doping concentration is 1×10 18 cm-2 3 ~5×10 18 cm-2 3 , and the thickness is 0.5 μm~1.5 μm, serving as a buffer region;

[0032] Semiconductor drift region (3): a lightly doped first conductive type semiconductor layer is epitaxially grown above the buffer region, the doping concentration is 1×10 15 cm-2 3 ~1×10 17 cm-2 3 , and the thickness is 3 μm~100 μm, forming a drift region;

[0033] S2 well region and contact region formation:

[0034] Second conductive type semiconductor well region (4): a P type semiconductor well region is formed at the top of the drift region by multiple aluminum ion implantation (dose 5×10 11 cm-2 2 ~5×10 13 cm-2 2 ), the depth is 0.5 μm~1.2 μm, and the doping concentration is higher than that of the drift region;

[0035] Second conductive type semiconductor body contact region (6): a heavily doped P type body contact region is formed at the top of the well region away from the middle position by high-dose aluminum ion implantation (dose 5×10 14 cm-2 2 ~5×10 15 cm-2 2 );

[0036] Second conductive type semiconductor shielding region lead-out end (7-1): a shielding region lead-out end is formed at the middle position of the top of the well region by aluminum ion implantation (dose 1×10 12 cm-2 2 ~5×10 13pieces / cm 2 ), forming a P-type shielding region lead-out terminal distributed in segments along the Z direction, with a thickness T1 = 0.8μm~1.5μm and a width W1 = 0.5μm~3.6μm. The wide W1 can prevent the semiconductor shielding region lead-out terminal from being exhausted during reverse operation, thereby affecting the reliability and short-circuit capability of the device;

[0037] S3 first trench and shielding area are formed:

[0038] Initial first trench (8): by photolithography and etching process, an initial trench is etched in the middle of the top of the drift region below the semiconductor source region, with a depth T3 = 0.3 μm ~ 0.6 μm and a width of 0.25 μm ~ 2 μm;

[0039] Second conductive type semiconductor shielding region (7-2): Then, aluminum ions (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region with a depth of T2 = 0.9 μm;

[0040] S4 trench optimization and carrier diffusion layer formation:

[0041] Adjusting the trench depth: covering the hard mask HM2, exposing the bottom of the trench after etching, and then thermally oxidizing and wet etching the amorphous region at the bottom of the trench so that the final depth of the first trench (8) exceeds the well region by 0.1 μm, forming a trench with a depth of 0.6 μm to 1.3 μm;

[0042] The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique nitrogen ion implantation (dose 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 ), forming an N-type carrier diffusion layer at the corner of the trench, and then removing the hard mask HM2;

[0043] S5 gate and interlayer dielectric preparation:

[0044] Gate structure: thermally oxidizing the inner wall of the trench to form a gate dielectric layer (10) with a thickness of 0.05 to 0.1 μm, depositing heavily doped polysilicon and etching back to form a gate electrode (11) 0.05 to 0.1 μm below the silicon carbide plane;

[0045] Interlayer dielectric and contact hole: depositing non-doped silicon oxide and borophosphosilicate glass (total thickness 0.8 μm) as an interlayer dielectric layer (12), etching the contact hole (13-1) and over-etching silicon carbide to form a second trench (13-2), such as a depth T4 = 0.15 μm and a width W4 = 0.1 μm;

[0046] S6 metal electrode preparation:

[0047] Source end metal electrode (14): nickel, titanium, titanium nitride, aluminum-copper alloy is sputtered above the interlayer dielectric, and an electrode is formed by etching, and an ohmic contact is formed with the first conductive type semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second trench (13-2);

[0048] Drain metal electrode (15): Nickel, titanium, nickel, and silver are sputtered below the drain region to form an electrode, forming an ohmic contact with the semiconductor drain region (1).

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] In the present invention, by introducing a carrier diffusion layer at the corner of the first trench, electrons on the lead-out side of the semiconductor shielding region can flow directly to the semiconductor drain region along the Z direction without the shielding region, thus avoiding the sacrifice of the shielding region to the conductive channel in the traditional structure. The net impurity concentration of the carrier diffusion layer formed by oblique ion implantation reaches 5×10 15 ~5×10 17 pieces / cm 3 , ensuring that the channel resistance is reduced during forward conduction. Combined with the surface area optimization of the second trench, the device's specific on-resistance is significantly reduced compared to traditional silicon carbide trench MOSFETs, significantly improving current conduction efficiency.

[0051] In the present invention, the thickness T1 of the semiconductor shielding region's lead-out end is at least 5% greater than the depth of the first trench, and the width W1 is at least 80% greater than the first trench's width. This wide width W1 effectively prevents depletion during reverse operation, improving the device's short-circuit capability and reliability. A second-conductivity semiconductor shielding region directly below the first trench is formed by high-energy ion implantation to a depth T2.

[0052] In the present invention, the manufacturing process uses a hard mask HM2 protection and a thermal oxidation wet etching process to precisely control the depth of the first trench to at least 0.1μm beyond the semiconductor well region, effectively eliminating amorphization defects at the trench bottom caused by high-energy implantation and preventing abnormal increases in leakage current. The segmented semiconductor shielding region lead-out terminals formed by ion implantation are distributed in stages along the Z direction, short-circuiting the second conductivity type semiconductor shielding region directly below the first trench with the source metal electrode, significantly improving device reliability.

[0053] In the application, through the synergistic design of the "carrier diffusion layer-segmented shielding area lead-out end-deep and narrow second trench", the contradiction between "gate oxide reliability and conductive channel" of traditional silicon carbide trench devices is broken. Compared with the planar MOSFET, the on-resistance is reduced under the same breakdown voltage; compared with the existing trench structure, the short circuit resistance is improved, and the leakage current is reduced, which provides an efficient solution for high-voltage and high-frequency scenarios (such as new energy vehicles and photovoltaic inverters), and promotes the commercialization application process of silicon carbide power devices. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a structural schematic diagram of embodiment 1 of the application;

[0055] Figure 2 is a structural schematic diagram of the initial structure manufactured in embodiment 1 of the application;

[0056] Figure 3 is a structural schematic diagram of the semiconductor shielding area lead-out end formed in embodiment 1 of the application;

[0057] Figure 4 is a structural schematic diagram of the semiconductor source area formed in embodiment 1 of the application;

[0058] Figure 5 is a structural schematic diagram of the semiconductor shielding area formed in embodiment 1 of the application;

[0059] Figure 6 is a structural schematic diagram of the carrier diffusion layer formed in embodiment 1 of the application;

[0060] Figure 7 is a schematic diagram of the gate structure formed in embodiment 1 of the application;

[0061] Figure 8 is a structural schematic diagram of the second trench formed in embodiment 1 of the application Figure 1 ;

[0062] Figure 9 is a structural schematic diagram of the second trench formed in embodiment 1 of the application Figure 2 ;

[0063] Figure 10 is a structural schematic diagram of the metal electrode formed in embodiment 1 of the application;

[0064] Figure 11 is a structural schematic diagram of embodiment 2 of the application.

[0065] In the figure, the correspondence between the component names and the reference signs is as follows: 1, semiconductor drain region; 2, semiconductor buffer region; 3, semiconductor drift region; 4, second-conductivity-type semiconductor well region; 5, first-conductivity-type semiconductor source region; 6, second-conductivity-type semiconductor body contact region; 7-1, second-conductivity-type semiconductor shielding region lead-out end; 8, first trench; 9, first-conductivity-type semiconductor carrier diffusion layer; 10, gate dielectric layer; 7-2, second-conductivity-type semiconductor shielding region; 11, gate electrode; 12, interlayer dielectric layer; 13-1, contact hole; 13-2, second trench; 14, source metal electrode; 15, drain metal electrode. DETAILED DESCRIPTION

[0066] The embodiments of the present application will be further described below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present application, but cannot be used to limit the scope of the present application. Example 1

[0067] Reference Figures 1-10 The specific structure and manufacturing steps of the silicon carbide trench power device are as follows:

[0068] 1. Laminated structure preparation:

[0069] Semiconductor buffer region (2): a first-conductivity-type semiconductor layer is epitaxially grown above the heavily doped first-conductivity-type (N-type) semiconductor drain region (1), with a doping concentration of 1×10 18 ~5×10 3 cm 18 ~1×10 3 cm

[0070] Semiconductor drift region (3): a lightly doped first-conductivity-type semiconductor layer is epitaxially grown above the buffer region, with a doping concentration of 1×10 15 ~1×10 3 cm 17 ~1×10 3 cm

[0071] 2. Well region and contact region formation:

[0072] Second-conductivity-type semiconductor well region (4): a P-type semiconductor well region is formed at the top end of the drift region by multiple aluminum ion implantation (dose 5×10 11 ~5×10 2 cm 13 ~1×10 2 cm

[0073] Second conductive type semiconductor body contact region (6): at the top of the well region away from the middle position, by high dose aluminum ion implantation (dose 5×10 14 cm 2 ~5×10 15 cm 2 ), a heavily doped P-type body contact region is formed;

[0074] Second conductive type semiconductor shielding region lead-out end (7-1): at the top of the well region in the middle position, by aluminum ion implantation (dose 1×10 12 cm 2 ~5×10 13 cm 2 ), a P-type shielding region lead-out end is formed along the Z direction, the thickness T1=0.8μm~1.5μm, the width W1=0.5μm~3.6μm, the wide W1 can avoid the semiconductor shielding region lead-out end being depleted when working in reverse, thereby affecting the reliability and short circuit capability of the device;

[0075] 3. First trench and shielding region formation:

[0076] Initial first trench (8): by lithography and etching process, an initial trench is etched at the top of the drift region below the semiconductor source region in the middle position, the depth T3=0.3μm~0.6μm, the width 0.25μm~2μm;

[0077] Second conductive type semiconductor shielding region (7-2): then with the hard mask HM1 remaining when the trench is prepared as a barrier, aluminum ions are injected (dose 1×10 12 cm 2 ~5×10 13 cm 2 ) to the bottom of the trench to form a P-type shielding region, the depth is T2=0.9μm;

[0078] 4. Trench optimization and carrier diffusion layer formation:

[0079] Trench depth adjustment: cover the hard mask HM2, after etching, the bottom of the trench is exposed, then by thermal oxidation and wet etching of the amorphous region at the bottom of the trench, the final depth of the first trench (8) exceeds the well region by 0.1μm, forming a trench with a depth of 0.6μm~1.3μm;

[0080] First conductive type semiconductor carrier diffusion layer (9): by oblique angle nitrogen ion implantation (dose 5×10 15 cm 3 ~5×10 17 cm 3 ), an N-type carrier diffusion layer is formed at the corner of the trench, and then the hard mask HM2 is removed;

[0081] 5. Gate and ILD preparation:

[0082] Gate structure: Thermal oxidation on the inner wall of the trench to form gate dielectric layer (10), thickness 0.05-0.1 μm, deposition of heavily doped polysilicon and etch back to form gate electrode (11), 0.05-0.1 μm below the silicon carbide plane;

[0083] ILD and contact hole: Deposition of undoped silicon oxide and boron phosphorus silicon glass (total thickness 0.8 μm) as ILD layer (12), etching of contact hole (13-1) and over-etching of silicon carbide to form second trench (13-2), such as depth T4=0.15 μm, width W4=0.1 μm;

[0084] 6. Metal electrode preparation:

[0085] Source metal electrode (14): Sputtering of nickel, titanium, titanium nitride, aluminum copper alloy above the ILD, etching to form the electrode, forming ohmic contact with the first conductivity type semiconductor source region (5) and the second conductivity type semiconductor body contact region (6) through the second trench (13-2);

[0086] Drain metal electrode (15): Sputtering of nickel, titanium, nickel, silver below the drain region to form the electrode, forming ohmic contact with the semiconductor drain region (1). Example 2

[0087] Reference Figure 11 The difference from Example 1 is the timing of the preparation of the semiconductor shield region lead-out 7-1:

[0088] After the first trench depth exceeds the semiconductor well region depth (such as 1.2 μm), a Z-direction segmented window is defined by photoresist, and aluminum ions are obliquely implanted (dose 1 x 10 12 / cm 2 ~5 x 10 13 / cm 2 ), forming a segmented distribution of shield region lead-outs, and the subsequent process is consistent with Example 1.

[0089] The embodiments of the present application are given for the purpose of illustration and description, and are not intended to be exhaustive or to limit the application to the disclosed form. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, and to enable others skilled in the art to understand the application for various embodiments with various modifications as are suited to the particular use contemplated.

Claims

1. A silicon carbide trench power device, characterized in that: include: Semiconductor drain region (1): heavily doped first conductivity type semiconductor material; Semiconductor buffer region (2): a first conductive type semiconductor material having a doping concentration second only to that of the semiconductor drain region (1); Semiconductor drift region (3): lightly doped first conductivity type semiconductor material, located above the semiconductor buffer region (2); A second conductive type semiconductor well region (4): having a higher doping concentration than the semiconductor drift region (3) and located at the top of the semiconductor drift region (3); The first conductive type semiconductor source region (5) is heavily doped and is located in the middle of the top of the second conductive type semiconductor well region (4); A second conductive type semiconductor body contact region (6): located at the top of the semiconductor well region (4) and away from the middle; A second conductive type semiconductor shielding region lead-out terminal (7-1) is segmented and arranged in the middle of the upper portion of the semiconductor drift region (3) along the Z direction; A first trench (8): located in the middle of the top of the semiconductor drift region (3), extending from the first conductive type semiconductor source region (5) to the interior of the semiconductor drift region (3); A first conductive type semiconductor carrier diffusion layer (9): adjacent to a corner of the first trench (8); A second conductive type semiconductor shielding region (7-2) is located directly below the first trench (8); Gate dielectric layer (10): covering the inner wall of the first trench (8); Gate electrode (11): located on the gate dielectric layer (10); Interlayer dielectric layer (12): covering the gate electrode (11); A contact hole (13-1) is provided in the interlayer dielectric layer (12), and the bottom of the contact hole is over-etched with silicon carbide to form a second trench (13-2); A source metal electrode (14) forms an ohmic contact with the semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second groove (13-2); Drain metal electrode (15): located below the semiconductor drain region (1) and forming an ohmic contact.

2. A silicon carbide trench power device according to claim 1, characterized in that: The thickness of the second conductive type semiconductor shielding region lead-out end (7-1) is T1, which is at least greater than 5% of the depth of the first trench (8); and the width thereof is W1, which is at least wider than 80% of the first trench (8).

3. The silicon carbide trench power device according to claim 1, wherein: The depth of the second conductive type semiconductor shielding region (7-2) continuously distributed below the first trench is determined by the energy of the high energy ion implantation, and the depth is T2.

4. A silicon carbide trench power device according to claim 1, characterized in that: The initial depth T3 of the first trench (8) is less than the depth of the second conductive type semiconductor well region (4).

5. The silicon carbide trench power device according to claim 1, characterized in that: The first trench (8) is formed by the following steps: Covering the initial first trench (8) with a hard mask HM2 having a thickness T3; The hard mask HM2 is etched to expose the silicon carbide at the bottom of the trench, and then a second conductive type semiconductor shielding region (7-2) with a depth of T2 is formed at the bottom of the initial first trench by high-energy ion implantation. Considering that high-energy particles will cause the bottom of the initial first trench to become amorphous, thermal oxidation is performed, and then the oxide layer, i.e., the amorphous region at the bottom of the trench, is removed by wet etching, so that the depth of the first trench (8) is finally made to exceed the depth of the second conductive type semiconductor well region (4) by more than 0.1 μm.

6. The silicon carbide trench power device according to claim 1, characterized in that: The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique angle ion implantation in the semiconductor region at the corner of the first trench (8), and its net impurity doping concentration can be 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 .

7. The silicon carbide trench power device according to claim 1, characterized in that: The depth T4 of the second trench (13-2) may be 0.15 μm, and the width W4 may be 0.1 μm, and the surface area thereof increases as T4 increases and W4 decreases, thereby reducing the ohmic contact resistance.

8. A method for manufacturing a silicon carbide trench power device according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1 stacked structure preparation: Semiconductor cache region (2): a first conductive type semiconductor layer is epitaxially grown on the heavily doped first conductive type (N type) semiconductor drain region (1), with a doping concentration of 1×10 18 pieces / cm 3 ~5×10 18 pieces / cm 3 , thickness 0.5μm~1.5μm, as a buffer area; Semiconductor drift region (3): A lightly doped first conductivity type semiconductor layer is grown epitaxially above the buffer region, with a doping concentration of 1×10 15 pieces / cm 3 ~1×10 17 pieces / cm 3 , with a thickness of 3μm~100μm, forming a drift region; S2 well region and contact region are formed: The second conductive type semiconductor well region (4): is formed at the top of the drift region by multiple aluminum ion implantations (dose 5×10 11 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type semiconductor well region with a depth of 0.5μm~1.2μm and a doping concentration higher than that of the drift region; The second conductive type semiconductor body contact region (6): at the top of the well region away from the middle position, by high-dose aluminum ion implantation (dose 5×10 14 pieces / cm 2 ~5×10 15 pieces / cm 2 ), forming a heavily doped P-type body contact region; The second conductive type semiconductor shielding region lead-out terminal (7-1): in the middle of the top of the well region, by aluminum ion implantation (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region lead-out terminal distributed in segments along the Z direction, with a thickness T1 = 0.8μm~1.5μm and a width W1 = 0.5μm~3.6μm. The wide W1 can prevent the semiconductor shielding region lead-out terminal from being exhausted during reverse operation, thereby affecting the reliability and short-circuit capability of the device; S3 first trench and shielding area are formed: Initial first trench (8): by photolithography and etching process, an initial trench is etched in the middle of the top of the drift region below the semiconductor source region, with a depth T3 = 0.3 μm ~ 0.6 μm and a width of 0.25 μm ~ 2 μm; Second conductive type semiconductor shielding region (7-2): Then, aluminum ions (dose 1×10 12 pieces / cm 2 ~5×10 13 pieces / cm 2 ), forming a P-type shielding region with a depth of T2 = 0.9 μm; S4 trench optimization and carrier diffusion layer formation: Adjusting the trench depth: covering the hard mask HM2, exposing the bottom of the trench after etching, and then thermally oxidizing and wet etching the amorphous region at the bottom of the trench so that the final depth of the first trench (8) exceeds the well region by 0.1 μm, forming a trench with a depth of 0.6 μm to 1.3 μm; The first conductive type semiconductor carrier diffusion layer (9) is formed by oblique nitrogen ion implantation (dose 5×10 15 pieces / cm 3 ~5×10 17 pieces / cm 3 ), forming an N-type carrier diffusion layer at the corner of the trench, and then removing the hard mask HM2; S5 gate and interlayer dielectric preparation: Gate structure: thermally oxidizing the inner wall of the trench to form a gate dielectric layer (10) with a thickness of 0.05 to 0.1 μm, depositing heavily doped polysilicon and etching back to form a gate electrode (11) 0.05 to 0.1 μm below the silicon carbide plane; Interlayer dielectric and contact hole: depositing non-doped silicon oxide and borophosphosilicate glass (total thickness 0.8 μm) as an interlayer dielectric layer (12), etching the contact hole (13-1) and over-etching silicon carbide to form a second trench (13-2), such as a depth T4 = 0.15 μm and a width W4 = 0.1 μm; S6 metal electrode preparation: Source end metal electrode (14): nickel, titanium, titanium nitride, aluminum-copper alloy is sputtered above the interlayer dielectric, and an electrode is formed by etching, and an ohmic contact is formed with the first conductive type semiconductor source region (5) and the second conductive type semiconductor body contact region (6) through the second trench (13-2); Drain metal electrode (15): Nickel, titanium, nickel, or silver is sputtered below the drain region to form an electrode, forming an ohmic contact with the semiconductor drain region (1).

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