Semiconductor devices and their fabrication methods, chips

Abstract

This disclosure provides a semiconductor device and its fabrication method, and a chip, relating to the field of semiconductor chip technology, aiming to solve the problem of poor adhesion between electrodes and the surface of a diamond substrate; the semiconductor device includes a diamond substrate, a dielectric layer, electrodes, and a gate; the dielectric layer is disposed on one side of the diamond substrate; the gate is disposed on the side of the dielectric layer away from the diamond substrate; the electrodes are disposed on one side of the diamond substrate and are located on the same side of the diamond substrate as the dielectric layer; the electrodes include a first electrode and a second electrode, and the dielectric layer is at least partially disposed between the first electrode and the second electrode; the gate is disposed on the side of the dielectric layer away from the diamond substrate; wherein, the electrodes include a first metal layer; the material of the first metal layer includes: a first metal and a metal carbide of the first metal, and the metal carbide of the first metal is located on the side of the first metal layer close to the diamond substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method and chip. Background Technology

[0002] In diamond-substrate metal-oxide-semiconductor field-effect transistors (MOSFETs), the ohmic contact uses Au, a metal with a high work function, as the contact electrode to form a low barrier height, thereby improving the transport capacity of charge carriers between the metal and diamond. However, the poor adhesion between Au and the diamond substrate surface makes it easy for Au, as the electrode, to detach during subsequent processes. Summary of the Invention

[0003] The embodiments of this disclosure provide a semiconductor device and its fabrication method, as well as a chip, aimed at solving the problem of poor adhesion between the electrode and the surface of the diamond substrate.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a semiconductor device is provided. The semiconductor device includes: a diamond substrate, a dielectric layer, an electrode, and a gate.

[0006] A dielectric layer is disposed on one side of a diamond substrate. A gate electrode is disposed on the side of the dielectric layer away from the diamond substrate. An electrode is disposed on one side of the diamond substrate and is located on the same side of the diamond substrate as the dielectric layer. The electrode includes a first electrode and a second electrode, and the dielectric layer is at least partially disposed between the first electrode and the second electrode. The gate electrode is disposed on the side of the dielectric layer away from the diamond substrate.

[0007] The electrode includes a first metal layer. The material of the first metal layer includes a first metal and a metal carbide of the first metal, wherein the metal carbide of the first metal is located on the side of the first metal layer closest to the diamond substrate.

[0008] In the semiconductor device provided by the above embodiments of this disclosure, the first metal carbide can form strong covalent bonds (such as C-C, C-metal bonds) with the diamond surface, so that the first metal layer and diamond have a strong bonding ability, which can improve the interfacial bonding force between the electrode and the diamond substrate, thereby improving the adhesion between the electrode and the diamond substrate surface, making the electrode less likely to fall off in subsequent processes and improving the reliability of the semiconductor device; moreover, it can reduce the interfacial barrier height, promote the transfer of holes from the diamond substrate to the electrode through a lower barrier or tunneling effect, and enable the semiconductor device to form a low-resistance ohmic contact.

[0009] Moreover, for semiconductor devices with diamond substrates, the use of Au, a metal with a high work function, as the contact electrode material can be avoided, thus reducing costs.

[0010] In some embodiments, the first metal includes at least one of Ti, W, Cr, and Mo.

[0011] In some embodiments, the dielectric layer has vias. Electrodes are located within the vias, and the sidewalls of the electrodes are in contact with the dielectric layer.

[0012] In some embodiments, the electrode also covers the sidewalls of the via and a portion of the dielectric layer away from the diamond substrate.

[0013] In some embodiments, the electrode further includes a second metal layer. The second metal layer is disposed on the side of the first metal layer away from the diamond substrate.

[0014] In some embodiments, the electrode further includes a protective layer. The protective layer is disposed on the side of the second metal layer away from the diamond substrate. The protective layer is made of ceramic.

[0015] In some embodiments, the diamond substrate includes a base, an oxygen-terminated region, and a hydrogen-terminated region. The oxygen-terminated region and the hydrogen-terminated region are respectively disposed between the base and the dielectric layer, with the oxygen-terminated region surrounding the hydrogen-terminated region. The oxygen-terminated region includes oxygen ions, and the hydrogen-terminated region includes hydrogen ions.

[0016] In some embodiments, the thickness of the electrode ranges from 40 nm to 350 nm.

[0017] On the other hand, a method for fabricating a semiconductor device is provided. This method includes:

[0018] A diamond substrate is provided. A dielectric layer is formed on one side of the diamond substrate. An electrode is formed on one side of the diamond substrate, and is located on the same side of the diamond substrate as the dielectric layer. The electrode includes a first electrode and a second electrode, and the dielectric layer is at least partially disposed between the first electrode and the second electrode; wherein the electrode includes a first metal layer. The material of the first metal layer includes: a first metal and a metal carbide of the first metal; the metal carbide of the first metal is located on the side of the first metal layer closer to the diamond substrate. A gate is formed on the side of the dielectric layer away from the diamond substrate, thereby obtaining a semiconductor device.

[0019] It is understood that the beneficial effects that the semiconductor device fabrication method provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here.

[0020] In some embodiments, prior to forming the electrode, the process further includes forming a via. The electrode is located within the via, and the sidewalls of the electrode are in contact with the dielectric layer.

[0021] In some embodiments, forming an electrode includes: forming an initial first electrode and forming an initial second electrode. The initial first electrode and the initial second electrode are heat-treated to react a first metal with a diamond substrate to form a metal carbide of the first metal, thereby obtaining the first electrode and the second electrode.

[0022] In some embodiments, the temperature range of the heat treatment is 400°C to 600°C.

[0023] On the other hand, a chip is provided. The chip includes: a semiconductor device.

[0024] It is understood that the beneficial effects that the chips provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of semiconductor devices described above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0026] Figure 1 This is a schematic diagram of the structure of a chip according to some embodiments of the present disclosure;

[0027] Figure 2 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure;

[0028] Figure 3 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure;

[0029] Figure 4 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure;

[0030] Figure 5 This is a schematic diagram of the structure of a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

[0032] Figure 7 This is a structural diagram corresponding to each step in a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

[0033] Figure 8 This is a structural diagram corresponding to each step in a method for fabricating a semiconductor device according to some embodiments of the present disclosure;

[0034] Figure 9 This is a structural diagram corresponding to each step in the fabrication method of a semiconductor device according to Example 1 of this disclosure;

[0035] Figure 10 This is a structural diagram corresponding to each step in a method for fabricating a semiconductor device according to Example 2 of this disclosure. Detailed Implementation

[0036] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0037] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0038] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0039] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0040] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0041] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0042] Furthermore, in this disclosure, directional terms such as "upper" and "lower" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0043] It should be noted that in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0044] It should be noted that, for example, 1 / 2 in the accompanying drawings of this disclosure, both structure 1 and structure 2 can refer to this structure. Figure 2 In this context, 30 / 31 / 30F indicates that electrode 30, first electrode 31, and first metal layer 30F can all refer to this structure. Other similar reference numerals appearing in the attached figures also follow the above description.

[0045] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself can be patterned. The material added to the substrate can be patterned or left unpatterned.

[0046] The technical terms used in the embodiments of this disclosure are explained below:

[0047] Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. Among them, when the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this disclosure, this type of impurity semiconductor is also called a conductive semiconductor, for example, a conductive silicon carbide material doped with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this disclosure, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0048] The technical solutions disclosed herein can be applied to electronic devices, including various types of user equipment or terminal devices such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; these electronic devices can also be network equipment such as base stations. The electronic devices can also be devices such as power amplifiers used in the aforementioned electronic devices. The embodiments of this disclosure do not impose any special limitations on the specific form of the aforementioned electronic devices.

[0049] Embodiments of this disclosure provide a chip 1000. For example... Figure 1 As shown, the chip 1000 includes: a semiconductor device 100.

[0050] Understandably, chip 1000 is part of an electronic device and serves as a carrier for integrated circuits. Semiconductor device 100 is a device with conductivity between that of a conductor and an insulator, which can be used to manufacture rectifiers, diodes, transistors, integrated circuits, etc.

[0051] In some instances, such as Figure 2 As shown, the semiconductor device 100 includes a diamond substrate 10, a dielectric layer 20, an electrode 30, and a gate 40.

[0052] The gate 40 is disposed on the side of the dielectric layer 20 away from the diamond substrate 10.

[0053] A dielectric layer 20 is disposed on one side of the diamond substrate 10. A gate electrode 40 is disposed on the side of the dielectric layer 20 away from the diamond substrate 10. An electrode 30 is disposed on one side of the diamond substrate 10 and is located on the same side of the diamond substrate 10 as the dielectric layer 20. The electrode 30 includes a first electrode 31 and a second electrode 32, and the dielectric layer 20 is at least partially disposed between the first electrode 31 and the second electrode 32.

[0054] The diamond substrate 10 can serve as a physical support carrier for the semiconductor device 100, providing a basis for crystal growth and a thermal management path.

[0055] For example, the switching of the semiconductor device 100 is controlled by forming a hydrogen terminal surface on the surface of the diamond substrate 10 to generate a high concentration of two-dimensional hole gas (2DHG).

[0056] Electrode 30 includes a first electrode 31 and a second electrode 32, which are used for the transport of charge carriers (electrons or holes) to complete the circuit on / off control.

[0057] For example, the first electrode 31 can be the source electrode and the second electrode 32 can be the drain electrode.

[0058] For example, the first electrode 31 can be the drain electrode and the second electrode 32 can be the source electrode.

[0059] The source electrode can inject charge carriers into the semiconductor region of the diamond substrate 10, forming an ohmic contact with the diamond substrate 10 and reducing the contact resistance. The drain electrode collects the charge carriers transported through the diamond substrate 10, forming an output current or power transfer path.

[0060] The dielectric layer 20 physically separates the first electrode 31 from the second electrode 32, preventing short circuits and ensuring electrical independence. For example, the dielectric layer 20 can protect the hydrogen-terminated region HQ of the diamond from significant degradation during annealing.

[0061] The gate 40 modulates the carrier concentration on the surface of the diamond substrate 10 by applying a voltage, thereby enabling the switching of the semiconductor device 100.

[0062] In some implementations of metal-oxide-semiconductor field-effect transistors, after a hydrogen terminal surface is formed on the surface of a diamond substrate 100, the semiconductor device 100 mainly relies on the two-dimensional hole gas generated by the transfer doping effect on the diamond surface for conduction. Its ohmic contact generally uses a metal Au with a high work function as the contact electrode, i.e., electrode 30, thereby forming a low barrier height to improve the transport capacity of charge carriers between the metal and diamond. However, the adhesion between the metal Au and the surface of the diamond substrate 10 is poor, which causes the metal Au used as electrode 30 to easily fall off in subsequent processes.

[0063] Based on this, embodiments of the present disclosure provide a semiconductor device 100. For example... Figure 2 As shown, the semiconductor device 100 includes a diamond substrate 10, a dielectric layer 20, and an electrode 30.

[0064] Here, the arrangement of the diamond substrate 10, dielectric layer 20 and electrode 30 is the same as that described above, and will not be repeated here.

[0065] The electrode 30 includes a first metal layer 30F. The material of the first metal layer 30F includes a first metal and a metal carbide of the first metal; the metal carbide of the first metal is located on the side of the first metal layer 30F close to the diamond substrate 10.

[0066] Understandably, the metal carbide of the first metal is closer to the diamond substrate 10 and can form strong covalent bonds (such as C-C and C-metal bonds) with the diamond surface, which makes the first metal layer 30F have a strong bonding ability with the diamond. This can improve the interfacial bonding force between the electrode 30 and the diamond substrate 10, thereby improving the adhesion between the electrode 30 and the surface of the diamond substrate 10, making the electrode 30 less likely to fall off in subsequent processes and improving the reliability of the semiconductor device 100. Moreover, it can also reduce the interfacial barrier height, promote the transfer of holes from the diamond substrate 10 to the electrode 30 through a lower barrier or tunneling effect, and enable the semiconductor device 100 to form a low-resistance ohmic contact.

[0067] Moreover, it avoids using Au, a metal with a high work function, as the contact electrode material for electrode 30, thus reducing costs.

[0068] In some embodiments, the first metal includes at least one of Ti, W, Cr, and Mo.

[0069] Understandably, at least one of Ti, W, Cr and Mo reacts with the carbon element of the diamond substrate 10 to form a metal carbide, which replaces physical adsorption through strong covalent bonds, thereby improving the adhesion between the electrode 30 and the surface of the diamond substrate 10.

[0070] Correspondingly, the first metal can form a metal carbide of the first metal, such as TiC, WC, Cr3C2, and Mo2C. In the semiconductor device 100, on the one hand, the TiC, WC, Cr3C2, and Mo2C carbides are bonded to diamond through strong chemical bonds, improving the adhesion between the electrode 30 and the surface of the diamond substrate 10 and suppressing the peeling off of the electrode 30; on the other hand, at least one of TiC, WC, Cr3C2, and Mo2C forms a low-barrier contact with diamond, reducing the contact resistance by narrowing or lowering the barrier height, and replacing the high-cost Au electrode.

[0071] In some embodiments, such as Figure 3 As shown, the dielectric layer 20 has a via K. The electrode 30 is located inside the via K, and the sidewall of the electrode 30 is in contact with the dielectric layer 20.

[0072] Understandably, via K allows the sidewall of electrode 30 to contact the dielectric layer 20, thereby enabling the dielectric layer 20 to act as a physical barrier, preventing the etchant from directly contacting the edge of electrode 30, reducing the possibility of burr formation, reducing edge discharge of electrode 30, and avoiding premature breakdown of semiconductor device 100 caused by burrs on the edge of electrode 30, thus improving the withstand voltage performance of semiconductor device 100; moreover, the dielectric layer 20 can also provide additional mechanical support for electrode 30, especially at the edge of electrode 30, which helps to enhance the structural stability of the entire semiconductor device 100.

[0073] In some embodiments, such as Figure 4 As shown, electrode 30 also covers the sidewall of via K and the portion of the surface of dielectric layer 20 away from diamond substrate 10.

[0074] Understandably, the above-mentioned arrangement can enhance the contact area between the electrode 30 and the dielectric layer 20, forming a tighter bond and mechanical bond, thereby reducing corrosion caused by the entry of gas or liquid, further reducing the formation of sharp burrs, reducing edge discharge of the electrode 30, avoiding premature breakdown of the semiconductor device 100 caused by edge burrs of the electrode 30, and thus improving the withstand voltage performance of the semiconductor device 100.

[0075] In some embodiments, such as Figure 5 As shown, the material of electrode 30 further includes a second metal layer 30S. The second metal layer 30S is disposed on the side of the first metal layer 30F away from the diamond substrate 10.

[0076] For example, the material of the second metal layer 30S can be Al.

[0077] Understandably, the second metal layer 30S can serve as a current spreading layer, efficiently diffusing the current generated at the interface between the first metal and diamond in the first metal layer 30F to the entire electrode area, avoiding local overheating caused by current concentration, and significantly reducing the resistance loss of the metal layer itself; and the second metal layer 30S can serve as a barrier layer, where the second metal will partially interdiffuse with the first metal to form an alloy, suppressing the excessive diffusion of the first metal to the surface of the electrode 30.

[0078] In some embodiments, the resistivity of the first metal is in the range of 1 × 10⁻⁶. -8 Ω·m ~5×10 -7 Ω·m.

[0079] For example, the resistivity of the first metal can be 1×10⁻⁶. -8 Ω·m, 1×10 -7 Ω·m, 2×10 -7 Ω·m, 3×10 -7 Ω·m, 4×10 -7 Ω·m or 5×10 -7 Ω·m, no limit is set here.

[0080] Understandably, by setting the resistivity of the first metal to 1×10⁻⁶... -8 Ω·m ~5×10 -7 Within the range of Ω·m, the resistivity of the first metal can be made smaller, the resistance of the electrode 30 can be lower, a higher conductivity channel can be provided, and the performance of the semiconductor device 100 can be further improved; it can also make the current distribution in the electrode 30 more uniform, further improving the stability and reliability of the semiconductor device 100.

[0081] In some embodiments, the resistivity of the second metal is in the range of 1 × 10⁻⁶. -8 Ω·m ~4×10 -8 Ω·m.

[0082] For example, the resistivity of the second metal can be 1×10⁻⁶. -8 Ω·m, 2×10 -8 Ω·m, 3×10 -8 Ω·m or 4×10 -8 Ω·m, no limit is set here.

[0083] Understandably, by setting the resistivity of the second metal to 1×10⁻⁶... -8 Ω·m ~4×10 -8Within the range of Ω·m, it indicates that the resistance of the second metal is low and does not affect the resistance of the electrode 30. This allows the second metal layer 30S to provide a lower resistivity, thereby reducing the overall contact resistance of the electrode 30 to provide a higher conductive path and improve the performance of the semiconductor device 100. The reduction in the resistance of the electrode 30 can also reduce local overheating and current congestion, making the current distribution in the electrode 30 more uniform, thereby improving the stability and reliability of the semiconductor device 100.

[0084] That is, the second metal layer 30S can reduce the series resistance of the metal layer in the electrode 30 and realize current spread. The second metal (e.g. Al) selected for the second metal layer 30S is a metal with excellent conductivity and low cost. Its thickness is usually thick (hundreds of nanometers) and can be used as a current spread layer to efficiently spread the current generated by the first metal of the first metal layer 30F and the diamond contact interface to the entire electrode area, avoid local overheating caused by current concentration, and significantly reduce the resistance loss of the metal layer itself.

[0085] In some embodiments, such as Figure 5 As shown, electrode 30 further includes a protective layer 30T, disposed on the side of the second metal layer 30S away from the diamond substrate 10. The material of the protective layer 30T is ceramic.

[0086] Understandably, the protective layer 30T can protect the material of the second metal layer 30S from the influence of the external environment (oxygen, water vapor, etc.), prevent the second metal layer 30S from being oxidized or corroded, maintain stable contact performance for a long time, and thus improve the stability and service life of the semiconductor device 100.

[0087] For example, the protective layer 30T can be made of ceramic, which has good hardness, wear resistance, and chemical stability, effectively resisting physical wear and chemical corrosion. For instance, it can be titanium nitride (TiN). It can be deposited on the surface of electrode 30 using processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form a uniform and dense protective layer 30T. That is, the protective layer 30T is a highly chemically stable ceramic material (resistant to oxidation and acids / alkalis), effectively isolating the second metal layer 30S from the external environment (oxygen, water vapor, etc.), preventing oxidation or corrosion of the second metal, and avoiding the formation of a high-resistance oxide layer that increases contact resistance. This ensures that electrode 30 can maintain stable contact performance over a long period.

[0088] In other words, in the electrode 30 of the semiconductor device 100 disclosed herein, the electrode 30 achieves a low resistance and high reliability ohmic contact through three film layers: the first metal layer 30F achieves adhesion, the second metal layer 30S achieves current expansion and resistance reduction, and the protective layer 30T achieves protection and stability.

[0089] In some embodiments, such as Figure 5 As shown, the diamond substrate 10 includes: a base 101, an oxygen-terminated region OQ, and a hydrogen-terminated region HQ.

[0090] Oxygen-terminated region OQ and hydrogen-terminated region HQ are respectively disposed between the base 101 and the dielectric layer 20, with the oxygen-terminated region OQ surrounding the hydrogen-terminated region HQ. The oxygen-terminated region OQ contains oxygen ions. The hydrogen-terminated region HQ contains hydrogen ions.

[0091] Understandably, in the semiconductor device 100 on the diamond substrate 10, the hydrogen-terminated region HQ forms a two-dimensional hole gas near the diamond surface, serving as a conductive channel. When a positive gate voltage is applied, the strong electric field formed at the interface between the gate 40 and the diamond causes the holes in the two-dimensional hole gas region to be depleted, achieving channel turn-off. When a negative gate voltage is applied, the hole concentration at the interface increases significantly, and the on-resistance decreases accordingly, giving the semiconductor device 100 excellent current control capability. The oxygen-terminated region OQ can make the diamond surface more hydrophilic (polar) and electrically insulating, reducing the hole concentration on the surface to achieve isolation of the semiconductor device 100.

[0092] In some embodiments, the thickness D of electrode 30 ranges from 40 nm to 350 nm.

[0093] For example, the thickness D of electrode 30 can be 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm or 350nm, etc., and there is no limitation here.

[0094] Understandably, by setting the thickness D of electrode 30 within the range of 40nm to 350nm, electrode 30 can provide sufficient metal to react with the diamond substrate 10, forming a continuous and dense metal compound layer. This significantly improves the interfacial adhesion and ensures a strong connection between electrode 30 and the diamond substrate 10. Furthermore, electrodes 30 with a thickness D within the range of 40nm to 350nm are less likely to detach or be damaged in subsequent processes (such as photolithography, etching, deposition, etc.). The stable electrode 30 structure helps improve the manufacturing yield and reliability of semiconductor device 100.

[0095] In some implementations, a wet etching process is typically used to fabricate the semiconductor device 100. However, the controllability and consistency of the wet etching process are poor, making it difficult to precisely control the distance between the first electrode 31 and the second electrode 32. Furthermore, the electrode 30 (e.g., Au) is prone to burrs under wet etching, leading to edge discharge and reducing the withstand voltage performance of the semiconductor device 100. In other implementations, an alloy or damaged layer is used to achieve ohmic contact between the electrode 30 and the diamond substrate 10. These methods require prolonged high-temperature annealing, which can cause desorption of adsorbates on the hydrogen-terminated region (HQ) surface, necessitating further surface treatment. Regardless of the method used, the metal of the electrode 30 is fabricated before other processes, leading to contamination of other equipment during subsequent processes.

[0096] Embodiments of this disclosure provide a method for fabricating a semiconductor device 100. For example... Figure 6 As shown, the method for fabricating the semiconductor device 100 includes: S1 to S4.

[0097] S1: Provides a diamond substrate 10.

[0098] S2: Form a dielectric layer 20, which is disposed on one side of the diamond substrate 10.

[0099] S3: An electrode 30 is formed, disposed on one side of the diamond substrate 10, and located on the same side of the diamond substrate 10 as the dielectric layer 20. The electrode 30 includes a first electrode 31 and a second electrode 32. The dielectric layer 20 is at least partially disposed between the first electrode 31 and the second electrode 32. The electrode 30 includes a first metal layer 30F. The material of the first metal layer 30F includes a first metal and a metal carbide of the first metal, with the metal carbide of the first metal located on the side of the first metal layer 30F closest to the diamond substrate 10.

[0100] S4: Form a gate 40 on the side of the dielectric layer 20 away from the diamond substrate 10 to obtain a semiconductor device 100.

[0101] Understandably, considering the desorption of adsorbates during the high-temperature annealing process mentioned above, and the potential risk of contamination of subsequent equipment by the metal of electrode 30, the semiconductor device 100 fabrication method of this disclosure first forms the dielectric layer 20, then forms the electrode 30, and then anneals. The dielectric layer 20 protects the conductivity of the hydrogen-terminated region HQ from the effects of annealing, thus maintaining the stability of the HQ surface and suppressing its degradation. Simultaneously, it effectively prevents contamination of other equipment by the metal of electrode 30, thereby providing a reliable process guarantee for improving the performance of the semiconductor device 100. Furthermore, the semiconductor device 100 fabrication method of this disclosure does not contain Au, which can significantly reduce production costs.

[0102] In some embodiments, before S2 forms electrode 30, the method further includes:

[0103] A via K is formed, and electrode 30 is located inside the via K, with the sidewall of electrode 30 in contact with the dielectric layer 20.

[0104] For example, the via K can be formed using a dry etching method.

[0105] Understandably, forming vias K can effectively avoid the poor controllability problem caused by wet corrosion, as well as the premature breakdown problem of semiconductor device 100 caused by burrs on the edge of electrode 30; moreover, by first forming the hydrogen terminal region HQ of dielectric layer 20, and then forming vias K, and filling the vias K with the metal of electrode 30, the possibility of burrs forming on the metal of electrode 30 is reduced.

[0106] In some embodiments, such as Figure 7 and Figure 8 As shown, S2 forms electrode 30, which includes: S2.1~S2.2.

[0107] S2.1: Forming the initial first electrode 31A and forming the initial second electrode 32A.

[0108] S2.2: Heat-treat the initial first electrode 31A and the initial second electrode 32A to react the first metal with the diamond substrate 10 to form a metal carbide of the first metal, thereby obtaining the first electrode 31 and the second electrode 32.

[0109] For example, the temperature range for heat treatment is 400°C to 600°C.

[0110] For example, the heat treatment temperature can be 400℃, 450℃, 500℃, 550℃ or 600℃, etc., and there is no limitation here.

[0111] Understandably, heat treatment can enable semiconductor device 100 to achieve good adhesion.

[0112] In some embodiments, S2.1 forming the initial first electrode 31A and forming the initial second electrode 32A further includes: S2.1.1A to S2.1.2A.

[0113] S2.1.1A: An initial electrode 30A is formed on the dielectric layer 20 and the diamond substrate 10. The initial electrode 30A includes an initial electrode 30A inside the via K and an initial electrode 30A outside the via K.

[0114] S2.1.2A: Remove the initial electrode 30A from the via K to form the initial first electrode 31A and the initial second electrode 32A.

[0115] In some embodiments, S2.1 forming the initial first electrode 31A and forming the initial second electrode 32A further includes: S2.1.1B to S2.1.4B.

[0116] S2.1.1B: Photoresist PR is formed on dielectric layer 20 and diamond substrate 10.

[0117] S2.1.2B: Exposure and development to remove the photoresist PR inside the via K.

[0118] S2.1.3B: Initial electrode 30A is formed on photoresist PR and inside via K.

[0119] S2.1.4B: Remove the photoresist PR and the initial electrode 30A on the photoresist PR to form the initial first electrode 31A and the initial second electrode 32A.

[0120] In some embodiments, the method for fabricating the semiconductor device 100 further includes:

[0121] An oxygen-terminated region OQ and a hydrogen-terminated region HQ are formed. The diamond substrate 10 includes a base 101, and the oxygen-terminated region OQ and the hydrogen-terminated region HQ are respectively disposed between the base 101 and the dielectric layer 20. The oxygen-terminated region OQ surrounds the hydrogen-terminated region HQ, and the oxygen-terminated region OQ includes oxygen ions, while the hydrogen-terminated region HQ includes hydrogen ions.

[0122] Here, from the perspective of process compatibility, the method for fabricating the semiconductor device 100 described above can be seamlessly integrated with existing mass production lines for Si, GaN, and SiC-based semiconductor devices 100 without requiring large-scale modifications to existing equipment and processes, thus demonstrating significant potential for engineering applications and cost advantages.

[0123] The following describes the scheme of this disclosure through a specific method for fabricating the semiconductor device 100.

[0124] Example 1

[0125] Example 1 provides a semiconductor device 100. For example... Figure 9 As shown. The fabrication method of this semiconductor device 100 includes: 1M~8M.

[0126] 1M: Provides a diamond substrate 10, the surface of which is cleaned.

[0127] For example, the specific cleaning method is as follows: the diamond substrate 10 is placed in a solution of HNO3:H2SO4 with a volume ratio of 1:1 at 250°C and cleaned for 20 minutes, and then placed in acetone solution, anhydrous ethanol and deionized water for ultrasonic cleaning for 15 minutes in sequence.

[0128] 2M: An initial hydrogen termination region HQA is formed on one side of the diamond substrate 10.

[0129] For example, the surface of the diamond substrate 10 is subjected to hydrogen plasma treatment, which involves hydrogenation at 650°C for 30 minutes under a microwave power of 2kW and a gas pressure of 80 torr, thereby forming an initial hydrogen termination region HQA on its surface.

[0130] 3M: An initial dielectric layer 20A is formed on the surface of the initial hydrogen terminal region HQA.

[0131] For example, using trimethylaluminum (TMA) and H2O as precursors, a 50 nm thick layer of Al2O3 was deposited at 400 °C by atomic layer deposition (ALD).

[0132] 4M: Form oxygen terminal region OQ, remove part of the initial dielectric layer 20A of the pre-formed oxygen terminal region OQ, and transform the pre-formed oxygen terminal region OQ into oxygen terminal region OQ.

[0133] For example, photoresist PR is spin-coated on the surface of the initial dielectric layer 20A, and the photoresist PR of the pre-formed oxygen terminal region OQ is removed by exposure and development. The initial dielectric layer 20A of the pre-formed oxygen terminal region OQ is etched away under the protection of the photoresist PR using a diluted nitric acid and hydrofluoric acid mixture (Buffered Oxide Etchant, BOE) solution. Then, it is placed in oxygen plasma for 5 minutes to convert the exposed surface of the pre-formed oxygen terminal region OQ into a high-resistivity oxygen terminal region OQ, thus forming the oxygen terminal region OQ, and removing the residual photoresist PR on the sample surface.

[0134] 5M: The initial dielectric layer 20A is removed by removing the pre-formed first electrode 31 region and the pre-formed second electrode 32 region on the initial dielectric layer 20A to obtain the via K, thus forming the dielectric layer 20.

[0135] For example, photoresist PR is spin-coated onto the initial dielectric layer 20A and the diamond substrate 10, and then removed by exposure and development to remove the photoresist PR from the pre-formed first electrode 31 region and the pre-formed second electrode 32 region. At a temperature of 60°C, using Cl2 / BC... l3 A mixed Ar gas is used to dry etch the exposed initial dielectric layer 20A to obtain via K, forming dielectric layer 20.

[0136] 6M: Forming the initial first electrode 31A and the initial second electrode 32A.

[0137] For example, using magnetron sputtering, an initial electrode 30A is formed on the diamond substrate 10 within the dielectric layer 20 and via K. The initial electrode 30A includes an initial electrode 30A within the via K and an initial electrode 30A outside the via K. The initial electrode 30A outside the via K is removed to form an initial first electrode 31A and an initial second electrode 32A. The electrode 30 includes a Ti layer, an Al layer, and a TiN layer stacked sequentially.

[0138] 7M: Forms the first electrode 31 and the second electrode 32.

[0139] For example, the initial first electrode 31A and the initial second electrode 32A are annealed at 500°C for 1 hour to form the first electrode 31 and the second electrode 32. The electrode 30 includes a first metal layer 30F, a second metal layer 30S and a protective layer 30T stacked sequentially. The materials of the first metal layer 30F are Ti and TiC, the material of the second metal layer 30S is Al, and the material of the protective layer 30T is TiN.

[0140] 8M: Forms gate 40.

[0141] For example, a 100nm layer of Al is deposited on the side of the dielectric layer 20 away from the diamond substrate 10, the side of the electrode 30 away from the diamond substrate 10, and the side of the oxygen termination region OQ away from the diamond substrate 10 to form an initial gate 40A. Photoresist PR is spin-coated on the side of the pre-formed gate 40 region away from the diamond substrate 10, exposed and developed, and the initial gate 40A outside the pre-formed gate 40 region is removed under the protection of the photoresist PR to form gate 40, thereby obtaining semiconductor device 100.

[0142] Example 2

[0143] Example 2 provides a semiconductor device 100. For example... Figure 10 As shown. The fabrication method of this semiconductor device 100 includes: 1N~8N.

[0144] 1N: Provide a diamond substrate 10 and clean its surface.

[0145] For example, the specific cleaning method is as follows: the diamond substrate 10 is placed in a solution of HNO3:H2SO4 with a volume ratio of 1:1 at 250°C and cleaned for 20 minutes, and then placed in acetone solution, anhydrous ethanol and deionized water for ultrasonic cleaning for 15 minutes in sequence.

[0146] 2N: An initial hydrogen termination region HQA is formed on one side of the diamond substrate 10.

[0147] For example, the surface of the diamond substrate 10 is subjected to hydrogen plasma treatment, which involves hydrogenation at 650°C for 30 minutes under a microwave power of 2kW and a gas pressure of 80 torr, thereby forming an initial hydrogen termination region HQA on its surface.

[0148] 3N: An initial dielectric layer 20A is formed on the surface of the initial hydrogen terminal region HQA.

[0149] For example, Al2O3 / SiO2 (thickness can be 40 nm or 100 nm) is deposited on the surface of the initial hydrogen terminal region HQA using ALD and plasma-enhanced chemical vapor deposition (PECVD), respectively.

[0150] 4N: Form oxygen terminal region OQ, remove the initial dielectric layer 20A of the pre-formed oxygen terminal region OQ, and transform the pre-formed oxygen terminal region OQ into oxygen terminal region OQ.

[0151] For example, photoresist PR is spin-coated onto the surface of the initial dielectric layer 20A. Exposure and development are used to remove the photoresist PR from the pre-formed oxygen-terminated region OQ. Using a BOE solution, under the protection of the photoresist PR, the initial dielectric layer 20A of the pre-formed oxygen-terminated region OQ is etched away, and the photoresist PR is removed. Then, the area is left to stand in an ozone and ultraviolet irradiation atmosphere for 30 minutes, transforming the surface of the pre-formed oxygen-terminated region OQ into a high-resistivity oxygen-terminated region OQ, thus forming the oxygen-terminated region OQ.

[0152] 5N: The initial dielectric layer 20A is removed by removing the pre-formed first electrode 31 region and the pre-formed second electrode 32 region on the initial dielectric layer 20A to obtain via K, thus forming dielectric layer 20.

[0153] For example, under the protection of photoresist PR, the initial dielectric layer 20A of the pre-formed first electrode 31 region and the pre-formed second electrode 32 region is first removed by wet etching with BOE solution. Then, at a temperature of 40°C, Cl2 / BCl... 3 / Ar mixed gas is used to dry etch the residual Al2O3 to remove the photoresist PR, resulting in via K and forming dielectric layer 20.

[0154] 6N: Forms the initial first electrode 31A and the initial second electrode 32A.

[0155] For example, photoresist PR is spin-coated on dielectric layer 20 and diamond substrate 10, and photoresist PR in via K is removed by exposure and development. Initial electrode 30A is formed in photoresist PR and via K by electron beam evaporation with thicknesses of 40nm, 20nm and 100nm respectively. Photoresist PR and initial electrode 30A on photoresist PR are removed by lift-off process to form initial first electrode 31A and initial second electrode 32A. Initial electrode 30A includes Ti layer, Al layer and TiN layer stacked sequentially.

[0156] 7N: Forms the first electrode 31 and the second electrode 32.

[0157] For example, the initial first electrode 31A and the initial second electrode 32A are annealed at 500°C for 1 hour to form the first electrode 31 and the second electrode 32. The electrode 30 includes a first metal layer 30F, a second metal layer 30S and a protective layer 30T stacked sequentially. The materials of the first metal layer 30F are Ti and TiC, the material of the second metal layer 30S is Al, and the material of the protective layer 30T is TiN.

[0158] 8N: Forms gate 40.

[0159] Specifically, spin-coating photoresist PR, exposure and development to remove the photoresist PR in the pre-formed gate 40 region, electron beam evaporation to deposit a 100nm layer of Al on the surface of the photoresist PR and the pre-formed gate 40 region to form the initial gate 40A, and lift-off process to remove the initial gate 40A and photoresist PR outside the pre-formed gate 40 region to form the gate 40, thus obtaining the semiconductor device 100.

[0160] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Diamond substrate; A dielectric layer is disposed on one side of the diamond substrate; A gate is disposed on the side of the dielectric layer away from the diamond substrate; as well as, An electrode is disposed on one side of the diamond substrate and on the same side of the diamond substrate as the dielectric layer; the electrode includes a first electrode and a second electrode, and the dielectric layer is at least partially disposed between the first electrode and the second electrode; The electrode includes a first metal layer; the material of the first metal layer includes a first metal and a metal carbide of the first metal; the metal carbide of the first metal is located on the side of the first metal layer closest to the diamond substrate; the dielectric layer has a via, the electrode is located in the via, and the sidewall of the electrode is in contact with the dielectric layer; the electrode also covers the sidewall of the via and covers a portion of the dielectric layer away from the diamond substrate; the first metal includes at least one of Ti, W, Cr, and Mo, but does not include Au.

2. The semiconductor device according to claim 1, characterized in that, The electrode further includes a second metal layer disposed on the side of the first metal layer away from the diamond substrate.

3. The semiconductor device according to claim 2, characterized in that, The electrode further includes a protective layer disposed on the side of the second metal layer away from the diamond substrate; the material of the protective layer is ceramic.

4. The semiconductor device according to claim 1, characterized in that, The diamond substrate includes: Base; An oxygen-terminated region and a hydrogen-terminated region are respectively disposed between the base and the dielectric layer, with the oxygen-terminated region surrounding the hydrogen-terminated region. The oxygen-terminated region includes oxygen ions, and the hydrogen-terminated region includes hydrogen ions.

5. The semiconductor device according to claim 1, characterized in that, The thickness of the electrode ranges from 40 nm to 350 nm.

6. A method for fabricating a semiconductor device, characterized in that, include: Provide diamond substrate; A dielectric layer is formed on one side of the diamond substrate; An electrode is formed on one side of the diamond substrate and located on the same side of the diamond substrate as the dielectric layer. The electrode includes a first electrode and a second electrode, and the dielectric layer is at least partially disposed between the first electrode and the second electrode. The electrode includes a first metal layer. The material of the first metal layer includes a first metal and a metal carbide of the first metal. The metal carbide of the first metal is located on the side of the first metal layer closest to the diamond substrate. The dielectric layer has a via, and the electrode is located within the via, with its sidewall in contact with the dielectric layer. The electrode also covers the sidewall of the via and a portion of the dielectric layer surface away from the diamond substrate. The first metal includes at least one of Ti, W, Cr, and Mo, but does not include Au. A gate is formed and disposed on the side of the dielectric layer away from the diamond substrate to obtain a semiconductor device.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Before forming the electrode, the method further includes: A via is formed, the electrode is located within the via, and the sidewall of the electrode is in contact with the dielectric layer.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The electrode formation includes: Forming an initial first electrode and forming an initial second electrode; The initial first electrode and the initial second electrode are heat-treated to react the first metal with the diamond substrate to form a metal carbide of the first metal, thereby obtaining the first electrode and the second electrode.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, The temperature range for the heat treatment is 400℃~600℃.

10. A chip, characterized in that, include: The semiconductor device as described in any one of claims 1 to 5.

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