Transistor packaging structure and preparation method thereof
By simplifying the connection method of transistor packaging structure and reducing wires and solder joints, the problems of complex and cost in the existing technology are solved, and a higher performance and reliability package is achieved.
Patent Information
- Application Number
- CN202510415128.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-08-22
AI Technical Summary
The existing transistor packaging structure is complex and has high cost, and the number of internal wires is large, which increases manufacturing difficulty and cost.
The drain of the MOS is electrically connected to the source of the HEMT through a wire, and the wires of the source and the source metal layer of the MOS are eliminated. The conductive metal layer and insulating layer connection structure between the MOS and the substrate are cancelled, and the device is connected by a silver glue layer.
Simplifies the transistor package structure, reduces the number of wires and solder joints, and improves performance and reliability.
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Figure CN120529629A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of light-emitting power devices, and in particular to a transistor packaging structure and a preparation method thereof. Background Art
[0002] Transistors are widely used in wireless communications, RF amplification, satellite communications, radar systems, and efficient power management due to their excellent power handling capabilities and low noise characteristics. The transistor packaging structure can improve the transistor's voltage resistance and circuit performance.
[0003] Related art provides a transistor packaging structure, which includes a substrate, a source metal layer, a drain terminal, a gate terminal, a metal-oxide-semiconductor field-effect transistor (MOS), a high electron mobility transistor (HEMT), a connection structure, and a wire. The connection structure includes a conductive metal layer and an insulating layer, with the conductive metal layer being located on the insulating layer. The source metal layer, the drain terminal, and the gate terminal are arranged at intervals on the substrate, and the insulating layer of the connection structure and the HEMT are arranged on the source metal layer. The source of the MOS is electrically connected to the source metal layer via a wire, the drain of the MOS is located on the conductive metal layer of the connection structure, and the gate of the MOS is electrically connected to the gate terminal via a wire; the source of the HEMT is electrically connected to the conductive metal layer of the connection structure via a wire, the drain of the HEMT is electrically connected to the drain terminal via a wire, and the gate of the HEMT is electrically connected to the source metal layer via a wire.
[0004] In the related art, the transistor packaging structure is complex and the cost is high. Summary of the Invention
[0005] The present disclosure provides a transistor packaging structure and a method for manufacturing the same, which reduces manufacturing complexity and cost. The technical solution is as follows:
[0006] In one aspect, a transistor package structure is provided, comprising:
[0007] A substrate, a source metal layer, a drain terminal, a gate terminal, a MOS and a HEMT; the source metal layer, the drain terminal and the gate terminal are arranged on the substrate at intervals, and the MOS and the HEMT are arranged on the source metal layer at intervals;
[0008] The source of the MOS is electrically connected to the source metal layer, the drain of the MOS is electrically connected to the source of the HEMT via a first wire, and the gate of the MOS is electrically connected to the gate terminal via a second wire; the drain of the HEMT is electrically connected to the drain terminal via a third wire, and the gate of the HEMT is electrically connected to the source metal layer via a fourth wire.
[0009] Optionally, the transistor package structure further includes: a first connection layer,
[0010] The source of the MOS is located on a first surface of the MOS, the drain and the gate of the MOS are located on a second surface of the MOS, and the first surface of the MOS is electrically connected to the source metal layer through the first connection layer.
[0011] Optionally, the second connection layer,
[0012] The source, drain and gate of the HEMT are located on the second surface of the HEMT, and the first surface of the HEMT is connected to the source metal layer through the second connection layer.
[0013] Optionally, the first connecting layer is a silver glue layer;
[0014] Alternatively, the second connecting layer is a silver glue layer.
[0015] Optionally, the substrate is rectangular, the source metal layer is located on one side of the rectangle, and the drain terminal and the gate terminal are located on the other side of the rectangle.
[0016] In another aspect, a method for preparing a transistor package structure is provided, the method comprising:
[0017] Fabricating a source metal layer, a drain terminal, and a gate terminal on a substrate, wherein the source metal layer, the drain terminal, and the gate terminal are arranged at intervals on the substrate;
[0018] Bonding a MOS and a HEMT to the source metal layer, wherein the MOS and the HEMT are spaced apart on the source metal layer; the source of the MOS is electrically connected to the source metal layer;
[0019] The drain of the MOS is electrically connected to the source of the HEMT via a first wire, the gate of the MOS is electrically connected to the gate terminal via a second wire, the drain of the HEMT is electrically connected to the drain terminal via a third wire, and the gate of the HEMT is electrically connected to the source metal layer via a fourth wire.
[0020] Optionally, the source of the MOS is located on a first surface of the MOS, and the drain and gate of the MOS are located on a second surface of the MOS;
[0021] Bonding the MOS to the source metal layer, comprising:
[0022] The first surface of the MOS is bonded to the source metal layer through a first connection layer.
[0023] Optionally, the source, drain and gate of the HEMT are located on the second side of the HEMT;
[0024] Bonding the HEMT to the source metal layer, comprising:
[0025] The first surface of the HEMT is connected to the source metal layer through a second connection layer.
[0026] Optionally, the first connecting layer is a silver glue layer;
[0027] Alternatively, the second connecting layer is a silver glue layer.
[0028] Optionally, the substrate is rectangular, the source metal layer is located on one side of the rectangle, and the drain terminal and the gate terminal are located on the other side of the rectangle.
[0029] The technical solutions provided by the embodiments of the present disclosure have the following beneficial effects:
[0030] In the disclosed embodiment, the drain of the MOS is electrically connected to the source of the HEMT via a wire, while the source of the MOS is in contact with the source metal layer. This eliminates the need for a wire connecting the source of the MOS to the source metal layer and eliminates the need for a connection structure comprising a conductive metal layer and an insulating layer between the MOS and the substrate. This simplifies the internal structure of the transistor package and reduces the number of wires and corresponding solder joints. This optimization improves the performance and reliability of the transistor package. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0032] Figure 1 It is a schematic diagram of a transistor packaging structure provided by related technology;
[0033] Figure 2 1 is a schematic diagram of a packaging structure of a transistor provided by an embodiment of the present disclosure;
[0034] Figure 3is a top view of a transistor packaging structure provided by an embodiment of the present disclosure;
[0035] Figure 4 is a circuit diagram of a transistor packaging structure provided by an embodiment of the present disclosure;
[0036] Figure 5 This is a flow chart of a method for preparing a transistor packaging structure provided by an embodiment of the present disclosure;
[0037] Figure 6 This is a schematic diagram of a transistor packaging structure optimization process provided by an embodiment of the present disclosure.
[0038] The reference numerals are as follows:
[0039] 100: substrate; 200: MOS; 300: HEMT; 400: connection structure;
[0040] 101: source metal layer; 102: drain terminal; 103: gate terminal;
[0041] 201: Source of MOS; 202: Drain of MOS; 203: Gate of MOS;
[0042] 301: source of HEMT; 302: drain of HEMT; 303: gate of HEMT;
[0043] 401: conductive metal layer; 402: insulating layer;
[0044] 501: first connection layer; 502: second connection layer;
[0045] 600: wire; 601: first wire; 602: second wire; 603: third wire; 604: fourth wire. DETAILED DESCRIPTION
[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.
[0047] Figure 1 This is a schematic diagram of a transistor packaging structure provided by related technology. Figure 1 As shown, the transistor package structure provided by the related art includes: a substrate 100, a MOS 200, a HEMT 300, a connection structure 400 and a wire 600. The connection structure 400 includes a conductive metal layer 401 and an insulating layer 402, and the conductive metal layer 401 is located on the insulating layer 402.
[0048] The source metal layer 101, drain terminal 102, and gate terminal 103 are arranged alternately on the substrate 100. The insulating layer 402 of the connection structure 400 and the HEMT 300 are arranged on the source metal layer 101. The source 201 of the MOS 200 is electrically connected to the source metal layer 101 via a wire 600. The drain 202 of the MOS 200 is located on the conductive metal layer 401 of the connection structure 400. The gate 203 of the MOS 200 is electrically connected to the gate terminal 103 via a wire 600. The source 301 of the HEMT 300 is electrically connected to the conductive metal layer 401 of the connection structure 400 via a wire 600. The drain 302 of the HEMT 300 is electrically connected to the drain terminal 102 via a wire 600. The gate 303 of the HEMT 300 is electrically connected to the source metal layer 101 via a wire 600.
[0049] like Figure 1 As shown, in the related art, the source and gate of MOS200 are located on the upper surface of MOS, while the drain is located on the lower surface of MOS. Although the above-mentioned transistor packaging structure has the advantages of improving the voltage resistance of the transistor and optimizing the circuit performance, its structure is relatively complex. The main problems are: the number of wires inside the transistor packaging structure is large, which increases the complexity and cost of manufacturing the transistor packaging structure. In addition, a connection structure needs to be set between the MOS and the source metal layer in the transistor packaging structure, which further increases the complexity and cost of manufacturing the transistor packaging structure.
[0050] Figure 2 Schematic diagram of a transistor packaging structure provided by an embodiment of the present disclosure. Figure 2 The transistor package structure includes: a substrate 100, a source metal layer 101, a drain terminal 102, a gate terminal 103, a MOS 200, a HEMT 300, a first wire 601, a second wire 602, a third wire 603, and a fourth wire 604; the source metal layer 101, the drain terminal 102, and the gate terminal 103 are arranged at intervals on the substrate 100, and the MOS 200 and the HEMT 300 are arranged at intervals on the source metal layer 101.
[0051] The source 201 of the MOS 200 is electrically connected to the source metal layer 101. The drain 202 of the MOS 200 is electrically connected to the source 301 of the HEMT 300 via a first wire 601. The gate 203 of the MOS 200 is electrically connected to the gate terminal 103 via a second wire 602. The drain 302 of the HEMT 300 is electrically connected to the drain terminal 102 via a third wire 603. The gate 303 of the HEMT 300 is electrically connected to the source metal layer 101 via a fourth wire 604.
[0052] In the disclosed embodiment, the drain of the MOS is electrically connected to the source of the HEMT via a wire, while the source of the MOS is in contact with the source metal layer. This eliminates the need for a wire connecting the source of the MOS to the source metal layer and eliminates the need for a connection structure comprising a conductive metal layer and an insulating layer between the MOS and the substrate. This simplifies the internal structure of the transistor package and reduces the number of wires and corresponding solder joints. This optimization improves the performance and reliability of the transistor package.
[0053] In the embodiment of the present disclosure, the substrate 100 is rectangular, the source metal layer 101 is located on one side of the rectangle, and the drain terminal 102 and the gate terminal 103 are located on the other side of the rectangle.
[0054] In this implementation, the above distribution method is beneficial to the arrangement of MOS and HEMT, and facilitates the routing between various devices and terminals.
[0055] In other implementations, the source metal layer 101 , the drain terminal 102 , and the gate terminal 103 may also be arranged in other ways, such as being arranged in a straight line.
[0056] In other embodiments, the substrate 100 may also be in other shapes, such as an elliptical shape.
[0057] In the embodiment of the present disclosure, the material of the source metal layer 101 , the drain terminal 102 , and the gate terminal 103 may be copper plated with tin.
[0058] In the embodiment of the present disclosure, the source metal layer 101 may be rectangular.
[0059] In other examples, the source metal layer 101 may also be circular or have other shapes.
[0060] In the embodiment of the present disclosure, the drain terminal 102 may be rectangular.
[0061] In other examples, the drain terminal 102 may also be circular or have other shapes.
[0062] In the embodiment of the present disclosure, the gate terminal 103 may be rectangular.
[0063] In other examples, the gate terminal 103 may also be circular or have other shapes.
[0064] In the embodiment of the present disclosure, the MOS 200 may be a Nixon PK8B0BA type MOS, in which the source of the MOS is on one side and the gate and drain are on the other side, so that the aforementioned connection method of the MOS with other devices can be realized.
[0065] In other embodiments, the MOS 200 may be other types of MOS, but it is necessary to ensure that the source of the MOS is on one side, and the gate and the drain are on the other side.
[0066] In the embodiment of the present disclosure, the HEMT 300 may be a GaN-based HEMT. In the GaN-based HEMT, the source, gate, and drain of the HEMT are on the same surface, which enables the aforementioned connection method between the HEMT and other devices.
[0067] In other embodiments, the HEMT 300 may be another type of HEMT, but the source, gate, and drain of the HEMT must be on the same side.
[0068] In the embodiment of the present disclosure, the first conductive wire 601 , the second conductive wire 602 , the third conductive wire 603 and the fourth conductive wire 604 may be copper wires.
[0069] In other embodiments, the first conductive line 601 , the second conductive line 602 , the third conductive line 603 , and the fourth conductive line 604 may also be other metal wires.
[0070] In the embodiment of the present disclosure, the transistor package structure further includes: a first connection layer 501,
[0071] The source 201 of the MOS 200 is located on the first surface of the MOS 200 , the drain 202 and the gate 203 of the MOS 200 are located on the second surface of the MOS 200 , and the first surface of the MOS 200 is electrically connected to the source metal layer 101 through the first connection layer 501 .
[0072] In this implementation, the first connection layer can make the first surface of the MOS and the source metal layer more firmly connected, and realize the electrical connection between the source of the MOS and the source metal layer.
[0073] In the embodiment of the present disclosure, the first connection layer 501 may be a silver paste layer.
[0074] In this implementation, the silver paste layer is conductive and can form an electrical connection, and the silver paste layer can make the connection between the MOS and the source metal layer more secure.
[0075] In other examples, the first connection layer 501 may also be other conductive adhesive layers. In the embodiment of the present disclosure, the transistor package structure further includes: a second connection layer 502,
[0076] The source 301 , the drain 302 , and the gate 303 of the HEMT 300 are located on the second surface of the HEMT 300 . The first surface of the HEMT 300 is connected to the source metal layer 101 via the second connection layer 502 .
[0077] In this implementation, the second connection layer can connect the first surface of the HEMT to the source metal layer to ensure a firm connection.
[0078] In the embodiment of the present disclosure, the second connection layer 502 may be a silver paste layer.
[0079] In this implementation, the silver paste layer can make the first surface of the HEMT and the source metal layer more firmly connected.
[0080] In other examples, the second connection layer 502 may also be another conductive adhesive layer, or a non-conductive adhesive layer.
[0081] In the embodiment of the present disclosure, the area of the first connection layer 501 is larger than the area of the MOS 200 .
[0082] In other examples, the area of the first connection layer 501 may also be equal to or smaller than the area of the MOS 200 .
[0083] In the embodiment of the present disclosure, the area of the second connection layer 502 is equal to the area of the HEMT 300 .
[0084] In other examples, the area of the second connection layer 502 may also be smaller or larger than the area of the HEMT 300 .
[0085] Figure 3 is a top view of a transistor packaging structure provided by an embodiment of the present disclosure. Figure 3 , the number of the first wires 601 can be 6.
[0086] In other examples, the number of the first conductive lines 601 may be less than or equal to 6 or more than 6.
[0087] In the embodiment of the present disclosure, the number of the second wire 602 may be one.
[0088] In other examples, the number of the second conductive wires 602 may be two or more.
[0089] In the embodiment of the present disclosure, the number of the third wires 603 may be 6.
[0090] In other examples, the number of the third conductive wires 603 may be less than or equal to 6.
[0091] In the embodiment of the present disclosure, the number of the fourth wire 604 may be one.
[0092] In other examples, the number of fourth conductive lines 604 may be two or more.
[0093] Figure 4 is a circuit diagram of a transistor packaging structure provided by an embodiment of the present disclosure. Figure 4 In the figure, the source, gate and drain are Figure 2 and Figure 3 The source metal layer, gate terminal and drain terminal in the MOS are controlled by the gate, so that the signal input from the source passes through the MOS and HEMT and is finally output from the drain.
[0094] Figure 5 This is a flow chart of a method for preparing a transistor packaging structure provided by an embodiment of the present disclosure. Figure 5 , the method steps include:
[0095] S11. Fabricate a source metal layer, a drain terminal, and a gate terminal on a substrate, wherein the source metal layer, the drain terminal, and the gate terminal are spaced apart on the substrate.
[0096] In the embodiment of the present disclosure, the substrate is rectangular, the source metal layer is located on one side of the rectangle, and the drain terminal and the gate terminal are located on the other side of the rectangle.
[0097] In this implementation, the above distribution method is beneficial to the arrangement of MOS and HEMT, and facilitates the routing between various devices and terminals.
[0098] In other implementations, the source metal layer, the drain terminal, and the gate terminal may also be arranged in other ways, such as being arranged in a straight line.
[0099] In other embodiments, the substrate may also be in other shapes, such as an oval shape.
[0100] In the embodiment of the present disclosure, the material of the source metal layer, the drain terminal, and the gate terminal may be copper plated with tin.
[0101] In the embodiment of the present disclosure, the source metal layer may be rectangular.
[0102] In other examples, the source metal layer may also be circular or have other shapes.
[0103] In the embodiment of the present disclosure, the drain terminal may be rectangular.
[0104] In other examples, the drain terminal may also be circular or have other shapes.
[0105] In the embodiment of the present disclosure, the gate terminal may be rectangular.
[0106] In other examples, the gate terminal may also be circular or have other shapes.
[0107] S12, bonding a MOS and a HEMT to the source metal layer, wherein the MOS and the HEMT are spaced apart on the source metal layer; and electrically connecting the source of the MOS to the source metal layer.
[0108] In the disclosed embodiment, the source of the MOS is located on the first side of the MOS, and the drain and gate of the MOS are located on the second side of the MOS;
[0109] Bonding the MOS to the source metal layer includes:
[0110] The first surface of the MOS is bonded to the source metal layer through the first connection layer.
[0111] In this implementation, the first connection layer can make the first surface of the MOS and the source metal layer more firmly connected, and realize the electrical connection between the source of the MOS and the source metal layer.
[0112] In the disclosed embodiment, the source, drain, and gate of the HEMT are located on the second side of the HEMT;
[0113] Bonding the HEMT to the source metal layer includes:
[0114] The first surface of the HEMT is connected to the source metal layer through the second connection layer.
[0115] In this implementation, the second connection layer can electrically connect the first surface of the HEMT to the source metal layer, and the second connection layer can make the connection between the HEMT and the source metal layer more secure.
[0116] In the embodiment of the present disclosure, the first connection layer is a silver glue layer;
[0117] Alternatively, the second connecting layer is a silver paste layer.
[0118] In this implementation, the silver paste layer is conductive and can form an electrical connection, and the silver paste layer can connect the metal layer to make the structure more solid.
[0119] In other examples, the first connection layer may be other conductive adhesive layers;
[0120] Alternatively, the second connection layer may also be other conductive adhesive layers or non-conductive adhesive layers.
[0121] In the embodiment of the present disclosure, the area of the first connection layer is larger than the area of the MOS.
[0122] In other examples, the area of the first connection layer may also be equal to or smaller than the area of the MOS.
[0123] In the embodiment of the present disclosure, the area of the second connection layer is equal to the area of the HEMT.
[0124] In other examples, the area of the second connection layer may also be smaller or larger than the area of the HEMT.
[0125] In the embodiment of the present disclosure, the MOS can be a Nixon PK8B0BA type MOS. In this type of MOS, the source of the MOS is on one side, and the gate and drain are on the other side, which can realize the connection method of the MOS with other devices.
[0126] In other embodiments, the MOS may be other types of MOS, but it is necessary to ensure that the source of the MOS is on one side, and the gate and the drain are on the other side.
[0127] In the embodiment of the present disclosure, the HEMT may be a GaN-based HEMT. In the GaN-based HEMT, the source, gate, and drain of the HEMT are on the same surface, which enables the aforementioned connection method of the HEMT with other devices.
[0128] In other embodiments, the HEMT may be another type of HEMT, but it is necessary to ensure that the source, gate, and drain of the HEMT are on the same side.
[0129] S13. Electrically connect the drain of the MOS to the source of the HEMT through a first wire, electrically connect the gate of the MOS to the gate terminal through a second wire, electrically connect the drain of the HEMT to the drain terminal through a third wire, and electrically connect the gate of the HEMT to the source metal layer through a fourth wire.
[0130] In the embodiment of the present disclosure, the first conductive wire, the second conductive wire, the third conductive wire, and the fourth conductive wire may be copper wires.
[0131] In other embodiments, the first conductive line, the second conductive line, the third conductive line, and the fourth conductive line may also be other metal wires.
[0132] In the embodiment of the present disclosure, the number of the first conductive lines may be 6.
[0133] In other examples, the number of first conductive lines may be less than or equal to 6 or more than 6.
[0134] In the embodiment of the present disclosure, the number of the second wire may be one.
[0135] In other examples, the number of second conductive wires may be 2 or more.
[0136] In the embodiment of the present disclosure, the number of the third wires may be 6.
[0137] In other examples, the number of third conductive wires may be less than or equal to 6 or more than 6.
[0138] In the embodiment of the present disclosure, the number of the fourth wire may be one.
[0139] In other examples, the number of fourth conductive lines may be 2 or more.
[0140] In the disclosed embodiment, the drain of the MOS is electrically connected to the source of the HEMT via a wire, while the source of the MOS is in contact with the source metal layer. This eliminates the need for a wire connecting the source of the MOS to the source metal layer and eliminates the need for a connection structure comprising a conductive metal layer and an insulating layer between the MOS and the substrate. This simplifies the internal structure of the transistor package and reduces the number of wires and corresponding solder joints. This optimization improves the performance and reliability of the transistor package.
[0141] Figure 6 This is a schematic diagram of a transistor packaging structure optimization process provided by an embodiment of the present disclosure. Figure 6 ,exist Figure 1 In the case where the source and gate of MOS200 are on the same surface, if the source 201 of MOS200 is directly connected to the source metal layer 101, the gate 203 of MOS200 will also be in direct contact with the source metal layer 101, thus causing a short circuit. Therefore, it is necessary to adjust the position of the gate 203 of MOS200 to be on the same surface as the drain 202 of MOS200, thereby completing the optimization and thus Figure 1 The structural optimization of Figure 2 The structure shown.
[0142] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.
Claims
1. A transistor packaging structure, characterized in that: The transistor packaging structure comprises: a substrate (100), a source metal layer (101), a drain terminal (102), a gate terminal (103), a MOS (200) and a HEMT (300); the source metal layer (101), the drain terminal (102) and the gate terminal (103) are arranged at intervals on the substrate (100), and the MOS (200) and the HEMT (300) are arranged at intervals on the source metal layer (101); The source (201) of the MOS (200) is electrically connected to the source metal layer (101); the drain (202) of the MOS (200) is electrically connected to the source (301) of the HEMT (300) via a first wire (601); the gate (203) of the MOS (200) is electrically connected to the gate terminal (103) via a second wire (602); the drain (302) of the HEMT (300) is electrically connected to the drain terminal (102) via a third wire (603); and the gate (303) of the HEMT (300) is electrically connected to the source metal layer (101) via a fourth wire (604).
2. The transistor packaging structure according to claim 1, wherein: The transistor packaging structure further comprises: a first connection layer (501), The source (201) of the MOS (200) is located on a first surface of the MOS (200), the drain (202) and the gate (203) of the MOS (200) are located on a second surface of the MOS (200), and the first surface of the MOS (200) is electrically connected to the source metal layer (101) through the first connection layer (501).
3. The transistor packaging structure according to claim 2, wherein: The transistor package structure further comprises: a second connection layer (502), The source (301), drain (302) and gate (303) of the HEMT (300) are located on the second surface of the HEMT (300), and the first surface of the HEMT (300) is connected to the source metal layer (101) via the second connection layer (502).
4. The transistor packaging structure according to claim 3, wherein: The first connecting layer (501) is a silver glue layer; Alternatively, the second connecting layer (502) is a silver glue layer.
5. The transistor package structure according to any one of claims 1 to 4, characterized in that: The substrate (100) is rectangular, the source metal layer (101) is located on one side of the rectangle, and the drain terminal (102) and the gate terminal (103) are located on the other side of the rectangle.
6. A method for preparing a transistor packaging structure, characterized in that: The transistor packaging structure preparation method comprises: Fabricating a source metal layer, a drain terminal, and a gate terminal on a substrate, wherein the source metal layer, the drain terminal, and the gate terminal are arranged at intervals on the substrate; Bonding a MOS and a HEMT to the source metal layer, wherein the MOS and the HEMT are spaced apart on the source metal layer; the source of the MOS is electrically connected to the source metal layer; The drain of the MOS is electrically connected to the source of the HEMT via a first wire, the gate of the MOS is electrically connected to the gate terminal via a second wire, the drain of the HEMT is electrically connected to the drain terminal via a third wire, and the gate of the HEMT is electrically connected to the source metal layer via a fourth wire.
7. The method for preparing a transistor package structure according to claim 6, wherein: The source of the MOS is located on a first surface of the MOS, and the drain and gate of the MOS are located on a second surface of the MOS; Bonding the MOS to the source metal layer, comprising: The first surface of the MOS is bonded to the source metal layer through a first connection layer.
8. The method for preparing a transistor package structure according to claim 7, wherein: The source, drain and gate of the HEMT are located on the second side of the HEMT; Bonding the HEMT to the source metal layer, comprising: The first surface of the HEMT is connected to the source metal layer through a second connection layer.
9. The method for preparing a transistor package structure according to claim 8, wherein: The first connecting layer is a silver glue layer; Alternatively, the second connecting layer is a silver glue layer.
10. The method for preparing a transistor package structure according to any one of claims 6 to 9, characterized in that: The substrate is rectangular, the source metal layer is located on one side of the rectangle, and the drain terminal and the gate terminal are located on the other side of the rectangle.
Citation Information
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