Power device and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, in particular to a power device and a preparation method thereof. The application comprises the following steps: providing a semiconductor structure comprising a substrate, a first oxide layer, a plurality of deep trenches, at least one voltage-resisting gate structure and at least one gate filling structure; shielding the voltage-resisting gate structure and etching back the gate filling structure to obtain a shielded gate; removing the shielding layer and removing the first oxide layer on the surface of the substrate and at least part of the etched-back deep trench wall; forming a second oxide layer covering at least the exposed deep trench wall, the shielded gate and the surface of the substrate, the second oxide layer being continuous with the remaining first oxide layer on the deep trench wall; forming a control gate above the shielded gate to obtain a shielded gate structure, the control gate, the shielded gate and the substrate being isolated by the first oxide layer and the second oxide layer; and at least performing surface oxidation on the control gate to form a third oxide layer continuous with the second oxide layer. The application can simplify the integration process of BCD devices and SGT devices and avoid gate leakage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a power device and a method for preparing the same. Background Art

[0002] Integrating BCD (Bipolar CMOS DMOS) and SGT (Shielded Gate Trench) modules into the same power device chip can reduce the number of pins, device space, and connection complexity. However, the preparation process for integrating BCD and SGT on the same chip is highly complex and there is a risk of gate leakage. Summary of the Invention

[0003] To solve the above technical problems, the present application discloses, in one aspect, a method for preparing a power device, which comprises:

[0004] A semiconductor structure is provided, comprising a substrate, a first oxide layer, a plurality of deep trenches, at least one voltage-resistant gate structure, and at least one gate filling structure, wherein the substrate comprises a first device region and a second device region of different conductivity types, the gate filling structure is located in the first device region, the first oxide layer is located on the surface of the substrate and covers the walls of the deep trenches, and the voltage-resistant gate structure and the gate filling structure respectively fill the deep trenches;

[0005] Shielding the voltage-resistant gate structure and etching back the gate filling structure to obtain a shielding gate;

[0006] removing the shielding layer, and removing the first oxide layer on the substrate surface and at least a portion of the etched-back deep trench wall;

[0007] forming a second oxide layer covering at least the exposed deep trench wall, the shielding gate, and the surface of the substrate, wherein the second oxide layer is continuous with the first oxide layer remaining on the deep trench wall;

[0008] forming a control gate located above the shielding gate to obtain a shielding gate structure, wherein the control gate, the shielding gate, and the substrate are isolated by the first oxide layer and the second oxide layer;

[0009] At least the control gate is surface-oxidized to form a third oxide layer continuous with the second oxide layer.

[0010] In a possible embodiment, the preparation method satisfies at least one of the following characteristics:

[0011] The thickness of at least a portion of the second oxide layer does not exceed a first preset thickness, wherein the first preset thickness is 70-120 Å;

[0012] The thickness of the third oxide layer exceeds a second preset thickness, and the second preset thickness is 100-130 Å.

[0013] In a possible implementation manner, removing the shielding layer and removing the first oxide layer on the substrate surface and at least a portion of the etched-back deep trench wall includes:

[0014] Removing the first oxide layer region on the unmasked deep trench wall and the unmasked first oxide layer region on the substrate surface to expose the unmasked deep trench wall, the unmasked substrate surface and the unmasked portion of the sidewall of the shielding gate;

[0015] The shielding layer and the remaining first oxide layer area on the surface of the substrate are removed.

[0016] In a possible implementation manner, removing the shielding layer and the first oxide layer region remaining on the surface of the substrate includes:

[0017] removing the shielding layer;

[0018] thinning the remaining first oxide layer region on the substrate surface based on a chemical mechanical polishing process to expose the substrate surface;

[0019] or,

[0020] The removing of the shielding layer and the first oxide layer region remaining on the surface of the substrate comprises:

[0021] removing the shielding layer;

[0022] Performing surface thermal oxidation treatment on the exposed substrate surface, the exposed deep trench wall, the exposed shielding gate and the gate filling structure to form a second sacrificial oxide layer;

[0023] The second sacrificial oxide layer and the remaining first oxide layer region on the surface of the substrate are removed based on an oxide layer etching process.

[0024] In a possible embodiment, the shield gate structure includes a first shield gate structure and a second shield gate structure; before removing the first oxide layer region on the unshielded deep trench wall and the unshielded first oxide layer region on the substrate surface, the preparation method further includes:

[0025] shielding the shielding gate in the deep trench corresponding to the first shielding gate structure;

[0026] The step of removing the first oxide layer region on the unshielded deep trench wall comprises:

[0027] A portion of the first oxide layer region on the wall of the deep trench corresponding to the second shield gate structure is removed.

[0028] In a possible implementation manner, forming the second oxide layer covering at least the exposed deep trench wall, the shield gate, and the substrate surface includes:

[0029] The second oxide layer is formed based on a deposition process or a thermal oxidation process; the second oxide layer covers the surface of the substrate, the exposed surface of the shielding gate and the exposed deep trench wall, and the third oxide layer covers the surface of the control gate and the surface of the voltage-resistant gate structure; or, the second oxide layer covers the surface of the substrate, the exposed surface of the shielding gate, the exposed deep trench wall and the surface of the voltage-resistant gate structure, and the third oxide layer covers the surface of the control gate.

[0030] In a possible implementation manner, forming a control gate located above the shielding gate includes:

[0031] Depositing a gate material to backfill the back-etched deep trench to form a second gate material layer filling the deep trench and located on the second oxide layer;

[0032] The second oxide layer is used as a stop layer, and the second gate material layer is thinned to form control gates isolated from each other.

[0033] In a possible implementation, providing a semiconductor structure including a substrate, a first oxide layer, a plurality of deep trenches, at least one voltage-resistant gate structure, and at least one gate filling structure includes:

[0034] Providing a substrate including the first device region and the second device region;

[0035] forming a plurality of deep trenches spaced apart from each other in the substrate;

[0036] forming a first oxide layer covering the surface of the substrate and the wall of the deep trench;

[0037] The multiple deep trenches are filled with gate material to form the voltage-resistant gate structure and the gate filling structure.

[0038] In a possible implementation manner, the substrate surface includes a pad oxide layer, and forming the first oxide layer covering the substrate surface and the deep trench wall includes:

[0039] Performing thermal oxidation treatment on the wall of the deep trench to form a first sacrificial oxide layer located on the wall of the deep trench;

[0040] removing the first sacrificial oxide layer and the pad oxide layer to expose the substrate surface and the deep trench wall;

[0041] The first oxide layer is formed on the surface of the substrate and the wall of the deep trench based on a deposition process or a thermal oxidation process.

[0042] In a possible implementation manner, filling the plurality of deep trenches with a gate material to form the voltage-resistant gate structure and the gate filling structure includes:

[0043] Depositing a gate material to form a first gate material layer filling the deep trench and covering the first oxide layer;

[0044] The first oxide layer is used as a stop layer, and the first gate material layer is thinned to obtain voltage-resistant gate structures and gate filling structures that are isolated from each other.

[0045] In a possible implementation manner, after performing surface oxidation on at least the control gate to form a third oxide layer continuous with the second oxide layer, the preparation method further comprises:

[0046] forming a plurality of shallow trenches spaced apart from each other in the second device region;

[0047] The shallow trenches are filled with an isolation material to form the plurality of shallow trench isolation structures arranged at intervals.

[0048] In a possible implementation manner, after forming the plurality of shallow trench isolation structures arranged at intervals, the preparation method further includes:

[0049] Doping structures are formed in the first device region and the second device region based on an ion implantation process. At least a portion of the doping structure in the first device region and at least a portion of the doping structure in the second device region are formed in the same ion implantation process.

[0050] In another aspect, the present application discloses a power device, comprising:

[0051] The substrate includes a first device region and a second device region having different conductivity types;

[0052] A plurality of deep grooves are located in the substrate;

[0053] a voltage-resistant gate structure filling the deep trench;

[0054] a shield gate structure filling the deep trench, comprising a control gate and a shield gate;

[0055] A first oxide layer is located on the wall of the deep trench;

[0056] A second oxide layer covers at least a portion of the deep trench wall, the surface of the shield gate and the surface of the substrate, and the control gate, the shield gate and the substrate are isolated by the first oxide layer and the second oxide layer;

[0057] The third oxide layer at least covers the surface of the control gate.

[0058] In a possible implementation manner, the thickness of at least a portion of the second oxide layer does not exceed a first preset thickness, and the first preset thickness is 70-120 Å.

[0059] In a possible implementation manner, the thickness of the third oxide layer exceeds a second preset thickness, and the second preset thickness is 100-130 Å.

[0060] In a possible implementation manner, the at least one voltage-resistant gate structure includes a first voltage-resistant gate structure located in the first device region and a second voltage-resistant gate structure located in the second device region.

[0061] In another aspect, the present application further discloses an integrated circuit, which includes the above-mentioned power device.

[0062] In another aspect, the present application further discloses an electronic device, which includes the above-mentioned power device.

[0063] Based on the above technical solution, this application has the following beneficial effects:

[0064] The substrate of the present application includes a first device region and a second device region of different conductivity types to facilitate the modular integration of SGT devices and BCD devices, provide a connection structure foundation for internal communication between modules, reduce the number of pins, simplify connections, expand the process window, and be suitable for mass production. In addition, when preparing the gate structure of the SGT module, the first oxide layer on the substrate surface and part of the wall of the deep trench where the shield gate structure is located is removed at one time, so that the second oxide layer at least covers the exposed deep trench wall, the shield gate, and the substrate surface. The film layer is continuous and the thickness is controllable, effectively isolating the shield gate, the control gate, and the substrate structure while simplifying the oxidation process and preventing the substrate surface oxide layer from being too thick and affecting the subsequent doping injection effect. In addition, a third oxide layer is formed by surface oxidation treatment, covering at least the control gate and continuous with the second oxide layer. The thicker oxide structure formed by self-oxidation of the gate material prevents element penetration during the subsequent ion implantation process, thereby solving the IGSS (Gate Reverse Current) leakage problem. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0066] Figure 1 A schematic flow chart of a method for preparing a power device provided in accordance with an exemplary embodiment of the present application;

[0067] Figure 2-20 A schematic cross-sectional view of a power device during preparation according to an embodiment of the present application;

[0068] Figure 21-29 A schematic cross-sectional view of another power device during preparation according to an embodiment of the present application;

[0069] The following is a supplementary description of the accompanying drawings:

[0070] 100-substrate, 101-first device region, 102-second device region, 103-epitaxial layer, 104-substrate layer, 201-first mask layer, 201a-pad oxide layer, 201b-hard mask layer, 202-deep trench, 203-first sacrificial oxide layer, 204-first oxide layer, 205-first gate material layer, 206-voltage-withstand gate structure, 207-gate filling structure, 208-second sacrificial oxide layer, 209-shielding gate structure, 209a-first shielding gate structure, 209b-second shielding gate structure, 210-shielding gate, 211-control gate, 212-second oxide layer, 213-shielding layer, 214-second gate material layer, 215-third oxide layer, 216-annular spacer, 301-shallow trench, 302-shallow trench isolation structure, 303-second mask layer, 401-doping structure. DETAILED DESCRIPTION

[0071] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0072] References to "one embodiment" or "embodiment" herein refer to specific features, structures, or characteristics that may be included in at least one implementation of the present application. Throughout the description of this application, it should be understood that the terms "upper," "lower," "top," and "bottom," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely for ease of description and simplification. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly specifying the number of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. Furthermore, the terms "first," "second," etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential sequence. It should be understood that such terms are interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0073] When a numerical range is disclosed herein, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe a feature or characteristic, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. For example, a specified range from "1 to 10" should be considered to include any and all subranges between a minimum of 1 and a maximum of 10. Exemplary subranges of the range 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0074] The term "layer" as used in this application refers to a portion of a material that includes an area having a certain thickness. A layer can extend over the entire underlying or superstructure, or can extend over a localized area of ​​the underlying or superstructure. In addition, a layer can be an area of ​​a homogeneous or heterogeneous continuous structure whose thickness is less than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a shaped surface. A layer can include multiple layers. For example, the substrate 100 can include multiple sublayers, etc., and can be made of the same or different materials.

[0075] It should be understood that the definitions of “consistent” and “vertical” used in this application refer to basic consistency or basic verticality that satisfies process errors, and do not refer to absolute consistency or absolute verticality in the physical sense.

[0076] It should be understood that, as used in this application, "surface", such as "first surface", "second surface", etc. refers to the XY plane of the substrate 100 or the substrate structure, etc. corresponding to the XY plane of the power device, "in-plane direction", "lateral direction" refers to the direction parallel to the XY plane, and "thickness direction", "trench depth direction" or "longitudinal direction" refers to the Z direction relative to the XY plane.

[0077] The following describes the preparation method of the power device provided in the embodiments of the present application, Figure 1-29 The preparation method of the power device provided in the embodiments of the present application is described below, Figure 1 is a flowchart of the preparation method of the power device. The present specification provides method operation steps such as embodiments or flowcharts, but more or fewer operation steps can be included based on conventional or non-creative labor. The order of steps listed in the embodiments is only one of the many execution orders of the steps, and does not represent the only execution order. In actual preparation method execution, the method order shown in the embodiments or the drawings can be executed or executed in parallel. The preparation method can include S11-S15:

[0078] S11: providing a semiconductor structure including a substrate 100, a first oxide layer 204, a plurality of deep trenches 202, at least one voltage-resistant gate structure 206 and at least one gate filling structure 207.

[0079] Specifically, the substrate 100 includes a first device region 101 and a second device region 102 of different conductive types. The substrate 100 is a semiconductor base capable of semiconductor device processing. Exemplarily, the constituent material of the substrate 100 can be at least one of silicon, a material containing silicon (such as a III-V compound semiconductor material of gallium arsenide (GaAs)), at least one of silicon on insulator (SOI), or other types of semiconductor materials capable of forming the substrate 100.

[0080] In possible embodiments, substrate 100 may be a continuous structure, such as a wafer substrate, or may include a substrate layer 104 and an epitaxial layer 103. The epitaxial layer 103 may be formed by an epitaxial growth process. It may be an epitaxial layer 103 homogeneous with the substrate layer 104, such as one that continues to grow along the lattice direction of the substrate layer 104 to form the epitaxial layer 103, or a heteroepitaxial layer 103. Specific process conditions, such as the growth temperature, may be the same as those of existing processes or may be adaptively adjusted. The epitaxial layer 103 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other methods. Exemplary materials for the epitaxial layer 103 include silicon, germanium, gallium arsenide, gallium phosphide (GaP), gallium nitride (GaN), or other materials that can be epitaxially grown or deposited on the substrate layer 104 and that can be processed in the device region. In a possible implementation, reference Figure 2 , the first device region 101 and the second device region 102 may be formed in the epitaxial layer 103 .

[0081] Specifically, the first device region 101 is a substrate region for forming an SGT device and has a first conductivity type, and the second device region 102 is a substrate region for forming a BCD device and has a second conductivity type. In a possible embodiment, the first device region 101 and the second device region 102 are adjacent to each other to facilitate the preparation of a communication structure between the two devices. In one embodiment, the first conductivity type is N-type and the second conductivity type is P-type. Exemplarily, the first device region 101 is an N-type deep well region and the second device region 102 is a P-type deep well region, or the first device region 101 is a P-type deep well region and the second device region 102 is an N-type deep well region.

[0082] Specifically, the deep trench 202 can be formed based on a patterned etching process, and a plurality of deep trenches 202 are distributed in the first device area 101, or can be distributed in the first device area 101 and the second device area 102. The first oxide layer 204 is located on the surface of the substrate 100 and covers the groove wall of the deep trench 202. The first oxide layer 204 can be formed by a deposition process or a thermal oxidation process. Optionally, the material of the first oxide layer 204 can include but is not limited to silicon dioxide, etc. In some embodiments, the width of the deep trench 202 of the shielding gate structure 209 is 0.4μm-0.6μm, preferably 0.5μm. In some embodiments, the thickness of the first oxide layer 204 is 1800-2400A.

[0083] Specifically, the gate filling structure 207 is located in the first device region 101, and the voltage-resistant gate structure 206 and the gate filling structure 207 respectively fill the deep trench 202. The gate filling structure 207 and the voltage-resistant gate filling structure are formed in the same gate material backfilling process. The gate filling structure 207 is used to form a shielding gate structure 209 of the SGT device. The voltage-resistant gate structure 206 can be located in the first device region 101 or in the second device region 102, or at least two voltage-resistant gate structures 206 are distributed in the first device region 101 and the second device region 102, such as at least one voltage-resistant gate structure 206 including a first voltage-resistant gate structure 206 located in the first device region 101 and a second voltage-resistant gate structure 206 located in the second device region 102. Optionally, refer to Figure 9 The first voltage-resistant gate structure 206 is located between each gate filling structure 207 and the second device region 102 , and is disposed adjacent to the second device region 102 . The active region of the BCD device is disposed between the first voltage-resistant gate structure 206 and the second voltage-resistant gate structure 206 .

[0084] In some embodiments, reference Figure 2-9 The step S11 of providing a semiconductor structure including a substrate 100 , a first oxide layer 204 , a plurality of deep trenches 202 , at least one voltage-resistant gate structure 206 , and at least one gate filling structure 207 may include steps S111 - S114 :

[0085] S111: providing a substrate 100 including the first device region 101 and the second device region 102;

[0086] S112: forming a plurality of deep trenches 202 spaced apart in the substrate 100;

[0087] S113: forming a first oxide layer 204 covering the surface of the substrate 100 and the wall of the deep trench 202;

[0088] S114 : Filling the multiple deep trenches 202 with gate material to form the voltage-resistant gate structure 206 and the gate filling structure 207 .

[0089] Specifically, refer to Figure 4 , multiple deep trenches 202 are laterally distributed in the first device region 101 and the second device region 102, and are formed based on a patterned etching process. In a specific embodiment, referring to Figure 3 , a first mask layer 201 is formed on the substrate 100, spanning the first device region 101 and the second device region 102, and a photoresist is spin-coated on the first mask layer 201, and the photoresist is subjected to a patterning exposure process to achieve patterning, thereby forming a plurality of developing windows corresponding to the deep trenches 202. Then, referring to Figure 4Using the patterned photoresist as an etch stop, the first mask layer 201 is patterned based on the development window to form an etch window to expose the substrate 100 areas corresponding to the deep trenches 202 in the first device region 101 and the second device region 102. Subsequently, the photoresist is removed, and deep trench etching is performed using the first mask layer 201 as an etch stop to form a plurality of deep trenches 202. It will be appreciated that the plurality of deep trenches 202 in the first device region 101 and the second device region 102 can be formed simultaneously in the same etching process to integrate the trench etching steps for the two devices and reduce process costs.

[0090] Specifically, the first mask layer 201 covers at least the active area (AA) of the first device region 101 and the active area of ​​the second device region 102. In a possible embodiment, refer to Figure 3 The first mask layer 201 includes a pad oxide layer 201a located on the surface of the substrate 100 and a hard mask layer 201b located on the pad oxide layer 201a. The pad oxide layer 201a is used to isolate and protect the surface of the substrate 100 to avoid contamination of the surface of the substrate 100 and reduce the stress of the hard mask layer 201b. The pad oxide layer 201a can be formed on the surface of the substrate 100 by thermal oxidation or deposition process. Optionally, the material of the pad oxide layer 201a can include but is not limited to silicon dioxide. The hard mask layer 201b can be used for pattern transfer and to improve the accuracy of patterned etching. It can be formed by a deposition process. Optionally, the material of the hard mask layer 201b can include at least one of silicon nitride, titanium nitride, silicon dioxide, etc., or can also be other materials that can achieve pattern transfer. In one embodiment, the pad oxide layer 201a is a silicon oxide layer formed by thermal oxidation treatment, and the hard mask layer 201b is a deposited silicon dioxide layer.

[0091] Optionally, the deposition process can be implemented using a chemical vapor deposition (CVD) process, such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDPECVD), subatmospheric pressure chemical vapor deposition (SACVD), low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other types of chemical vapor deposition processes.

[0092] Optionally, deep trench etching can adopt a wet etching process, such as using phosphoric acid as the etching solution for wet etching, or a dry etching process can be adopted, including but not limited to at least one of ion milling etching, plasma etching, reactive ion etching, and laser ablation, such as plasma etching can be performed using a mixed gas of C4F8 and O2.

[0093] In one embodiment, the substrate 100 includes a pad oxide layer 201a. Figure 5-7 , the S113: forming a first oxide layer 204 covering the surface of the substrate 100 and the wall of the deep trench 202 may include: performing thermal oxidation treatment on the wall of the deep trench 202 to form a first sacrificial oxide layer 203 located on the wall of the deep trench 202; removing the first sacrificial oxide layer 203 and the pad oxide layer 201a to expose the surface of the substrate 100 and the wall of the deep trench 202; based on a deposition process or a thermal oxidation process, forming the first oxide layer 204 on the surface of the substrate 100 and the wall of the deep trench 202.

[0094] Specifically, before or after the hard mask layer 201b is removed, the exposed deep trench 202 wall may be thermally oxidized to oxidize the substrate 100 material into a sacrificial oxide layer of a certain thickness. Figure 5 Then, the sacrificial oxide layer and the pad oxide layer 201a on the surface of the substrate 100 are removed by wet etching or dry etching to form a deep trench 202 (such as Figure 6 ), thereby performing subsequent gate structure fabrication. Forming and removing the sacrificial oxide layer removes trench wall defects formed during deep trench etching, flattening the trench walls. The hard mask layer 201b removal process can include wet etching or dry etching.

[0095] Specifically, refer to Figure 7 The first oxide layer 204 is a continuous film layer covering the wall of the deep trench 202, the surface of the substrate 100 in the first device region 101 and the surface of the substrate 100 in the second device region 102, and a portion of the first oxide layer can be used as a field oxide layer of the SGT device.

[0096] In another specific embodiment, the S113: forming a first oxide layer 204 covering the surface of the substrate 100 and the wall of the deep trench 202 may include: removing the first mask layer 201, performing thermal oxidation treatment on the wall of the deep trench 202 to form a first sacrificial oxide layer 203 located on the wall of the deep trench 202 and the surface of the substrate 100; removing the first sacrificial oxide layer 203 to expose the surface of the substrate 100 and the wall of the deep trench 202; based on a deposition process or a thermal oxidation process, forming the first oxide layer 204 on the surface of the substrate 100 and the wall of the deep trench 202.

[0097] In a specific embodiment, referring to Figure 8-9 , S114: Filling the multiple deep trenches 202 with gate material to form the voltage-resistant gate structure 206 and the gate filling structure 207 may include: depositing gate material to form a first gate material layer 205 that fills the deep trenches 202 and covers the first oxide layer 204; using the first oxide layer 204 as a stop layer, thinning the first gate material layer 205 to obtain each voltage-resistant gate structure 206 and each gate filling structure 207 that are isolated from each other.

[0098] Specifically, refer to Figure 8 , a gate material is deposited to form a first gate material layer 205. The material of the first gate material layer 205 may include, but is not limited to, polysilicon. Then, a chemical mechanical planarization process may be performed on the first gate material layer 205 covering the surface of the substrate 100 to remove the gate material covering the first oxide layer 204, thereby obtaining a voltage-resistant gate structure 206 and a gate fill structure 207 that are isolated from each other and flush with the first oxide layer 204. The formation of the first oxide layer 204 forms a field oxide structure for the subsequent shielding gate 210, and also serves as a grinding stop layer for the gate structure preparation, simplifying the process and protecting the substrate 100 structure.

[0099] In some embodiments, reference Figure 9 , thinning the first gate material layer 205 using the first oxide layer 204 as a stop layer, i.e., stopping thinning after exposing the first oxide layer 204. In other embodiments, the first gate material layer 205 is thinned to expose the first oxide layer 204 on the surface of the substrate 100 based on a chemical mechanical planarization process, and the first oxide layer 204 on the surface of the substrate 100 is further thinned to a first thickness to reduce the oxide layer thickness on the surface of the substrate 100. This reduces the step difference between the remaining first oxide layer 204 on the surface of the substrate 100 and other areas during the subsequent removal of the first oxide layer 204, thereby reducing oxide layer removal loss. In one embodiment, the first thickness can be 900-1200 Å.

[0100] S12 : shielding the voltage-resistant gate structure 206 and etching back the gate filling structure 207 to obtain a shielding gate 210 .

[0101] Specifically, refer to Figure 10 , shielding the voltage-resistant gate structure 206 with a shielding layer 213, a photoresist can be coated on the surface of the substrate 100, and the photoresist in the area except the voltage-resistant gate structure 206 is exposed to form a shielding layer 213 that exposes each gate filling structure 207 and the surface of the substrate 100. Alternatively, the photoresist in the first device area 101 except the area of ​​the voltage-resistant gate structure 206 can be exposed to form a shielding layer 213 on the surface of the substrate 100 that shields the voltage-resistant gate structure 206 and the second device area 102. Then, the gate filling structure 207 is etched back, referring to Figure 11 , to remove part of the gate fill structure 207, leaving the remaining portion as the shield gate 210. The etching depth is determined based on the trench structure and electric field distribution requirements of the SGT device. Optionally, the etching process can be implemented based on wet etching or dry etching. Wet etching can be carried out by acid etching or plasma etching.

[0102] S13: removing the shielding layer 213 and removing the first oxide layer 204 on the surface of the substrate 100 and at least a portion of the etched-back wall of the deep trench 202 .

[0103] In some embodiments, reference Figure 13 , 14 and 16, S13 may specifically include S131-S132:

[0104] S131: removing the first oxide layer region on the unmasked wall of the deep trench 202 and the unmasked first oxide layer region on the surface of the substrate 100 to expose the unmasked wall of the deep trench 202, the unmasked surface of the substrate 100 and the unmasked portion of the sidewall of the shield gate 210;

[0105] S132: removing the shielding layer 213 and the remaining first oxide layer area on the surface of the substrate 100.

[0106] Specifically, refer to Figure 13, while retaining the shielding layer 213, the unshielded first oxide layer area is removed based on the oxide layer etching process to protect the first oxide layer 204 on the wall of the deep trench 202 where the voltage-resistant gate structure 206 is located, thereby avoiding the loss of the field oxygen structure of the voltage-resistant gate. The first oxide layer 204 above the shielding gate 210 is exposed in the back-etched deep trench 202. Based on the etching process, the exposed first oxide layer area and the first oxide layer area on the sidewall of the shielding gate 210 are removed, thereby exposing a portion of the sidewall of the shielding gate 210. After removing the shielding layer 213, the remaining first oxide layer 204 is exposed, and the first oxide layer area remaining on the surface of the substrate 100 is removed to obtain a semiconductor structure with a flat surface, so as to facilitate the subsequent oxide layer formation, gate material backfilling and thinning control.

[0107] In one specific embodiment, S132: removing the shielding layer 213 and the first oxide layer region remaining on the surface of the substrate 100 may include: removing the shielding layer 213; and thinning the first oxide layer region remaining on the surface of the substrate 100 using a chemical mechanical polishing process to expose the surface of the substrate 100. Specifically, after removing the unshielded first oxide layer region using an etching process, removing the shielding layer 213 to expose the first oxide layer region remaining on the surface of the substrate 100, and thinning the remaining first oxide layer 204 using a chemical mechanical polishing process to expose the surface of the substrate 100, thereby simplifying the process and achieving planarization of the surface of the substrate 100.

[0108] In another specific embodiment, referring to Figure 13-16 , S132: The removing of the shielding layer 213 and the remaining first oxide layer area on the surface of the substrate 100 may include: removing the shielding layer 213; performing surface thermal oxidation treatment on the exposed surface of the substrate 100, the exposed deep trench 202 wall, the exposed shielding gate 210 and the gate filling structure 207 to form a second sacrificial oxide layer 208; and removing the second sacrificial oxide layer 208 and the remaining first oxide layer area on the surface of the substrate 100 based on an oxide layer etching process.

[0109] Specifically, the shielding layer 213 can be removed based on a photoresist cleaning process, and then oxidized based on a thermal oxidation process to oxidize the exposed deep trench 202 walls, the top surface and exposed sidewalls of the shielding gate 210, the surface of the gate filling structure 207, and the surface of the substrate 100 to form a second sacrificial oxide layer 208. The second sacrificial oxide layer 208 can be continuous with the first oxide layer 204 remaining on the surface of the substrate 100. The second sacrificial oxide layer 208 and the first oxide layer 204 on the surface of the substrate 100 can be collaboratively removed through an etching process, and the first oxide layer region between the shielding gate 210 and the substrate 100, and between the voltage-resistant gate structure 206 and the substrate 100, that is, the field oxide layer is retained. By forming the sacrificial oxide layer, the overall removal of the surface oxide layer is achieved, the process is clean, and damage to the substrate 100 and the gate structure is reduced. In some embodiments, reference Figure 15 The thickness of the remaining first oxide layer 204 is greater than that of the second sacrificial oxide layer 208, and the thickness of the oxide layer formed by the voltage-resistant gate structure 206 in the second sacrificial oxide layer 208 is greater than the thickness of the oxide layer formed on the surface of the substrate 100, and is close to the thickness of the first oxide layer 204, which is beneficial to the high consistency between the voltage-resistant gate structure 206 and the surface of the substrate 100 after the oxide layer is removed, while reducing the structural loss of the substrate 100 on the wall of the deep trench 202.

[0110] In some embodiments, the thickness of the second sacrificial oxide layer 208 is 300 Å-500 Å, preferably 400 Å. After the second sacrificial oxide layer 208 is removed, the loss of the first oxide layer 204 is about 1000 Å, illustratively, 800 Å-1200 Å.

[0111] It can be understood that in the aforementioned embodiment, during the formation of the voltage-resistant gate structure 206 and the gate filling structure 207, after thinning the first gate material layer 205 to expose the first oxide layer 204 on the surface of the substrate 100, the first oxide layer 204 can be further thinned to the first thickness, so that the remaining first oxide layer 204 on the surface of the substrate 100 is thinner, reducing the heat treatment time of the second sacrificial oxide layer 208, and reducing the thickness difference between the oxide layer formed by the voltage-resistant gate structure 206 and the first oxide layer 204.

[0112] In some embodiments, the shielding gate 210 and the control gate 211 of each shielding gate structure 209 have the same structure (not shown). After forming a shielding layer 213 that shields the voltage-resistant gate structure 206, step S131 is performed to remove the exposed first oxide layer area, thereby removing the first oxide layer 204 on part of the groove wall of the deep trench 202 where each gate filling structure 207 is located.

[0113] In other embodiments, reference Figure 19 and 23, the shield gate structure 209 includes a first shield gate structure 209a and a second shield gate structure 209b; the control gate 211 and the shield gate 210 of the first shield gate structure 209a are different from the control gate 211 and the shield gate 210 of the second shield gate structure 209b; accordingly, before removing the first oxide layer region on the unshielded deep trench 202 wall and the unshielded first oxide layer region on the surface of the substrate 100 in S131, refer to Figure 12 The preparation method further includes: shielding the shield gate 210 in the deep trench 202 corresponding to the first shield gate structure 209a, thereby forming a shielding layer 213 that at least shields the voltage-resistant gate structure 206 and the first shield gate structure 209a, so as to retain the first oxide layer 204 on the wall of the deep trench 202 where the first shield gate structure 209a is located. Figure 13-14 Removing the first oxide layer region on the unshielded wall of the deep trench 202 in S131 may include: removing a portion of the first oxide layer region on the wall of the deep trench 202 corresponding to the second shielding gate structure 209b to expose a portion of the sidewall of the shielding gate 210, thereby forming a ring-shaped spacer 216 in a subsequent process.

[0114] In some embodiments, the width of the top of the shielding gate 210 in the second shielding gate structure 209 b is 2000 Å-2400 Å.

[0115] S14 : forming a second oxide layer 212 that at least covers the exposed trench wall of the deep trench 202 , the shielding gate 210 and the surface of the substrate 100 .

[0116] Specifically, the second oxide layer 212 is continuous with the first oxide layer 204 remaining on the wall of the deep trench 202, that is, the second oxide layer region formed in the deep trench 202 is continuous with the first oxide layer 204 remaining in the deep trench 202, and the first oxide layer region of the wall of the deep trench 202 where the voltage-resistant gate structure 206 is located is continuous with the second oxide layer 212 on the surface of the substrate 100, thereby isolating the shielding gate 210 and the substrate 100 structure, isolating the shielding gate 210 and the control gate 211, and isolating the voltage-resistant gate structure 206 and the substrate 100 structure.

[0117] In some embodiments, S14: forming the second oxide layer 212 covering at least the exposed deep trench 202 wall, the shielding gate 210 and the surface of the substrate 100 may include: forming the second oxide layer 212 based on a deposition process or a thermal oxidation process. Figure 17 and Figure 21, the shield gate 210, the deep trench 202 groove wall and the substrate 100 surface are thermally oxidized to form a second oxide layer 212 in situ that is continuous with the first oxide layer 204, without the need for additional patterning and masking, while avoiding the problem of excessive oxide layer thickness caused by oxide layer deposition. The second oxide layer 212 is a film layer continuous with the first oxide layer 204 to achieve coverage of the shield gate 210, the deep trench 202 groove wall and the active area surface of the substrate 100, so as to isolate the shield gate 210 and avoid the adverse effects of film stress, thereby protecting the active area of ​​the substrate 100. It can be understood that due to the difference in gate material and substrate 100 material, the thickness of the second oxide layer 212 formed by thermal oxidation in the area located on the substrate 100 is less than the thickness of the area located on the surface of the shield gate 210, thereby ensuring the shield gate electric field control effect while improving the electrical isolation effect between the shield gate 210 and the control gate 211.

[0118] In a specific embodiment, referring to Figure 17-20 The second oxide layer 212 covers the surface of the substrate 100, the exposed surface of the shielding gate 210, the exposed deep trench 202 wall and the surface of the voltage-resistant gate structure 206, and the third oxide layer 215 covers the surface of the control gate 211. Figure 16 and 17 After removing the remaining first oxide layer area on the surface of the substrate 100 in S132, the exposed deep trench 202 groove wall, the shielding gate 210, the surface of the voltage-resistant gate structure 206 and the surface of the substrate 100 are directly subjected to thermal oxidation treatment, so that the substrate 100 material, the shielding gate 210 material and the voltage-resistant gate material are in-situ oxidized, or an oxide layer is deposited to obtain a second oxide layer 212.

[0119] In another embodiment, referring to Figures 21-24 The second oxide layer 212 covers the surface of the substrate 100, the exposed surface of the shielding gate 210 and the exposed wall of the deep trench 202, and the third oxide layer 215 covers the surface of the control gate 211 and the surface of the voltage-resistant gate structure 206. Figure 16 and 21 After removing the remaining first oxide layer area on the surface of the substrate 100 in S132, the voltage-resistant gate structure 206 is shielded, and then an oxide layer is deposited or thermally oxidized to form a second oxide layer 212. The shielding structure on the voltage-resistant gate structure 206 is then removed to facilitate the preparation of the control gate 211.

[0120] S15 : forming a control gate 211 located above the shielding gate 210 to obtain a shielding gate structure 209 .

[0121] Specifically, after forming the second oxide layer 212 , the gate material is backfilled by a deposition process to obtain a control gate 211 that fills the deep trench 202 and is electrically isolated from the shielding gate 210 . The backfilled gate material may include but is not limited to polysilicon.

[0122] Specifically, refer to Figure 19 and 23 The shield gate structure 209 specifically includes a control gate 211 located at the top of the trench and a shield gate 210 located at the bottom of the trench. The control gate 211, the shield gate 210, and the substrate 100 are isolated by the first oxide layer 204 and the second oxide layer 212. The control gate 211 is used to control the conduction and cutoff of the channel of the SGT device, and the shield gate 210 is used to adjust the electric field distribution within the channel.

[0123] In a possible implementation, S15: forming the control gate 211 located above the shielding gate 210 may include S151-S152:

[0124] S151 : depositing a gate material to backfill the back-etched deep trench 202 , forming a second gate material layer 214 filling the deep trench 202 and located on the second oxide layer 212 ;

[0125] S152 : Using the second oxide layer 212 as a stop layer, thinning the second gate material layer 214 to form control gates 211 isolated from each other.

[0126] Specifically, refer to Figure 18-23 The deposition process of the gate material may include, but is not limited to, plasma enhanced chemical vapor deposition, high density plasma chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. The backfill depth exceeds the depth of the deep trench 202 to form a second gate material layer 214 covering the second oxide layer 212. The thickness of the second gate material layer 214 is set based on process requirements. In this way, the second gate material layer 214 above the substrate 100 is removed by using the second oxide layer 212 as a stop layer, without the need for complex mask preparation and other steps, simplifying the preparation process of the control gate 211 and reducing process costs.

[0127] Next, the second gate material layer 214 is thinned by a chemical mechanical polishing process until the second oxide layer 212 is exposed, or the second gate material layer 214 is thinned by a chemical mechanical polishing process until the layer thickness reaches the second thickness, and then the gate material is etched back to remove the gate material on the surface of the second oxide layer 212 by an etching process, thereby exposing the second oxide layer 212. The gate material remaining in the deep trench 202 forms the control gate 211 to obtain a shielding structure. Figure 18-19, when the second oxide layer 212 covers the voltage-resistant gate structure 206, it is preferred to first thin the second gate material layer 214 to the second thickness based on a chemical mechanical polishing process, and then etch back the thinned second gate material layer 214 based on an etching process, thereby removing the gate material on the surface of the substrate 100 and exposing the second oxide layer 212, thereby avoiding gate material residue on the surface of the substrate 100. In this way, by depositing a certain thickness of the second gate material layer 214 and then thinning it, the second gate material layer 214 is flattened before etching, so as to facilitate etching precision control and ensure the control precision of the control gate 211. In one embodiment, the second thickness can be 800-1100A, preferably 1000A. Optionally, this embodiment can also use a chemical mechanical polishing process to directly thin the second gate material layer 214 to expose the second oxide layer 212. Reference Figure 22-23 In the case where the second oxide layer 212 does not cover the voltage-withstand gate structure 206, it is preferred that the second oxide layer 212 be used as a polishing stop layer, and the second gate material layer 214 be thinned using a chemical mechanical polishing process until the second oxide layer 212 is exposed, thereby removing the gate material on the surface of the substrate 100 and reducing the loss of the voltage-withstand gate structure 206. Alternatively, in this embodiment, the second gate material may be thinned using a chemical mechanical polishing process and then etched back using an etching process until the second oxide layer 212 is exposed.

[0128] Specifically, refer to Figure 19 and Figure 23 There is an annular spacer 216 between the second oxide layer 212 on the shielding gate 210 of the second shielding gate structure 209b and the second oxide layer 212 on the wall of the deep trench 202, and both are continuous with the first oxide layer 204 remaining in the deep trench 202. The control gate 211 fills the top of the shielding gate 210 and the annular spacer 216, forming a plug structure with the shielding gate 210.

[0129] S16 : performing surface oxidation on at least the control gate 211 to form a third oxide layer 215 continuous with the second oxide layer 212 .

[0130] Understandably, under the same oxidation time, the thickness of the oxide layer formed by the in-situ oxidation of the gate material is greater than the thickness of the oxide layer formed by the silicon material of the substrate 100. Through surface oxidation treatments such as thermal oxidation, a thicker third oxide layer 215 is formed, effectively isolating and protecting the gate structure, preventing element penetration into the gate structure during subsequent ion implantation, thereby avoiding IGSS leakage issues. Simultaneously, a thinner second oxide layer 212 is formed on the surface of the substrate 100 before the gate surface is oxidized, preventing the oxide layer on the surface of the substrate 100 from thickening, thereby ensuring the effectiveness of subsequent ion implantation in the active area.

[0131] In summary, the substrate 100 of the above technical solution includes a first device region 101 and a second device region 102 of different conductivity types, which facilitates the modular integration of SGT devices and BCD devices, provides a connection structure foundation for internal communication between modules, reduces the number of pins, simplifies connections, expands the process window, and is suitable for mass production. In addition, when preparing the gate structure of the SGT module, the first oxide layer 204 on the surface of the substrate 100 and a portion of the groove wall of the deep trench 202 where the shielding gate structure 209 is located is removed at one time, so that the second oxide layer 212 at least covers the exposed groove wall of the deep trench 202, the shielding gate 210, and the surface of the substrate 100. The film layer is continuous and the thickness is controllable. While effectively isolating the shielding gate 210, the control gate 211, and the substrate 100 structure, it simplifies the oxidation process and prevents the oxide layer on the surface of the substrate 100 from being too thick and affecting the subsequent doping injection effect. In addition, a third oxide layer 215 is formed by surface oxidation treatment, which at least covers the control gate 211 and is continuous with the second oxide layer 212. The thicker oxide structure formed by the self-oxidation of the gate material prevents the penetration of elements during the subsequent ion implantation process, thereby solving the IGSS (Gate Reverse Current) leakage problem.

[0132] In some embodiments, reference Figure 19 and 20 The second oxide layer 212 covers the surface of the substrate 100, the exposed surface of the shielding gate 210, the exposed deep trench 202 wall and the surface of the voltage-resistant gate structure 206. Accordingly, S16 may include: performing thermal oxidation treatment on the surface of the exposed control gate 211 to form a third oxide layer 215 continuous with the second oxide layer 212.

[0133] In other embodiments, reference Figure 23 and 24 The second oxide layer 212 covers the surface of the substrate 100, the exposed surface of the shielding gate 210 and the exposed wall of the deep trench 202. Accordingly, S16 may include: performing thermal oxidation treatment on the surface of the exposed control gate 211 and the surface of the exposed voltage-resistant gate structure 206 to form a third oxide layer 215 continuous with the second oxide layer 212.

[0134] Specifically, the exposed surface of the control gate 211 is thermally oxidized to form a third oxide layer 215 of a desired thickness, thereby preventing the oxide layer on the surface of the substrate 100 from thickening, ensuring the effect of subsequent ion implantation in the active area, and preventing implantation damage to the control gate 211, thereby avoiding the IGSS (Gate Reverse Current) leakage problem.

[0135] Specifically, the top and / or bottom surfaces of the second oxide layer region and the third oxide layer 215 formed by thermal oxidation of the gate material are arc surfaces. Accordingly, the second oxide layer region and the third oxide layer 215 formed by thermal oxidation are semi-ellipsoidal or ellipsoidal with convex top and / or bottom surfaces.

[0136] In some embodiments, the thickness of at least a portion of the second oxide layer 212 does not exceed a first predetermined thickness, which is 70-120 Å, preferably 100 Å. In a preferred embodiment, the thickness of the second oxide layer 212 on the surface of the substrate 100 does not exceed the first predetermined thickness, preferably 70-100 Å, to provide isolation protection while improving the ion implantation effect.

[0137] In some embodiments, the thickness of the third oxide layer 215 is greater than the thickness of the second oxide layer 212 on the surface of the substrate 100. The thickness of the third oxide layer 215 exceeds a second predetermined thickness, which is 100-130 Å, preferably 100 Å. In one example, the thickness of the third oxide layer 215 is 110 Å. This provides effective isolation protection and avoids IGSS leakage problems caused by subsequent annealing of the shallow trench isolation structure 302.

[0138] In some embodiments, after surface oxidation of at least the control gate 211 is performed in S16 to form a third oxide layer 215 continuous with the second oxide layer 212, the preparation method further includes S17-S18:

[0139] S17: forming a plurality of shallow trenches 301 arranged at intervals in the second device region 102;

[0140] S18: Filling the shallow trenches 301 with isolation material to form the plurality of shallow trench isolation structures 302 arranged at intervals.

[0141] Specifically, the shallow trench isolation structure 302 is located between the voltage-withstand gate structure 206 of the first device region 101 and the second voltage-withstand gate structure 206 of the second device region 102 .

[0142] Specifically, the second device region 102 is processed based on the shallow trench 301 process to form a plurality of shallow trench isolation structures 302. The patterning process of the shallow trench 301 is similar to the patterning process of the deep trench 202. Figures 25-28 A second mask layer 303 may be formed on the surface of the substrate 100, a photoresist may be coated on the second mask layer 303, and the photoresist may be patterned to expose a portion of the second mask layer 303. The patterned photoresist may be used as an etching barrier layer to etch the second mask layer 303 to form an etching window for the shallow trench 301. The shallow trench may be etched using a wet or dry etching process, such as Figure 26The material of the second mask can include, but is not limited to, at least one of silicon nitride, titanium nitride, silicon dioxide, etc. In an example, the second mask layer 303 is a silicon nitride layer.

[0143] Specifically, the isolation material filling can be implemented at least by a deposition process, which includes but is not limited to plasma enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, sub-atmospheric chemical vapor deposition, low-pressure chemical vapor deposition, atomic layer deposition, plasma enhanced atomic layer deposition, etc. The isolation material can include, but is not limited to, silicon oxide.

[0144] In some embodiments, after S18: the forming of the plurality of spaced shallow trench isolation structures 302, the preparation method further includes S19: forming a doping structure 401 in the first device region 101 and the second device region 102 based on an ion implantation process, at least part of the doping structure 401 in the first device region 101 and at least part of the doping structure 401 in the second device region 102 are formed in the same ion implantation process.

[0145] Specifically, the same type of doping structure 401 in the first device region 101 and the second device region 102 can be formed in the same ion implantation process, so that not only the modular integration of SGT devices and BCD devices is achieved, but also similar process steps of the two types of devices can be integrated to simplify the device preparation process and reduce the preparation cost while improving the communication performance.

[0146] Specifically, the doping structure 401 can include a well region, and a source structure or a drain structure. For example, referring to Figure 29 The P well in the active region of the SGT device and the P well in the active region of the BCD device can be formed in the same ion implantation process, and the N+ well in the active region of the SGT device and the N+ well in the active region of the BCD device can be formed in the same ion implantation process. In one embodiment, the ion implantation process includes at least an ion implantation process and an annealing process, and the third oxide layer 215 can not only avoid ion implantation into the gate structure, but also reduce the risk of device damage during the annealing process.

[0147] In some embodiments, the SGT device formed in the first device region 101 is an SGT MOSFET, to further improve the performance of the semiconductor device, reduce the on-resistance, and improve the efficiency and reliability of the device circuit.

[0148] The present application also provides a power device prepared based on the above preparation method. For example, referring to Figure 20, 24, 28 and 29, the power device specifically includes a substrate 100, a plurality of deep trenches 202, a voltage-resistant gate structure 206 filling the deep trenches 202, a shielding gate structure 209 filling the deep trenches 202, a first oxide layer 204, a second oxide layer 212 and a third oxide layer 215; the substrate 100 includes a first device area 101 and a second device area 102 with different conductivity types; a plurality of deep trenches 202 are located in the substrate 100; the shielding gate structure 209 includes a control gate 211 and a shielding gate 210; the first oxide layer 204 is located in the groove wall of the deep trench 202; the second oxide layer 212 covers at least part of the groove wall of the deep trench 202, the surface of the shielding gate 210 and the surface of the substrate 100, the control gate 211, the shielding gate 210 and the substrate 100 are isolated by the first oxide layer 204 and the second oxide layer 212; the third oxide layer 215 covers at least the surface of the control gate 211.

[0149] In a possible implementation manner, the thickness of at least a portion of the second oxide layer 212 does not exceed a first preset thickness, and the first preset thickness is 70-120 Å.

[0150] In a possible implementation manner, the thickness of the third oxide layer 215 exceeds a second preset thickness, and the second preset thickness is 100-130 Å.

[0151] In a possible implementation, the at least one voltage-withstanding gate structure 206 includes a first voltage-withstanding gate structure 206 located in the first device region 101 and a second voltage-withstanding gate structure 206 located in the second device region 102 .

[0152] In a possible implementation, the second oxide layer 212 covers the surface of the substrate 100 , the exposed surface of the shielding gate 210 and the exposed wall of the deep trench 202 , and the third oxide layer 215 covers the surface of the control gate 211 and the surface of the voltage-resistant gate structure 206 .

[0153] In a possible implementation, the second oxide layer 212 covers the surface of the substrate 100 , the exposed surface of the shielding gate 210 , the exposed wall of the deep trench 202 and the surface of the voltage-resistant gate structure 206 , and the third oxide layer 215 covers the surface of the control gate 211 .

[0154] Specifically, the shielding gate structure 209 is formed based on the gate filling structure 207 , and the voltage-resistant gate structure 206 and the gate filling structure 207 are formed by filling the plurality of deep trenches 202 with gate materials.

[0155] In some embodiments, the second oxide layer 212 is formed by a deposition process. In other embodiments, the second oxide layer 212 is formed by a thermal oxidation process.

[0156] In a possible implementation, the shield gate structure 209 includes a first shield gate structure 209a and a second shield gate structure 209b; the peripheral side of the shield gate 210 of the first shield gate structure 209a and the peripheral side of the control gate 211 are covered by the first oxide layer 204, the top surface of the shield gate 210 and the bottom surface of the control gate 211 are separated by the second oxide layer 212, the control gate 211 and the shield gate 210 of the first shield gate structure 209a are oppositely arranged columnar structures; the lower part of the groove wall of the deep trench 202 where the second shield gate structure 209b is located is covered by the first oxide layer 204, and the upper part is covered by the second oxide layer 212, the upper end of the peripheral side of the shield gate 210 is covered by the second oxide layer 212, the second oxide layer 212 on the shield gate 210 and the second oxide layer 212 of the groove wall of the deep trench 202 have annular spacing 216 therebetween and are continuous with the first oxide layer 204 remaining in the deep trench 202, and the control gate 211 fills the top of the shield gate 210 and the annular spacing 216 to form a plug structure with the shield gate 210.

[0157] Specifically, the thickness of the second oxide layer 212 on the surface of the shield gate 210 formed by thermal oxidation is greater than the thickness of the second oxide layer 212 on the surface of the substrate 100.

[0158] Specifically, the thickness of the oxide layer on the surface of the control gate 211 and / or the surface of the voltage resistance gate structure 206 formed by thermal oxidation is greater than the thickness of the second oxide layer 212 on the surface of the substrate 100.

[0159] Specifically, the top surface and / or the bottom surface of the oxide layer structure formed by thermal oxidation of the gate material is arc-shaped, such as the third oxide layer 215, the second oxide layer 212 on the surface of the shield gate 210, and the second oxide layer 212 on the surface of the voltage resistance gate structure 206, specifically, the top surface and / or the bottom surface is convex semi-ellipsoidal or ellipsoidal.

[0160] In a possible implementation, the power device further includes a doping structure 401, referring to Figure 29 At least part of the doping structure 401 of the first device region 101 and at least part of the doping structure 401 of the second device region 102 are formed in the same ion implantation process.

[0161] It should be noted that the power device embodiments of the present application are realized based on the power device preparation method embodiments, and both are based on the same inventive concept.

[0162] The electronic device provided in the embodiments of the present application includes the power device and an electronic component connected to the power device.

[0163] The electronic device of the embodiments of the present application can be selected from any electronic product or device such as a mobile phone, a Personal Digital Assistant (PDA), a pad, a notebook computer, a game machine, a television, a Video Compact Disc (VCD), a Digital Video Disc (DVD), a navigator, a camera, a camcorder, a voice recorder, an MP3, an MP4, a PlayStation Portable (PSP), and the like, and can also be an intermediate product of any electronic device including the power device.

[0164] It should be noted that the above-mentioned embodiments of the present application are in the order of description only, and do not represent the advantages and disadvantages of the embodiments. The above-mentioned embodiments of the present application are described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that in the embodiments and still achieve the desired result. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In some embodiments, multi-task processing and parallel processing are possible or advantageous.

[0165] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the difference from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments.

[0166] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk.

[0167] The above-mentioned is only the preferred embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a power device, characterized in that: include: A semiconductor structure is provided, comprising a substrate, a first oxide layer, a plurality of deep trenches, at least one voltage-resistant gate structure, and at least one gate filling structure, wherein the substrate comprises a first device region and a second device region of different conductivity types, the gate filling structure is located in the first device region, the first oxide layer is located on the surface of the substrate and covers the walls of the deep trenches, and the voltage-resistant gate structure and the gate filling structure respectively fill the deep trenches; The substrate surface includes a pad oxide layer; The first oxide layer is formed by: performing a thermal oxidation process on the deep trench wall to form a first sacrificial oxide layer located on the deep trench wall; removing the first sacrificial oxide layer and the pad oxide layer to expose the substrate surface and the deep trench wall; and forming the first oxide layer on the substrate surface and the deep trench wall based on a deposition process or a thermal oxidation process; Shielding the voltage-resistant gate structure and etching back the gate filling structure to obtain a shielding gate; removing the shielding layer, and removing the first oxide layer on the substrate surface and at least a portion of the etched-back deep trench wall; forming a second oxide layer covering at least the exposed deep trench wall, the shielding gate, and the surface of the substrate, wherein the second oxide layer is continuous with the first oxide layer remaining on the deep trench wall; forming a control gate located above the shielding gate to obtain a shielding gate structure, wherein the control gate, the shielding gate, and the substrate are isolated by the first oxide layer and the second oxide layer; At least the control gate is surface-oxidized to form a third oxide layer continuous with the second oxide layer.

2. The preparation method according to claim 1, characterized in that The preparation method satisfies at least one of the following characteristics: The thickness of at least a portion of the second oxide layer does not exceed a first preset thickness, wherein the first preset thickness is 70-120 Å; The thickness of the third oxide layer exceeds a second preset thickness, and the second preset thickness is 100-130 Å.

3. The preparation method according to claim 1, characterized in that The step of removing the shielding layer and removing the first oxide layer on the substrate surface and at least a portion of the etched-back deep trench wall comprises: Removing the first oxide layer region on the unmasked deep trench wall and the unmasked first oxide layer region on the substrate surface to expose the unmasked deep trench wall, the unmasked substrate surface and the unmasked portion of the sidewall of the shielding gate; The shielding layer and the remaining first oxide layer area on the surface of the substrate are removed.

4. The preparation method according to claim 3, characterized in that The removing of the shielding layer and the first oxide layer region remaining on the surface of the substrate comprises: removing the shielding layer; thinning the remaining first oxide layer region on the substrate surface based on a chemical mechanical polishing process to expose the substrate surface; or, The removing of the shielding layer and the first oxide layer region remaining on the surface of the substrate comprises: removing the shielding layer; Performing surface thermal oxidation treatment on the exposed substrate surface, the exposed deep trench wall, the exposed shielding gate and the gate filling structure to form a second sacrificial oxide layer; The second sacrificial oxide layer and the remaining first oxide layer region on the surface of the substrate are removed based on an oxide layer etching process.

5. The preparation method according to claim 3, characterized in that The shielding grid structure includes a first shielding grid structure and a second shielding grid structure; Before removing the first oxide layer region on the unshielded deep trench wall and the unshielded first oxide layer region on the substrate surface, the preparation method further comprises: shielding the shielding gate in the deep trench corresponding to the first shielding gate structure; The step of removing the first oxide layer region on the unshielded deep trench wall comprises: A portion of the first oxide layer region on the wall of the deep trench corresponding to the second shield gate structure is removed.

6. The preparation method according to claim 1, characterized in that The forming of the second oxide layer covering at least the exposed deep trench wall, the shield gate and the substrate surface comprises: The second oxide layer is formed based on a deposition process or a thermal oxidation process; the second oxide layer covers the surface of the substrate, the exposed surface of the shielding gate and the exposed deep trench wall, and the third oxide layer covers the surface of the control gate and the surface of the voltage-resistant gate structure; or, the second oxide layer covers the surface of the substrate, the exposed surface of the shielding gate, the exposed deep trench wall and the surface of the voltage-resistant gate structure, and the third oxide layer covers the surface of the control gate.

7. The preparation method according to any one of claims 1 to 6, characterized in that The forming of the control gate located above the shielding gate comprises: Depositing a gate material to backfill the back-etched deep trench to form a second gate material layer filling the deep trench and located on the second oxide layer; The second oxide layer is used as a stop layer, and the second gate material layer is thinned to form control gates isolated from each other.

8. The preparation method according to any one of claims 1 to 6, characterized in that The semiconductor structure comprising a substrate, a first oxide layer, a plurality of deep trenches, at least one voltage-resistant gate structure, and at least one gate filling structure is provided, comprising: Providing a substrate including the first device region and the second device region; forming a plurality of deep trenches spaced apart from each other in the substrate; forming a first oxide layer covering the surface of the substrate and the wall of the deep trench; The multiple deep trenches are filled with gate material to form the voltage-resistant gate structure and the gate filling structure.

9. The preparation method according to claim 8, characterized in that Filling the plurality of deep trenches with a gate material to form the voltage-resistant gate structure and the gate filling structure includes: Depositing a gate material to form a first gate material layer filling the deep trench and covering the first oxide layer; The first oxide layer is used as a stop layer, and the first gate material layer is thinned to obtain voltage-resistant gate structures and gate filling structures that are isolated from each other.

10. The preparation method according to any one of claims 1 to 6, characterized in that: After performing surface oxidation on at least the control gate to form a third oxide layer continuous with the second oxide layer, the preparation method further comprises: forming a plurality of shallow trenches spaced apart from each other in the second device region; The shallow trenches are filled with an isolation material to form the plurality of shallow trench isolation structures arranged at intervals.

11. The preparation method according to claim 10, characterized in that: After forming the plurality of shallow trench isolation structures arranged at intervals, the preparation method further includes: Doping structures are formed in the first device region and the second device region based on an ion implantation process. At least a portion of the doping structure in the first device region and at least a portion of the doping structure in the second device region are formed in the same ion implantation process.

12. A power device, prepared based on the preparation method according to any one of claims 1 to 11, characterized in that: include: The substrate includes a first device region and a second device region having different conductivity types; A plurality of deep grooves are located in the substrate; A voltage-resistant gate structure filling the deep trench; a shield gate structure filling the deep trench, comprising a control gate and a shield gate; A first oxide layer is located on the wall of the deep trench; A second oxide layer covers at least a portion of the deep trench wall, the surface of the shield gate and the surface of the substrate, and the control gate, the shield gate and the substrate are isolated by the first oxide layer and the second oxide layer; The third oxide layer at least covers the surface of the control gate.

13. The power device according to claim 12, characterized in that: The power device meets at least one of the following characteristics: The thickness of at least a portion of the second oxide layer does not exceed a first preset thickness, wherein the first preset thickness is 70-120 Å; The thickness of the third oxide layer exceeds a second preset thickness, and the second preset thickness is 100-130 Å; The at least one voltage-resistant gate structure includes a first voltage-resistant gate structure located in the first device region and a second voltage-resistant gate structure located in the second device region.

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