Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and is used for solving the problem of how to improve a grid forming process. The semiconductor device comprises a plurality of fin structures, a plurality of gate structures, a plurality of epitaxial parts, an isolation structure and a plurality of etching stop parts. The fin structures extend along a first direction, the plurality of fin structures are arranged along a second direction, and the first direction intersects with the second direction; the gate structure is arranged across the plurality of fin structures along a second direction; epitaxial parts are arranged on the two sides of the gate structure in the first direction respectively, and the epitaxial parts are located on the fin structure; the isolation structure cuts off the plurality of gate structures along the first direction; the plurality of etching stop portions and the cut portions of the plurality of gate structures are alternately arranged along the first direction, and the etching stop portions along the second direction are located between the adjacent epitaxial portions on two sides of the isolation structure. The semiconductor device can be used to form a chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] With the continuous development of integrated circuit technology, the feature size of the semiconductor devices that make up integrated circuits has been continuously reduced in order to increase the integration density of integrated circuits, improve their operating speed and reduce their energy consumption. However, this reduction in feature size has brought difficulties to the manufacturing process.

[0003] For example, when preparing semiconductor fin field-effect transistor (FinFET) devices, the gate size is also reduced due to the principle of proportional reduction. The existing process has shortcomings in forming the gate with reduced size, and the process of forming the gate needs to be further improved. Summary of the Invention

[0004] Embodiments of the present application provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device to solve the problem of how to improve the process of forming a gate.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, embodiments of the present application provide a semiconductor device comprising: a plurality of fin structures, a plurality of gate structures, a plurality of epitaxial portions, an isolation structure, and a plurality of etch stop portions. The fin structures extend along a first direction, and the plurality of fin structures are arranged along a second direction, with the first direction intersecting the second direction. The gate structure is arranged across the plurality of fin structures along the second direction. The epitaxial portions are provided on both sides of the gate structure along the first direction, and the epitaxial portions are located on the fin structure. The isolation structure truncates the plurality of gate structures along the first direction. The plurality of etch stop portions and the truncation portions of the plurality of gate structures are arranged alternately along the first direction, and the etch stop portions are located between adjacent epitaxial portions on both sides of the isolation structure along the second direction.

[0007] Thus, during the formation of multiple gate structures, a first etching process can be used to first remove material from a first region. The first region spans across multiple gate structures along a first direction and is located between adjacent epitaxial portions along a second direction. The first region can be defined by a photoforming process. The first etching process can have a low selectivity for the gate structures, meaning that the gate structures are etched more slowly. When removing material from the first region, the portion of the gate structures removed is negligible. Consequently, a greater amount of material can be removed between adjacent gate structures along the first direction, thereby forming a first recess between two adjacent gate structures.

[0008] Then, an etch-stop material can be formed on the surface of the side where the first groove is located. By controlling the thickness of the etch-stop material during deposition, the etch-stop material on both sidewalls of the first groove along the first direction can contact each other, so that the etch-stop material fills the first groove. Finally, a second etching process can be performed from the etch-stop material toward the gate structure to cut off the multiple gate structures. The second etching process has a low selectivity for the etch-stop material, that is, the etch-stop material is removed more slowly than the gate structure material.

[0009] In the initial stage of the second etching process, the second etching process simultaneously removes the etch-stop material deposited on the gate structure and the etch-stop material in the first groove. When the etch-stop material on the gate structure is completely removed and the etching process continues, the gate structure material can be removed more quickly. In the area where the first groove is located, the presence of a large amount of etch-stop material prevents the second etching process from continuing to etch the area between the epitaxial portions, thereby avoiding damage to the epitaxial portions. After the gate structure material is etched to form a trench and cut off the gate structure, the etch-stop material in the first groove forms an etch-stop portion, and the etch-stop portion prevents further etching of the area between the epitaxial portions, thereby avoiding damage to the epitaxial portions.

[0010] Furthermore, the first recess is defined by the first region defined by the photoforming process. This means the photoforming process defines the dimensions of the first recess along the second direction. Because etch-stop material is formed on the surface of one side of the first recess, a certain thickness of etch-stop material is also formed on the sidewalls of both sides of the first region along the second direction. Therefore, when the trench that ultimately forms the gate structure is cut off, the etch-stop material on these sidewalls is not removed. Therefore, the trench's dimensions along the second direction, i.e., the recess formed on the etch-stop portion, are reduced by the thickness of the etch-stop material on these sidewalls. This allows the trench's dimensions to exceed those of the first region defined by the photoforming process, helping to overcome the limitations of the photoforming process on miniaturization of semiconductor devices.

[0011] In one possible implementation of the first aspect, the isolation structure includes a plurality of isolation portions, each isolation portion interrupting a gate structure along a first direction; the plurality of isolation portions and the plurality of etch stop portions are alternately arranged along the first direction. The plurality of isolation portions are arranged along the first direction, respectively interrupting the plurality of gate structures arranged along the first direction, thereby forming independently controllable gates.

[0012] In one possible implementation of the first aspect, the semiconductor device further includes an interlayer dielectric layer, the interlayer dielectric layer filling the gaps between the multiple fin structures and covering the multiple epitaxial portions; the isolation portion penetrates the interlayer dielectric layer, and the etch stop portion is embedded in the surface of the interlayer dielectric layer near the multiple epitaxial portions. In this way, the isolation portion penetrates the interlayer dielectric layer, ensuring that the gate structure is completely cut off. Furthermore, the etch stop portion embedded in the interlayer dielectric layer prevents removal of the interlayer dielectric layer in the area where the etch stop portion is located, thereby preventing damage to the epitaxial portions on the fin structures.

[0013] In one possible implementation of the first aspect, the isolation structure further includes an isolation layer, the isolation layer covering and connecting the plurality of isolation portions; the isolation layer also covering a portion of each etch stop portion. Thus, the isolation layer connects the plurality of isolation portions into a single entity, allowing the isolation layer and the plurality of isolation portions to be deposited using the same process.

[0014] In a possible implementation of the first aspect, the etch stop portion is formed with a groove, and a portion of the isolation layer is disposed in the groove. In this way, the isolation layer extends in the first direction and connects the plurality of isolation portions arranged along the first direction.

[0015] In one possible implementation of the first aspect, the semiconductor device further includes gate spacers, each provided on either side of the gate structure along the first direction; the gate spacers further extending between the etch stop portion and an isolation portion adjacent to the etch stop portion. Thus, the etch stop portions and the isolation portions are alternately arranged, and the gate spacers extend between the etch stop portions and the isolation portion adjacent to the etch stop portion. Therefore, the gate spacers can be located on both sides of the isolation portion, facilitating the formation of the isolation portion.

[0016] In one possible implementation of the first aspect, the semiconductor device further includes a substrate, the substrate including a first surface and a second surface opposing each other in a thickness direction of the substrate, the plurality of fin structures being disposed on the second surface; and a distance from an end of the etch stop portion proximate the first surface to the first surface is greater than or equal to a distance from an end of the gate sidewall proximate the first surface to the first surface. In this manner, when forming the first recess to accommodate the isolation portion, the first recess is prevented from being excessively recessed and thereby damaging the epitaxial portion.

[0017] In one possible implementation of the first aspect, a portion of the gate spacer between the etch stop portion and an isolation portion adjacent to the etch stop portion is covered by the isolation structure, so that the isolation structure can extend in the first direction and intercept the plurality of gate structures.

[0018] In one possible implementation of the first aspect, a first distance is defined between an end of the etch stop portion closest to the first surface of the substrate and the first surface, a second distance is defined between positions of two adjacent extension portions on either side of the etch stop portion closest to each other and the first surface, and the first distance is greater than or equal to the second distance. This prevents excessive depression of the first recess, which could damage the extension portion, when forming the first recess to accommodate the isolation portion.

[0019] In one possible implementation of the first aspect, the gate structure comprises a first material, and the etch stop comprises a second material. Under a predetermined etching process, the etching rate of the first material is greater than the etching rate of the second material. Thus, during the second etching process, the gate structure can be cut off first, thereby forming the etch stop.

[0020] In a possible implementation manner of the first aspect, the material of the etch stop portion includes silicon nitride or silicon oxynitride, so as to slow down the etching speed of the etch stop portion.

[0021] In a second aspect, the present application provides a method for preparing a semiconductor device, comprising: forming a plurality of fin structures, a plurality of initial gate structures, a plurality of epitaxial portions and an interlayer dielectric layer on a substrate; the fin structures extend along a first direction, and the plurality of fin structures are arranged along a second direction, the first direction intersecting the second direction; the initial gate structure is arranged across the plurality of fin structures along the second direction; epitaxial portions are provided on both sides of the initial gate structure along the first direction, and the epitaxial portions are located on the fin structures; an interlayer dielectric layer is filled in the gaps between the plurality of fin structures and covers the plurality of epitaxial portions, and the plurality of initial gate structures are embedded in the surface of the interlayer dielectric layer away from the substrate; a plurality of first grooves are formed on the surface of the interlayer dielectric layer away from the substrate, the plurality of first grooves and the initial gate structures are alternately arranged along the first direction, and the first grooves are at least partially located between adjacent epitaxial portions on both sides of the initial gate structure along the second direction; a plurality of etch stop portions are formed in the plurality of first grooves; based on the plurality of etch stop portions, the initial gate structure is etched to form a trench that cuts off the initial gate structure along the first direction; the remaining initial gate structure forms a gate structure; and an isolation structure is formed in the trench.

[0022] In this way, a plurality of etch stop portions are formed in the plurality of first grooves, and the plurality of etch stop portions can prevent further etching toward the region between the epitaxial portions, thereby avoiding damage to the epitaxial portions.

[0023] In one possible implementation of the second aspect, forming a plurality of first recesses on a surface of an interlayer dielectric layer remote from the substrate includes: forming a hard mask layer having a first opening, wherein the first opening spans across the plurality of initial gate structures along a first direction and is located between two adjacent epitaxial portions along a second direction; and etching the interlayer dielectric layer based on the hard mask layer to form the plurality of first recesses. In this manner, by selecting an etching process with a low selectivity for the initial gate structures, the plurality of first recesses can be simultaneously formed while etching the interlayer dielectric layer in the areas exposed by the first openings.

[0024] In one possible implementation of the second aspect, forming multiple etch-stop portions in the multiple first recesses includes: forming an etch-stop layer, the etch-stop layer covering surfaces of the hard mask layer and the initial gate structure exposed by the first opening, and filling the multiple first recesses; removing portions of the etch-stop layer covering the hard mask layer and the initial gate structure, and forming the multiple etch-stop portions with the etch-stop layer remaining in the multiple first recesses. Thus, by filling the multiple first recesses with the etch-stop layer, the portions of the etch-stop layer covering the hard mask layer and the initial gate structure and the etch-stop layer in the first recesses can be simultaneously etched, and after removing the portions of the etch-stop layer covering the hard mask layer and the initial gate structure, the multiple etch-stop portions are formed in the first recesses.

[0025] In one possible implementation of the second aspect, etching the initial gate structure based on the multiple etch-stop portions includes: etching the initial gate structure based on the hard mask layer and the multiple etch-stop portions to form a trench; the trench includes multiple sub-trenches, each sub-trench intercepting one initial gate structure along a first direction, and the multiple sub-trenches and the multiple etch-stop portions are alternately arranged along the first direction; forming an isolation structure in the trench includes: filling the trench with a predetermined material to form the isolation structure; and forming the predetermined material filled in the multiple sub-trenches into multiple isolation portions of the isolation structure. In this way, the initial gate structure can be intercepted by the sub-trenches, and the isolation structure can be formed in the trench, thereby forming multiple gate structures.

[0026] In one possible implementation of the second aspect, twice the thickness of the etch-stop layer is greater than or equal to a dimension of the first recess along the first direction. In this manner, the etch-stop layers on two opposing sidewalls of the first recess along the first direction contact each other, thereby ensuring that the dimension of the etch-stop layer in the first recess in the substrate thickness direction is greater than that of other portions. Consequently, after the second etching process removes the portion of the etch-stop layer covering the hard mask layer and the initial gate structure, multiple etch-stop portions are formed in the first recess.

[0027] In a third aspect, the present application provides a chip comprising any semiconductor device according to the first aspect. Because the semiconductor device can form a smaller gate structure and, in the process of cutting off the gate structure, can break through the light shaping limit, the semiconductor device can be reduced in size, thereby increasing the integration of the chip including the semiconductor device, thereby improving the performance of the chip.

[0028] In a fourth aspect, the present application provides an electronic device comprising a printed circuit board and a chip as in the third aspect, wherein the chip is disposed on the printed circuit board. Since the chip used in the electronic device has high performance, the performance of the electronic device can also be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of an electronic device provided in an embodiment of the present application;

[0030] Figure 2a A schematic diagram of the three-dimensional structure of a semiconductor device provided in an embodiment of the present application;

[0031] Figure 2b for Figure 2a A schematic diagram of the top view structure of the semiconductor device;

[0032] Figure 2c for Figure 2a A schematic diagram of the cross-sectional structure of the semiconductor device along the B1-B1 direction;

[0033] Figure 2d for Figure 2a A schematic diagram of the cross-sectional structure of the semiconductor device along the A1-A1 direction;

[0034] Figure 3 Provided in the embodiments of this application Figure 2a A schematic diagram of the cross-sectional structure of the semiconductor device along the C1-C1 direction during the manufacturing process;

[0035] Figure 4a A schematic diagram of the three-dimensional structure of another semiconductor device provided in an embodiment of the present application;

[0036] Figure 4b for Figure 4a A schematic diagram of the top view structure of the semiconductor device;

[0037] Figure 4c along Figure 4a A schematic diagram of the cross-sectional structure of the semiconductor device along the B2-B2 direction;

[0038] Figure 4d along Figure 4a A schematic diagram of the cross-sectional structure of the semiconductor device along the C2-C2 direction;

[0039] Figure 4e along Figure 4a A schematic diagram of the cross-sectional structure of the semiconductor device along the A2-A2 direction;

[0040] Figure 5 A flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0041] Figures 6 to 10d Provided in the embodiments of this application Figure 4a Schematic diagram of the structure of the semiconductor device during the preparation process. DETAILED DESCRIPTION

[0042] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meanings understood by those skilled in the art. The terms "first", "second", "third" and similar words used in this specification and claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Thus, features defined as "first", "second", and "third" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, "multiple" means two or more.

[0043] The directional terms such as "left", "right", "up" and "down" are defined relative to the orientation of the device schematically placed in the accompanying drawings. It should be understood that these directional terms are relative concepts. They are used for relative descriptions and clarifications, and they may change accordingly according to changes in the orientation of the chip or semiconductor packaging structure.

[0044] The present application provides an electronic device, which is a type of electronic device with a chip. The electronic device can be a terminal device such as a mobile phone, tablet computer, smart bracelet, etc., or a personal computer (PC), server, workstation, vehicle-mounted device, etc.

[0045] See Figure 1 , Figure 1 The present invention provides a schematic diagram of an electronic device 10 according to an embodiment of the present invention. The electronic device 10 includes a chip 11 and a printed circuit board (PCB) 12. The chip 11 is disposed on the PCB 12. For example, the PCB 12 is provided with conductive wires, and the chip 11 is electrically connected to the conductive wires.

[0046] The chip 11 may be an application processor (AP) for processing application programs, a graphics processing unit (GPU) for processing image data, a random access memory (RAM) for storing data, or a communication chip for signal processing.

[0047] Chip 11 may include multiple semiconductor devices, which may be electronic components constituting chip 11. In other words, the semiconductor device may be at least a portion of chip 11. For example, the semiconductor device may be multiple FinFETs in chip 11. Furthermore, the semiconductor device may also be at least a portion of an intermediate product during the manufacturing process of chip 11.

[0048] See Figure 2a to Figure 2d , Figure 2a This is a schematic diagram of the three-dimensional structure of a semiconductor device 100 provided in an embodiment of the present application. Figure 2a The rectangular coordinates shown in FIG. 1 are as follows, wherein an XY plane formed by the X direction and the Y direction coincides with the lower surface of the semiconductor device 100, and the Z direction is perpendicular to the XY plane, that is, the Z direction extends along the thickness direction of the semiconductor device 100. For ease of understanding, the thickness direction of the semiconductor device 100 is referred to as the Z direction in the following content. Figure 2b yes Figure 2a FIG. 1 is a schematic diagram of a top view of the semiconductor device 100, Figure 2c for Figure 2a A schematic diagram of the cross-sectional structure of the semiconductor device 100 along the B1-B1 direction, Figure 2d for Figure 2a Schematic diagram of the cross-sectional structure of the semiconductor device 100 along the A1-A1 direction.

[0049] See Figure 2a to Figure 2d, the semiconductor device 100 includes a substrate 102, a fin structure 104, an epitaxial portion 106, an interlayer dielectric layer 114, a gate structure 108 and an isolation structure 110. A plurality of fin structures 104 protrude from the substrate 102. For example, the plurality of fin structures 104 extend in the thickness direction of the substrate 102, i.e., the Z direction; the plurality of fin structures 104 extend along a first direction and are arranged along a second direction. The first direction intersects with the second direction. For example, the first direction may coincide with the X direction, and the second direction may coincide with the Y direction. For ease of understanding, the following content is explained as an example in which the X direction refers to the first direction and the Y direction refers to the second direction. A plurality of gate structures 108 are provided, and the gate structures 108 are arranged across the plurality of fin structures 104 along the Y direction; a plurality of epitaxial portions 106 are located on the fin structures 104, and along the X direction, the epitaxial portions 106 are arranged on both sides of the gate structure 108. The interlayer dielectric layer 114 fills the gaps between the fin structures 104 and covers the epitaxial portions 106 . The gate structures 108 are embedded in the interlayer dielectric layer 114 .

[0050] Thus, a transistor array can be formed, where the source and drain of each transistor are the extensions 106 on either side of the gate structure 108, the transistor's channel is the portion of the fin structure 104 covered by the gate structure 108, and the transistor's gate is the portion of the gate structure 108 located between the two extensions 106. To facilitate partitioned control of the transistors, the isolation structure 110 can extend in the X direction and truncate multiple gate structures 108 to form multiple gates 138, each of which independently controls a transistor. Furthermore, in the Z direction, after truncation of the gate structure 108, the isolation structure 110 can penetrate the interlayer dielectric layer 114 and be partially embedded in the substrate 102.

[0051] Can be formed using the "cut metal gate" (CMG) process Figure 2a to Figure 2d That is, before forming the epitaxial portion 106 of the semiconductor device 100, a dummy gate structure 109 is first formed at a predetermined position on the substrate 102 as a placeholder. After forming the epitaxial portion 106, the dummy gate structure 109 is removed and replaced with the initial gate structure 128. Finally, a groove is formed to cut through the initial gate structure 128 to form the gate structure 108, so that the isolation structure 110 can be formed in the groove to cut off the gate structure 108.

[0052] In order to ensure that the gate structure 108 is completely cut off, the groove 107 needs to penetrate the interlayer dielectric layer 114 between the initial gate structure 128 and the substrate 102. Figure 3 , Figure 3 for Figure 2aThe cross-sectional structure of the semiconductor device along the C1-C1 axis during fabrication is shown. Because the recess 107 forming the truncated gate structure 108 penetrates the interlayer dielectric layer 114 between the gate structure 108 and the substrate 102 and spans the region where multiple fin structures 104 are located along the X-direction, a portion of the recess 107 passes through the region between two adjacent epitaxial portions 106 in the Y-direction. In advanced manufacturing processes, the distance between two adjacent epitaxial portions 106 in the Y-direction is also very small, and the recess 107 is formed very close to the epitaxial portion 106. For example, in some manufacturing processes, the ideal distance D between the recess 107 and the epitaxial portion is 8 nm. Therefore, the epitaxial portion 106 can be easily damaged during the formation of the recess 107. Furthermore, as the feature size of semiconductor devices is further reduced, the limitations of the photolithography process make it difficult to precisely define the recess dimensions, making it difficult to avoid damaging the epitaxial portion 106 during the formation of the recess 107.

[0053] To this end, the present application provides a semiconductor device 100, see Figure 4a to Figure 4e ,in, Figure 4a is a schematic diagram of the three-dimensional structure of another semiconductor device 100 provided in an embodiment of the present application. Figure 4b yes Figure 4a FIG. 1 is a schematic diagram of a top view of the semiconductor device 100. Figure 4c for Figure 4a A schematic diagram of the cross-sectional structure of the semiconductor device 100 along the B2-B2 direction, Figure 4d for Figure 4a A schematic cross-sectional view of the semiconductor device 100 along the C2-C2 direction, Figure 4e for Figure 4a Schematic diagram of the cross-sectional structure of the semiconductor device 100 along the A2-A2 direction.

[0054] The semiconductor device 100 may include a substrate 102 , a plurality of fin structures 104 , a plurality of epitaxial portions 106 , a plurality of gate structures 108 , an isolation structure 110 , and a plurality of etch stops 118 .

[0055] The substrate 102 includes a first surface 101 and a second surface 103, which are arranged opposite to each other in the thickness direction of the substrate 102. For example, the first surface 101 of the substrate 102 may be the lower surface of the semiconductor device 100, that is, the thickness direction of the substrate 102 coincides with the Z direction, and the first surface 101 coincides with the XY plane.

[0056] The substrate 102 may be formed of silicon (Si) or other Group III, Group IV, and / or Group V elements. For example, the substrate 102 may be made of a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The substrate 102 may also be made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenide phosphide (GaAsP), or gallium indium phosphide (GaInP). The substrate 102 may also be in the form of a semiconductor-on-insulator (SOI), such as silicon on insulator (SOI). A SOI substrate may include a silicon substrate body, an insulator layer, and a semiconductor material layer. The insulator layer is formed on the silicon substrate body, and the semiconductor material layer is formed on the insulator layer. The insulator layer may be a buried oxide or the like. The semiconductor material layer may be made of silicon, germanium, or the like.

[0057] The plurality of fin structures 104 extend along the X direction and are arranged along the Y direction. The plurality of fin structures 104 have a certain height, that is, the plurality of fin structures 104 have a certain size in the Z direction. For example, the plurality of fin structures 104 may be provided on the second surface 103 of the substrate 102.

[0058] The fin structure 104 may include one or more semiconductor materials, such as one or more suitable materials such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), gallium arsenic phosphide (GaAsP), etc. For example, the fin structure 104 may be made of the same material as the substrate 102. For example, the fin structure 104 includes alternating stacked layers of two different semiconductor materials, such as alternating stacked silicon layers and silicon germanium layers. The multiple fin structures 104 may additionally or alternatively include dopants for improving the performance of the semiconductor device 100. For example, the fin structure 104 may include n-type dopants such as phosphorus or arsenic, or p-type dopants such as boron or indium.

[0059] Multiple gate structures 108 are arranged across the multiple fin structures 104 along the Y direction, where the multiple in the multiple fin structures 104 refers to two or more. In addition, the multiple gate structures 108 can also be arranged along the X direction. Exemplarily, the gate structure 108 may include a high-k gate dielectric layer and a conductive gate electrode (neither of which is shown in the figure). The material of the conductive gate electrode may include a metal such as tungsten (W) or titanium nitride (TiN). The gate structure 108 may also include other film layers, exemplarily including one or more of an interface layer, a capping layer, a diffusion layer, a barrier layer, a hard mask layer, and other suitable material layers. For example, the gate structure 108 further includes an interface layer, a high-k gate dielectric layer disposed above the interface layer, and a conductive gate electrode disposed above the high-k dielectric layer. In addition, the multiple gate structures 108 may include the same or different film layers.

[0060] A plurality of epitaxial portions 106 are disposed on the fin structure 104. For example, the epitaxial portions 106 may be formed by epitaxially growing a semiconductor material on an end of the fin structure 104 that is away from the first surface 101 of the substrate 102. Furthermore, along the X-direction, the epitaxial portions 106 are disposed on both sides of the gate structure 108. For example, along the X-direction, the epitaxial portions 106 and the gate structure 108 may be alternately disposed, and several of the plurality of epitaxial portions 106 may be arranged along the Y-direction between two adjacent gate structures 108 along the X-direction.

[0061] Epitaxial portion 106 can serve as the source or drain region of the transistor and can be doped with n-type dopants and / or p-type dopants. Exemplarily, epitaxial portion 106 includes an epitaxial layer of silicon and / or carbon, wherein the silicon-containing epitaxial layer or the carbon-containing epitaxial layer can be doped with phosphorus and / or other n-type dopants. Epitaxial portion 106 can also include materials or dopants that achieve desired tensile and / or compressive stress in the channel region of the transistor.

[0062] The isolation structure 110 intercepts the multiple gate structures 108 along the X direction. For example, the isolation structure 110 may extend along the X direction and intersect with the multiple gate structures 108 respectively, intercepting the multiple gate structures 108 at the intersection positions. In other words, the intersection positions of the isolation structure 110 and the multiple gate structures 108 are the locations where the multiple gate structures 108 are intercepted, so that each gate structure 108 forms multiple independently controllable gates 138.

[0063] The isolation structure 110 may include one or more dielectric materials. For example, the dielectric material may be a nitride, an oxide, an oxynitride, spin-on glass (SOG), fluoride-doped silicate glass (FSG), a low-k dielectric material, or other suitable insulating materials. For example, the nitride may be silicon nitride, the oxide may be silicon oxide or aluminum oxide, and the oxynitride may be silicon oxynitride. It will be readily understood that the dielectric material included in the portion of the isolation structure 110 that is in physical contact with the gate structure 108 does not react with the material included in the gate structure 108.

[0064] like Figure 4e As shown, multiple etch stop portions 118 are arranged along the X-direction, and the multiple etch stop portions 118 may be arranged alternately with the truncated portions of the multiple gate structures 108 along the X-direction. For example, along the X-direction, the etch stop portion 118 may be disposed between any two adjacent truncated portions of the gate structures 108 along the X-direction. Simultaneously, the multiple etch stop portions 118 are also located between the extension portions 106 on both sides of the isolation structure 110. In other words, multiple etch stop portions 118 and the isolation structure 110 are disposed simultaneously between two adjacent extension portions 106 along the Y-direction. The etch stop portion 118 may comprise one or more of silicon nitride, silicon oxynitride, silicon carbonitride, and other suitable materials.

[0065] Thus, during the formation of multiple gate structures 108, a first region can be exposed between two adjacent epitaxial portions 106 in the Y direction. The first region extends along the X direction and spans across the multiple gate structures 108. Material in the first region is removed through a first etching process. The first etching process can primarily be used to remove other material between any two adjacent gate structures 108 in the X direction and has a high selectivity for this material. That is, the etching rate of the gate structure 108 material is lower than the etching rate of other material between any two adjacent gate structures 108 in the X direction. Therefore, a first recess is formed in the portion between the gate structures 108 in the X direction. Furthermore, because the first etching process has a high selectivity for other material between any two adjacent gate structures 108 in the X direction, the removal rate of the gate structure 108 material is slower than the removal rate of other material between any two adjacent gate structures 108. Therefore, the depth of the first recess can be easily controlled, avoiding damage to the epitaxial portion 106 during the formation of the first recess.

[0066] Next, an etch stop material of the etch stop portion 118 may be deposited on the substrate to fill the first groove. At this time, the thickness of the etch stop material may be controlled so that the etch stop materials on both side walls of the first groove along the X direction contact each other, that is, the etch stop material fills the first groove.

[0067] During the process of severing the gate structure 108, a second etching process can be used to remove the material of the gate structure 108 (the first material) in the first region. The second etching process has a high selectivity for the material of the gate structure 108, i.e., the etching rate of the gate structure 108 material is greater than the etching rate of the etch-stop material (the second material). In the initial stage, the second etching process simultaneously removes the etch-stop material deposited on the gate structure 108 and the etch-stop material in the first groove. When the etch-stop material on the gate structure 108 is completely removed and the etching process continues, the gate structure 108 material can be removed more quickly. After the gate structure 108 is completely severed, only a small portion of the etch-stop material in the first groove is removed. The remaining portion of the etch-stop material in the first groove forms an etch-stop portion 118. In other words, the etch-stop portion 118 in the first groove prevents the second etching process from continuing to etch toward the substrate 102 in the Z direction in the region where the etch-stop portion 118 is located, thereby avoiding damage to the epitaxial portion 106.

[0068] A second etching process forms a trench extending in the X direction. The trench intercepts the gate structure 108. The portion of the trench between adjacent gate structures 108 in the X direction stops at the etch stop 118. In other words, the trench is more recessed in the X direction where it intercepts the gate structure 108, and less recessed in the region between the gate structures 108 in the X direction. A dielectric material is then deposited in the trench to form the isolation structure 110, which intercepts the gate structure 108.

[0069] Illustratively, the first etching process and the second etching process may both adopt a dry etching process, such as a plasma etching process.

[0070] Please continue to see Figure 4b to Figure 4e The isolation structure 110 may include a plurality of isolation portions 111. The isolation portions 111 are formed by dielectric materials deposited in the recessed region of the trench. That is, the isolation portions 111 are portions of the isolation structure 110 that protrude toward the substrate 102. Thus, the isolation portions 111 cut off the gate structure 108 to form a plurality of gates. For example, see Figure 4e , the isolation portions 111 and the etch stop portions 118 may be arranged alternately.

[0071] Please continue to see Figure 4a to Figure 4eIn some embodiments, the semiconductor device 100 further includes an interlayer dielectric layer 114, which fills the gaps between the multiple fin structures 104 and covers the multiple epitaxial portions 106. The multiple gate structures 108 are embedded in the interlayer dielectric layer 114. The multiple gate structures 108 can be embedded in the interlayer dielectric layer 114 in various ways. For example, the upper surfaces of the multiple gate structures 108 can be exposed on the upper surface of the interlayer dielectric layer 114, or the multiple gate structures 108 can be completely embedded in the interlayer dielectric layer 114, that is, the multiple gate structures 108 are also covered by the interlayer dielectric layer 114. In addition, other structures, such as a wiring layer or a passivation layer (not shown in the figure), can also be formed above the multiple gate structures 108.

[0072] The etch stop portion 118 may also be embedded in the interlayer dielectric layer 114 . For example, the etch stop portion 118 is embedded in a surface of the interlayer dielectric layer 114 away from the first surface 101 of the substrate 102 .

[0073] The interlayer dielectric layer 114 may include one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide, xerogel, aerogel, amorphous fluorinated carbon, parylene, benzocyclobutene (BCB), polyimide, or other suitable dielectric materials. The interlayer dielectric layer 114 may also include a multilayer structure including multiple dielectric materials.

[0074] For example, the isolation portion 111 of the isolation structure 110 may penetrate the interlayer dielectric layer 114 in the Z direction. That is, after cutting off the gate structure 108, the isolation portion 111 continues to extend toward the substrate 102, thereby ensuring that the gate structure 108 is completely cut off. For example, a portion of the isolation portion 111 extends into the substrate 102, that is, is embedded in the substrate 102.

[0075] In some embodiments, the isolation structure 110 further includes an isolation layer 112, which is also formed by depositing an isolation material in the trench. It will be readily understood that the isolation portion 111 and the isolation layer 112 can be deposited using the same process, and thus, the isolation portion 111 and the isolation layer 112 can be integrally formed. The isolation layer 112 extends across the multiple gate structures 108 in the X-direction and covers the multiple isolation portions 111, meaning that the isolation layer 112 connects the multiple isolation portions 111. Furthermore, since the isolation layer 112 extends across the multiple gate structures 108 in the X-direction and the etch stop portion 118 is disposed between the multiple gates in the X-direction, the isolation layer 112 may also cover a portion of the etch stop portion 118.

[0076] See Figure 4d Exemplarily, etch stop 118 is formed as a recess, with a portion of isolation layer 112 disposed within the recess, such that isolation layer 112 covers a portion of etch stop 118. For example, the recess may have a U-shaped cross-section. Furthermore, as can be seen from the aforementioned process for forming etch stop 118, the recess is formed by etching the etch stop material deposited in the first recess. While removing the etch stop material, the etching also removes a portion of gate structure 108, thereby forming a trench that interrupts gate structure 108. In other words, the recess is a portion of the trench, and the dimension of the recess along the Y direction is equal to the dimension of the trench along the Y direction. The first recess is defined by the first region defined by the photoforming process. Specifically, the photoforming process requires defining the dimension D1 of the first recess along the Y direction. However, the final trench that interrupts gate structure 108 has a dimension D2 along the Y direction, which is the dimension of the recess formed on etch stop 118 along the Y direction. This allows the trench formation process to exceed the dimension of the first region defined by the photoforming process, facilitating overcoming the limitations of the photoforming process on miniaturization of semiconductor device 108.

[0077] In some embodiments, gate spacers 116 are provided on both sides of the gate structure 108 along the X-direction. In other words, the semiconductor device 100 further includes gate spacers 116. The gate spacers 116 are not interrupted by the isolation structure 110. Therefore, the gate spacers 116 extend between the etch stop portion 118 and the isolation portion 111 adjacent to the etch stop portion 118. When the isolation structure 110 extends along the X-direction to the region where the gate spacers 116 are located, it may also cover the gate spacers 116.

[0078] Please continue to see Figure 4d In the Z direction, the distance between the end of the etch stop portion 118 closest to the first surface 101 and the first surface 101 is a first distance h1. That is, the first distance h1 is the distance between the portion of the etch stop portion 118 closest to the first surface 101 of the substrate 102 and the first surface 101. The distance between the two adjacent extension portions 106 on either side of the etch stop portion 118 and the first surface 101 is a second distance h2. For example, the two adjacent extension portions 106 on either side of the etch stop portion 118 are extension portion A and extension portion B. The second distance h2 refers to the distance between the position of extension portion A closest to extension portion B and the first surface 101, and the distance between the position of extension portion B closest to extension portion A and the first surface 101. For example, the cross-sectional shape of the extension portion 106 may be a rhombus, and the positions of the two extension portions 106 closest to each other are two opposing corners of the rhombus. In this case, the distance between the two opposing corners of the rhombus and the first surface 101 is the second distance h2.

[0079] The first distance h1 may be greater than or equal to the second distance h2. That is, the first distance h1 is greater than or equal to the distance from the position of the extension portion A closest to the extension portion B to the first surface 101, and greater than or equal to the distance from the position of the extension portion B closest to the extension portion A to the first surface 101. This allows the height of the etch stop portion 118 to be higher than the position where the two extension portions 106 are closest to each other, and the height of the etch stop portion 118 to be higher than the height of the position where the distance between the two extension portions 106 is the smallest in the Y direction, thereby preventing damage to the extension portions 106 when etching the first groove between the two extension portions 106 to accommodate the etch stop portion.

[0080] See Figure 4e , the distance from the portion of the gate spacer 116 closest to the first surface 101 of the substrate 102 to the first surface 101 is the third distance h3. It is easy to understand that the surface of the gate spacer 116 close to the first surface 101 of the substrate 102 can be approximately parallel to the first surface 101 of the substrate 102. In this case, the third distance h3 is the distance between any point on the surface and the first surface 101 of the substrate 102. The surface of the gate spacer 116 close to the first surface 101 of the substrate 102 can also be irregular or non-parallel to the first surface 101 of the substrate 102. In this case, the third distance h3 is the distance from the portion of the gate spacer 116 closest to the first surface 101 of the substrate 102 to the first surface 101. Exemplarily, the first distance h1 can also be greater than or equal to the third distance h3. In this way, when forming the first groove, the first groove can be prevented from being too concave. It is easy to understand that the smaller the depression of the first groove is, the less the interlayer dielectric layer 114 covering the epitaxial portion 106 in the first region will be removed, and the first groove will be farther away from the epitaxial portion 106, thereby avoiding damage to the epitaxial portion when forming the first groove.

[0081] In some embodiments, the semiconductor device 100 may not include the substrate 102 . For example, the substrate 102 may be removed after the electronic components on the substrate 102 are fabricated.

[0082] In addition, this application also provides a method for preparing a semiconductor device 100, see Figure 5 , Figure 5 The flowchart of forming the semiconductor device 100 is shown, which is only an example and is not intended to limit the present application beyond what is clearly described in the claims. Figures 6 to 10d The preparation method is described, wherein Figure 6 It is a schematic diagram of the three-dimensional structure of the semiconductor device 100 in an intermediate step of the preparation method. Figure 7a 、 Figure 8a 、 Figure 9a 、 Figure 10aSchematic diagrams of various top views of the semiconductor device 100 in the intermediate steps of the manufacturing method;

[0083] Figure 7b 、 Figure 8b 、 Figure 9b 、 Figure 10b Schematic diagrams of various cross-sectional structures of the semiconductor device 100 along the B3-B3 direction in the intermediate steps of the manufacturing method; Figure 7c 、 Figure 8c 、 Figure 9c 、 Figure 10c Schematic diagrams of various cross-sectional structures of the semiconductor device 100 along the C3-C3 direction in the intermediate steps of the manufacturing method; Figure 7d 、 Figure 8d 、 Figure 9d 、 Figure 10d Schematic diagrams of various cross-sectional structures along the A3 - A3 direction of the semiconductor device 100 in the intermediate steps of the preparation method.

[0084] S100, see Figure 6 , a plurality of fin structures 104 , a plurality of initial gate structures 128 , a plurality of epitaxial portions 106 and an interlayer dielectric layer 114 are formed on the substrate 102 .

[0085] For example, the fin structure 104 extends along the X direction, and the plurality of fin structures 104 are arranged along the Y direction, with the X direction intersecting the Y direction; the initial gate structure 128 is arranged across the plurality of fin structures 104 along the Y direction; an extension portion 106 is provided on both sides of the initial gate structure 128 along the X direction, and the extension portion 106 is located on the fin structure 104; the interlayer dielectric layer 114 is filled in the gaps between the plurality of fin structures 104 and covers the plurality of extension portions 106, and the plurality of initial gate structures 128 are embedded in the surface of the interlayer dielectric layer 114 away from the substrate. Figure 4a to Figure 4e The following describes various possible materials for the substrate 102, the plurality of fin structures 104, the plurality of gate structures 108, the plurality of epitaxial portions 106, and the interlayer dielectric layer 114. Since the gate structure 108 is formed from the initial gate structure 128, these materials can be used as a reference. Furthermore, the materials for the various other structures involved in this method can also be referred to above and will not be described in detail here.

[0086] The above structure may be formed by the following steps:

[0087] S101 , epitaxially growing one or more semiconductor layers on a substrate 102 to form a fin structure 104 .

[0088] A sacrificial structure extending in the X direction may be formed on the substrate 102, and a fin structure 104 may be formed on the side of the sacrificial structure, with the fin structure 104 also extending in the X direction. For example, a chemical vapor deposition process may be used to deposit the material of the fin structure 104 on the side of the sacrificial structure to form the fin structure 104. The sacrificial structure is then removed.

[0089] S102 , forming a dielectric material between the fin structures 104 .

[0090] The dielectric material formed between the fin structures 104 can be used to isolate adjacent fin structures 104 , and the dielectric material can be formed of one or more materials such as silicon oxide, silicon carbide, silicon nitride, etc. A portion of the fin structure 104 remains protruding from the formed dielectric material.

[0091] S103 , forming a sacrificial gate structure.

[0092] A sacrificial gate structure is formed by a deposition process, extending along the Y direction and spanning the plurality of fin structures 104. The sacrificial gate structure may be made of silicon oxide or polysilicon.

[0093] S104 , forming the epitaxial portion 106 .

[0094] Epitaxial portions 106 are formed by epitaxial growth on the fin structure 104 on both sides of the sacrificial gate structure.

[0095] S105 , replacing the sacrificial gate structure with the initial gate structure 128 .

[0096] The sacrificial gate structure is removed by an etching process, and then an initial gate structure 128 is formed by a deposition process.

[0097] Finally, a dielectric material may be further formed to cover the initial gate structure 128 and planarized by chemical mechanical polishing (CMP). After planarization, the initial gate structure 128 may be exposed. Thus, the dielectric material between the initial gate structure 128 and the fin structure 104 may form an interlayer dielectric layer 114.

[0098] In some embodiments, gate spacers 116 may be further formed on the substrate 102. For example, between step S103 and step S104, gate spacers 116 may be further formed on both sides of the sacrificial gate structure along the X direction, with the gate spacers 116 extending along the Y direction. That is, after the epitaxial portion 106 is formed, the gate spacers 116 are located between the sacrificial gate structure and the epitaxial portion in the X direction.

[0099] S200, see Figure 8dA plurality of first grooves 117 are formed on the surface of the interlayer dielectric layer 114 away from the substrate 102. The plurality of first grooves 117 and the initial gate structure 128 are alternately arranged along the X direction, and along the Y direction, the first grooves 117 are at least partially located between adjacent extension portions on both sides of the initial gate structure 128.

[0100] The first groove 117 may be formed by a photolithography process and an etching process, which may specifically include the following steps:

[0101] S201, see Figure 7a to Figure 7d A hard mask layer 120 and a photoresist (not shown) can be sequentially formed on the substrate 102. The hard mask layer 120 and the photoresist cover the fin structure 104 and other structures on the substrate 102. To improve the accuracy of the photolithography process, a carbon coating or a Si-containing anti-reflective coating can be provided between the hard mask layer 120 and the photoresist. Then, a first opening 130 is formed in the hard mask layer 120 through a photolithography process and an etching process.

[0102] Please continue to see Figure 7a , the first opening 130 extends along the X direction and crosses the multiple initial gate structures 128. That is, the first opening 130 not only exposes a portion of the region where the multiple initial gate structures 128 are located, but also exposes the interlayer dielectric layer 114 between adjacent initial gate structures 128 along the X direction. Figure 7a to Figure 7d , the first opening 130 is at least partially located between adjacent extensions 106 along the Y direction. Exemplarily, along the Y direction, the size of the first opening 130 is greater than or equal to the distance between adjacent extensions 106, and the projection of the sidewall of the first opening 130 on the substrate 102 coincides with the projection of the extension 106 on the substrate 102. Exemplarily, the first opening 130 may also be completely located between adjacent extensions 106 along the Y direction. In this case, along the Y direction, the size of the first opening 130 is less than the distance between adjacent extensions 106.

[0103] S202, please combine Figures 8a to 8d The interlayer dielectric layer 114 exposed by the first opening 130 is removed through the first opening 130, thereby forming a plurality of first recesses 117 on the surface of the interlayer dielectric layer 114 away from the substrate 102. For example, a first etching process can be used to remove a portion of the material of the interlayer dielectric layer 114 to form the plurality of first recesses 117. The first etching process can include one or more of dry etching, wet etching, reactive ion etching (RIE), or other suitable processes.

[0104] The first etching process for removing a portion of the interlayer dielectric layer 114 may have a low selectivity for the material of the initial gate structure 128. Therefore, when removing a portion of the interlayer dielectric layer 114, a very small amount of material of the initial gate structure 128 is removed. In other words, it can be considered that the initial gate structure 128 remains unchanged. As a result, the plurality of first recesses 117 and the initial gate structure 128 are formed, alternating along the X-direction.

[0105] Furthermore, because the first etching process has a low selectivity for the material of the initial gate structure 128, the depth of the first recess 117 can be easily controlled when removing the interlayer dielectric layer 114 exposed by the first opening 130. In other words, when the size of the first opening 130 is larger than the distance between adjacent epitaxial portions 106, by controlling the depth of the first recess 117, damage to the epitaxial portions 106 caused by the formation of the first recess 117 can be avoided.

[0106] In some embodiments, see Figure 7d and Figure 8d Along the X-direction, gate spacers 116 may be provided on both sides of the initial gate structure 128. It is easy to understand that the portion of the gate spacers 116 that overlaps with the area where the first opening 130 is located is also exposed. When the first etching process removes a portion of the interlayer dielectric layer 114 material, the first etching process used to remove the interlayer dielectric layer 114 material may also have a low selectivity ratio for the material of the gate spacers 116. Therefore, after the first etching process, it can be considered that the gate spacers 116 have not changed. In this case, the gate spacers 116 can form the sidewalls of the first groove 117 along the X-direction.

[0107] S300, see Figure 10d , a plurality of etching stoppers 118 are formed in the plurality of first grooves 117 .

[0108] Forming the plurality of etch stop portions 118 may include depositing an etch stop material to form an etch stop layer 140 and removing a portion of the etch stop layer 140 to form the plurality of etch stop portions 118 . Specifically, the steps may include:

[0109] S301, see Figure 9a to Figure 9d, an etch stop material may be deposited on the substrate 102 to form an etch stop layer 140, the etch stop layer 140 covering the hard mask layer 120 on the substrate 102 and the area exposed by the first opening 130 of the hard mask layer 120, wherein the surface of the initial gate structure 128 exposed by the first opening 130 is also covered by the etch stop layer 140. The etch stop material may be deposited using an atomic layer deposition (ALD) process. For example, when the ALD process is used, it can be approximately considered that the thickness of the etch stop layer 140 formed by the etch stop material in the horizontal plane is equal to the thickness of the etch stop layer 140 formed on the sidewall, for example, see Figure 9b and Figure 9c The thickness of the etch stop layer 140 formed on the surface of the hard mask layer 120 is equal to the thickness of the etch stop layer 140 formed on the sidewall of the first opening 130 in the hard mask layer 120 .

[0110] Please combine Figure 8d and Figure 9d , an etch-stop material is also formed in the first groove 117, and an etch-stop layer 140 of a certain thickness is also formed on the sidewalls of the first groove 117, that is, the etch-stop layer 140 fills the multiple first grooves 117. Exemplarily, twice the thickness of the etch-stop layer 140 may be greater than or equal to the size of the first groove 117 along the X-direction. In this case, the etch-stop layers 140 on two opposing sidewalls of the first groove 117 in the X-direction may contact each other. For example, when gate spacers 116 are provided on both sides of the initial gate structure 128 along the X-direction, twice the thickness of the etch-stop layer 140 may be greater than or equal to the distance between the gate spacers 116 on both sides of the first groove 117. Thus, in the Z-direction, the size of the etch-stop layer 140 in the first groove 117 is greater than the size of the etch-stop layer 140 on the initial gate structure 128.

[0111] S302, see Figures 10a to 10d Then, the portion of the etch-stop layer 140 covering the hard mask layer 120 and the initial gate structure 128 is removed, and the etch-stop layer 140 remains in the plurality of first recesses 117 to form a plurality of etch-stop portions 118. For example, a second etching process may be used to etch from the etch-stop layer 140 toward the substrate 102, for example, along the Z direction, from the etch-stop layer 140 toward the substrate 102, thereby forming trenches 127 in the first openings 130. The second etching process may include one or more of dry etching, wet etching, reactive ion etching (RIE), or other suitable processes.

[0112] During the second etching process, since etch-stop layer 140 is formed over the entire substrate 102, at the beginning of the etching process, the etch-stop material can be removed indiscriminately in the Z-direction until the size of the removed etch-stop material in the Z-direction equals the thickness of the deposited etch-stop layer 140. That is, after the etch-stop layer 140 above the hard mask layer 120 is completely removed in the Z-direction, the etch-stop layer 140 over the initial gate structure 128 is also completely removed. However, since the size of the etch-stop layer 140 in the first recess 117 in the Z-direction is larger than the size of the etch-stop layer 140 over the initial gate structure 128 and the hard mask layer 120, some etch-stop layer 140 remains in the first recess 117. This remaining etch-stop layer 140 forms an etch-stop portion 118. Since multiple first recesses 117 are formed, multiple etch-stop portions 118 can also be formed.

[0113] S400, please continue to see Figures 9a to 10d Based on the multiple etch stop portions 118 , the initial gate structure 128 is etched to form a trench 127 that cuts off the initial gate structure 128 along the X direction; the remaining initial gate structure 128 forms the gate structure 108 .

[0114] After removing the portion of the etch stop layer 140 covering the hard mask layer 120 and the initial gate structure 128, a third etching process may be used to continue etching the initial gate structure 128 based on the plurality of etch stops 118. The third etching process may be the same as or different from the second etching process. For example, the third etching process is the same as the second etching process. In this way, the process of removing the portion covering the hard mask layer 120 and the initial gate structure 128 and the process of forming the trench 127 in the etch stop layer 140 may be completed in the same equipment chamber.

[0115] While etching the initial gate structure 128, the plurality of etch stop portions 118 are also continuously etched. After the initial gate structure 128 is etched until the plurality of gate structures 128 are completely severed, a trench 127 is formed that interrupts the initial gate structure 128 along the X-direction. As will be readily understood, the trench 127 includes a recess 137 formed on the etch stop portion 118 as the etch stop portion 118 is continuously etched.

[0116] For example, as etching continues from the etch-stop layer 140 toward the substrate 102, the etching rate of the multiple etch-stop portions 118 formed in the first groove 117 is lower than the etching rate of the initial gate structure 128. Therefore, after etching continues until the multiple gate structures 128 are cut off, a smaller portion of the etch-stop portion 118 is removed. In other words, the depth of the trench 127 at the portion intersecting the multiple initial gate structures 128 is much greater than the depth of the portion above the etch-stop portion 118. In other words, the trench 127 includes multiple sub-trenches 129. The sub-trench 129 is a portion of the trench 127 with a larger depth, which at least includes a portion that cuts off the initial gate structure 128. In other words, one sub-trench 129 cuts off one initial gate structure 128 along the X-direction. In addition, because the etch-stop portion 118 is formed between adjacent initial gate structures 128 along the X-direction, the multiple sub-trenches 129 and the multiple etch-stop portions 118 are arranged alternately along the X-direction.

[0117] Because etch-stop layer 140 is formed on the sidewalls of both first recess 117 and first opening 130, and because etch-stop layer 140 is formed on the sidewalls in the direction from etch-stop layer 140 toward substrate 102, etch-stop layer 140 remains on the sidewalls of first recess 117 and first opening 130 after etching proceeds from etch-stop layer 140 toward substrate 102, and the thickness of etch-stop layer 140 changes slightly and is negligible. Therefore, during continued etching to sever initial gate structure 128, the maximum dimension of trench 127 formed in the Y direction is reduced by twice the thickness of etch-stop layer 140. Consequently, the dimension of trench 127 in the Y direction can be reduced during formation, breaking through the limitations of the photolithography process and further reducing the size of semiconductor device 100.

[0118] S500, please continue to see Figure 4e , an isolation structure is formed in the trench 127 .

[0119] After forming the trench 127, an isolation material may be deposited in the trench 127 to form an isolation structure. The isolation structure may be formed by one or more deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition processes.

[0120] In some embodiments, after the isolation material is deposited in the trench 127, a planarization process may be performed, such as a chemical mechanical polishing (CMP) process. After planarization, other semiconductor processes may be performed to form other structures on the substrate 102, such as an ohmic contact process or an interlayer interconnect process.

[0121] The above are only specific embodiments of the present application, but the scope of protection of the application is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: a plurality of fin structures, the fin structures extending along a first direction and arranged along a second direction, the first direction intersecting the second direction; a plurality of gate structures, the gate structures being arranged across the plurality of fin structures along the second direction; a plurality of epitaxial portions, each of which is provided on both sides of the gate structure along the first direction, and the epitaxial portions are located on the fin structure; an isolation structure, cutting off the plurality of gate structures along the first direction; A plurality of etch stop portions are alternately arranged with the truncated portions of the plurality of gate structures along the first direction, and the etch stop portions are located between adjacent epitaxial portions on both sides of the isolation structure along the second direction.

2. The semiconductor device according to claim 1, wherein The isolation structure includes a plurality of isolation portions, one of the isolation portions intercepting one of the gate structures along the first direction; the plurality of isolation portions and the plurality of etching stop portions are alternately arranged along the first direction.

3. The semiconductor device according to claim 2, wherein Also included is an interlayer dielectric layer, wherein the interlayer dielectric layer fills the gaps between the plurality of fin structures and covers the plurality of epitaxial portions; The isolation portion penetrates the interlayer dielectric layer, and the etch stop portion is embedded in a surface of the interlayer dielectric layer close to the plurality of epitaxial portions.

4. The semiconductor device according to claim 2 or 3, wherein: The isolation structure further includes an isolation layer, which covers the plurality of isolation parts and is connected to the plurality of isolation parts; the isolation layer also covers a portion of each of the etch stop parts.

5. The semiconductor device according to claim 4, wherein The etch stopper is formed with a groove, and a portion of the isolation layer is disposed in the groove.

6. The semiconductor device according to any one of claims 2 to 5, wherein: It also includes gate sidewalls, which are respectively provided on both sides of the gate structure along the first direction; the gate sidewalls further extend between the etch stop portion and the isolation portion adjacent to the etch stop portion.

7. The semiconductor device according to claim 6, wherein The invention also includes a substrate, wherein the substrate includes a first surface and a second surface opposite to each other in a thickness direction of the substrate, and the plurality of fin structures are provided on the second surface; A distance between an end of the etch stop portion close to the first surface and the first surface is greater than or equal to a distance between an end of the gate spacer close to the first surface and the first surface.

8. The semiconductor device according to claim 6 or 7, wherein: A portion of the gate spacer located between the etch stop portion and the isolation portion adjacent to the etch stop portion is covered by the isolation structure.

9. The semiconductor device according to any one of claims 1 to 8, wherein The distance from one end of the etch stop portion close to the first surface of the substrate to the first surface is a first distance, and the distance from the closest position of the two adjacent extension portions on both sides of the etch stop portion to the first surface is a second distance, and the first distance is greater than or equal to the second distance.

10. The semiconductor device according to any one of claims 1 to 9, wherein The gate structure includes a first material, the etch stop portion includes a second material, and under a preset etching process, an etching rate of the first material is greater than an etching rate of the second material.

11. The semiconductor device according to claim 10, wherein The material of the etch stop portion includes one or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

12. A method for preparing a semiconductor device, characterized in that: include: forming a plurality of fin structures, a plurality of initial gate structures, a plurality of epitaxial portions and an interlayer dielectric layer on a substrate; The fin structure extends along a first direction, and the multiple fin structures are arranged along a second direction, the first direction intersecting the second direction; the initial gate structure is arranged across the multiple fin structures along the second direction; the extension portions are respectively provided on both sides of the initial gate structure along the first direction, and the extension portions are located on the fin structure; the interlayer dielectric layer fills the gaps between the multiple fin structures and covers the multiple extension portions, and the multiple initial gate structures are embedded in the surface of the interlayer dielectric layer away from the substrate; forming a plurality of first grooves on a surface of the interlayer dielectric layer away from the substrate, wherein the plurality of first grooves and the initial gate structure are alternately arranged along the first direction, and the first grooves are at least partially located between adjacent extension portions on both sides of the initial gate structure along the second direction; forming a plurality of etch stops in the plurality of first recesses; etching the initial gate structure based on the plurality of etching stoppers to form a trench that intercepts the initial gate structure along the first direction; The remaining initial gate structure forms a gate structure; An isolation structure is formed in the trench.

13. The method according to claim 12, wherein: The forming of a plurality of first grooves on a surface of the interlayer dielectric layer away from the substrate comprises: forming a hard mask layer having a first opening, wherein the first opening spans across the plurality of initial gate structures along the first direction and is located between two adjacent epitaxial portions along the second direction; The interlayer dielectric layer is etched based on the hard mask layer to form the plurality of first grooves.

14. The method according to claim 13, wherein The forming of a plurality of etching stoppers in the plurality of first grooves comprises: forming an etch stop layer, wherein the etch stop layer covers the hard mask layer and the surface of the initial gate structure exposed by the first opening and fills the plurality of first grooves; A portion of the etch stop layer covering the hard mask layer and the initial gate structure is removed, and the etch stop layer remaining in the plurality of first grooves forms the plurality of etch stop portions.

15. The method according to claim 14, wherein The etching the initial gate structure based on the plurality of etch stop portions comprises: Based on the hard mask layer and the plurality of etch stop portions, the initial gate structure is etched to form the trench; the trench includes a plurality of sub-trenches, each sub-trench intercepting one of the initial gate structures along the first direction, and the plurality of sub-trenches and the plurality of etch stop portions are alternately arranged along the first direction; The step of forming an isolation structure in the trench comprises: The trench is filled with a preset material to form the isolation structure; and the plurality of sub-trench are filled with the preset material to form a plurality of isolation portions of the isolation structure.

16. The method according to claim 14 or 15, characterized in that Two times the thickness of the etch stop layer is greater than or equal to a dimension of the first groove along the first direction.

17. A chip, characterized in that: The semiconductor device comprises the semiconductor device according to any one of claims 1 to 11.

18. An electronic device, characterized in that: The device comprises a printed circuit board and the chip according to claim 17, wherein the chip is arranged on the printed circuit board.

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