Display device and preparation method thereof

Abstract

The invention provides a display device and a preparation method thereof. The display device includes a thin film transistor including a polysilicon layer having specific structural characteristics. The volume of the space charge part on the drain side of the thin film transistor is smaller than or equal to 0.028 mu m < 3 >, and the ratio of the area of the cross section of the edge inclined part of the polycrystalline silicon layer to the total area of the cross section of the polycrystalline silicon layer is smaller than or equal to 1.2%. According to the structural design, the light absorption volume and the space charge part volume are reduced, the photo-generated leakage current is remarkably reduced, and a shading layer does not need to be arranged; meanwhile, the area proportion of the edge inclined part is reduced, the hump effect is effectively inhibited, the starting current is improved, the sub-threshold swing is optimized, and the display quality and reliability are improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device and a method for manufacturing the same. Background Art

[0002] In modern display technology, polycrystalline silicon thin-film transistors (Poly-Si TFTs) are widely used in liquid crystal displays (LCDs) and organic light-emitting diode displays (OLEDs) due to their superior device properties. Compared to amorphous silicon thin-film transistors (A-Si TFTs), Poly-Si TFTs have higher electron mobility and better switching performance.

[0003] However, poly-Si TFTs are susceptible to light leakage current in high-light environments. Light leakage current refers to the increased leakage current in poly-Si TFTs caused by the generation of photogenerated carriers (electrons and holes) under bright conditions. This phenomenon reduces the on / off current ratio of the poly-Si TFT, affecting the display's contrast and color accuracy. Furthermore, light leakage current can cause voltage instability on the pixel electrode, affecting grayscale control.

[0004] To reduce light leakage current, conventional technology typically places a light shielding layer between the Poly-Si TFT and the light source to block light. However, this approach increases the complexity and cost of the manufacturing process.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a display device and a method for manufacturing the same, aiming to reduce the photogenerated leakage current of the thin film transistor in the display device.

[0007] An embodiment of the present application provides a display device, which includes a thin film transistor, which includes a polysilicon layer, and the ratio of the cross-sectional area of ​​the edge inclined portion of the polysilicon layer to the total cross-sectional area of ​​the polysilicon layer is less than or equal to 1.2%.

[0008] In the above display device, the thickness of the polysilicon layer is less than 45 nm.

[0009] In the above display device, the thickness of the polysilicon layer is greater than or equal to 25 nm and less than 45 nm.

[0010] In the above-mentioned display device, the display device also includes a substrate, a buffer layer, a gate insulating layer, a first insulating layer and a second insulating layer, and the thin film transistor also includes a gate; the buffer layer is arranged on the substrate, the polysilicon layer is arranged on the buffer layer, the gate insulating layer is arranged on the polysilicon layer and the buffer layer, the gate is arranged on the gate insulating layer, the first insulating layer is arranged on the gate and the gate insulating layer, and the second insulating layer is arranged on the first insulating layer; the thickness of the buffer layer is greater than the thickness of the gate insulating layer, and less than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer.

[0011] In the above display device, the thickness of the buffer layer is greater than or equal to 3000 angstroms.

[0012] In the above display device, the polysilicon layer further includes a space charge portion, which is located at the junction of the channel portion and the lightly doped portion of the polysilicon layer, and the volume of the space charge portion is less than or equal to 0.028 μm 3 .

[0013] An embodiment of the present application also provides a method for preparing a display device, comprising: forming a buffer layer on a substrate; forming a polysilicon layer on the buffer layer, wherein the ratio of the cross-sectional area of ​​the edge inclined portion of the polysilicon layer to the total cross-sectional area of ​​the polysilicon layer is less than or equal to 1.2%; forming a gate insulating layer on the polysilicon layer and the buffer layer; forming a gate on the gate insulating layer; forming a first insulating layer and a second insulating layer on the gate insulating layer and the gate in sequence; etching the gate insulating layer, the first insulating layer, and the second insulating layer to form a first through hole and a second through hole; forming a source and a drain on the second insulating layer, wherein a portion of the source is provided A portion of the drain electrode is disposed in the second through hole and electrically connected to the polysilicon layer in the first through hole and electrically connected to the polysilicon layer; a flat layer is formed on the source electrode, the drain electrode and the second insulating layer; the flat layer is etched to form a third through hole; a common electrode is formed on the flat layer; a passivation layer is formed on the flat layer and the common electrode; the passivation layer is etched to form a fourth through hole, the position of the fourth through hole corresponds to the third through hole, and the third through hole and the fourth through hole are nested; and a pixel electrode is formed on the passivation layer, a portion of the pixel electrode is disposed in the fourth through hole and electrically connected to the drain electrode.

[0014] In the above method for manufacturing the display device, the thickness of the polysilicon layer is less than 45 nm.

[0015] In the above method for manufacturing the display device, the thickness of the polysilicon layer is greater than or equal to 25 nm and less than 45 nm.

[0016] In the above-mentioned method for manufacturing the display device, the polysilicon layer further includes a space charge portion, which is located at the junction of the channel portion and the lightly doped portion of the polysilicon layer, and the volume of the space charge portion is less than or equal to 0.028 μm 3 .

[0017] In the above-mentioned method for preparing the display device, the display device also includes a substrate, a buffer layer, a gate insulating layer, a first insulating layer and a second insulating layer, and the thin film transistor also includes a gate; the buffer layer is arranged on the substrate, the polysilicon layer is arranged on the buffer layer, the gate insulating layer is arranged on the polysilicon layer and the buffer layer, the gate is arranged on the gate insulating layer, the first insulating layer is arranged on the gate and the gate insulating layer, and the second insulating layer is arranged on the first insulating layer; the thickness of the buffer layer is greater than the thickness of the gate insulating layer, and less than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer.

[0018] In the above method for manufacturing the display device, the thickness of the buffer layer is greater than or equal to 3000 angstroms.

[0019] In the display device and its manufacturing method of the present application, the thin-film transistor includes a polysilicon layer with specific thickness characteristics, which effectively controls the light absorption volume and the volume of the space charge portion of the thin-film transistor, thereby significantly reducing photogenerated leakage current. This reduction in photogenerated leakage current is due to the specific structure of the polysilicon layer reducing the number of photogenerated carriers generated under illumination, effectively suppressing the absorption of incident light in the polysilicon layer, and thus reducing the generation of leakage current.

[0020] The volume of the space charge portion on the drain side of the thin film transistor of this application is controlled to 0.028 μm 3 This characteristic further enhances the suppression of photogenerated leakage current. By precisely controlling the volume of the space charge region, where photogenerated carriers primarily originate, leakage current under illumination is significantly reduced, enabling the thin-film transistor to maintain stable switching characteristics even in strong illumination, improving the operating stability of the display device under various lighting conditions.

[0021] The ratio of the cross-sectional area of ​​the edge slope of the polysilicon layer of this application to the total cross-sectional area of ​​the polysilicon layer is controlled to below 1.2%. This structural characteristic effectively suppresses the hump effect. The edge slope is the main area where the hump effect occurs. Due to its unique geometry, the electric field is concentrated, which easily forms parasitic transistors. By controlling this ratio, the current-voltage characteristics of the thin-film transistor are significantly improved, making it smoother, increasing the turn-on current, and optimizing the subthreshold swing, thereby improving the uniformity and overall display quality of the display device at low grayscale.

[0022] Because the thin-film transistors of this application have extremely low photoinduced leakage current, they can eliminate the light-shielding layer used in traditional processes to block light. This not only simplifies the manufacturing process and reduces manufacturing costs, but also increases device integration, facilitating miniaturization and higher resolution of display devices. Eliminating the light-shielding layer also reduces the overall thickness of the device, making the display thinner and lighter.

[0023] In summary, the present application effectively solves the photoinduced leakage current and hump effect problems of low-temperature polysilicon thin-film transistors through a specially designed polysilicon layer structure, improves the display quality and reliability of the display device, simplifies the manufacturing process, reduces manufacturing costs, and has significant technical effects and practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a schematic diagram of a thin film transistor in a conventional display device.

[0025] Figure 2 yes Figure 1 Schematic diagram of the AA' cross section of the thin film transistor shown.

[0026] Figure 3 yes Figure 1 and Figure 2 The equivalent circuit diagram of the thin film transistor is shown.

[0027] Figure 4 It is aimed at Figures 1 to 3 The diagram shows a hump phenomenon in a thin film transistor under two different conditions: Vds=10V and Vds=0.1V.

[0028] Figure 5 yes Figure 4 The figure shows a decomposition diagram of the curve of the thin film transistor at Vds=0.1V.

[0029] Figure 6 is a schematic diagram of a display device provided in an embodiment of the present application.

[0030] Figure 7 is a cross-sectional view of a display panel in a display device provided in an embodiment of the present application.

[0031] Figure 8 yes Figure 7 A top view of the gate electrode and polysilicon layer of a thin film transistor in a display panel is shown.

[0032] Figure 9 yes Figure 8 Schematic diagram showing the cross-sectional area of ​​the edge slope portion of the polysilicon layer and the total cross-sectional area of ​​the polysilicon layer.

[0033] Figures 10 to 17It is a schematic diagram of a method for preparing a display device provided in an embodiment of the present application.

[0034] Figure 18 Schematic diagram showing the improvement effect of the two embodiments of the display device of the present application on the photogenerated leakage current compared with the traditional solution.

[0035] Figure 19 It is a schematic diagram showing the improvement effect of the hump phenomenon of the two embodiments of the display device of the present application compared with the traditional solution.

[0036] Figure 20 1 is another schematic diagram illustrating the improvement effect of the two embodiments of the display device of the present application on the hump phenomenon compared with the traditional solution. DETAILED DESCRIPTION

[0037] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0038] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0039] The embodiments of the present application may be combined with each other.

[0040] like Figure 7 As shown, an embodiment of the present application provides a display device having a low-temperature polysilicon thin-film transistor (LTPS) having a relatively thin polysilicon layer 703. This polysilicon layer 703 has a relatively small light absorption volume and a relatively small space charge portion 7032, thereby significantly reducing photoinduced leakage current (leakage current of the LTPS TFT under light irradiation) without requiring a light-shielding layer. Furthermore, the cross-sectional area of ​​the edge slope portion 7031 of the polysilicon layer 703 in the predetermined direction BB' (the direction connecting the source and drain) is relatively small, effectively suppressing the hump effect, increasing the turn-on current, optimizing the subthreshold swing of the TFT, reducing power consumption, and preventing the high subthreshold swing from affecting the response speed and power consumption of the pixel.

[0041] like Figure 1 and Figure 2As shown, in a conventional low-temperature polysilicon thin-film transistor of a display device, the polysilicon layer 101 has an end inclined portion 1012 and a main portion 1011 along the width direction. The end inclined portion 1012 is located at both ends of the main portion 1011 and is inclined. The gate 102 covers the main portion 1011 and the end inclined portion 1012 of the polysilicon layer 101. Under the bias of the gate 102, due to the geometric characteristics of the end inclined portion 1012, the electric field intensity generated in this area is relatively high, resulting in more carriers gathering at the width-wise edge of the polysilicon layer 101. In this case, the end inclined portion 1012 actually forms a parasitic transistor T_1012, generating an additional current channel.

[0042] like Figure 3 As shown in the figure, from a circuit perspective, the low-temperature polysilicon thin-film transistor is equivalent to a parallel structure of a main transistor T_1011 and a parasitic transistor T_1012. The gate of the main transistor T_1011 is electrically connected to the gate of the parasitic transistor T_1012, the source of the main transistor T_1011 is electrically connected to the source of the parasitic transistor T_1012, and the drain of the main transistor T_1011 is electrically connected to the drain of the parasitic transistor T_1012.

[0043] like Figure 4 As shown in Figure 2, under different drain-source voltage conditions (Vds=0.1V and Vds=10V), the drain current-gate voltage characteristic curve (ID-VG characteristic curve) of the low-temperature polysilicon thin film transistor shows a hump phenomenon, as shown in Figure 2. Figure 4 This is shown in section H1 in Figure 1. This is manifested as an abnormal increase in current in the subthreshold region (the region where the gate voltage is lower than the normal turn-on threshold).

[0044] Figure 5 The formation mechanism of the hump phenomenon is further explained. As can be seen from the figure, the drain current-gate voltage characteristic curve of the low-temperature polysilicon thin-film transistor can be decomposed into the ID-VG characteristic curves of the main transistor T_1011 and the parasitic transistor T_1012. Due to the low threshold voltage of the parasitic transistor T_1012, it begins to conduct before the main transistor T_1011 is fully turned on, resulting in an abnormal increase in the total current in the subthreshold region, forming a characteristic "hump". This hump effect can cause uneven brightness of pixels in low grayscale states in display devices, seriously affecting display quality, especially in high-resolution, high-contrast display devices.

[0045] like Figure 7 As shown, the thickness of the polysilicon layer 703 (active layer) in the low-temperature polysilicon thin-film transistor of the present application is 30nm or 35nm, which is significantly smaller than the traditional 45nm. This specific thickness effectively limits the volume of the space charge portion 7032 to 0.028μm3 The following significantly reduces the generation of photogenerated carriers in the low-temperature polysilicon thin-film transistor, reducing photogenerated leakage current. The polysilicon layer 703 of the present application can effectively improve the leakage performance of the low-temperature polysilicon thin-film transistor device and enhance the reliability of the low-temperature polysilicon thin-film transistor. At the same time, due to the significant reduction in photogenerated leakage current, the display device of the present application can eliminate the light shielding layer used in traditional processes to block light, thereby simplifying the process flow and reducing manufacturing costs.

[0046] like Figure 7 、 Figure 8 and Figure 9 As shown, the ratio of the cross-sectional area S1 of the edge inclined portion 7031 of the polysilicon layer 703 in the predetermined direction BB' to the total cross-sectional area S2 of the polysilicon layer 703 in the predetermined direction BB' is less than or equal to 1.2%. This can effectively improve the hump effect of the low-temperature polysilicon thin-film transistor device. The improvement of the hump effect makes the drain current-gate voltage characteristic curve (ID-VG characteristic curve) of the low-temperature polysilicon thin-film transistor device smoother, as shown in FIG. Figure 18 As shown, the turn-on current is increased, the subthreshold swing is optimized, and the stability and reliability of the low-temperature polysilicon thin-film transistor device are improved.

[0047] like Figure 6 As shown, the display device provided in an embodiment of the present application includes a display panel, a timing controller TCON, a source driver circuit DD, and a power management chip. The display panel may be, for example, a liquid crystal display panel. The display panel includes a display area and a non-display area. The display area is provided with m×n pixels PX arranged in an array, where m and n are integers greater than 1. The non-display area is located around the display area and is used to arrange driver circuits and various signal lines. The display panel also includes a plurality of gate lines (GL1 to GLn), a plurality of data lines (DL1 to DLm), and a gate driver circuit GOA. The plurality of gate lines extend along a first direction and are arranged along a second direction, and the plurality of data lines extend along a second direction and are arranged along the first direction, with the first direction being perpendicular to the second direction. The gate driver circuit GOA is provided in the non-display area and is electrically connected to the plurality of gate lines. The source driver circuit DD is electrically connected to the plurality of data lines via a flexible printed circuit board. The timing controller TCON is electrically connected to the gate driver circuit GOA and the source driver circuit DD, respectively.

[0048] The display panel includes a thin-film transistor array substrate, an opposing substrate, and a liquid crystal layer disposed between the two substrates. The thin-film transistor array substrate comprises, in order, a substrate 701, a buffer layer 702, a polysilicon layer 703 (active layer), a gate insulating layer 704, a gate electrode 705 (first metal layer), a first insulating layer 706, a second insulating layer 707, a source electrode 708 and a drain electrode 709 (second metal layer), a planarization layer 710, a common electrode 711 (third metal layer), a passivation layer 712, and a pixel electrode 713 (fourth metal layer). The buffer layer 702 is disposed on the substrate 701. The polysilicon layer 703 is disposed on the buffer layer 702. According to the technical solution of this application, its thickness is less than 45 nm, preferably 30 nm or 35 nm. The gate insulating layer 704 is disposed on the polysilicon layer 703 and the buffer layer 702 to insulate the polysilicon layer 703 from the gate electrode 705. The gate electrode 705 is formed from the first metal layer and disposed on the gate insulating layer 704. A first insulating layer 706 and a second insulating layer 707 are sequentially disposed on the gate 705 to insulate the gate 705 from the source 708 and drain 709. The thickness of the buffer layer 702 is greater than that of the gate insulating layer 704, but less than the sum of the thicknesses of the first insulating layer 706 and the second insulating layer 707. Specifically, the thickness of the buffer layer 702 is greater than or equal to 3000 angstroms. The source 708 and drain 709 are formed from the second metal layer and disposed on the second insulating layer 707. They are electrically connected to different regions of the polysilicon layer 703 via first and second through-holes 714 and 715, respectively. A planarization layer 710 is disposed on the source 708 and drain 709 to planarize the device surface. A common electrode 711 is formed from the third metal layer and disposed on the planarization layer 710. A passivation layer 712 is disposed on the common electrode 711 and the planarization layer 710. The pixel electrode 713 is formed of a fourth metal layer, is disposed on the passivation layer 712 , and is electrically connected to the drain electrode 709 through a third through hole 716 and a fourth through hole 717 .

[0049] The opposing substrate is located above the thin-film transistor array substrate, with a liquid crystal layer filling the space between the two substrates. The opposing substrate includes a substrate, a black matrix disposed on the substrate, and a color filter layer disposed on the black matrix. The black matrix is ​​made of a light-shielding material and is used to block light from non-display areas, preventing light leakage and improving display contrast. The color filter layer includes red, green, and blue filter units, which are used to filter out light of corresponding colors to create a color display effect. The color filter layer can also be disposed on the thin-film transistor array substrate instead of the opposing substrate.

[0050] Each pixel PX includes at least one thin-film transistor and a pixel electrode 713. The gate electrode 705 of the thin-film transistor is electrically connected to the corresponding gate line, the source electrode 708 is electrically connected to the corresponding data line, and the drain electrode 709 is electrically connected to the corresponding pixel electrode 713. When the gate line outputs a high-level scanning signal, the thin-film transistor is turned on, and the data signal on the data line is transmitted to the pixel electrode 713 through the thin-film transistor. When the gate line outputs a low-level scanning signal, the thin-film transistor is turned off, and the pixel electrode 713 maintains the voltage corresponding to the data signal.

[0051] The gate drive circuit GOA includes n cascaded gate drive sub-circuits, each of which is electrically connected to a gate line. Under the control of the timing controller TCON, the gate drive sub-circuits sequentially output scan signals to scan each row of pixels PX in the display area line by line. Under the control of the timing controller TCON, the source drive circuit DD generates and outputs data signals based on image data. The timing controller TCON is used to receive and process external image data and timing signals, generate control signals, and transmit image data to the source drive circuit DD. The power management chip is used to provide operating voltages for various parts of the display device, including providing a common voltage for the common electrode 711 of the display panel, providing a gate drive voltage for the gate drive circuit GOA, and providing a gamma voltage for the source drive circuit DD.

[0052] like Figure 7 As shown, the present application proposes a display device, which includes a display panel, which includes a substrate 701, a buffer layer 702, a polysilicon layer 703 (active layer), a gate insulating layer 704, a gate 705, a first insulating layer 706, a second insulating layer 707, a source electrode 708, a drain electrode 709, a planarization layer 710, a common electrode 711, a passivation layer 712, and a pixel electrode 713. The polysilicon layer 703 is a polysilicon layer having a specific thickness.

[0053] A buffer layer 702 is disposed on a substrate 701, a polysilicon layer 703 is disposed on the buffer layer 702, a gate insulating layer 704 is disposed on the polysilicon layer 703 and the buffer layer 702, a gate 705 is disposed on the gate insulating layer 704, a first insulating layer 706 is disposed on the gate 705 and the gate insulating layer 704, and a second insulating layer 707 is disposed on the first insulating layer 706. A first through-hole 714 and a second through-hole 715 are disposed in the second insulating layer 707, the first insulating layer 706, and the gate insulating layer 704. The first through-hole 714 and the second through-hole 715 both penetrate the second insulating layer 707, the first insulating layer 706, and the gate insulating layer 704. A source electrode 708 and a drain electrode 709 are disposed on the second insulating layer 707. A portion of the source electrode 708 is disposed in the first through-hole 714 and is electrically connected to the polysilicon layer 703. A portion of the drain electrode 709 is disposed in the second through-hole 715 and is electrically connected to the polysilicon layer 703. A planarization layer 710 is disposed on the source electrode 708, the drain electrode 709, and the second insulating layer 707. A third through-hole 716 is disposed on the planarization layer 710. The third through-hole 716 penetrates the planarization layer 710 and exposes a portion of the drain electrode 709. A common electrode 711 is disposed on the planarization layer 710. A passivation layer 712 is disposed on the common electrode 711 and the planarization layer 710. A fourth through-hole 717 is disposed on the passivation layer 712. The fourth through-hole 717 is located corresponding to the third through-hole 716. The fourth through-hole 717 penetrates the passivation layer 712 and exposes a portion of the drain electrode 709. The fourth through-hole 717 and the third through-hole 716 are nested. A pixel electrode 713 is disposed on the passivation layer 712. A portion of the pixel electrode 713 is disposed within the fourth through-hole 717 and is electrically connected to the drain electrode 709.

[0054] The thickness of the buffer layer 702 is greater than that of the gate insulating layer 704 and less than the sum of the thickness of the first insulating layer 706 and the thickness of the second insulating layer 707. Specifically, the thickness of the buffer layer 702 is greater than or equal to 3000 angstroms.

[0055] The first through hole 714 and the second through hole 715 are formed in the same process, and the source 708 and the drain 709 are formed in the same process.

[0056] In one embodiment of the present application, the thickness of the polysilicon layer 703 is less than 45 nm. Preferably, the thickness of the polysilicon layer 703 is greater than or equal to 25 nm and less than 45 nm. More preferably, the thickness of the polysilicon layer 703 is 35 nm or 30 nm. Polysilicon layers 703 of this specific thickness have a smaller light absorption volume and a smaller volume of the space charge portion 7032, thereby reducing photoinduced leakage current and improving the performance of low-temperature polysilicon thin-film transistors.

[0057] In one embodiment of the present application, the polysilicon layer 703 of the low-temperature polysilicon thin film transistor includes a space charge portion 7032, and the volume of the space charge portion 7032 is less than or equal to 0.028 μm 3 In particular, the volume of the space charge portion 7032 of the polysilicon layer 703 of the low-temperature polysilicon thin film transistor close to the drain 709 is less than or equal to 0.028 μm 3 The space charge portion 7032 is located at the junction of the channel portion 7035 and the lightly doped portion 7034 of the polysilicon layer 703. The space charge portion 7032 is the portion of the polysilicon layer 703 where the lightly doped portion 7034 and the channel region form a PN junction. That is, the space charge portion 7032 is part of the junction between the lightly doped portion 7034 and the channel portion 7035 of the polysilicon layer 703 and is the primary light-absorbing portion. By controlling the thickness of the polysilicon layer 703 and limiting the volume of the space charge portion 7032 of the polysilicon layer 703 to this specific range, the generation of photogenerated carriers can be effectively reduced, reducing photogenerated leakage current and improving the stability of the low-temperature polysilicon thin-film transistor under strong light conditions.

[0058] In one embodiment of the present application, the ratio of the cross-sectional area S1 of the edge bevel portion 7031 of the polysilicon layer 703 in the predetermined direction BB' to the total cross-sectional area S2 of the polysilicon layer 703 in the predetermined direction BB' is less than or equal to 1.2%. The edge bevel portion 7031 refers to the two end (corner) portions of the polysilicon layer 703 in the predetermined direction BB'. Due to the sharp angles of the two end (corner) portions of the polysilicon layer 703, the electric field in these portions is high (the voltage is high), which easily forms parasitic transistors and causes a hump effect. By controlling the cross-sectional area ratio of the edge bevel portion 7031 of the low-temperature polysilicon thin-film transistor within this range, the electric field concentration phenomenon at the edge of the low-temperature polysilicon thin-film transistor can be effectively reduced, reducing the impact of the parasitic transistor, thereby improving the hump effect and enabling the low-temperature polysilicon thin-film transistor to have better switching characteristics.

[0059] In one embodiment of the present application, the low-temperature polysilicon thin-film transistor does not include a light-shielding layer. Because the polysilicon layer 703 of the present application has a specific thickness, light-induced leakage current is significantly reduced. Therefore, the light-shielding layer used in conventional processes can be omitted, simplifying the manufacturing process and reducing costs. Furthermore, the integration density of the low-temperature polysilicon thin-film transistor can be increased.

[0060] like Figures 10 to 17 As shown, the present application also provides a method for preparing a display device, comprising the following steps: Step 1: If Figure 10As shown, a buffer layer 702 is formed on a substrate 701, and a polysilicon layer 703 is formed on the buffer layer 702. The polysilicon layer 703 is processed so that the polysilicon layer 703 includes a channel portion 7035, a lightly doped portion 7034, and a heavily doped portion 7033. The thickness of the polysilicon layer 703 is less than 45 nm. Preferably, the thickness of the polysilicon layer 703 is greater than or equal to 25 nm and less than 45 nm. More preferably, the thickness of the polysilicon layer 703 is 35 nm or 30 nm. The polysilicon layer 703 can be formed by a low-temperature polysilicon process, such as laser annealing technology, to crystallize the amorphous silicon layer into the polysilicon layer 703.

[0061] Step 2: If Figure 11 As shown, a gate insulating layer 704 is formed on the polysilicon layer 703 and the buffer layer 702, and a first metal layer is formed on the gate insulating layer 704. The first metal layer is patterned to form a gate 705. The gate insulating layer 704 can be made of materials such as silicon dioxide and silicon nitride. The gate 705 can be made of metal materials such as chromium, aluminum, and molybdenum.

[0062] Step 3: If Figure 12 As shown, a first insulating layer 706 and a second insulating layer 707 are sequentially formed on the gate insulating layer 704 and the gate 705. The gate insulating layer 704, the first insulating layer 706, and the second insulating layer 707 are then etched to form a first through hole 714 and a second through hole 715. The first through hole 714 and the second through hole 715 are formed in the same process, which simplifies the process flow and improves production efficiency. The first insulating layer 706 may be a silicon nitride layer, and the second insulating layer 707 may be a silicon dioxide layer.

[0063] Step 4: If Figure 13 As shown, a second metal layer is formed on the second insulating layer 707 and patterned to form a source electrode 708 and a drain electrode 709. The source electrode 708 and the drain electrode 709 are formed in the same process to improve manufacturing efficiency and reduce costs. The source electrode 708 and the drain electrode 709 can be made of a metal material such as aluminum, molybdenum, titanium, or an alloy thereof.

[0064] Step 5: If Figure 14 As shown, a planarization layer 710 is formed on the source electrode 708, the drain electrode 709 and the second insulating layer 707, and the planarization layer 710 is etched to form a third through hole 716. The planarization layer 710 can be made of an organic material or an inorganic material to planarize the device surface.

[0065] Step 6: If Figure 15 As shown, a third metal layer is formed on the planar layer 710 and patterned to form a common electrode 711. The common electrode 711 may be made of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

[0066] Step 7: If Figure 16 As shown, a passivation layer 712 is formed on the planar layer 710 and the common electrode 711, and the passivation layer 712 is etched to form a fourth through hole 717. The position of the fourth through hole 717 corresponds to the position of the third through hole 716, and the third through hole 716 and the fourth through hole 717 are nested. The passivation layer 712 can be made of materials such as silicon nitride and silicon dioxide to protect the underlying devices.

[0067] Step 8: If Figure 17 As shown, a fourth metal layer is formed on the passivation layer 712 and patterned to form a pixel electrode 713. The pixel electrode 713 can be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), and is used to form an electrode of the liquid crystal cell.

[0068] By using the above-mentioned preparation method, a display device can be prepared. The display device includes a low-temperature polysilicon thin film transistor and has the advantages of low photoinduced leakage current, improved hump effect, low manufacturing cost, etc.

[0069] Experimental results show that when the polysilicon layer 703 is 35nm thick (Example 2), the photoinduced leakage current is improved by 44%, significantly reducing the hump effect. When the polysilicon layer 703 is 30nm thick (Example 1), the photoinduced leakage current is further improved to 67%. The difference in threshold voltage (the voltage at which the transistor turns on) between the main transistor and the parasitic transistor of the low-temperature polysilicon thin-film transistor is improved from 1.227V (conventional solution) to 1.039V (Example 2) and 0.907V (Example 1).

[0070] like Figure 18 As shown, the three bar graphs under each lighting condition represent the conventional solution, Example 2, and Example 1 from left to right. Under the five lighting conditions of 0 nits, 5000 nits, 10000 nits, 15000 nits, and 20000 nits, as the light intensity increases, the photogenerated leakage current in the conventional solution, Example 1 of the present application, and Example 2 of the present application also increases. However, under the four lighting conditions of 5000 nits, 10000 nits, 15000 nits, and 20000 nits, the photogenerated leakage current of Example 1 of the present application decreases by 67% relative to the conventional solution, and the photogenerated leakage current of Example 2 of the present application decreases by 44% relative to the conventional solution. In Example 1, the thickness of the polysilicon layer 703 is 30nm, in Example 2, the thickness of the polysilicon layer 703 is 35nm, and in the conventional solution, the thickness of the polysilicon layer 703 is 45nm.

[0071] like Figure 19As shown, the difference in threshold voltage between the main transistor and the parasitic transistor in the conventional low-temperature polysilicon thin-film transistor is 1.227 V, the difference in threshold voltage between the main transistor and the parasitic transistor in the low-temperature polysilicon thin-film transistor of Example 2 is 1.039 V, and the difference in threshold voltage between the main transistor and the parasitic transistor in the low-temperature polysilicon thin-film transistor of Example 1 is 0.907 V. The smaller the difference in threshold voltage between the main transistor and the parasitic transistor, the less obvious the hump effect.

[0072] Taking all factors into consideration, the solution with a polysilicon layer 703 thickness of 30 nm (Example 1) is the optimal solution, which not only greatly reduces the photogenerated leakage current, but also significantly improves the hump effect, while maintaining good device performance.

[0073] In the embodiment of the present application, by setting the polysilicon layer 703 of the low-temperature polysilicon thin film transistor to a polysilicon layer with a specific thickness, the channel light absorption volume of the low-temperature polysilicon thin film transistor is reduced, thereby reducing the photoinduced leakage current. At the same time, the ratio of the cross-sectional area of ​​the edge inclined portion 7031 of the polysilicon layer 703 to the cross-sectional area of ​​the entire low-temperature polysilicon thin film transistor is small, thereby improving the hump effect. Figure 20 As shown, the hump phenomenon no longer occurs in the H2 portion of Examples 1 and 2 of the present application. This special structure of the low-temperature polysilicon thin-film transistor does not require an additional light-shielding layer, simplifies the manufacturing process, reduces costs, and improves device performance and reliability.

[0074] When used in a high-temperature environment, the polysilicon layer 703 of a specific thickness may undergo microstructural changes due to thermal stress, resulting in degradation of the performance of the polysilicon thin-film transistor. In particular, the photogenerated leakage current may increase with increasing temperature.

[0075] In order to solve the above technical problems, the present application adds a heat diffusion layer between the substrate 701 and the buffer layer 702. The heat diffusion layer is made of a material with high thermal conductivity, such as aluminum nitride or silicon nitride. The heat diffusion layer can quickly transfer the heat generated by the polysilicon layer 703 to the substrate 701, thereby preventing the local temperature of the polysilicon layer 703 from being too high. At the same time, the thickness of the heat diffusion layer is less than the thickness of the buffer layer 702, and will not significantly increase the total thickness of the polysilicon thin film transistor. The heat diffusion layer can also further prevent impurities in the substrate 701 from diffusing upward, thereby improving the purity and stability of the polysilicon layer 703, so that the polysilicon thin film transistor can still maintain good photoelectric properties in a high temperature environment.

[0076] This structure forms a four-layer structure: substrate 701 - heat diffusion layer - buffer layer 702 - polysilicon layer 703. The interface between the heat diffusion layer and buffer layer 702 is smooth, with a roughness lower than that of a standard buffer layer 702, ensuring the crystalline quality of the upper polysilicon layer 703. The thermal conductivity of the heat diffusion layer is significantly higher than that of conventional buffer layer 702 materials, forming an efficient heat conduction path. This structure significantly reduces the temperature rise of the polysilicon layer 703 in high-temperature environments, effectively suppressing microstructural changes caused by thermal stress and maintaining the stability and performance of the polysilicon thin-film transistor.

[0077] Although the polysilicon layer 703 of a certain thickness has significantly reduced the photo-generated leakage current, the residual photo-generated leakage current may still affect the display quality under extremely strong light conditions (such as direct sunlight outdoors).

[0078] In order to solve the above technical problems, the present application introduces nitrogen doping technology in the channel portion 7035 of the polysilicon layer 703, and forms energy level traps in the polysilicon layer 703 through low-dose nitrogen ion implantation to capture photogenerated carriers. Specifically, after the polysilicon layer 703 is formed and before the gate insulating layer 704 is formed, the channel portion 7035 of the polysilicon layer 703 is treated using a nitrogen ion implantation process with appropriate energy and dose. Nitrogen atoms form stable trap centers in the polysilicon lattice, effectively capturing carriers generated by light and preventing them from forming leakage current. This technology makes the photogenerated leakage current of low-temperature polysilicon thin-film transistors under strong light conditions significantly lower than that of untreated polysilicon thin-film transistors, while not significantly affecting the normal switching characteristics and mobility of low-temperature polysilicon thin-film transistors, ensuring that the display device can still maintain a high-quality display effect under strong light conditions.

[0079] The polysilicon layer 703, after nitrogen doping, includes a surface nitrogen-doped region and an inner intrinsic region. The thickness of the surface nitrogen-doped region is less than one-third of the total thickness of the polysilicon layer 703 and is located on the upper surface of the polysilicon layer 703. The nitrogen atom concentration is distributed in a gradient, with the highest concentration at the surface and gradually decreasing inward. Nitrogen atoms replace some silicon atoms in the polysilicon lattice or occupy interstitial positions, forming Si-N bonding structures. These Si-N bonding structures form uniformly distributed energy level traps in the polysilicon layer 703. The energy position of these energy level traps is located slightly below the middle of the polysilicon band gap and is moderately distant from the valence band top, making them suitable for capturing photogenerated holes. However, their ability to capture electrons is relatively weak, so they do not significantly affect the normal conduction characteristics of the low-temperature polysilicon thin-film transistor. This special band structure enables the polysilicon thin-film transistor to effectively suppress photogenerated leakage current under illumination conditions while maintaining good switching characteristics.

[0080] After the thickness of the polysilicon layer 703 is reduced, defects at the interface between the polysilicon layer 703 and the gate insulating layer 704 have a more significant impact on the performance of the polysilicon thin film transistor, which may cause threshold voltage drift and instability.

[0081] To solve the above technical problems, the present application adopts interface passivation treatment technology. After the polysilicon layer 703 is formed and before the gate insulating layer 704 is deposited, the surface of the polysilicon layer 703 is treated with hydrogen plasma, and the plasma power and treatment time are controlled within an appropriate range. Subsequently, oxidation treatment is immediately performed in a vacuum environment to form an ultra-thin oxide layer as a transition layer, the thickness of which is much smaller than the thickness of the gate insulating layer 704. Finally, the gate insulating layer 704 is deposited using atomic layer deposition (ALD) technology to ensure a smooth transition of the interface. This three-step interface treatment process can effectively passivate the dangling bonds on the polysilicon surface, significantly reduce the interface state density, reduce the threshold voltage drift, and improve the long-term stability and reliability of polysilicon thin film transistors.

[0082] After interface passivation, a unique three-layer interface structure is formed between the polysilicon layer 703 and the gate insulating layer 704: a hydrogen passivation layer, an ultra-thin oxide transition layer, and the gate insulating layer 704. The hydrogen passivation layer, which is thinner than the ultra-thin oxide transition layer and located on the outermost surface of the polysilicon layer 703, forms Si-H bonds formed by hydrogen atoms bonding with dangling bonds on the polysilicon surface. These Si-H bonds saturate the dangling bonds on the polysilicon surface, significantly reducing the interface state density. The ultra-thin oxide transition layer is composed of highly ordered SiO2, and its lattice constant forms a gradual transition between the polysilicon and the overlying gate insulating layer 704, reducing interface stress and defects. The gate insulating layer 704 forms a smooth interface with the ultra-thin oxide transition layer, with an interface roughness lower than that achieved in conventional processes. This unique three-layer interface structure creates a high-quality interface between the polysilicon layer 703 and the gate insulating layer 704, with low interface state density and minimal interface stress, significantly improving the stability and reliability of the polysilicon thin-film transistor. The electron trap density and hole trap density at the interface are significantly reduced, so that the threshold voltage drift of the polysilicon thin film transistor after long-term operation is kept within a small range.

[0083] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display device includes a thin film transistor, the thin film transistor includes a polysilicon layer, and a ratio of an area of ​​a cross section of an edge inclined portion of the polysilicon layer to a total area of ​​a cross section of the polysilicon layer is less than or equal to 1.2%.

2. The display device according to claim 1, wherein The thickness of the polysilicon layer is less than 45 nm.

3. The display device according to claim 2, wherein: The thickness of the polysilicon layer is greater than or equal to 25 nm and less than 45 nm.

4. The display device according to claim 1, wherein The display device further includes a substrate, a buffer layer, a gate insulating layer, a first insulating layer and a second insulating layer, and the thin film transistor further includes a gate; The buffer layer is provided on the substrate, the polysilicon layer is provided on the buffer layer, the gate insulating layer is provided on the polysilicon layer and the buffer layer, the gate is provided on the gate insulating layer, the first insulating layer is provided on the gate and the gate insulating layer, and the second insulating layer is provided on the first insulating layer; The thickness of the buffer layer is greater than the thickness of the gate insulating layer, and less than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer.

5. The display device according to claim 4, wherein: The thickness of the buffer layer is greater than or equal to 3000 angstroms.

6. The display device according to claim 1, wherein The polysilicon layer further includes a space charge portion, which is located at the junction of the channel portion 7035 and the lightly doped portion 7034 of the polysilicon layer. The volume of the space charge portion is less than or equal to 0.028 μm 3 .

7. A method for preparing a display device, characterized in that: include: forming a buffer layer on the substrate; forming a polysilicon layer on the buffer layer, wherein a ratio of an area of ​​a cross section of an edge inclined portion of the polysilicon layer to a total area of ​​a cross section of the polysilicon layer is less than or equal to 1.2%; forming a gate insulating layer on the polysilicon layer and the buffer layer; forming a gate on the gate insulating layer; forming a first insulating layer and a second insulating layer in sequence on the gate insulating layer and the gate; Etching the gate insulating layer, the first insulating layer, and the second insulating layer to form a first through hole and a second through hole; forming a source electrode and a drain electrode on the second insulating layer, wherein a portion of the source electrode is disposed in the first through hole and electrically connected to the polysilicon layer, and a portion of the drain electrode is disposed in the second through hole and electrically connected to the polysilicon layer; forming a planarization layer on the source electrode, the drain electrode, and the second insulating layer; etching the planar layer to form a third through hole; forming a common electrode on the planar layer; forming a passivation layer on the planar layer and the common electrode; Etching the passivation layer to form a fourth through hole, wherein the position of the fourth through hole corresponds to the third through hole, and the third through hole and the fourth through hole are nested; as well as A pixel electrode is formed on the passivation layer, wherein a portion of the pixel electrode is disposed in the fourth through hole and electrically connected to the drain electrode.

8. The method for manufacturing a display device according to claim 7, wherein: The thickness of the polysilicon layer is less than 45 nm.

9. The method for manufacturing a display device according to claim 8, wherein: The thickness of the polysilicon layer is greater than or equal to 25 nm and less than 45 nm.

10. The method for manufacturing a display device according to claim 7, wherein: The polysilicon layer further includes a space charge portion, which is located at the junction of the channel portion and the lightly doped portion of the polysilicon layer, and the volume of the space charge portion is less than or equal to 0.028 μm 3 .

11. The method for manufacturing a display device according to claim 7, wherein: The display device further includes a substrate, a buffer layer, a gate insulating layer, a first insulating layer and a second insulating layer, and the thin film transistor further includes a gate; The buffer layer is provided on the substrate, the polysilicon layer is provided on the buffer layer, the gate insulating layer is provided on the polysilicon layer and the buffer layer, the gate is provided on the gate insulating layer, the first insulating layer is provided on the gate and the gate insulating layer, and the second insulating layer is provided on the first insulating layer; The thickness of the buffer layer is greater than the thickness of the gate insulating layer, and less than the sum of the thickness of the first insulating layer and the thickness of the second insulating layer.

12. The method for manufacturing a display device according to claim 11, wherein: The thickness of the buffer layer is greater than or equal to 3000 angstroms.

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