A back contact battery with a locally highly conductive polycrystalline structure and a method for preparing the same

Abstract

The present invention belongs to the technical field of back-contact batteries, and specifically relates to a back-contact battery with a locally highly conductive polycrystalline structure and a preparation method thereof, comprising: S2, sequentially forming a first tunneling oxide layer and an N-type doped amorphous silicon layer on the back of a silicon wafer, followed by depositing a plasma-resistant mask layer; S3, opening a portion of the plasma-resistant mask layer corresponding to the metal electrode to form an opening region W0; then performing annealing; S4, performing a phosphine plasma treatment to form a highly conductive polycrystalline region; depositing an alkali-resistant mask layer on the back; S5, forming a second semiconductor opening region; S6, performing texturing and cleaning; and S9, depositing a second semiconductor layer on the back. The present invention can form a locally highly conductive polycrystalline structure, which is beneficial for carrier transport. At the same time, the film layer in the non-electrode contact area can be thinned and can be suitably low-doped and low-crystallinity, which is beneficial for reducing parasitic absorption of the film layer, achieving both high FF and high current density, thereby improving the overall conversion efficiency of the battery.

Description

Technical Field

[0001] The present invention belongs to the technical field of back-contact batteries, and in particular relates to a back-contact battery with a locally highly conductive polycrystalline structure and a preparation method thereof. Background Art

[0002] At present, the process with lower equipment cost in the preparation of back contact batteries is the post-texturing process, and its process flow is generally as follows:

[0003] S101, providing a double-sided polished silicon wafer;

[0004] S102, sequentially coating a first semiconductor layer and a first mask layer on the back side of the silicon wafer, wherein the first mask layer is generally silicon nitride or silicon oxynitride;

[0005] S103, laser or etching an opening on the back side of the silicon wafer to remove the first mask layer and a portion of the first semiconductor layer to form a second semiconductor opening region;

[0006] S104, texturing and cleaning the silicon wafer to remove the first semiconductor layer in the second semiconductor opening area;

[0007] S105, forming a passivation layer and an anti-reflection layer on the front side;

[0008] S106, removing the backside coating, and cleaning to further purify the second semiconductor opening area;

[0009] S107, forming a second semiconductor layer on the back side of the silicon wafer;

[0010] S108, laser or etching an opening on the back side of the silicon wafer to form a first semiconductor opening region alternately arranged with the second semiconductor opening region;

[0011] S109, depositing a conductive film layer on the back side of the silicon wafer;

[0012] S110, forming an insulating trench between the first semiconductor opening region and the second semiconductor opening region by laser or etching;

[0013] S111 , forming metal electrodes outside corresponding areas of the first semiconductor opening region and the second semiconductor opening region of the silicon wafer.

[0014] However, in existing back-contact cell post-texturing processes, S102, the back side of the silicon wafer, typically uses tubular PECVD to form the first semiconductor layer, which includes a first tunneling oxide layer and an N-type doped polycrystalline layer. In existing processes, if the doping concentration of the N-type doped polycrystalline layer is too high, it can easily lead to numerous defects in the polycrystalline layer, causing severe carrier recombination and affecting current density. If the doping concentration of the polycrystalline layer is too low, it can easily lead to insufficient conductivity, affecting carrier transport and resulting in a low FF.

[0015] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or public known technology. Summary of the Invention

[0016] The purpose of the present invention is to overcome the defect in the prior art that the structure of the first semiconductor layer in the back-contact battery cannot take into account both high FF and high current density, and to provide a back-contact battery with a local high-conductivity polycrystalline structure and a preparation method thereof, which can form a local high-conductivity polycrystalline structure, which is beneficial to carrier transport. At the same time, the film layer in the non-electrode contact area can be thinned and can be suitable for low doping and low crystallinity, which is beneficial to reducing the parasitic absorption of the film layer, taking into account high FF and high current density, thereby helping to improve the overall conversion efficiency of the battery.

[0017] To achieve the above objectives, in a first aspect, the present invention provides a method for preparing a back-contact battery with a locally highly conductive polycrystalline structure, comprising the following steps:

[0018] S1, provide double-sided polished silicon wafers;

[0019] S2, forming a first tunneling oxide layer and an N-type doped amorphous silicon layer on the back side of the silicon wafer in sequence, and then depositing a plasma resistant mask layer;

[0020] S3, opening a portion of the plasma resistant mask layer corresponding to the metal electrode to form an opening area W0;

[0021] Then, annealing is performed to form an N-type doped polysilicon layer from the N-type doped amorphous silicon layer, and a portion of the N-type doped polysilicon layer covered by the plasma resistant mask layer forms a phosphorus-doped and oxygen-doped polycrystalline layer;

[0022] S4. Performing a phosphine plasma treatment on the opening area W0 so that a portion of the thickness of the N-type doped polycrystalline silicon layer within the opening area W0 forms a highly conductive polycrystalline region, wherein the phosphorus doping concentration of the highly conductive polycrystalline region is 1.4-10 times the phosphorus doping concentration of the N-type doped polycrystalline silicon layer, and the crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times the crystallinity of the N-type doped polycrystalline silicon layer;

[0023] An alkali-resistant mask layer is then deposited on the back side;

[0024] S5, performing a second etching opening on the back side to expose the silicon wafer, forming second semiconductor opening regions arranged at intervals; the second semiconductor opening regions and the opening region W0 are arranged alternately;

[0025] S6, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area, and removing the alkali-resistant mask layer, the plasma-resistant mask layer, and the phosphorus-doped and oxygen-doped polycrystalline layer;

[0026] S9. Depositing a second semiconductor layer on the back side.

[0027] In some preferred embodiments of the present invention, in S2, the plasma resistant mask layer is at least one of silicon oxide, silicon oxynitride, and oxygen-containing polysilicon; and / or the thickness of the plasma resistant mask layer is 10-40 nm.

[0028] In some preferred embodiments of the present invention, in S2, the thickness of the first tunnel oxide layer is 1-2 nm, the thickness of the N-type doped amorphous silicon layer is 80-150 nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 .

[0029] In some preferred embodiments of the present invention, in S3, the thickness of the N-type doped polysilicon layer formed is 80-150 nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 ; The crystallinity of the N-type doped polysilicon layer is 70%-85%.

[0030] In some preferred embodiments of the present invention, in S3, the width of the opening region W0 is 100-200 μm; and / or, in S3, the thickness of the phosphorus-doped and oxygen-doped polycrystalline layer is 0.5-10 nm.

[0031] In some preferred embodiments of the present invention, in S3, the annealing conditions include: introducing one selected from nitrogen, argon or a nitrogen-argon mixture, a temperature of 800-1000° C., an annealing pressure of 100-900 mbar, and an annealing time of 30-90 min.

[0032] In some preferred embodiments of the present invention, in S4, the phosphorus doping concentration of the highly conductive polycrystalline region is 1×10 19 cm -3 -6×10 20 cm -3 , the crystallinity is 77%-98%, the thickness of the high conductive polycrystalline region is 0.5-10nm, and the width of the high conductive polycrystalline region is 100-200µm.

[0033] In some preferred embodiments of the present invention, in S4, the alkali-resistant mask layer is selected from at least one of silicon nitride, silicon oxynitride, silicon oxide, and carbon-doped silicon nitride.

[0034] In some preferred embodiments of the present invention, in S4, the conditions for the phosphine plasma treatment include:

[0035] The hydrogen-carrying phosphine mixed gas, hydrogen and protective gas are introduced, the volume flow ratio of the hydrogen-carrying phosphine mixed gas, hydrogen and protective gas is 1: (0.5-10): (0.5-10), the treatment temperature is 400-600 ° C, and the treatment time is 30-300 s;

[0036] and / or,

[0037] The flow rate of the hydrogen-phosphine mixture is 500-3000 sccm, the flow rate of phosphine in the hydrogen-phosphine mixture is 2%-8%, the flow rate of hydrogen is 1000-10000 sccm, the flow rate of the protective gas is 1000-10000 sccm, the gas pressure is 1500-4000 mtorr, and the power is 5000-15000 kW.

[0038] In some preferred embodiments of the present invention, in S9, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer, and the P-type doped silicon layer is P-type doped amorphous silicon or microcrystalline silicon.

[0039] In some preferred embodiments of the present invention, the preparation method further includes: performing S7 after S6, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S8, removing the back side coating layer and cleaning the second semiconductor opening area; and then performing S9.

[0040] In some preferred embodiments of the present invention, the preparation method further comprises:

[0041] S10, performing a third etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0042] S11, depositing a conductive film layer on the back surface obtained in S10;

[0043] S12, performing a fourth etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench;

[0044] S13 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0045] In a second aspect, the present invention provides a back-contact battery with a local high-conductivity polycrystalline structure, which is prepared by the preparation method of the back-contact battery with a local high-conductivity polycrystalline structure described in the first aspect.

[0046] In a third aspect, the present invention provides a back-contact battery with a locally highly conductive polycrystalline structure, comprising a silicon wafer, and a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, wherein both ends of the second semiconductor layer extend outward to cover the portion of the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is opened on the back side of the first semiconductor layer, as well as a conductive film layer and a metal electrode sequentially arranged outside the first semiconductor layer and the second semiconductor layer, an insulating groove being opened on the conductive film layer; the first semiconductor layer comprises a first tunneling oxide layer and an N-type doped polycrystalline silicon layer and a highly conductive polycrystalline region sequentially arranged on the back side of the silicon wafer, the highly conductive polycrystalline region being arranged outside the region of the N-type doped polycrystalline silicon layer corresponding to the corresponding metal electrode and between the N-type doped polycrystalline silicon layer and the conductive film layer; wherein the phosphorus doping concentration of the highly conductive polycrystalline region is 1.4-10 times that of the phosphorus doping concentration of the N-type doped polycrystalline silicon layer, and the crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times that of the N-type doped polycrystalline silicon layer.

[0047] In some preferred embodiments of the present invention, the back contact cell further comprises at least one of the following structures:

[0048] Structure 1: The width of the highly conductive polycrystalline region is 100-200µm, and the thickness of the highly conductive polycrystalline region is 0.5-10nm;

[0049] Structure 2: The thickness of the N-type doped polysilicon layer is 75-140nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 ; The crystallinity of the N-type doped polysilicon layer is 70%-85%;

[0050] Structure 3: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer, and the P-type doped silicon layer is P-type doped amorphous silicon or microcrystalline silicon;

[0051] Structure 4: A second semiconductor opening region is formed between adjacent first semiconductor layers, the second semiconductor opening region and the first semiconductor opening region being spaced apart, and the area therebetween being a spacer region; an insulating trench is provided in the spacer region, and the metal electrodes are provided on outer surfaces of the conductive film layers corresponding to the second semiconductor opening region and the first semiconductor opening region, respectively; a portion of the silicon wafer located at the second semiconductor opening region is a textured surface, and a portion of the silicon wafer located at a position corresponding to the first semiconductor layer is a polished surface;

[0052] Structure 5. The back contact cell also includes a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, and the front side of the silicon wafer is a textured surface.

[0053] Beneficial effects:

[0054] The present invention uses the above technical solutions, especially S2-S4 and S6, to form a highly conductive polycrystalline region in the electrode contact area corresponding to the metal electrode of the first semiconductor layer. Because the portion of the N-type doped polycrystalline silicon layer under the anti-plasma mask layer area on the back is blocked by the anti-plasma mask layer, the phosphine plasma treatment will not cause its doping concentration to increase. Therefore, a first semiconductor layer structure is formed in which the highly conductive polycrystalline region and the N-type doped polycrystalline silicon layer in the non-electrode contact area are alternately arranged, and the phosphorus doping concentration of the highly conductive polycrystalline region is controlled to be 1 / 4 of the phosphorus doping concentration of the N-type doped polycrystalline silicon layer. The crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times that of the N-type doped polycrystalline silicon layer. The doping concentration and crystallinity of the highly conductive polycrystalline region are significantly improved, which is beneficial to carrier transport. At the same time, the N-type doped polycrystalline silicon layer corresponding to the non-electrode contact region has a suitable low doping and low crystallinity ratio relative to the highly conductive polycrystalline region, which is beneficial to reducing the parasitic absorption of the film layer, taking into account high FF and high current density. The combination of the advantages of the highly conductive polycrystalline region and the N-type doped polycrystalline silicon layer in the non-electrode contact region is beneficial to improving the overall conversion efficiency of the battery.

[0055] Among them, after S3 annealing of the present invention, the N-type doped amorphous silicon layer forms an N-type doped polycrystalline silicon layer. During the annealing process, part of the N-type doped polycrystalline silicon layer covered by the anti-plasma mask layer will have some oxygen ions penetrate into the N-type doped polycrystalline silicon layer to form a phosphorus-doped and oxygen-doped polycrystalline layer. The phosphorus-doped and oxygen-doped polycrystalline layer is easily corroded and removed in the acid solution, so it will be removed in the subsequent texturing and cleaning process. After annealing, a back film layer structure in which phosphorus-doped and oxygen-doped polycrystalline layers and N-type doped polycrystalline silicon layers are alternately arranged is formed, and a back film layer structure in which phosphorus-doped and oxygen-doped polycrystalline layers and high conductive polycrystalline regions are alternately arranged is formed through subsequent phosphine plasma treatment. The phosphorus-doped and oxygen-doped polycrystalline layer is removed in the subsequent texturing and cleaning process to expose the N-type doped polycrystalline silicon layer underneath, and then finally a first semiconductor layer structure in which highly conductive polycrystalline regions and thinner N-type doped polycrystalline silicon layers in non-electrode contact regions are alternately arranged is formed. The thinned polycrystalline layer thickness is beneficial to reducing the parasitic absorption of the film layer and improving the current density of the battery.

[0056] In the back contact battery of the present invention, a first semiconductor layer structure in which a high conductive polycrystalline region and an N-type doped polycrystalline silicon layer in a non-electrode contact region are alternately arranged and matched with a first tunneling oxide layer is adopted, and the phosphorus doping concentration of the high conductive polycrystalline region is controlled to be 1.4-10 times the phosphorus doping concentration of the N-type doped polycrystalline silicon layer, and the crystallinity of the high conductive polycrystalline region is 1.1-1.3 times the crystallinity of the N-type doped polycrystalline silicon layer, which is beneficial to carrier transport. At the same time, the film layer in the non-electrode contact region can be thinned and can be suitable for low doping and low crystallinity, which is beneficial to reducing the parasitic absorption of the film layer, taking into account high FF and high current density, thereby helping to improve the overall conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0058] Figure 1 This is a schematic structural diagram of a specific embodiment of the back contact battery of the present invention.

[0059] Figure 2 This is a schematic diagram of a partial preparation process flow of a specific embodiment of the back contact battery preparation method of the present invention.

[0060] Description of Reference Numerals

[0061] Silicon wafer 1, first tunneling silicon oxide layer 2, N-type doped amorphous silicon layer 301, N-type doped polycrystalline silicon layer 3, plasma-resistant mask layer 4, alkali-resistant mask layer 5, passivation layer 6, anti-reflection layer 7, intrinsic hydrogenated amorphous silicon layer 8, P-type doped amorphous silicon layer 9, conductive film layer 10, metal electrode 11, highly conductive polycrystalline region 12. Opening region W0, second semiconductor opening region W2, first semiconductor opening region W1, insulation trench W3. DETAILED DESCRIPTION

[0062] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0063] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0064] The endpoints of the ranges and any values ​​disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoints of each range, the endpoints of each range and individual point values, and the individual point values ​​can be combined to form one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed herein. The terms "optional" and "optional" both mean that a range may or may not be included (or may or may not be present).

[0065] In the present invention, the area close to the silicon wafer is considered as the inside, and the area far from the silicon wafer is considered as the outside.

[0066] In a first aspect, the present invention provides a method for preparing a back-contact battery with a locally highly conductive polycrystalline structure, comprising the following steps:

[0067] S1, provide double-sided polished silicon wafers;

[0068] S2, forming a first tunneling oxide layer and an N-type doped amorphous silicon layer on the back side of the silicon wafer in sequence, and then depositing a plasma resistant mask layer;

[0069] S3, opening a portion of the plasma resistant mask layer corresponding to the metal electrode to form an opening area W0;

[0070] Then, annealing is performed to form an N-type doped polysilicon layer from the N-type doped amorphous silicon layer, and a portion of the N-type doped polysilicon layer covered by the plasma resistant mask layer forms a phosphorus-doped and oxygen-doped polycrystalline layer;

[0071] S4. Performing a phosphine plasma treatment on the opening region W0 so that a partially thick N-type doped polycrystalline silicon layer within the opening region W0 forms a highly conductive polycrystalline region, wherein the phosphorus doping concentration of the highly conductive polycrystalline region is 1.4-10 times, preferably 2-10 times, and further preferably 4-10 times, of the phosphorus doping concentration of the N-type doped polycrystalline silicon layer, and the crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times, preferably 1.18-1.30 times, of the crystallinity of the N-type doped polycrystalline silicon layer;

[0072] An alkali-resistant mask layer is then deposited on the back side;

[0073] S5, performing a second etching opening on the back side to expose the silicon wafer, forming second semiconductor opening regions arranged at intervals; the second semiconductor opening regions and the opening region W0 are arranged alternately;

[0074] S6, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area, and removing the alkali-resistant mask layer, the plasma-resistant mask layer, and the phosphorus-doped and oxygen-doped polycrystalline layer;

[0075] S9. Depositing a second semiconductor layer on the back side.

[0076] In the present invention, a plasma-resistant mask layer refers to a film layer that resists plasma treatment and protects underlying film layers from the effects of plasma treatment. In some preferred embodiments of the present invention, in S2, the plasma-resistant mask layer is at least one of silicon oxide, silicon oxynitride, and oxygen-containing polysilicon. While the oxygen-containing plasma-resistant mask layer resists plasma treatment, the portion of the N-type doped polysilicon layer covered by the plasma-resistant mask layer forms a phosphorus-doped and oxygen-doped polysilicon layer, facilitating thinning of the first semiconductor layer.

[0077] In the present invention, the thickness of the plasma-resistant mask layer is preferably 10-40 nm, more preferably 10-39 nm. The plasma-resistant phosphorus doping resistance of the plasma-resistant mask layer of the present invention is different from the alkali-resistant effect of conventional mask layers. Therefore, the plasma-resistant mask layer does not need to be too thick. Using a suitably thin plasma-resistant mask layer is more conducive to achieving the plasma-resistant effect while facilitating subsequent removal in a solution.

[0078] The deposition method of the plasma resistant mask layer can be carried out by referring to the prior art. For example, it can be deposited by tubular PECVD. For example, the deposition conditions preferably include: at 400-600°C, silane and other target element gas sources (such as nitrous oxide and other gases) are introduced, the silane flow rate is 1500-5000sccm, the flow rate of other target element gas sources is 7500-50000sccm, the gas pressure is 1500-4000mtorr, and the power is 5000-15000kW.

[0079] In some preferred embodiments of the present invention, in S2, the thickness of the first tunnel oxide layer is 1-2 nm, the thickness of the N-type doped amorphous silicon layer is 80-150 nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 It is understood that after the N-type doped amorphous silicon layer is annealed to form the N-type doped polysilicon layer, the thickness and phosphorus doping concentration remain unchanged. The first tunneling oxide layer and the N-type doped polysilicon layer form the first semiconductor layer.

[0080] The deposition method of the N-type doped amorphous silicon layer of the present invention can be carried out with reference to the prior art. For example, it can be deposited by tubular PECVD, and its deposition conditions preferably include: a deposition temperature of 400-600°C, and the introduction of gases including silane, hydrogen and phosphine. The flow rate of silane is 1500-5000sccm, the flow rate of hydrogen is 3000-20000sccm, the flow rate of the hydrogen mixture carrying phosphine is 100-1000sccm, the volume flow rate of phosphine in the hydrogen mixture carrying phosphine accounts for 2%-8%, the gas pressure is 1500-4000mtorr, and the power is 5000-15000kW.

[0081] The opening in S3 of the present invention can be a laser opening or a chemical solution etching opening, and laser opening is preferred because laser opening is simpler and cleaner.

[0082] In some preferred embodiments of the present invention, in S3, the thickness of the N-type doped polysilicon layer formed is 80-150 nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 The N-type doped polysilicon layer of the present invention can be thinner and have a lower phosphorus doping concentration. When combined with structures such as a highly conductive polycrystalline region, it can still achieve excellent passivation to improve battery conversion efficiency.

[0083] In the present invention, the crystallinity of the N-type doped polysilicon layer is preferably 70%-85%. The crystallinity of the N-type doped polysilicon layer of the present invention is suitable, and the crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times that of the N-type doped polysilicon layer, which is more conducive to improving the conductivity of the film layer.

[0084] In some preferred embodiments of the present invention, in S3, the width of the opening region W0 is 100-200 µm. Using an opening region W0 of an appropriate width can provide a highly conductive polycrystalline region of an appropriate width, which is more conducive to carrier transport and improves the conductivity of the film layer and the electrode.

[0085] In S3 of the present invention, the laser used for the laser opening may be an ultraviolet or green picosecond laser, and preferably, the pulse width thereof is less than 10 ps.

[0086] In the present invention, preferably, in S3, the thickness of the phosphorus-doped and oxygen-doped polycrystalline layer is 0.5-10 nm, preferably 0.5-9 nm. The present invention can control the thickness of the phosphorus-doped and oxygen-doped polycrystalline layer by adjusting the plasma treatment time. Using an appropriately thin phosphorus-doped and oxygen-doped polycrystalline layer further effectively prevents excessive penetration of phosphorus atoms into non-highly conductive polycrystalline regions.

[0087] In some preferred embodiments of the present invention, in S3, the annealing conditions include: introducing one selected from nitrogen, argon or a nitrogen-argon mixture, a temperature of 800-1000° C., an annealing pressure of 100-900 mbar, and an annealing time of 30-90 min.

[0088] In some preferred embodiments of the present invention, in S4, the phosphorus doping concentration of the highly conductive polycrystalline region is 1×10 19 cm -3 -6×10 20 cm -3 , more preferably 2×10 20 cm -3 -6×10 20 cm-3 , more preferably 3×10 20 cm -3 -6×10 20 cm -3 The crystallinity is 77%-98%, more preferably 93%-98%. The use of the highly conductive polycrystalline region of this preferred solution is more conducive to improving the conductive performance and increasing FF.

[0089] In the present invention, the thickness of the highly conductive polycrystalline region is preferably 0.5-10 nm, more preferably 2-10 nm. The thickness of the highly conductive polycrystalline region can be controlled by adjusting the time and / or power of the plasma treatment.

[0090] In the present invention, the width of the highly conductive polycrystalline region is preferably 100-200 μm, more preferably 120-200 μm. The width of the highly conductive polycrystalline region can be controlled by adjusting the opening area W0.

[0091] The present invention adopts a high-conductivity polycrystalline region with a suitable thin thickness and / or a suitable width, which is more conducive to taking into account both passivation and conductive properties.

[0092] In some preferred embodiments of the present invention, in S4, the alkali-resistant mask layer is selected from at least one of silicon nitride, silicon oxynitride, silicon oxide, and carbon-doped silicon nitride.

[0093] The deposition method of the alkali-resistant mask layer in S4 of the present invention can be carried out according to the target type with reference to the method of the prior art. For example, the deposition conditions may include: a silane flow rate of 1000-2000sccm, a flow rate of other target element gas sources (such as ammonia) of 5000-15000sccm, a pressure of 200-400Pa, a power supply of 3-20kW, a temperature of 400-600°C, and a time of 300-800s.

[0094] In some preferred embodiments of the present invention, in S4, the conditions for the phosphine plasma treatment include: introducing hydrogen-carrying phosphine mixed gas, hydrogen and protective gas, and the volume flow ratio of the hydrogen-carrying phosphine mixed gas, hydrogen and protective gas is 1:(0.5-10):(0.5-10), more preferably 1:(0.5-4):(2-10). The phosphine plasma treatment of the present invention involves the introduction of phosphine (phosphine is introduced in the form of a hydrogen-carrying phosphine mixed gas), hydrogen (i.e., hydrogen introduced alone), and a protective gas. During the plasma treatment process, hydrogen can dominate chemical etching and lattice reconstruction, while a protective gas, such as argon, can enhance physical activation and energy transfer. The two gases work together to achieve efficient conversion of the amorphous phase, significantly improving the crystallization rate of the polycrystalline material. The use of an appropriate ratio of phosphine, hydrogen, and protective gas facilitates both increasing the doping concentration in the laser-opened electrode contact region and improving its crystallinity and electrical conductivity. After phosphine plasma treatment under these conditions, the phosphorus doping concentration of the highly conductive polycrystalline region with high conductivity and high crystallization rate is increased by 2-10 times, and the crystallinity is increased by 10%-30% compared to the electrode non-contact region.

[0095] The protective gas can be selected from at least one of argon, helium, neon, etc., preferably argon.

[0096] Preferably, in the present invention, the conditions for the phosphine plasma treatment include: a treatment temperature of 400-600° C., and a treatment time of 30-300 s.

[0097] In some preferred embodiments of the present invention, in S4, the conditions for the phosphine plasma treatment include: a flow rate of 500-3000 sccm of the hydrogen-phosphine mixed gas, a flow rate of 1000-10000 sccm of hydrogen, and a flow rate of 1000-10000 sccm of the protective gas. Further preferably, the flow rate of phosphine in the hydrogen-phosphine mixed gas accounts for 2%-8%.

[0098] Preferably, in the present invention, the conditions for the phosphine plasma treatment include: a gas pressure of 1500-4000 mtorr and a power of 5000-15000 kW.

[0099] The conditions for the texturing cleaning in S6 of the present invention can be carried out with reference to the prior art. For example, the texturing solution used is a mixture of alkali (such as potassium hydroxide or sodium hydroxide), a texturing additive and water, wherein the mass percentage of the alkali is 1%-5%, and the mass percentage of the texturing additive is 0.5%-1%. Furthermore, the texturing conditions may include: a texturing time of 8-30 minutes, and a texturing temperature of 75°C-85°C. The texturing additive can be obtained commercially. The final cleaning conditions in the texturing cleaning can be adjusted according to the target mask layer to be removed. For example, when the mask layer needs to be removed, the final cleaning conditions include: the cleaning solution used for the final cleaning is an acid solution such as HF, the mass percentage of HF in the HF acid solution is 0.5%-5%, the mass percentage of deionized water contained is 95%-99.5%, the processing temperature is 20°C-30°C, and the removal time is 60-500s.

[0100] In some preferred embodiments of the present invention, in S9, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer. Further preferably, the P-type doped silicon layer is P-type doped amorphous silicon or microcrystalline silicon. The second semiconductor layer of the present invention can be formed by existing methods such as plate-type CVD, and the deposition temperature of the second semiconductor layer is 150-250°C.

[0101] More preferably, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer. The combined passivation structure of this preferred solution is more conducive to improving the battery conversion efficiency.

[0102] More preferably, the intrinsic hydrogenated amorphous silicon layer has a thickness of 3-15 nm, the P-type doped silicon layer has a thickness of 5-15 nm, and the boron doping concentration is 1×10 18 -9×10 19 cm -3 .

[0103] In some preferred embodiments of the present invention, the preparation method further comprises:

[0104] After S6, S7 is performed to form a passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0105] S8, removing the back side coating layer and cleaning the second semiconductor opening area; then proceeding to S9.

[0106] The types and thicknesses of the front passivation layer and anti-reflection layer of the present invention can be determined by reference to existing technologies and can be applied to the present invention. Preferably, the front passivation layer is at least one of amorphous silicon, oxygen-doped amorphous silicon, phosphorus-doped amorphous silicon, silicon oxide, and aluminum oxide. For example, the anti-reflection layer can be at least one of silicon nitride, silicon oxynitride, carbon-doped silicon nitride, silicon oxide, and carbon-doped silicon oxide.

[0107] The present invention may also include other conventional steps. In some preferred embodiments of the present invention, the preparation method further includes:

[0108] S10, performing a third etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region;

[0109] S11, depositing a conductive film layer on the back surface obtained in S10;

[0110] S12, performing a fourth etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench;

[0111] S13 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

[0112] In a second aspect, the present invention provides a back-contact battery with a local high-conductivity polycrystalline structure, which is prepared by the preparation method of the back-contact battery with a local high-conductivity polycrystalline structure described in the first aspect.

[0113] In a third aspect, the present invention provides a back-contact cell with a locally highly conductive polycrystalline structure, comprising a silicon wafer, and a first semiconductor layer and a second semiconductor layer alternately disposed on the back side of the silicon wafer, wherein both ends of the second semiconductor layer extend outwardly beyond the portion of the back side covering the adjacent first semiconductor layer, and a first semiconductor opening region is defined on the back side of the first semiconductor layer that does not cover the second semiconductor layer; a conductive film layer and a metal electrode are sequentially disposed outside the first and second semiconductor layers, and an insulating trench is defined above the conductive film layer; the first semiconductor layer comprises a first tunneling oxide layer, an N-type doped polycrystalline silicon layer, and a highly conductive polycrystalline region disposed sequentially on the back side of the silicon wafer, the highly conductive polycrystalline region being disposed outside the region of the N-type doped polycrystalline silicon layer corresponding to the corresponding metal electrode and between the N-type doped polycrystalline silicon layer and the conductive film layer; wherein the phosphorus doping concentration of the highly conductive polycrystalline region is 1.4-10 times that of the N-type doped polycrystalline silicon layer, and the crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times that of the N-type doped polycrystalline silicon layer. This back-contact cell has the same structure and performance as the back-contact cell of the second aspect.

[0114] In some preferred embodiments of the present invention, the width of the highly conductive polycrystalline region is 100-200 μm.

[0115] In the present invention, the thickness of the highly conductive polycrystalline region is preferably 0.5-10 nm. Using a suitably thin highly conductive polycrystalline region is more conducive to taking into account the passivation performance.

[0116] In some preferred embodiments of the present invention, the thickness of the N-type doped polysilicon layer is 75-140 nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 ; The crystallinity of the N-type doped polysilicon layer is 70%-85%.

[0117] In some preferred embodiments of the present invention, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polysilicon layer. Further preferably, the P-type doped silicon layer is P-type doped amorphous silicon or microcrystalline silicon.

[0118] In some preferred embodiments of the present invention, a second semiconductor opening region is formed between adjacent first semiconductor layers, the second semiconductor opening region is spaced apart from the first semiconductor opening region, and the area between them is a spacing region; the insulating groove is arranged in the spacing region, and the metal electrode is arranged on the outer surface of the corresponding conductive film layer of the second semiconductor opening region and the first semiconductor opening region.

[0119] Preferably, in the present invention, a portion of the silicon wafer located at the second semiconductor opening region is a textured surface, and a portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface.

[0120] In some preferred embodiments of the present invention, the back contact cell further comprises a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, and the front side of the silicon wafer is a textured surface.

[0121] The embodiments of the present invention are described in detail below, which are exemplary and only used to explain the present invention, and are not to be construed as limiting the present invention.

[0122] Example 1

[0123] A back contact battery, the structure of which is as follows Figure 1 As shown, it includes Figure 2 The following steps are shown:

[0124] S1, silicon wafer 1 (N-type single crystal silicon wafer) double-sided polishing;

[0125] S2. Forming a first tunneling silicon oxide layer 2, an N-type doped amorphous silicon layer 301, and a plasma-resistant mask layer 4 on the back side of the silicon wafer 1 in sequence:

[0126] The anti-plasma mask layer 4 is a silicon oxide layer with a thickness of 20 nm. The first tunneling silicon oxide layer 2 has a thickness of 1.5 nm, and the N-type doped amorphous silicon layer 301 has a thickness of 120 nm and a phosphorus doping concentration of 9×10 19 cm -3 .

[0127] The N-type doped amorphous silicon layer 301 is deposited by tubular PECVD under the following conditions: at 500° C., silane, hydrogen, and phosphine are introduced, the silane flow rate is 2000 sccm, the hydrogen flow rate is 7000 sccm, the flow rate of the hydrogen mixture carrying phosphine is 600 sccm, the volume flow rate of phosphine in the hydrogen mixture carrying phosphine accounts for 3%, the gas pressure is 2000 mtorr, and the power is 8000 kW.

[0128] Then, the plasma-resistant mask layer 4 is deposited under the following deposition conditions: at 500° C., silane and nitrous oxide are introduced, the silane flow rate is 2000 sccm, the nitrous oxide flow rate is 12000 sccm, the gas pressure is 2000 mtorr, and the power is 8000 kW.

[0129] S3, laser opening and annealing of the anti-plasma mask layer 4:

[0130] The plasma-resistant mask layer 4 is laser-opened to form an opening area W0 . The width of the opening area W0 is 150 μm. The laser used is an ultraviolet picosecond laser with a pulse width of 5 ps.

[0131] After laser opening, the N-type doped amorphous silicon layer 301 and the plasma-resistant mask layer 4 are annealed to form an N-type doped polysilicon layer 3. The doping concentration and thickness remain unchanged. The annealing conditions are: a temperature of 910°C, nitrogen gas, an annealing pressure of 200 mbar, and an annealing time of 50 minutes. The N-type doped polysilicon layer 3 has a crystallinity of 80%.

[0132] After annealing, the N-type doped amorphous silicon layer 301 is annealed to form an N-type doped polysilicon layer 3. During the annealing process, some oxygen ions penetrate into the corresponding portion of the N-type doped polysilicon layer 3 covered by the plasma-resistant mask layer 4, forming a phosphorus-doped and oxygen-doped polycrystalline layer (not shown). The phosphorus-doped and oxygen-doped polycrystalline layer has a thickness of 5 nm and is easily removed by etching in an acid solution. After annealing, a backside film structure is formed in which the phosphorus-doped and oxygen-doped polycrystalline layers and the N-type doped polysilicon layer 3 are alternately arranged.

[0133] S4, perform phosphine plasma treatment on the opening area W0 of the laser opening, and then deposit an alkali-resistant mask layer 5 on the back side:

[0134] A phosphine plasma treatment was performed in the opening region W0. The phosphine plasma treatment conditions included: a temperature of 500°C, the introduction of phosphine, hydrogen, and argon gases; a hydrogen-phosphine mixture (phosphine volumetric ratio of 5%) at a flow rate of 1000 sccm, a hydrogen flow rate of 3000 sccm, and an argon flow rate of 3000 sccm; a flow ratio of 1:3:3 between the hydrogen-phosphine mixture and the hydrogen and argon gases; a pressure of 3000 mtorr, a power of 10,000 kW, and a treatment time of 100 seconds. This resulted in the formation of a highly conductive, high-crystallization polycrystalline region 12 in the N-type doped polysilicon layer 3 corresponding to the opening region W0. The highly conductive polycrystalline region 12 had a thickness of 3 nm and a width of 150 µm. The phosphorus doping concentration in the highly conductive polycrystalline region was six times that of the N-type doped polysilicon layer, and the crystallinity of the highly conductive polycrystalline region was 1.2 times that of the N-type doped polysilicon layer.

[0135] An alkali-resistant mask layer 5 is then deposited on the back surface. This layer is resistant to corrosion from alkaline solutions. This layer is made of silicon nitride and is deposited under the following conditions: a silane flow rate of 1200 sccm, an ammonia flow rate of 9000 sccm, a pressure of 300 Pa, a power supply of 10 kW, a temperature of 500°C, and a deposition time of 500 seconds.

[0136] S5, a second opening is made on the back side of the silicon wafer 1 to form a second semiconductor opening region W2;

[0137] S6, texturing and cleaning the second semiconductor opening areas W2 on the front and back sides of the silicon wafer 1:

[0138] The second semiconductor opening W2 on the front and back sides of the silicon wafer 1 was cleaned and texturized using a texturizing solution consisting of 1% potassium hydroxide, a texturizing additive, and water. The potassium hydroxide content was 1% by weight, and the texturizing additive content was 0.5% by weight. The texturizing conditions were: a texturizing time of 20 minutes and a texturizing temperature of 80°C.

[0139] During the front texturing process, the alkali-resistant mask layer 5 and its plasma-resistant mask layer 4 and the phosphorus-doped and oxygen-doped polycrystalline layer on the back of the silicon wafer 1 are also removed by the final cleaning solution. The removal solution used is an HF solution with a HF mass percentage of 0.5% and a deionized water mass percentage as the balance. The treatment temperature is 25°C and the removal time is 400 seconds.

[0140] S7, forming a passivation layer 6 and an anti-reflection layer 7 on the front surface of the silicon wafer 1;

[0141] S8, removing the back side coating and cleaning the second semiconductor opening area W2;

[0142] S9, forming a second semiconductor layer on the back side of the silicon wafer 1;

[0143] The second semiconductor layer is an intrinsic hydrogenated amorphous silicon layer 8 and a P-type doped amorphous silicon layer 9 arranged in sequence. The second semiconductor layer is formed by plate-type CVD. The intrinsic hydrogenated amorphous silicon layer 8 has a thickness of 11 nm, the P-type doped amorphous silicon layer 9 has a thickness of 10 nm, and a boron doping concentration of 3.5×10 19 cm -3 , the deposition temperature of the second semiconductor layer is 200°C.

[0144] S10, etching an opening on the back side of the silicon wafer 1 for the third time to form a first semiconductor opening region W1;

[0145] S11, depositing a conductive film layer 10 (ITO) on the back side of the silicon wafer 1;

[0146] S12, performing a fourth etching opening on the conductive film layer 10 on the back side of the silicon wafer 1 to form an insulating trench W3; after etching, the resistance between the first semiconductor and the second semiconductor is greater than 1 kΩ.

[0147] S13 , forming metal electrodes 11 outside corresponding areas of the first semiconductor opening region W1 and the second semiconductor opening region W2 on the back side of the silicon wafer 1 .

[0148] Example 2

[0149] The treatment was carried out in the same manner as in Example 1, except that the flow rate ratio of argon in the gas introduced during the phosphine plasma treatment was adjusted so that the volume flow ratio of the hydrogen-carried phosphine mixed gas to the argon gas was 1:1. The resulting phosphorus doping concentration in the highly conductive polycrystalline region 12 was three times that of the N-type doped polycrystalline silicon layer 3, and the crystallinity of the highly conductive polycrystalline region 12 was 1.16 times that of the N-type doped polycrystalline silicon layer 3.

[0150] Example 3

[0151] The treatment was carried out in the same manner as in Example 1, except that the flow rate ratio of hydrogen in the gas introduced during the phosphine plasma treatment was adjusted so that the volume flow ratio of the hydrogen-phosphine mixed gas to the hydrogen was 1:5. The resulting phosphorus doping concentration in the highly conductive polycrystalline region 12 was 1.45 times that of the N-type doped polycrystalline silicon layer 3, and the crystallinity of the highly conductive polycrystalline region 12 was 1.12 times that of the N-type doped polycrystalline silicon layer 3.

[0152] Example 4

[0153] The process is carried out with reference to Example 1, except that the thickness of the highly conductive polycrystalline region 12 is adjusted to 1 nm. To meet this condition, the following adjustments are made: the phosphine plasma treatment time is shortened by 75%.

[0154] Example 5

[0155] The same process is carried out with reference to Example 1, except that the width of the highly conductive polycrystalline region 12 is adjusted to 100 μm. To meet this condition, the width of the opening region W0 is correspondingly adjusted to 100 μm.

[0156] Example 6

[0157] The process was carried out in the same manner as in Example 1, except that the thickness of the phosphorus-doped and oxygen-doped polycrystalline layer was adjusted to 10 nm. The process parameters adjusted accordingly to meet this condition were: the phosphine plasma treatment time was extended by 1 time. Under these conditions, the phosphorus doping concentration of the highly conductive polycrystalline region 12 obtained was 1.8 times that of the N-type doped polycrystalline silicon layer 3. The crystallinity of the highly conductive polycrystalline region 12 was 1.06 times (approximately 1.1 times) that of the N-type doped polycrystalline silicon layer 3. The thickness of the highly conductive polycrystalline region 12 was 9.2 nm.

[0158] Example 7

[0159] The method is carried out in accordance with Example 1, except that the second semiconductor layer is adjusted to a stack of a second tunnel oxide layer with a thickness of 1.5 nm and a P-type doped polysilicon layer, the thickness of the P-type doped polysilicon layer is 80 nm, the boron doping concentration is 5×10 19 cm -3 .

[0160] Comparative Example 1

[0161] The process is carried out in accordance with Example 1, except that the highly conductive polycrystalline region 12 is not provided. Specifically, the laser opening to form the opening region W0 is not performed in S3, the phosphine plasma treatment in S4 is not performed, and the alkali-resistant mask layer deposition is not performed.

[0162] Comparative Example 2

[0163] The process was carried out in accordance with Example 1, except that the conditions for the phosphine plasma treatment were adjusted so that the phosphorus doping concentration of the highly conductive polycrystalline region 12 was 21 times that of the N-type doped polycrystalline silicon layer 3, and the crystallinity of the highly conductive polycrystalline region 12 was 1.02 times that of the N-type doped polycrystalline silicon layer 3. To meet these conditions, the conditions for the phosphine plasma treatment were adjusted accordingly: only hydrogen was introduced during the phosphine plasma treatment to carry the phosphine mixed gas and hydrogen, and the treatment time was extended by 3.5 times; argon gas was not introduced.

[0164] Test Case

[0165] The back-contact cells obtained in Examples 1-7 and Comparative Examples 1-2 were subjected to performance testing, and the results are shown in Table 1. The performance indicators of each example and comparative example were calculated using Example 1 as a reference. The data for Example 1 was normalized to 1.000, and the other examples were calculated based on Example 1. For example, the FF of Comparative Example 1 / FF of Example 1 was 0.981.

[0166] Table 1

[0167]

[0168] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention is beneficial to carrier transport, while reducing the parasitic absorption of the film layer, taking into account high FF and high current density, thereby improving the overall conversion efficiency of the battery.

[0169] Furthermore, according to Example 1 and Examples 2-7, it can be seen that the preferred solution of the present invention is more conducive to improving FF and high current density, thereby further improving the overall conversion efficiency of the battery.

[0170] The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, various simple variations of the technical solution of the present invention may be made, including combining the various technical features in any other appropriate manner. These simple variations and combinations should also be regarded as disclosed in the present invention and fall within the scope of protection of the present invention.

Claims

1. A method for preparing a back contact battery with a locally highly conductive polycrystalline structure, characterized in that: The steps include: S1, provide double-sided polished silicon wafers; S2, forming a first tunneling oxide layer and an N-type doped amorphous silicon layer on the back side of the silicon wafer in sequence, and then depositing a plasma resistant mask layer; S3, opening a portion of the plasma resistant mask layer corresponding to the metal electrode to form an opening area W0; Then, annealing is performed to form an N-type doped polysilicon layer from the N-type doped amorphous silicon layer, and a portion of the N-type doped polysilicon layer covered by the plasma resistant mask layer forms a phosphorus-doped and oxygen-doped polycrystalline layer; S4. Performing a phosphine plasma treatment on the opening area W0 so that a portion of the thickness of the N-type doped polycrystalline silicon layer within the opening area W0 forms a highly conductive polycrystalline region, wherein the phosphorus doping concentration of the highly conductive polycrystalline region is 1.4-10 times the phosphorus doping concentration of the N-type doped polycrystalline silicon layer, and the crystallinity of the highly conductive polycrystalline region is 1.1-1.3 times the crystallinity of the N-type doped polycrystalline silicon layer; An alkali-resistant mask layer is then deposited on the back side; S5, performing a second etching opening on the back side to expose the silicon wafer and form a second semiconductor opening region arranged at intervals; The second semiconductor opening regions and the opening regions W0 are arranged alternately; S6, texturing and cleaning, forming a texture surface on the front side of the silicon wafer and the second semiconductor opening area, and removing the alkali-resistant mask layer, the plasma-resistant mask layer, and the phosphorus-doped and oxygen-doped polycrystalline layer; S9. Depositing a second semiconductor layer on the back side.

2. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, characterized in that: In S2, the plasma-resistant mask layer is at least one of silicon oxide, silicon oxynitride, and oxygen-containing polysilicon; and / or the thickness of the plasma-resistant mask layer is 10-40 nm.

3. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, characterized in that: In S2, the thickness of the first tunnel oxide layer is 1-2 nm, the thickness of the N-type doped amorphous silicon layer is 80-150 nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 ; and / or, In S3, the thickness of the N-type doped polysilicon layer formed is 80-150nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 ; The crystallinity of the N-type doped polysilicon layer is 70%-85%.

4. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, wherein: In S3, the width of the opening region W0 is 100-200 μm; and / or, In S3, the thickness of the phosphorus-doped and oxygen-doped polycrystalline layer is 0.5-10 nm.

5. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, characterized in that: In S3 , the annealing conditions include: introducing one selected from nitrogen, argon or a nitrogen-argon mixture, a temperature of 800-1000° C., an annealing pressure of 100-900 mbar, and an annealing time of 30-90 min.

6. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, characterized in that: In S4, the phosphorus doping concentration of the highly conductive polycrystalline region is 1×10 19 cm -3 -6×10 20 cm -3 , the crystallinity is 77%-98%, the thickness of the highly conductive polycrystalline region is 0.5-10nm, and the width of the highly conductive polycrystalline region is 100-200µm; and / or, In S4, the alkali-resistant mask layer is selected from at least one of silicon nitride, silicon oxynitride, silicon oxide, and carbon-doped silicon nitride.

7. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1 or 6, characterized in that: In S4, the conditions for the phosphine plasma treatment include: The hydrogen-carrying phosphine mixed gas, hydrogen and protective gas are introduced, the volume flow ratio of the hydrogen-carrying phosphine mixed gas, hydrogen and protective gas is 1: (0.5-10): (0.5-10), the treatment temperature is 400-600 ° C, and the treatment time is 30-300 s; and / or, The flow rate of the hydrogen-phosphine mixture is 500-3000 sccm, the flow rate of phosphine in the hydrogen-phosphine mixture is 2%-8%, the flow rate of hydrogen is 1000-10000 sccm, the flow rate of the protective gas is 1000-10000 sccm, the gas pressure is 1500-4000 mtorr, and the power is 5000-15000 kW.

8. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, wherein: In S9, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer or a stack of a second tunneling oxide layer and a P-type doped polysilicon layer, and the P-type doped silicon layer is P-type doped amorphous silicon or microcrystalline silicon.

9. The method for preparing a back-contact battery with a locally highly conductive polycrystalline structure according to claim 1, characterized in that: The preparation method further includes: after S6, performing S7, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S8, removing the back side coating layer and cleaning the second semiconductor opening area; and then performing S9; And / or, the preparation method further comprises: S10, performing a third etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a first semiconductor opening region spaced apart from the second semiconductor opening region; S11, depositing a conductive film layer on the back surface obtained in S10; S12, performing a fourth etching opening on a portion of the conductive film layer located between the first semiconductor opening region and the second semiconductor opening region to form an insulating trench; S13 , forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening region and the second semiconductor opening region are located.

10. A back contact battery with a locally highly conductive polycrystalline structure, characterized in that: The battery is prepared by the method for preparing a back-contact battery with a local high-conductivity polycrystalline structure as claimed in any one of claims 1 to 9.

11. A back-contact battery with a locally highly conductive polycrystalline structure, comprising a silicon wafer, and a first semiconductor layer and a second semiconductor layer alternately arranged on the back side of the silicon wafer, wherein both ends of the second semiconductor layer extend outward to cover a portion of the back side of the adjacent first semiconductor layer, and a first semiconductor opening region that does not cover the second semiconductor layer is provided on the back side of the first semiconductor layer, and a conductive film layer and a metal electrode are sequentially provided outside the first and second semiconductor layers, and an insulating groove is provided on the conductive film layer; characterized in that: The first semiconductor layer includes a first tunneling oxide layer, an N-type doped polysilicon layer, and a high-conductivity polycrystalline region sequentially arranged on the back side of the silicon wafer. The high-conductivity polycrystalline region is arranged outside the area of ​​the N-type doped polysilicon layer corresponding to the corresponding metal electrode and is located between the N-type doped polysilicon layer and the conductive film layer; wherein the phosphorus doping concentration of the high-conductivity polycrystalline region is 1.4-10 times the phosphorus doping concentration of the N-type doped polysilicon layer, and the crystallinity of the high-conductivity polycrystalline region is 1.1-1.3 times the crystallinity of the N-type doped polysilicon layer.

12. The back contact battery with a locally highly conductive polycrystalline structure according to claim 11, characterized in that: The back contact cell further includes at least one of the following structures: Structure 1: The width of the highly conductive polycrystalline region is 100-200µm, and the thickness of the highly conductive polycrystalline region is 0.5-10nm; Structure 2: The thickness of the N-type doped polysilicon layer is 75-140nm, and the phosphorus doping concentration is 5×10 18 cm -3 -9.9×10 19 cm -3 ; The crystallinity of the N-type doped polysilicon layer is 70%-85%; Structure 3: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped silicon layer, or a stack of a second tunneling oxide layer and a P-type doped polycrystalline silicon layer, and the P-type doped silicon layer is P-type doped amorphous silicon or microcrystalline silicon; Structure 4: A second semiconductor opening region is formed between adjacent first semiconductor layers, the second semiconductor opening region and the first semiconductor opening region are spaced apart, and the area between them is a spacer region; an insulating trench is provided in the spacer region, and the metal electrodes are provided on outer surfaces of the conductive film layers corresponding to the second semiconductor opening region and the first semiconductor opening region; The portion of the silicon wafer located at the second semiconductor opening region is a textured surface, and the portion of the silicon wafer at a position corresponding to the first semiconductor layer is a polished surface; Structure 5. The back contact cell also includes a passivation layer and an anti-reflection layer sequentially arranged on the front side of the silicon wafer, and the front side of the silicon wafer is a textured surface.

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