Display device, display panel and vehicle

Abstract

The invention discloses a display device, a display panel and a vehicle. A display device according to an exemplary embodiment of the present disclosure may include: a substrate including an active area including a plurality of sub-pixels and a non-active area outside the active area; a plurality of data lines connected to the plurality of sub-pixels; a plurality of data link lines electrically connected to the plurality of data lines in the active area; a plurality of power lines disposed in the active area and disposed in the same metal layer as at least one of the plurality of data lines; and a power supply pattern disposed in the non-active area and electrically connected to at least one of the plurality of power supply lines.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to a display device, and more particularly, to a display device having, for example but not limited to, a data link structure capable of reducing a bezel. Background Art

[0002] A display device may include an active area that displays an image and an inactive area that does not. Various structures, circuits, and wiring may be disposed within the inactive area of ​​the display device. Therefore, reducing the bezel of the display panel is not easy. In particular, since the link lines used to transmit data signals to the data lines are disposed within the inactive area of ​​the display panel, reducing the bezel is not easy.

[0003] The description provided in the discussion of related art section should not be assumed to be prior art simply because it is mentioned in or related to that section. The discussion of related art section may include information describing one or more aspects of the subject technology, and the descriptions in this section do not limit the present invention. Summary of the Invention

[0004] Exemplary embodiments of the present disclosure may provide a display device having a data link structure capable of reducing a bezel.

[0005] Exemplary embodiments of the present disclosure may provide a display device having a power line structure capable of stably transmitting a power voltage.

[0006] A display device according to an exemplary embodiment of the present disclosure may include: a substrate, the substrate including an active area including a plurality of sub-pixels and an inactive area outside the active area; a plurality of data lines, the plurality of data lines being connected to the plurality of sub-pixels; a plurality of data link lines, the plurality of data link lines being electrically connected to the plurality of data lines in the active area; a plurality of power lines, the plurality of power lines being arranged in the active area and being arranged in the same metal layer as at least one of the plurality of data lines; and a power pattern, the power pattern being arranged in the inactive area and electrically connected to at least one of the plurality of power lines.

[0007] According to an exemplary embodiment of the present disclosure, a display device may include: a substrate, the substrate including an active area for displaying an image and an inactive area outside the active area; a plurality of data link lines, the plurality of data link lines being electrically connected to a plurality of data lines and being arranged in the active area; a plurality of pixel electrodes, the plurality of pixel electrodes being arranged in the active area; a common electrode, the common electrode overlapping with the plurality of pixel electrodes; and a plurality of power lines, the plurality of power lines being arranged in a grid form in the active area and being arranged in the same metal layer as the plurality of data link lines and being electrically connected to the common electrodes or receiving a power supply voltage applied to the common electrodes.

[0008] According to an exemplary embodiment of the present disclosure, a display device may include: a substrate, the substrate including an active area including a plurality of sub-pixels and an inactive area outside the active area; a plurality of data lines, the plurality of data lines being connected to the plurality of sub-pixels; a plurality of data link lines, the plurality of data link lines electrically connecting a plurality of pads in the inactive area and the plurality of data lines in the active area, wherein the plurality of data link lines include a plurality of first data link lines each extending along a first direction in the active area and a plurality of second data link lines each extending along a second direction different from the first direction in the active area, and wherein the plurality of second data link lines electrically connects the plurality of pads and the plurality of first data link lines, and the plurality of first data link lines electrically connect the plurality of second data link lines and the plurality of data lines.

[0009] A vehicle according to various embodiments of the present disclosure may include at least one display device.

[0010] According to various embodiments of the present disclosure, the display panel may include: a plurality of data lines, which are arranged in the active area; a plurality of solder pads, which are arranged in the non-active area; and a plurality of data link lines, which are arranged in the active area and the non-active area and are configured to electrically connect the plurality of solder pads and the plurality of data lines, wherein the plurality of data link lines include a plurality of first data link lines each extending along a first direction in the active area and a plurality of second data link lines each extending along a second direction different from the first direction in the active area, and wherein the plurality of second data link lines electrically connect the plurality of solder pads and the plurality of first data link lines, and the plurality of first data link lines electrically connect the plurality of second data link lines and the plurality of data lines.

[0011] Technical Effects

[0012] According to exemplary embodiments of the present disclosure, a display device having a data link structure capable of reducing a bezel may be provided.

[0013] According to exemplary embodiments of the present disclosure, a display device having a power line structure capable of stably transmitting a power voltage may be provided.

[0014] According to exemplary embodiments of the present disclosure, a display device having a power line structure suitable for a data link structure capable of reducing a bezel may be provided.

[0015] According to exemplary embodiments of the present disclosure, a display device having a power line structure capable of distributively supplying a power voltage may be provided.

[0016] According to exemplary embodiments of the present disclosure, a display device capable of alleviating or preventing heat concentration due to a power supply voltage may be provided.

[0017] According to exemplary embodiments of the present disclosure, a display device having a power line structure capable of reducing an undesirable voltage drop of a power voltage may be provided.

[0018] According to the exemplary embodiments of the present disclosure, the weight of the display device may be reduced by reducing the bezel through the data link structure capable of reducing the bezel.

[0019] According to exemplary embodiments of the present disclosure, the need to increase the power supply voltage to be input to the display panel in consideration of the voltage drop can be eliminated by reducing the voltage drop of the power supply voltage, thereby ensuring additional voltage usage margin and achieving low power consumption design.

[0020] The objects according to the present disclosure are not limited to the above-mentioned objects. Other objects and advantages according to the present disclosure that are not mentioned can be understood based on the following description and can be more clearly understood based on the embodiments according to the present disclosure. In addition, it will be easily understood that the objects and advantages according to the present disclosure can be achieved using the devices shown in the claims or their combinations.

[0021] It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other objects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a diagram showing a system configuration of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 2is a diagram illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0025] Figure 3 is a cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0026] Figure 4 shows a substrate of a display panel according to an exemplary embodiment of the present disclosure;

[0027] Figure 5 is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0028] Figure 6 is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0029] Figure 7 shows three areas included in the active area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0030] Figure 8 is a plan view showing a display panel according to an exemplary embodiment of the present disclosure;

[0031] Figure 9 and Figure 10 is a cross-sectional view illustrating a display panel according to an exemplary embodiment of the present disclosure;

[0032] Figure 11 is a plan view illustrating an active area of ​​a display panel having a power line structure associated with a data link structure according to an exemplary embodiment of the present disclosure;

[0033] Figure 12 shows a power line structure of a display panel according to an exemplary embodiment of the present disclosure;

[0034] Figure 13 shows a first area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0035] Figure 14 shows a second area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0036] Figure 15 shows a third area of ​​a display panel according to an exemplary embodiment of the present disclosure;

[0037] Figure 16 shows a boundary area between the second area and the third area of ​​the display panel according to an exemplary embodiment of the present disclosure;

[0038] Figure 17is a plan view illustrating a non-corner area in a display panel according to an exemplary embodiment of the present disclosure;

[0039] Figure 18 is a plan view illustrating a corner area in a display panel according to an exemplary embodiment of the present disclosure;

[0040] Figure 19 It is along Figure 17 A cross-sectional view taken along line X1-X1' in FIG.

[0041] Figure 20 It is along Figure 17 A cross-sectional view taken along line X2-X2'.

[0042] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and descriptions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0043] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The progression of processing steps and / or operations described are examples; however, the order of the steps and / or operations is not limited to that set forth herein and may be varied as is known in the art, except that steps and / or operations must occur in a specific order. The names of the various elements used in the following description may have been selected solely for ease of writing the specification and, therefore, may differ from those used in an actual product.

[0044] Hereinafter, exemplary embodiments of the present disclosure are described in detail with reference to the accompanying drawings. When assigning reference numerals to the components of each drawing, the same components may be assigned the same numerals even if the same components are shown on different drawings. When it is determined that the subject matter of the present disclosure is unclear, the details of known technologies or functions may be skipped. As used herein, when a component "includes," "has," or "consists of" another component, the component may be added with other components unless the component "only" includes, has, or consists of other components. As used herein, unless otherwise expressly indicated herein, the singular forms "a" and "an" are also intended to include the plural forms.

[0045] References such as "first," "second," "A," "B," "(A)," and "(B)" may be used to describe components of the present disclosure. These references are provided solely to distinguish one component from another, and the nature, order, or number of the components is not limited by the references. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element without departing from the scope of the present disclosure.

[0046] When describing the positional relationship between components, when two or more components are described as being “connected,” “coupled,” or “linked,” the two or more components may be directly “connected,” “coupled,” or “linked,” or another component may intervene. Here, the other component may be included in one or more of the two or more components that are “connected,” “coupled,” or “linked” to each other.

[0047] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of a first element, a second element, and a third element" may include all combinations of two or more elements selected from the first element, the second element, and the third element, as well as each individual element of the first element, the second element, and the third element.

[0048] When terms such as “after,” “next,” “subsequently,” and “before” are used to describe a time flow relationship associated with components, operating methods, and manufacturing methods, they may include non-sequential relationships unless the terms “immediately” or “directly” are used.

[0049] When a component is specified with a value or its corresponding information (eg, level), the value or corresponding information may be interpreted as including tolerances that may occur due to various factors (eg, process factors, internal or external influences, or noise).

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, for example, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "part" or "unit" may apply to, for example, a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function as would be understood by one of ordinary skill in the art.

[0051] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0052] Figure 1 is a diagram illustrating a system configuration of a display apparatus 100 according to an exemplary embodiment of the present disclosure.

[0053] Reference Figure 1The display device 100 according to an exemplary embodiment of the present disclosure may include a display panel 110 and a display driving circuit as components for displaying an image. The display driving circuit may be a circuit for driving the display panel 110. The display driving circuit may include a data driving circuit 120, a gate driving circuit 130, and a controller 140, but the exemplary embodiment of the present disclosure is not limited thereto.

[0054] The display panel 110 may include a substrate 111 and a plurality of sub-pixels SP disposed on the substrate 111 .

[0055] The substrate 111 may include an active area AA capable of displaying an image and a non-active area NA located around or outside the active area AA.

[0056] The active area AA may also be referred to as a display area, and a plurality of sub-pixels SP for displaying an image may be disposed in the active area AA. The non-active area NA may also be referred to as a non-display area, and may include a pad area PA located at least one side of the active area AA in a column direction.

[0057] In the display panel 110 according to an exemplary embodiment of the present disclosure, the non-active area NA can be very small. In the present disclosure, the non-active area NA is also referred to as a "border" or "edge" area. For example, the non-active area NA may include a first non-active area located outside the active area AA in the column direction, a second non-active area located outside the active area AA in the row direction, a third non-active area located outside the active area AA in the column direction and opposite to the first non-active area, and a fourth non-active area located outside the active area AA in the row direction and opposite to the second non-active area. The first non-active area among the first to fourth non-active areas may include a pad area connected or bonded to a data driving circuit. Among the first to fourth non-active areas, the second to fourth non-active areas excluding the pad area may have a very small size, but the exemplary embodiments of the present disclosure are not limited thereto.

[0058] As another example, the boundary area between the active area AA and the non-active area NA may be bent so that the non-active area NA may be positioned below the active area AA. In this case, when the user observes the display device 100 from the front, no or little non-active area NA is visible to the user, but exemplary embodiments of the present disclosure are not limited thereto.

[0059] Various types of signal lines for driving the plurality of sub-pixels SP may be provided on the substrate 111 of the display panel 110. In addition, the display panel 110 includes one or more optical areas.

[0060] The display device 100 according to the exemplary embodiment of the present disclosure may be a liquid crystal display device (LCD), a plasma display device (PDP), a field emission display device (FED), or the like, or a self-luminous display device in which the display panel 110 emits light by itself, such as an organic light emitting diode (OLED) and a micro LED (micro light emitting diode) display device, but the exemplary embodiment of the present disclosure is not limited thereto. When the display device 100 according to the exemplary embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP may include a light emitting element.

[0061] For example, the display device 100 according to the exemplary embodiment of the present disclosure may be an organic light-emitting diode display in which the light-emitting elements are implemented as organic light-emitting diodes (OLEDs). As another example, the display device 100 according to the exemplary embodiment of the present disclosure may be an inorganic light-emitting display device in which the light-emitting elements are implemented as light-emitting diodes based on inorganic materials. As another example, the display device 100 according to the exemplary embodiment of the present disclosure may be a quantum dot display device in which the light-emitting elements are implemented as quantum dots, which are self-luminous semiconductor crystals. As another example, the display device 100 according to the exemplary embodiment of the present disclosure may be a micro-LED display device or a mini-LED display device.

[0062] Each of the plurality of sub-pixels SP is the smallest unit configuring the display area, and n sub-pixels SP form a pixel. Each of the plurality of sub-pixels SP can emit light having a different wavelength from one another. The plurality of sub-pixels can include first to third sub-pixels that emit light of different colors from one another. Each pixel P can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel for color display. Each pixel P can also include a white sub-pixel. The plurality of sub-pixels SP can be modified in various ways in terms of color and configuration as needed. However, the present disclosure is not limited thereto.

[0063] For example, the plurality of sub-pixels SP may include red, green, and blue sub-pixels, wherein the red, green, and blue sub-pixels may be arranged in a repeated manner. Alternatively, the plurality of sub-pixels SP may include red, green, blue, and white sub-pixels, wherein the red, green, blue, and white sub-pixels may be arranged in a repeated manner, or the red, green, blue, and white sub-pixels may be arranged in a square shape. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be arranged in sequence along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be arranged in sequence along the row direction. However, in an embodiment of the present disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not restrictive and may be configured in various forms according to the luminous characteristics, device life, and device specifications.

[0064] At the same time, sub-pixels can have different light-emitting areas depending on their light-emitting characteristics. For example, a sub-pixel that emits light of a different color than a blue sub-pixel can have a different light-emitting area than the blue sub-pixel. For example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel, or a red sub-pixel, a blue sub-pixel, a white sub-pixel, and a green sub-pixel can all have different light-emitting areas.

[0065] The structure of each of the plurality of sub-pixels SP may vary depending on the type of the display device 100. For example, when the display device 100 is a self-luminous display device in which the sub-pixels SP emit light by themselves, each sub-pixel SP may include a self-luminous light-emitting element, one or more transistors, and one or more capacitors, but embodiments of the present disclosure are not limited thereto.

[0066] For example, the various types of signal lines may include a plurality of data lines DL for transmitting data signals (also referred to as data voltages or image signals) and a plurality of gate lines GL for transmitting gate signals (also referred to as scan signals).

[0067] A plurality of data lines DL and a plurality of gate lines GL may cross each other. Each of the plurality of data lines DL may be arranged to extend in a column direction. Each of the plurality of gate lines GL may be arranged to extend in a row direction. According to an exemplary embodiment of the present disclosure, the column direction and the row direction may be opposite directions. For example, depending on the viewpoint, the column direction may be the row direction, and depending on the viewpoint, the row direction may also be the column direction. For ease of description, an example is described below in which each of the plurality of data lines DL is arranged in a column direction and each of the plurality of gate lines GL is arranged in a row direction, but the embodiments of the present disclosure are not limited thereto. In an embodiment of the present disclosure, the angle between the row direction and the column direction may be 90 degrees or an angle different from 90 degrees. In addition, in an exemplary embodiment of the present disclosure, the row direction may be referred to as a first direction and the column direction may be referred to as a second direction. Alternatively, the column direction may be referred to as a first direction and the row direction may be referred to as a second direction.

[0068] The data driving circuit 120 may be a circuit for driving a plurality of data lines DL. The data driving circuit 120 may output data signals to the plurality of data lines DL. The gate driving circuit 130 may be a circuit for driving a plurality of gate lines GL and may supply gate signals to the plurality of gate lines GL.

[0069] The data driving circuit 120 may receive digital image data DATA from the controller 140 and may convert the received digital image data DATA into analog data signals and output them to the plurality of data lines DL.

[0070] For example, the data driving circuit 120 may be connected to the display panel 110 through a tape automated bonding (TAB) method, or connected to a conductive pad such as a bonding pad of the display panel 110 through a chip on glass (COG) or chip on panel (COP) method, or may be implemented through a chip on film (COF) method and connected to the display panel 110, but the embodiments of the present disclosure are not limited thereto.

[0071] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. Alternatively, depending on a driving scheme or panel design scheme, the data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or to two or more of the four sides (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110.

[0072] The data driving circuit 120 may be connected outside the active area AA of the display panel 110 , but as another example, the data driving circuit 120 may be disposed within the active area AA of the display panel 110 .

[0073] The gate driving circuit 130 is a circuit for driving the plurality of gate lines GL and may output gate signals to the plurality of gate lines GL.

[0074] The gate driving circuit 130 may receive a first gate voltage corresponding to an on-level voltage and a second gate voltage corresponding to an off-level voltage and various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to a plurality of gate lines GL.

[0075] In the display device 100 according to an exemplary embodiment of the present disclosure, the gate driving circuit 130 may be embedded in the display panel 110 in a gate-in-panel (GIP) type. When the gate driving circuit 130 is a gate-in-panel type, the gate driving circuit 130 may be formed on the substrate 111 of the display panel 110 during the manufacturing process of the display panel 110.

[0076] For example, the gate driving circuit 130 may be disposed in the non-active area NA of the display panel 110 .

[0077] As another example, the gate driving circuit 130 may be disposed in the active area AA of the display panel 110. In this case, for example, the gate driving circuit 130 may be disposed in a first partial area (e.g., a left area or a right area) in the active area AA. As another example, the gate driving circuit 130 may be disposed in a first partial area (e.g., a left area or a right area) and a second partial area (e.g., a right area or a left area) in the active area AA.

[0078] In the present disclosure, the gate driving circuit 130 embedded in the display panel 110 in an in-panel gate type may also be referred to as an “in-panel gate circuit.” The gate driving circuit 130 may be disposed on or connected to the substrate 111 .

[0079] The controller 140 is a device for controlling the data driving circuit 120 and the gate driving circuit 130 and may control driving timings of the plurality of data lines DL and driving timings of the plurality of gate lines GL.

[0080] The controller 140 may supply a data driving control signal DCS to the data driving circuit 120 to control the data driving circuit 120 , and may supply a gate driving control signal GCS to the gate driving circuit 130 to control the gate driving circuit 130 .

[0081] The controller 140 may receive input image data from the host system 150 and supply image data DATA to the data driving circuit 120 based on the input image data.

[0082] The controller 140 may be implemented as a separate component from the data driving circuit 120, or the controller 140 and the data driving circuit 120 may be integrated into an integrated circuit (IC). However, the present disclosure is not limited thereto.

[0083] The controller 140 may be a timing controller for display technology, a controller or control device that can perform other control functions as well as the functions of the timing controller, or a control device other than the timing controller, or may be a circuit or component included in the controller or control device. The controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor, but is not limited thereto.

[0084] The controller 140 may be mounted on a printed circuit board or a flexible printed circuit, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board or the flexible printed circuit, or the like.

[0085] The controller 140 may send a signal to the data driver circuit 120 or receive a signal from the data driver circuit 120 according to one or more predetermined interfaces. The interface may include, for example, a low voltage differential signaling (LVDS) interface, an embedded clock point-to-point interface (EPI), and a serial peripheral interface (SPI), but the embodiments of the present disclosure are not limited thereto. Similarly, the controller 140 may send a signal to the gate driver circuit 130 or receive a signal from the gate driver circuit 130 via one or more predetermined interfaces.

[0086] In order to provide a touch sensing function as well as an image display function, the display device 100 according to an exemplary embodiment of the present disclosure may include a touch sensor and a touch sensing circuit that can sense the touch sensor to detect whether a touch occurs through a touch object (such as a finger or a pen) or the position of the touch. The touch sensor may be a touch unit.

[0087] The touch sensing circuit may include, but is not limited to, a touch driving circuit that drives and senses the touch sensor and generates and outputs touch sensing data, and a touch controller that can detect the occurrence of a touch or the position of a touch using the touch sensing data.

[0088] The touch sensor may include a plurality of touch electrodes and a plurality of touch lines for electrically connecting the plurality of touch electrodes and a touch driving circuit.

[0089] The touch sensor may be located outside the display panel 110 in the form of a touch panel, or may be located inside the display panel 110. When the touch panel is located outside the display panel 110 in the form of a touch panel, the touch panel is an external type. When the touch sensor is an external type, the touch panel and the display panel 110 may be manufactured separately or may be combined during the assembly process. An external type touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.

[0090] When the touch sensor exists inside the display panel 110 , the touch sensor may be formed on a substrate together with signal lines and electrodes related to display driving during a manufacturing process of the display panel 110 .

[0091] The touch driving circuit may supply a touch driving signal to at least one of the plurality of touch electrodes and may sense at least one of the plurality of touch electrodes to generate touch sensing data.

[0092] The touch sensing circuit may perform touch sensing in a self-capacitance sensing scheme or a mutual-capacitance sensing scheme, without being limited thereto.

[0093] When the touch sensing circuit performs touch sensing in a self-capacitance sensing scheme, the touch sensing circuit can perform touch sensing based on the capacitance between each touch electrode and a touch object (e.g., a finger or pen). According to the self-capacitance sensing scheme, each of the multiple touch electrodes can function as both a driving touch electrode and a sensing touch electrode. The touch drive circuit can drive all or part of the multiple touch electrodes and can sense all or part of the multiple touch electrodes.

[0094] When the touch sensing circuit performs touch sensing in a mutual capacitance sensing scheme, the touch sensing circuit can perform touch sensing based on the capacitance between touch electrodes. In a mutual capacitance sensing scheme, multiple touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch drive circuit can drive the driving touch electrodes and sense the sensing touch electrodes.

[0095] The touch driving circuit and the touch controller included in the touch sensing circuit may be implemented as separate devices or a single device, without being limited thereto. The touch driving circuit and the data driving circuit may be implemented as separate devices or a single device, without being limited thereto.

[0096] The display device 100 may further include a power supply circuit for supplying various types of power to the display driver integrated circuit and / or the touch sensing circuit. The power supply circuit may provide various voltages related to display driving and a power supply voltage to the display driver circuit or the display panel 110.

[0097] The display device 100 according to an exemplary embodiment of the present disclosure may be a mobile terminal such as a laptop computer, a smart phone, or a tablet computer, or a monitor or television (TV) of various sizes, but is not limited thereto and may be a display of various types and sizes capable of displaying information or images.

[0098] The display device 100 according to an exemplary embodiment of the present disclosure may further include electronic devices such as a camera (image sensor), a detection sensor, etc. For example, the detection sensor may be a sensor that detects an object or a human body by receiving light such as infrared rays, ultrasonic waves, or ultraviolet rays.

[0099] Figure 2 A display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0100] Reference Figure 2 The display panel 110 may include a substrate 111 provided with a plurality of sub-pixels SP and an encapsulation layer 200 on the substrate 111. The encapsulation layer 200 may also be referred to as an encapsulation substrate or an encapsulation portion.

[0101] Reference Figure 2 When the display device 100 according to the exemplary embodiment of the present disclosure is a self-luminous display device, each of the plurality of sub-pixels SP provided on the substrate 111 may include a light emitting element ED and a sub-pixel circuit SPC for driving the light emitting element ED.

[0102] Reference Figure 2The sub-pixel circuit SPC may include a plurality of transistors and at least one capacitor for driving the light-emitting element ED, but the embodiments of the present disclosure are not limited thereto. In the present disclosure, the sub-pixel circuit SPC may drive the light-emitting element ED by supplying a driving current to the light-emitting element ED at a predetermined timing. The light-emitting element ED may be driven by the driving current to emit light.

[0103] The plurality of transistors may include a driving transistor DT for driving the light emitting element ED and a scan transistor ST that is turned on or off according to a scan signal SC.

[0104] The driving transistor DT may provide a driving current to the light emitting element ED.

[0105] The scan transistor ST may be configured to control an electrical state of a corresponding node in the sub-pixel circuit SPC or to control a state or operation of the drive transistor DT.

[0106] The at least one capacitor may include a storage capacitor Cst for maintaining a constant voltage during one frame. The storage capacitor Cst may be disposed between a first node N1 and a second node N2 of the driving transistor DT.

[0107] To drive the subpixel SP, a data signal VDATA as an image signal and a scan signal SC as a gate signal may be applied to the subpixel SP. In addition, to drive the subpixel SP, a common pixel driving voltage including a first common driving voltage VDD and a second common driving voltage VSS may be applied to the subpixel SP.

[0108] The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE.

[0109] For example, the pixel electrode PE may be an electrode provided in each sub-pixel SP, and the common electrode CE may be an electrode commonly provided in all sub-pixels SP. For example, the pixel electrode PE may be an anode, and the common electrode CE may be a cathode, but embodiments of the present disclosure are not limited thereto. As another example, the pixel electrode PE may be a cathode, and the common electrode CE may be an anode. For ease of description, an example is described in which the pixel electrode PE is an anode and the common electrode CE is a cathode.

[0110] When the light-emitting element ED is an organic light-emitting element, the intermediate layer EL may include a light-emitting layer EML, a first common intermediate layer COM1 located between the pixel electrode PE and the light-emitting layer EML, and a second common intermediate layer COM2 located between the light-emitting layer EML and the common electrode CE. The first common intermediate layer COM1 and the second common intermediate layer COM2 may be collectively referred to as a common intermediate layer EL_COM.

[0111] A light emitting layer EML may be provided for each sub-pixel SP, and a common intermediate layer EL_COM may be provided over the plurality of sub-pixels SP.

[0112] A light emitting layer EML may be provided for each light emitting region, and a common intermediate layer EL_COM may be provided across a plurality of light emitting regions and non-light emitting regions.

[0113] For example, the first common intermediate layer COM1 may include a hole injection layer HIL and a hole transport layer HTL, but the embodiments of the present disclosure are not limited thereto. The second common intermediate layer COM2 may include an electron transport layer ETL and an electron injection layer EIL.

[0114] The hole injection layer can inject holes from the pixel electrode PE into the hole transport layer, and the hole transport layer can transport holes to the emission layer EML. The electron injection layer can inject electrons from the common electrode CE into the electron transport layer, and the electron transport layer can transport electrons to the emission layer EML.

[0115] For example, the common electrode CE may be electrically connected to a second common drive voltage line VSSL. The second common drive voltage VSS is a type of common pixel drive voltage that may be applied to the common electrode CE via the second common drive voltage line VSSL. The pixel electrode PE may be electrically connected directly or indirectly (via another transistor) to the first node N1 of the drive transistor DT of each sub-pixel SP. In the present disclosure, the "second common drive voltage VSS" may also be referred to as a "base voltage," and the "second common drive voltage line VSSL" may also be referred to as a "low potential power supply voltage line" or a "base voltage line."

[0116] Each light-emitting element ED may include a portion where the pixel electrode PE, the light-emitting layer in the intermediate layer LE, and the common electrode CE overlap. Each light-emitting element ED may form a predetermined light-emitting region. For example, the light-emitting region of each light-emitting element ED may include an overlapping region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0117] For example, the light emitting element ED may be an organic light emitting diode (OLED), an inorganic light emitting diode (LED), or a quantum dot light emitting element. For example, when the light emitting element ED is an organic light emitting diode (OLED), the intermediate layer EL in the light emitting element ED may include an intermediate layer EL containing an organic material.

[0118] The driving transistor DT may be a driving transistor for providing a driving current to the light emitting element ED. The driving transistor DT may be connected between the first common driving voltage line VDDL and the light emitting element ED.

[0119] The driving transistor DT may include a first node N1, a second node N2, and a third node N3. The first node N1 may be electrically connected to the light-emitting element ED, the second node N2 may receive a data signal VDATA, and the third node N3 may receive a first common driving voltage VDD from a first common driving voltage line VDDL. The driving transistor DT may be connected between the first node N1 and the third node N3.

[0120] In the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node or a drain node, and the third node N3 may be a drain node or a source node. Hereinafter, for ease of description, an example is described in which, in the driving transistor DT, the second node N2 may be a gate node, the first node N1 may be a source node, and the third node N3 may be a drain node, but embodiments of the present disclosure are not limited thereto.

[0121] Figure 2 The scan transistor ST shown included in the sub-pixel circuit SPC may be a switching transistor for transmitting the data signal VDATA, which is an image signal, to the second node N2, which is a gate node of the driving transistor DT.

[0122] The scan transistor ST included in the sub-pixel circuit SPC may be disposed between the data line DL and a second node N2 that is a gate node of the driving transistor DT. The scan transistor ST may be turned on or off in response to a scan signal SC applied through the scan line SCL.

[0123] For example, the scan transistor ST can be controlled to be turned on and off by a scan signal SC, which is a gate signal applied through a scan line SCL as a type of gate line GL, to control the electrical connection between the second node N2 of the drive transistor DT and the data line DL. The drain electrode or source electrode of the scan transistor ST can be electrically connected to the data line DL, the source electrode or drain electrode of the scan transistor ST can be electrically connected to the second node N2 of the drive transistor DT, and the gate electrode of the scan transistor ST can be electrically connected to the scan line SCL.

[0124] The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT. The storage capacitor Cst may include a first capacitor electrode electrically connected to or corresponding to the first node N1 of the driving transistor DT, and a second capacitor electrode electrically connected to or corresponding to the second node N2 of the driving transistor DT.

[0125] The capacitor Cst may be an external capacitor intentionally designed to be outside the driving transistor DT, rather than a parasitic capacitor (eg, Cgs or Cgd) that is an internal capacitor that may exist between the first node N1 and the second node N2 of the driving transistor DT.

[0126] Each of the driving transistor DT and the scanning transistor ST may be an n-type transistor or a p-type transistor.

[0127] The display panel 110 may have a top emission structure or a bottom emission structure, or a double-sided emission structure.

[0128] When the display panel 110 has a top emission structure, at least a portion of the sub-pixel circuit SPC may vertically overlap at least a portion of the light emitting element ED. Therefore, the area of ​​the light emitting region may be increased, and the aperture ratio may be increased.

[0129] When the display panel 110 has a bottom emission structure, the sub-pixel circuit SPC may not overlap with the light emitting element ED in a vertical direction.

[0130] like Figure 2 As shown, the sub-pixel circuit SPC may have a 2T (transistor) 1C (capacitor) structure including two transistors DT and ST and one capacitor Cst. In some cases, the sub-pixel circuit SPC may further include one or more transistors or one or more capacitors, but the embodiments of the present disclosure are not limited thereto.

[0131] For example, the sub-pixel circuit SPC may have an 8T1C structure including eight transistors and one capacitor. As another example, the sub-pixel circuit SPC may have a 6T2C structure including six transistors and two capacitors. As another example, the sub-pixel circuit SPC may have a 7T1C structure including seven transistors and one capacitor. The exemplary embodiments of the present disclosure are not limited thereto. Alternatively, the sub-pixel circuit SPC may have a 3T1C, 4T1C, 5T1C, 3T2C, 4T2C, 5T2C, 7T2C, 8T2C structure, etc., and may include more or fewer transistors and capacitors.

[0132] The type and number of gate lines or gate signals supplied to the subpixels SP may vary depending on the structure of the subpixel circuit SPC. In addition, the type and number of common pixel driving voltages supplied to the subpixels SP may vary depending on the structure of the subpixel circuit SPC.

[0133] Since the circuit elements in each sub-pixel SP (for example, the light-emitting elements ED implemented as organic light-emitting diodes (OLEDs) including organic materials) are susceptible to external moisture or oxygen, an encapsulation layer 200 for preventing external moisture or oxygen from penetrating into the circuit elements (for example, the light-emitting elements ED) may be provided on the display panel 110. The encapsulation layer 200 may be configured in various forms so that the light-emitting elements ED are not exposed to moisture or oxygen. For example, the encapsulation layer 200 may be composed of two or more layers in which organic films and inorganic films are alternately stacked, but the embodiments of the present disclosure are not limited thereto. For example, the encapsulation layer 200 may have a structure in which at least one organic film is provided between inorganic films.

[0134] The inorganic film may include an inorganic insulating material. For example, the inorganic film may include an inorganic insulating material capable of low temperature deposition, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), and aluminum oxide (Al2O3), but is not limited thereto.

[0135] The organic film may include an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, and silicon oxycarbide (SiOC), but is not limited thereto.

[0136] Reference Figure 2 According to an exemplary embodiment of the present disclosure, a display device 100 may include: a touch sensor layer 210, which includes a plurality of sensor electrodes to sense a user's touch; a touch drive circuit 220, which is configured to sense the plurality of sensor electrodes; and a touch controller 230, which is configured to use the sensing result (touch sensing data) of the touch drive circuit 220 to determine whether there is a touch or touch coordinates.

[0137] The touch sensor layer 210 may be embedded in the display panel 110. For example, the touch sensor layer 210 may be provided on the encapsulation layer 200 in the display panel 110.

[0138] The display panel 110 may further include a plurality of touch pads TP electrically connected to the touch driving circuit 220 and a plurality of touch routing lines for electrically connecting the plurality of sensor electrodes included in the touch sensor layer 210 to the plurality of touch pads TP connected to the touch driving circuit 220 .

[0139] Figure 3 is a cross-sectional view of a display panel 110 according to an exemplary embodiment of the present disclosure.

[0140] Reference Figure 3The display panel 110 according to an exemplary embodiment of the present disclosure may include a transistor unit, a light emitting element unit, and a packaging unit. For example, from a vertical structure perspective, the display panel 110 may include a transistor unit, a light emitting element unit, and a packaging unit.

[0141] The substrate 111 may be a single layer or multiple layers. When the substrate 111 includes multiple layers, the substrate 111 may include a first substrate 301, an intermediate layer 302, and a second substrate 303, but the embodiments of the present disclosure are not limited thereto. The intermediate layer 302 may be positioned between the first substrate 301 and the second substrate 303. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer, but the embodiments of the present disclosure are not limited thereto. Alternatively, each of the first substrate 301 and the second substrate 303 may be a glass or plastic layer, but the embodiments of the present disclosure are not limited thereto. The intermediate layer 302 may be an inorganic insulating layer. When electric charge is charged to the first substrate 301 as a polyimide layer, the intermediate layer 302 may prevent the electric charge from affecting the transistors provided on the second substrate 303 through the second substrate 303 as a polyimide layer.

[0142] In addition, the intermediate layer 302 can prevent moisture components from penetrating upwardly through the first substrate 301. For example, the intermediate layer 302 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, or may be formed of a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx), but is not limited thereto.

[0143] The transistor unit may include a substrate 111 , various insulating layers 311 , 312 , 313 , 321 , 322 , and 323 on the substrate 111 , various transistors TFT1 and TFT2 , a storage capacitor Cst, and various electrodes or signal lines, but embodiments of the present disclosure are not limited thereto.

[0144] The transistors TFT1 and TFT2 included in the transistor unit may include a first transistor TFT1 and a second transistor TFT2 .

[0145] The first transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c. The first active layer ACT1 may be provided on the first buffer layer 311. The first active layer ACT1 may be a first semiconductor layer, but embodiments of the present disclosure are not limited thereto. For example, the first active layer ACT1 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but embodiments of the present disclosure are not limited thereto. The first transistor TFT1 may be implemented as a p-channel transistor or an n-channel thin film transistor, but embodiments of the present disclosure are not limited thereto.

[0146] The first electrode E1a may be a gate electrode, the second electrode E1b may be a source electrode or a drain electrode, and the third electrode E1c may be a drain electrode or a source electrode. Hereinafter, for ease of description, the first electrode E1a is referred to as a first gate electrode E1a, the second electrode E1b is referred to as a first source electrode E1b, and the third electrode E1c is referred to as a first drain electrode E1c. However, exemplary embodiments of the present disclosure are not limited thereto.

[0147] The second transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c. The second active layer ACT2 may be disposed on the second buffer layer 321. The second active layer ACT2 may be a second semiconductor layer, but embodiments of the present disclosure are not limited thereto. For example, the second active layer ACT2 may be formed of an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low-temperature polycrystalline silicon (LTPS), but embodiments of the present disclosure are not limited thereto. The second transistor TFT2 may be implemented as a p-channel transistor or an n-channel thin film transistor, but embodiments of the present disclosure are not limited thereto.

[0148] The fourth electrode E2a may be a gate electrode, the fifth electrode E2b may be a source electrode or a drain electrode, and the sixth electrode E2c may be a drain electrode or a source electrode. Hereinafter, for ease of description, the fourth electrode E2a is referred to as a second gate electrode E2a, the fifth electrode E2b is referred to as a second source electrode E2b, and the sixth electrode E2c is referred to as a second drain electrode E2c. However, embodiments of the present disclosure are not limited thereto.

[0149] For example, one of the first transistor TFT1 and the second transistor TFT2 may be configured with an oxide semiconductor as an active layer. As another example, one of the first transistor TFT1 and the second transistor TFT2 may use low-temperature polysilicon as an active layer. As another example, the first transistor TFT1 and the second transistor TFT2 may be configured with an oxide semiconductor as an active layer. As another example, the first transistor TFT1 and the second transistor TFT2 may be configured with low-temperature polysilicon as an active layer. As another example, among the first transistor TFT1 and the second transistor TFT2, the driving transistor DT may be configured with an oxide semiconductor as an active layer, and the scanning transistor ST may be configured with low-temperature polysilicon as an active layer. As another example, among the first transistor TFT1 and the second transistor TFT2, the driving transistor DT may be configured with low-temperature polysilicon as an active layer, and the scanning transistor ST may be configured with an oxide semiconductor as an active layer. As another example, the transistors included in the gate-in-panel (GIP) type gate driving circuit 130 may be configured with an oxide semiconductor or low-temperature polysilicon as an active layer. As another example, all transistors configured on the substrate 111 and transistors included in the gate driving circuit 130 of a gate-in-panel (GIP) type may configure an oxide semiconductor as an active layer.

[0150] The second active layer ACT2 of the second transistor TFT2 may be positioned higher from the substrate 111 than the first active layer ACT1 of the first transistor TFT1 .

[0151] The first buffer layer 311 may be disposed below the first active layer ACT1 of the first transistor TFT1, and the second buffer layer 321 may be disposed below the second active layer ACT2 of the second transistor TFT2. For example, the first active layer ACT1 of the first transistor TFT1 may be positioned on the first buffer layer 311, and the second active layer ACT2 of the second transistor TFT2 may be positioned on the second buffer layer 321. The second buffer layer 321 may be positioned higher than the first buffer layer 311. In other words, the second active layer ACT2 positioned on the second buffer layer 321 may be positioned higher from the substrate 111 than the first active layer ACT1 disposed on the first buffer layer 311.

[0152] The storage capacitor Cst may be provided in various metal layers in the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. For example, the second capacitor electrode CAPE2 may be provided above the first capacitor electrode CAPE1 with the first interlayer insulating layer 313 provided therebetween.

[0153] The light emitting element unit may include a plurality of light emitting elements ED disposed on at least one of the planarization layers 331 and 332. Each of the plurality of light emitting elements ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. The intermediate layer EL may be disposed between the pixel electrode PE and the common electrode CE, and the pixel electrode PE may be disposed on the second planarization layer 332.

[0154] The encapsulation unit may include an encapsulation layer 200 located on the plurality of light emitting elements ED. The encapsulation layer 200 may be a single layer or a plurality of layers. In addition to the encapsulation layer 200, the encapsulation portion may further include a dam portion DAM.

[0155] In the following, reference is made to Figure 3 The vertical structure of the display panel 110 according to an exemplary embodiment of the present disclosure is described in more detail.

[0156] Reference Figure 3 , a first buffer layer 311 may be provided on the substrate 111. The first buffer layer 311 may be a single layer or a plurality of layers. When the first buffer layer 311 includes a plurality of layers, the first buffer layer 311 may include a lower buffer layer 311a and an upper buffer layer 311b provided on the lower buffer layer 311a.

[0157] The first active layer ACT1 of the first transistor TFT1 may be disposed on the first buffer layer 311. For example, the first active layer ACT1 of the first transistor TFT1 may be disposed on the upper buffer layer 311b. The first active layer ACT1 may include a channel region in which a channel is formed, a source connection region located on one side of the channel region, and a drain connection region located on the other side of the channel region.

[0158] A first gate insulating layer 312 may be provided on the first active layer ACT1 of the first transistor TFT1. A first gate electrode E1a of the first transistor TFT1 may be provided on the first gate insulating layer 312. A first interlayer insulating layer 313 may be provided on the first gate electrode E1a of the first transistor TFT1. For example, the first interlayer insulating layer 313 may be provided on the first gate electrode E1a of the first transistor TFT1 and on a portion of the first gate insulating layer 312.

[0159] The second buffer layer 321 may be disposed on the first interlayer insulating layer 313. In addition, the second buffer layer 321 may be disposed on the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0160] The second active layer ACT2 of the second transistor TFT2 may be disposed on the second buffer layer 321. The second active layer ACT2 may include a channel region in which a channel is formed, a source connection region on one side of the channel region, and a drain connection region on the other side of the channel region.

[0161] A second gate insulating layer 322 may be provided on the second active layer ACT2 of the second transistor TFT2. Specifically, the second gate insulating layer 322 may be provided on the second active layer ACT2 of the second transistor TFT2 and a portion of the second buffer layer 321. A second gate electrode E2a of the second transistor TFT2 may be provided. A second interlayer insulating layer 323 may be provided on the second gate electrode E2a of the second transistor TFT2.

[0162] The first source electrode E1 b and the first drain electrode E1 c of the first transistor TFT1 , and the second source electrode E2 b and the second drain electrode E2 c of the second transistor TFT2 may be disposed on the second interlayer insulating layer 323 .

[0163] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 may be respectively connected to the source connection region and the drain connection region of the first active layer ACT1 through holes of the second interlayer insulating layer 323 , the second gate insulating layer 322 , the second buffer layer 321 , the first interlayer insulating layer 313 , and the first gate insulating layer 312 .

[0164] The second source electrode E2 b and the second drain electrode E2 c of the second transistor TFT2 may be connected to the source connection region and the drain connection region of the second active layer ACT2 , respectively, through holes of the second interlayer insulating layer 323 and the second gate insulating layer 322 .

[0165] The first source electrode E1b and the first drain electrode E1c of the first transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2 may include a first metal and may be provided in a first metal layer. The first metal and the first metal layer may be referred to as a first source-drain metal and a first source-drain metal layer.

[0166] For example, refer to Figure 3 The storage capacitor Cst may be composed of a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst may be formed of three or more capacitor electrodes, or may have a form in which two or more capacitors are connected in parallel, but the embodiments of the present disclosure are not limited thereto.

[0167] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may be disposed on various metal layers provided in the display panel 110 .

[0168] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate electrode E1a of the first transistor TFT1 on the first gate insulating layer 312 and may be provided in the first gate metal layer, but embodiments of the present disclosure are not limited thereto.

[0169] For example, the second capacitor electrode CAPE2 may be disposed on the first interlayer insulating layer 313. The first interlayer insulating layer 313 may be disposed between the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2.

[0170] The second source electrode E2 b of the second transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 through the holes of the second interlayer insulating layer 323 , the second gate insulating layer 322 , and the second buffer layer 321 .

[0171] For example, the first transistor TFT1 may be Figure 2 The scanning transistor ST, the second transistor TFT2 can be Figure 2 The driving transistor DT is configured as follows, but the embodiments of the present disclosure are not limited thereto.

[0172] The transistor unit may further include various metal layers MP1 and MP2. For example, the first metal layer MP1 may be disposed between the lower buffer layer 311a and the upper buffer layer 311b included in the first buffer layer 311. The second metal layer MP2 may include the same first gate metal as the first gate electrode E1a of the first transistor TFT1 and may be disposed in the first gate metal layer. The first metal layer MP1 may be a first metal pattern, and the second metal layer MP2 may be a second metal pattern, but embodiments of the present disclosure are not limited thereto.

[0173] Each of the first metal layer MP1 and the second metal layer MP2 may be disposed in the active area AA or the non-active area NA.

[0174] Reference Figure 3 The transistor unit may further include a first shield metal BSM1 disposed on the substrate 111. The first shield metal BSM1 may overlap the first active layer ACT1 of the first transistor TFT1. The first shield metal BSM1 may be disposed below the first active layer ACT1 of the first transistor TFT1. For example, the first shield metal BSM1 may be disposed between the substrate 111 and the first buffer layer 311, or between the lower buffer layer 311a and the upper buffer layer 311b.

[0175] The transistor unit may further include a second shield metal BSM2 disposed on the substrate 111. The second shield metal BSM2 may overlap the second active layer ACT2 of the second transistor TFT2. The second shield metal BSM2 may be disposed below the second active layer ACT2 of the second transistor TFT2. For example, the second shield metal BSM2 may be disposed between the second buffer layer 321 and the first interlayer insulating layer 313.

[0176] For example, the second barrier metal BSM2 may be disposed in a metal layer between the first interlayer insulating layer 313 and the second buffer layer 321. The second barrier metal BSM2 may be disposed in the same metal layer as the second capacitor electrode CAPE2.

[0177] As another example, the second barrier metal BSM2 may be disposed in the same first gate metal layer as the first gate electrode E1 a of the first transistor TFT1 .

[0178] Reference Figure 3 , the transistor unit may further include a common drive voltage layer CVP to which a common drive voltage is applied. For example, the common drive voltage applied to the common drive voltage layer CVP may also be referred to as a power supply signal, and may be a first common drive voltage VDD or a second common drive voltage VSS. The first common drive voltage VDD may also be referred to as a high potential power supply voltage (high potential power supply signal), and the second common drive voltage VSS may also be referred to as a low potential power supply voltage (low potential power supply signal) or a base voltage. The common drive voltage layer CVP may be a common drive voltage pattern or a voltage pattern, but embodiments of the present disclosure are not limited thereto.

[0179] The common driving voltage layer CVP may be disposed in the active area AA or the non-active area NA.

[0180] At least one planarization layer may be provided on the first transistor TFT1 and the second transistor TFT2. Figure 3 In the example of FIG, two planarization layers 331 and 332 are provided on the first transistor TFT1 and the second transistor TFT2. In some cases, three or more planarization layers may be provided on the first transistor TFT1 and the second transistor TFT2, but the embodiments of the present disclosure are not limited thereto.

[0181] The planarization layers 331 and 332 may be formed of one or more materials of acrylic resin, epoxy resin, phenol resin, polyamide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, and benzocyclobutene, but the embodiment is not limited thereto.

[0182] Reference Figure 3The first planarization layer 331 may be disposed on the first source electrode E1b and the first drain electrode E1c of the first transistor TFT1, and the second source electrode E2b and the second drain electrode E2c of the second transistor TFT2. The first planarization layer 331 may be disposed on the first transistor TFT1 and the second transistor TFT2. For example, the first planarization layer 331 may be disposed to cover both the first transistor TFT1 and the second transistor TFT2.

[0183] Reference Figure 3 , a relay electrode RE may be provided on the first planarization layer 331. The relay electrode RE may electrically connect the second source electrode E2b of the second transistor TFT2 and the pixel electrode PE.

[0184] The relay electrode RE may be electrically connected to the second source electrode E2b of the second transistor TFT2 through the hole of the first planarization layer 331. The second source electrode E2b of the second transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0185] The relay electrode RE may be provided in a second metal layer on the first planarization layer 331 and may include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer.

[0186] The second planarization layer 332 may be disposed on the relay electrode RE.

[0187] Reference Figure 3 The light emitting element unit may be disposed on the second planarization layer 332. A light emitting element ED may be formed on the second planarization layer 332. The light emitting element ED may include a pixel electrode PE, an intermediate layer EL, and a common electrode CE. A light emitting region of the light emitting element ED may be formed in a region where the pixel electrode PE, the intermediate layer EL, and the common electrode CE overlap.

[0188] The pixel electrode PE may be disposed on the second planarization layer 332. The pixel electrode PE may be electrically connected to the relay electrode RE through a hole in the second planarization layer 332.

[0189] A bank 333 may be provided on the pixel electrode PE. The bank 333 may be provided on the pixel electrode PE and a portion of the second planarization layer 332. The opening of the bank 333 may expose a portion of the pixel electrode PE to form a light-emitting area. For example, the opening of the bank 333 may overlap a portion of the pixel electrode PE. For example, the bank 333 may be formed from a material including black pigment or an organic material such as benzocyclobutene resin, epoxy resin, polyimide resin, acrylic resin, or photopolymer, but embodiments of the present disclosure are not limited thereto. When the bank 333 is formed from a material including black pigment or black dye, it may be a black bank. When the bank 333 is formed from a material including black pigment or black dye, it can block external light or light reflected from the outside, thereby further enhancing the brightness of the display device. A spacer may be provided on the bank 333. The spacer may include an organic insulating material, but embodiments of the present disclosure are not limited thereto. The spacer may be formed from the same material as the bank 333, but embodiments of the present disclosure are not limited thereto.

[0190] The intermediate layer EL of the light emitting element ED may be disposed on the pixel electrode PE and a portion of the bank 333. The common electrode CE may be disposed on the intermediate layer EL.

[0191] Reference Figure 3 The encapsulation unit may be provided on the light emitting element unit and may be positioned on the common electrode CE. The encapsulation unit may include an encapsulation layer 200 formed on the common electrode CE.

[0192] The encapsulation layer 200 can prevent moisture or oxygen from penetrating into the light-emitting element ED. For example, the encapsulation layer 200 can prevent moisture or oxygen from penetrating into the organic material included in the intermediate layer EL of the light-emitting element ED. The encapsulation layer 200 can be formed of a single layer or a plurality of layers, but the embodiments of the present disclosure are not limited thereto.

[0193] For example, refer to Figure 3 The encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343, but the embodiments of the present disclosure are not limited thereto. For example, the first encapsulation layer 341 and the third encapsulation layer 343 may include an inorganic layer, and the second encapsulation layer 342 may include an organic layer, but the embodiments of the present disclosure are not limited thereto.

[0194] For example, the organic layer of the second encapsulation layer 342 may include an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, and silicon oxycarbide (SiOC). The inorganic layer may include an inorganic insulating material. For example, the inorganic layers of the first encapsulation layer 341 and the third encapsulation layer 343 may include an inorganic insulating material capable of low-temperature deposition, such as silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), and aluminum oxide (Al2O3), but are not limited thereto.

[0195] The display panel 110 according to an exemplary embodiment of the present disclosure may have a built-in touch sensor, but the embodiments of the present disclosure are not limited thereto. In this case, the display panel 110 according to an exemplary embodiment of the present disclosure may include a touch sensor layer 210 formed on the encapsulation layer 200.

[0196] Reference Figure 3 The touch sensor layer 210 may include a plurality of touch electrodes TE, and may include a sensor metal TSM and a bridge metal BRG to form the plurality of touch electrodes TE. In an embodiment of the present disclosure, the sensor metal TSM may be referred to as a sensor metal layer TSM, and the bridge metal BRG may be referred to as a bridge metal layer BRG.

[0197] The touch sensor layer 210 may further include insulating layers such as a touch buffer layer 351 on the encapsulation layer 200, a touch interlayer insulating layer 352 on the touch buffer layer 351, and a touch protection layer 353 on the touch interlayer insulating layer 352. Here, the touch buffer layer 351 may be omitted.

[0198] The bridge metal BRG may be provided between the touch buffer layer 351 and the touch interlayer insulating layer 352 . The sensor metal TSM may be provided between the touch interlayer insulating layer 352 and the touch protection layer 353 .

[0199] Each of the plurality of touch electrodes TE may be formed of a sensor metal TSM. Each of the plurality of touch electrodes TE may be a mesh type electrode having a plurality of openings.

[0200] The plurality of touch electrodes TE may include a first touch electrode TE1 and a second touch electrode TE2. The sensor metal TSM included in the first touch electrode TE1 may be electrically connected by a bridge metal BRG. For example, the sensor metal TSM spaced apart from each other may be electrically connected by a bridge metal BRG to form one first touch electrode TE1.

[0201] A bridge metal BRG may be provided on the touch buffer layer 351. A touch interlayer insulating layer 352 may be provided on the bridge metal BRG. For example, the touch interlayer insulating layer 352 may be provided on the bridge metal BRG and a portion of the touch buffer layer 351. A sensor metal TSM may be provided on the touch interlayer insulating layer 352. A portion of the sensor metal TSM may be connected to a corresponding bridge metal BRG through a hole in the touch interlayer insulating layer 352.

[0202] Reference Figure 3 The sensor metal TSM and the bridge metal BRG may be disposed so as not to overlap with the light emitting element ED. The sensor metal TSM and the bridge metal BRG may overlap with the bank 333 .

[0203] A plurality of sensor metals TSM may constitute a touch electrode and may be arranged in a grid and electrically connected. A portion of the sensor metal TSM and another portion of the sensor metal TSM may be electrically connected via a bridge metal BRG to constitute a touch electrode TE. For example, a portion of the sensor metal TSM and another portion of the sensor metal TSM may be electrically connected via a bridge metal BRG to constitute a first touch electrode TE1.

[0204] The touch protection layer 353 may be provided to cover the sensor metal TSM and the bridge metal BRG. For example, the touch protection layer 353 may be provided to cover the sensor metal TSM and a portion of the touch interlayer insulating layer 352.

[0205] Reference Figure 3 The touch line TL may electrically connect the touch electrode TE and the touch pad TP. The touch line TL may be formed of at least one of a sensor metal TSM and a bridge metal BRG.

[0206] When the display panel 110 is a touch sensor embedded type, the touch line TL may extend along the outer slope SLP_ENCAP of the encapsulation layer 200 and may extend beyond the upper portion of the dam portion DAM to the touch pad TP in the non-active area NA, but the embodiments of the present disclosure are not limited thereto.

[0207] Figure 4 A substrate 111 of a display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0208] Reference Figure 4 , the substrate 111 of the display panel 110 according to an exemplary embodiment of the present disclosure may include an active area AA which may display an image and a non-active area NA which does not display an image.

[0209] The non-active region NA may include a plurality of non-active regions such as a first non-active region NA1 , a second non-active region NA2 , a third non-active region NA3 , and a fourth non-active region NA4 .

[0210] The first non-active area NA1 may be located in the column direction from the active area AA. The second non-active area NA2 may be located in the row direction from the active area AA. The third non-active area NA3 may be located in the column direction from the active area AA and opposite the first non-active area NA1. The fourth non-active area NA4 may be located in the row direction from the active area AA and opposite the second non-active area NA2.

[0211] For example, the column direction may be the direction in which the data lines DL are arranged to extend, and the row direction may be the direction in which the gate lines GL are arranged to extend. As another example, the column direction may be the direction in which the gate lines GL are arranged to extend, and the row direction may be the direction in which the data lines DL are arranged to extend. The column direction and the row direction may be relative directions. For example, depending on the viewpoint, the column direction may be the row direction, and depending on the viewpoint, the row direction may also be the column direction. For ease of description, an example is described below in which each of the plurality of data lines DL is arranged along the column direction, and each of the plurality of gate lines GL is arranged along the row direction, but the embodiments of the present disclosure are not limited thereto.

[0212] Reference Figure 4 The first non-active area NA1 may include a pad area PA in which a plurality of pads electrically connected to at least one driving circuit or printed circuit board are disposed. For example, a plurality of data lines DL, a first common driving voltage line VDDL, a second common driving voltage line VSSL, etc. may be electrically connected to the plurality of pads.

[0213] Reference Figure 4 , the first non-active area NA1 may further include a bending area BA. In this case, the substrate 111 may be a flexible substrate. In some cases, the first non-active area NA1 may not include the bending area BA. For example, the flexible substrate may be made of any one of polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyethersulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film and polystyrene (PS), which are only examples and are not necessarily limited thereto.

[0214] The display panel 110 may further include a ground line provided in the non-active area NA of the substrate 111. The ground line may be provided from one point of the pad area PA to another point of the pad area PA via the second, third, and fourth non-active areas NA2, NA3, and NA4.

[0215] In the display panel 110 according to an exemplary embodiment of the present disclosure, the encapsulation layer 200 may have a structure in which an inorganic film and an organic film are stacked, but the embodiments of the present disclosure are not limited thereto. In this case, the edge of the encapsulation layer 200 may be an edge of the organic film. The encapsulation layer 200 may extend from the active area AA to a portion of the non-active area NA.

[0216] The display panel 110 according to an exemplary embodiment of the present disclosure may include at least one dam portion or at least one stopper positioned outward from the organic film included in the encapsulation layer 200 to prevent overflow of the organic film included in the encapsulation layer 200. The at least one dam portion or the at least one stopper may include the organic film, but embodiments of the present disclosure are not limited thereto.

[0217] Figure 5 is a plan view illustrating the display panel 110 according to an exemplary embodiment of the present disclosure, and is a plan view illustrating the display panel 110 having a data link structure.

[0218] Reference Figure 5 , the display panel 110 according to an exemplary embodiment of the present disclosure may include a plurality of data lines DL for supplying a data voltage VDATA and a plurality of pads PD disposed in the pad area PA and electrically connected to the data driving circuit 120 .

[0219] The display panel 110 according to an exemplary embodiment of the present disclosure may include a data link structure for electrically connecting a plurality of data lines DL and a plurality of pads PD. The data link structure according to an exemplary embodiment of the present disclosure may include a plurality of data link lines LINK.

[0220] A plurality of data link lines LINK may be provided in the non-active area NA. For example, the plurality of data link lines LINK may be provided in the first non-active area NA1 including the pad area PA. The plurality of data link lines LINK may be electrically connected to the plurality of data lines DL in the active area AA.

[0221] The first non-active area NA1 may further include a link area LA in addition to the pad area PA and the bending area BA.

[0222] For example, each of the plurality of data link lines LINK may be disposed over the pad area PA, the bending area BA, and the link area LA. Each of the plurality of data link lines LINK may include a first end (or a first side) electrically connected to the pad PD disposed in the pad area PA and a second end (or a second side) electrically connected to the data line DL disposed in the active area AA. A line portion between two opposite ends (the first end and the second end, or the first side and the second side) of each of the plurality of data link lines LINK may be disposed over the bending area BA and the link area LA.

[0223] For example, each of the plurality of data link lines LINK may be composed of a single line or two or more lines, but the embodiments of the present disclosure are not limited thereto. Each of the plurality of data link lines LINK may be provided on one metal layer or on two or more metal layers.

[0224] The bending area BA may be bent during the manufacture of the display panel 110. Therefore, when a user observes the display device 100 from the front, the bending area BA and the pad area PA are not visible from the front.

[0225] However, when the user observes the display device 100 from the front, the link area LA may be recognized as a bezel even if the link area LA is covered by the housing. Therefore, in order to achieve a narrow bezel, the area of ​​the link area LA may need to be reduced.

[0226] Reference Figure 5 , since all of the plurality of data link lines LINK must be electrically connected to the plurality of data lines DL in the link area LA in the first non-active area NA1 , the area of ​​the link area LA inevitably increases.

[0227] For example, when the length of the pad area PA in the row direction is shorter than the length of the active area AA in the row direction, each of the plurality of data link lines LINK in the left area LBZ and the right area RBZ in the link area LA should be electrically connected to the plurality of data lines DL while extending in the diagonal direction. Therefore, the length of the link area LA in the column direction is inevitably increased, and the area of ​​the link area LA is inevitably increased.

[0228] Therefore, if Figure 5 As shown, when the display panel 110 has a data link structure in which a plurality of data link lines LINK are provided in the first non-active area NA1, the area of ​​the link area LA in the first non-active area NA1 may increase. When a user observes the display device 100 from the front, the link area LA may be recognized as a large frame.

[0229] Therefore, in order to achieve a narrow frame, a data link structure capable of reducing the area of ​​the link area LA is required. Therefore, exemplary embodiments of the present disclosure provide a data link structure capable of achieving a narrow frame.

[0230] Hereinafter, a data link structure capable of achieving a narrow bezel according to an exemplary embodiment of the present disclosure is described.

[0231] Figure 6 is a plan view illustrating the display panel 110 according to an exemplary embodiment of the present disclosure, and is a plan view illustrating the display panel 110 having a data link structure. Figure 7 There are shown three areas A, B, and C distinguished within the active area AA by the data link structure of the display panel 110 according to an exemplary embodiment of the present disclosure. The data link structure according to the present disclosure may be a data link structure with a reduced bezel.

[0232] Reference Figure 6 The non-active area NA may include a first non-active area NA1 located in a column direction from the active area AA. The first non-active area NA1 may include a pad area PA and a link area LA located in a column direction from the active area AA.

[0233] The display panel 110 according to an exemplary embodiment of the present disclosure may include a data link structure capable of reducing a bezel while supplying a data voltage VDATA to a plurality of sub-pixels SP disposed in the active area AA.

[0234] Reference Figure 6 , the data link structure according to an exemplary embodiment of the present disclosure may include a plurality of data link lines LINK electrically connecting a plurality of data lines DL and a plurality of pads PD.

[0235] A plurality of data lines DL may be disposed in the active area AA and each may extend in a column direction and may be connected to a plurality of sub-pixels SP disposed in the active area AA.

[0236] A plurality of pads PD may be provided in the pad area PA included in the first non-active area NA1 .

[0237] The plurality of data link lines LINK may electrically connect the plurality of pads PD provided in the pad area PA included in the first non-active area NA1 and the plurality of data lines DL provided in the active area AA.

[0238] Reference Figure 6 , each of the plurality of data link lines LINK included in the data link structure of the narrow bezel according to an exemplary embodiment of the present disclosure may include a data link line LIA disposed in the active area AA.

[0239] Based on the data link structure according to an embodiment of the present disclosure, the plurality of data link lines LINK and the plurality of data lines DL may be electrically connected within the active area AA. For example, in the data link structure with reduced border according to an exemplary embodiment of the present disclosure, the data line connection holes CNT_DL between the plurality of data link lines LINK and the plurality of data lines DL may be located in the active area AA.

[0240] Therefore, each of the multiple data link lines LINK does not need to extend diagonally from the left area and the right area in the link area LA, and each of the multiple data link lines LINK can enter the active area AA by passing through the link area LA within a short distance in the column direction and be connected to the data line DL in the active area AA.

[0241] like Figure 6 As shown, since the display panel 110 according to the exemplary embodiment of the present disclosure has a data link structure with a reduced frame, the length of the link area LA in the column direction can be very short or zero. Therefore, the first non-active area NA1 that the user can see from the front can be very small.

[0242] Reference Figure 6 , in the data link structure according to the exemplary embodiment of the present disclosure, each of the plurality of data link lines LINK may include a data link line LIA disposed in the active area AA.

[0243] The data link lines LIA of the active area AA may include a first data link line HLIA disposed in the active area AA and extending in a first direction and a second data link line VLIA disposed in the active area AA and extending in a second direction.

[0244] Hereinafter, for ease of description, the first direction may be described as the row direction (horizontal direction), the second direction may be described as the column direction (vertical direction), the first data link line HLIA may be described as a "horizontal data link line", and the second data link line VLIA may be described as a "vertical data link line". The data link line LIA of the active area AA may be abbreviated as data link line LIA. However, this embodiment is not limited thereto.

[0245] The vertical data link line VLIA may electrically connect the pad PD and the horizontal data link line HLIA. The horizontal data link line HLIA may electrically connect the vertical data link line VLIA and the data line DL.

[0246] The horizontal data link line HLIA and the vertical data link line VLIA may be electrically connected in the link line connection hole CNT_LIA. The horizontal data link line HLIA and the data line DL may be electrically connected in the data line connection hole CNT_DL.

[0247] Reference Figure 6 , each of the plurality of data link lines LINK may further include a data link line LIN disposed in a non-active area in a first non-active area NA1 included in the non-active area NA.

[0248] The non-active data link line LIN may be integrated with the vertical data link line VLIA. Alternatively, the non-active data link line LIN may be a line electrically connected to the vertical data link line VLIA but disposed on a different metal layer than the vertical data link line VLIA. Alternatively, the non-active data link line LIN may include a line electrically connected to the vertical data link line VLIA but disposed on a different metal layer than the vertical data link line VLIA.

[0249] When the display panel 110 according to the exemplary embodiment of the present disclosure has Figure 6 In the data link structure shown, the horizontal data link line HLIA included in each of the plurality of data link lines LINK may be disposed in the active area AA and may be parallel to the plurality of gate lines GL each extending in a row direction (horizontal direction).

[0250] In addition, when the display panel 110 according to the exemplary embodiment of the present disclosure has Figure 6 In the data link structure shown, the horizontal data link line HLIA included in each of the plurality of data link lines LINK may overlap with at least one gate line GL in a vertical direction.

[0251] Among the plurality of vertical data link lines VLIA, the vertical data link lines VLIA electrically connected to the data lines DL positioned more inward may have a shorter length. Among the plurality of vertical data link lines VLIA, the vertical data link lines VLIA electrically connected to the data lines DL positioned more outward may have a longer length. The length of the vertical data link lines VLIA electrically connected to the data lines DL positioned more inward among the plurality of vertical data link lines VLIA may be shorter than the length of the vertical data link lines VLIA electrically connected to the data lines DL positioned more outward among the plurality of vertical data link lines VLIA.

[0252] Among the plurality of horizontal data link lines HLIA, the horizontal data link lines HLIA electrically connected to the data lines DL positioned more inward may have a shorter length. Among the plurality of horizontal data link lines HLIA, the horizontal data link lines HLIA electrically connected to the data lines DL positioned more outward may have a longer length. The horizontal data link lines HLIA electrically connected to the data lines DL positioned more inward among the plurality of horizontal data link lines HLIA may be shorter than the horizontal data link lines HLIA electrically connected to the data lines DL positioned more outward among the plurality of horizontal data link lines HLIA.

[0253] Among the plurality of horizontal data link lines HLIA, the length of the horizontal data link line HLIA closer to the pad area PA may be shorter. Among the plurality of horizontal data link lines HLIA, the length of the horizontal data link line HLIA located farther from the pad area PA may be longer. The length of the horizontal data link line HLIA closer to the pad area PA among the plurality of horizontal data link lines HLIA may be shorter than the length of the horizontal data link line HLIA located farther from the pad area PA among the plurality of horizontal data link lines HLIA.

[0254] The first link line LINK1 may include an active area data link line LIA1 and a non-active area data link line LIN1. The active area data link line LIA1 may include a first horizontal data link line HLIA1 and a first vertical data link line VLIA1.

[0255] The second link line LINK2 may include an active area data link line LIA2 and a non-active area data link line LIN2. The active area data link line LIA2 may include a second horizontal data link line HLIA2 and a second vertical data link line VLIA2.

[0256] A length of the first vertical data link line VLIA1 , which is electrically connected to the first data line DL1 located more outward among the first and second data lines DL1 and DL2 , may be longer than a length of the second vertical data link line VLIA2 .

[0257] A length of the first horizontal data link line HLIA1 or the second horizontal data link line HLIA2 , which is electrically connected to the first data line DL1 positioned more outward of the first and second data lines DL1 or DL2 , may be longer than a length of the second horizontal data link line HLIA2 .

[0258] Since the length of the first horizontal data link line HLIA1 is longer than that of the second horizontal data link line HLIA2 , a first area where the first horizontal data link line HLIA1 overlaps at least one gate line GL may be larger than a second area where the second horizontal data link line HLIA2 overlaps at least one gate line GL.

[0259] like Figure 6 As shown, the point CNT_DL where the data line DL connects to the horizontal data link line HLIA can form two first oblique lines SLT_DL. In addition, the point CNT_LIA where the vertical data link line VLIA connects to the horizontal data link line HLIA can form two second oblique lines SLT_LIA.

[0260] like Figure 6 As shown, two triangles may be formed by two first slanted lines SLT_DL and two second slanted lines SLT_LIA. In each of the two triangles, one of the three sides may be a horizontal side parallel to the horizontal data link line HLIA, and a vertex facing the horizontal side may be located at or near a boundary point between the active area AA and the first non-active area NA1.

[0261] Reference Figure 6 For example, the active area AA may include multiple wiring areas, such as a first wiring area WA1, a second wiring area WA2, and a third wiring area WA3. The third wiring area WA3 may be located between the first wiring area WA1 and the second wiring area WA2. Alternatively, the active area AA may include multiple areas, such as the first wiring area WA1 and the second wiring area WA2.

[0262] The first and second wiring areas WA1 and WA2 may have the same wiring arrangement structure, and the third wiring area WA3 may have a wiring arrangement structure different from those of the first and second wiring areas WA1 and WA2, but is not limited thereto.

[0263] The first and second line areas WA1 and WA2 may be areas where data lines DL and data link lines LIA are provided. The third line area WA3 may be an area where data lines DL are provided but data link lines LIA are not provided. In this case, some of the data lines DL may receive data voltages VDATA through the data link lines LIA.

[0264] As another example, the active area AA may include a first line area WA1 and a second line area WA2, but may not include a third line area WA3. Therefore, the first line area WA1 and the second line area WA2 may contact each other. The first line area WA1 and the second line area WA2 may be areas where the data lines DL and the data link line LIA are disposed. In this case, all the data lines DL may receive the data voltage VDATA through the data link line LIA.

[0265] When the display panel 110 according to the exemplary embodiment of the present disclosure has Figure 6 In the data link structure shown, the horizontal data link line HLIA included in each of the multiple data link lines LINK can be parallel to the multiple gate lines GL arranged in the active area AA and each extending in the row direction (horizontal direction), and the horizontal data link line HLIA included in each of the multiple data link lines LINK can overlap with at least one gate line GL in the vertical direction.

[0266] Reference Figure 7 , according to the data link structure, the active area AA can include three areas A, B, and C.

[0267] The first area A may be an area where a data link structure is not provided. For example, the first area A may be an area where horizontal data link lines HL1A and vertical data link lines VLIA are not provided. The second area B and the third area C may be areas where a data link structure is provided. The second area B may be an area where horizontal data link lines HL1A are provided. The third area C may be an area where vertical data link lines VLIA are provided. The data link structure may be a data link structure with a reduced border.

[0268] Among the first to fourth non-active regions NA1 to NA4 included in the non-active region NA, the first non-active region NA1 including the pad region PA may contact one side of each third region C. In addition, the first non-active region NA1 including the pad region PA may contact one side of each first region A.

[0269] The second region B may have an inverted triangle shape or an isosceles triangle shape. The active area AA may include two second regions B. The two second regions B may be positioned at two opposite sides of the first region A located in the middle.

[0270] The third region C may have a right triangle shape. The active area AA may include two third regions C. The two third regions C may be positioned at two opposite sides of the first region A located in the middle.

[0271] The first portion of the first region A may be located at the upper ends (or upper sides) of the two second regions B, the second portion of the first region A may be located between the two third regions C, or the third portion of the first region A may be located outside each of the two second regions B. The first region A located between the two third regions C may correspond to Figure 6 The third line area WA3.

[0272] Reference Figure 6 and Figure 7 , a boundary between the first area A and the second area B may correspond to a point CNT_DL at which the horizontal data link line HLIA and the data line DL are connected, and may form a first slant line SLT_DL.

[0273] A boundary between the second region B and the third region C may be a point CNT_LIA where the vertical data link line VLIA and the horizontal data link line HLIA are connected, and may form a second slanted line SLT_LIA.

[0274] Figure 8 is a plan view showing a display panel 110 having a data link structure according to an exemplary embodiment of the present disclosure. Figure 6 .

[0275] The first non-active area NA1 may include a pad area PA where a plurality of data pads are disposed. Figure 8 The first non-active area NA1 may include a pad area PA in which a plurality of data pads DP1 to DP4 are disposed. The plurality of data pads DP1 to DP4 may include a first data pad DP1, a second data pad DP2, a third data pad DP3, and a fourth data pad DP4.

[0276] The plurality of data lines DL may be disposed in the active area AA and may include a plurality of data lines. For example, the plurality of data lines may include a first data line DL1, a second data line DL2, a third data line DL3, and a fourth data line DL4. Each of the first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 may be disposed in the active area AA, extend in a column direction, and receive a data voltage, but is not limited thereto.

[0277] Reference Figure 8 A data link structure is provided in the active area AA adjacent to the first non-active area NA1. The data link structure may be a data link structure with a reduced frame.

[0278] The data link structure may include a data link line LIA of an active area. The data link line LIA of the active area may include a horizontal data link line HLIA and a vertical data link line VLIA.

[0279] Each horizontal data link line HLIA may be disposed in the active area AA. All or part of each vertical data link line VLIA may be disposed in the active area AA.

[0280] Reference Figure 8 The horizontal data link line HLIA may be electrically connected to the first data line DL1. The horizontal data link line HLIA may be disposed in the active area AA. The horizontal data link line HLIA may extend along a row direction. The horizontal data link line HLIA may include a first horizontal data link line HLIA1 located in the first metal layer ML1.

[0281] The vertical data link line VLIA may electrically connect the first horizontal data link line HLIA1 and the first data pad DP1. The vertical data link line VLIA may extend in a column direction. The vertical data link line VLIA may include a first vertical data link line VLIA1 located in a second metal layer ML2 different from the first metal layer ML1. All or part of the first vertical data link line VLIA1 may be disposed in the active area AA.

[0282] The horizontal data link line HLIA can be electrically connected to the second data line DL2. The horizontal data link line HLIA can be disposed in the active area AA. The horizontal data link line HLIA can extend along the row direction. The horizontal data link line HLIA can further include a second horizontal data link line HLIA2 located in the first metal layer ML1.

[0283] The vertical data link line VLIA may electrically connect the second horizontal data link line HLIA2 and the second data pad DP2. The vertical data link line VLIA may extend along the column direction. The vertical data link line VLIA may further include a second vertical data link line VLIA2 located in a second metal layer ML2 different from the first metal layer ML1. All or part of the second vertical data link line VLIA2 may be disposed in the active area AA.

[0284] Reference Figure 8 The display panel 110 according to an exemplary embodiment of the present disclosure may include a plurality of power lines LIA_P disposed in the active area AA. The plurality of power lines LIA_P may include a plurality of first power lines HLIA_P each extending along a first direction and a plurality of second power lines VLIA_P each extending along a second direction.

[0285] Hereinafter, for ease of description, the first direction may be described as a row direction, the second direction may be described as a column direction, the first power line HLIA_P may be described as a "horizontal power line HLIA_P," and the second power line VLIA_P may be described as a "vertical power line VLIA_P." However, the present embodiment is not limited thereto.

[0286] The horizontal power lines HLIA_P may be spaced apart from the horizontal data link lines HLIA to extend in the row direction and may be located in the first metal layer ML1. The vertical power lines VLIA_P may be spaced apart from the vertical data link lines VLIA to extend in the column direction and may be located in the second metal layer ML2.

[0287] The horizontal power lines HLIA_P may include first horizontal power lines HLIA1_P. The first horizontal power lines HLIA1_P may be spaced apart from the first horizontal data link lines HLIA1 and extend in a row direction, and may be located in the first metal layer ML1.

[0288] The horizontal power lines HLIA_P may include second horizontal power lines HLIA2_P. The second horizontal power lines HLIA2_P may be spaced apart from the second horizontal data link lines HLIA2 and extend in a row direction, and may be located in the first metal layer ML1.

[0289] The vertical power lines VLIA_P may include first vertical power lines VLIA1_P. The first vertical power lines VLIA1_P may be spaced apart from the first vertical data link lines VLIA1 and extend in a column direction, and may be located in the second metal layer ML2.

[0290] The vertical power lines VLIA_P may include second vertical power lines VLIA2_P. The second vertical power lines VLIA2_P may be spaced apart from the second vertical data link lines VLIA2 and extend in a column direction, and may be located in the second metal layer ML2.

[0291] If the first and second horizontal power lines HLIA1_P and HLIA2_P are not located within the region where the first and second horizontal power lines HLIA1_P and HLIA2_P are located, an imbalance may occur in the first metal layer between the region where the first and second horizontal data link lines HLIA1 and HLIA2 are located and the region where the first and second horizontal data link lines HLIA1 and HLIA2 are not located. As a result, significant deviations in light reflection characteristics may occur at various locations within display panel 110, resulting in image and appearance anomalies. The light may include at least one of internal light emitted by light-emitting element ED and external light introduced into display panel 110 from the outside.

[0292] Furthermore, if the first and second vertical power lines VLIA1_P and VLIA2_P are not located within the region where the first and second vertical power lines VLIA1_P and VLIA2_P are located, an imbalance may occur in the second metal layer between the region where the first and second vertical data link lines VLIA1 and VLIA2 are located and the region where the first and second vertical data link lines VLIA1 and VLIA2 are not located. Consequently, significant deviations in the light reflection characteristics may occur at various locations within the display panel 110, resulting in image and appearance anomalies. The light may include at least one of internal light emitted by the light-emitting element ED and external light introduced into the display panel 110 from the outside.

[0293] For example, through the first and second horizontal power lines HLIA1_P and HLIA2_P and the first and second vertical power lines VLIA1_P and VLIA2_P, image and appearance abnormalities due to imbalance of metal layers may be reduced.

[0294] The common driving voltage is a power supply voltage transmitted by the horizontal power line HLIA_P and the vertical power line VLIA_P, and may be one of a first common driving voltage VDD and a second common driving voltage VSS. However, the common driving voltage transmitted by the horizontal power line HLIA_P and the vertical power line VLIA_P is not limited thereto, and any direct current (DC) power supply voltage having a constant voltage level supplied to the display panel 110 may be used.

[0295] In the exemplary embodiment of the present disclosure, for convenience of description, an example is described in which the common driving voltage transmitted by the horizontal power line HLIA_P and the vertical power line VLIA_P is the second common driving voltage VSS applied to the common electrode CE. The second common driving voltage VSS is also called a base voltage or a low potential power voltage.

[0296] Reference Figure 8 The plurality of horizontal power lines HLIA_P and the plurality of vertical power lines VLIA_P included in the plurality of power lines LIA_P can be arranged (configured) in a grid. Therefore, the area over which the base voltage VSS, serving as the second common driving voltage, is transmitted through the horizontal power lines HLIA_P and the vertical power lines VLIA_P can be increased, significantly improving the transmission characteristics of the base voltage VSS.

[0297] In the same first row, the same horizontal metal pattern (the metal pattern of the first metal layer) is separated into the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P, in the same first column, the same vertical metal pattern (the metal pattern of the second metal layer) is separated into the first vertical data link line VLIA1 and the first vertical power line VLIA1_P, in the same second row, the same horizontal metal pattern (the metal pattern of the first metal layer) is separated into the second horizontal data link line HLIA2 and the second horizontal power line HLIA2_P, and in the same second column, the vertical metal pattern (the metal pattern of the second metal layer) is separated into the second vertical data link line VLIA2 and the second vertical power line VLIA2_P. Therefore, the length and area of ​​the path for transmitting the data voltage can be reduced. Consequently, parasitic capacitance associated with the second data line DL2 can be reduced.

[0298] The horizontal power lines HLIA_P and the vertical power lines VLIA_P may be lines transmitting a common driving voltage for display driving.

[0299] Figure 9 and Figure 10 is a cross-sectional view showing a display panel 110 having a data link structure according to an exemplary embodiment of the present disclosure. Figure 6 and Figure 8 .

[0300] Reference Figure 9 The first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P may be disposed on the second interlayer insulating layer 323. For example, the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P may be disposed on a portion of the second interlayer insulating layer 323. The first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P may be disposed to be spaced apart from each other. Specifically, a first open area OA1 may be disposed between the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P.

[0301] The first planarization layer 331 may be disposed on the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P. Specifically, the first planarization layer 331 may be disposed on a portion of the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P and a portion of the second interlayer insulating layer 323 .

[0302] A first vertical data link line VLIA1 and another vertical line (eg, a data line DL3 ) may be disposed on the first planarization layer 331 .

[0303] The first vertical data link line VLIA1 may be connected to the first horizontal data link line HLIA1 through a hole passing through the first planarization layer 331 .

[0304] The second planarization layer 332 may be disposed on the first vertical data link line VLIA1 and another vertical line (eg, the data line DL3 ). The bank 333 may be disposed on the second planarization layer 332 .

[0305] The metal layer where the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P are disposed may be a first metal layer ML1 between the second interlayer insulating layer 323 and the first planarization layer 331 .

[0306] A separation space between the first horizontal data link line HLIA1 and the first horizontal power line HLIA1_P in the first metal layer ML1 may be referred to as a first open area OA1 of the first metal layer ML1 .

[0307] The metal layer where the first vertical data link line VLIA1 and another vertical line (eg, the data line DL3 ) are disposed may be a second metal layer ML2 positioned between the first planarization layer 331 and the second planarization layer 332 .

[0308] Reference Figure 10 , the first horizontal data link line HLIA1 may be disposed on the second interlayer insulating layer 323 .

[0309] The first planarization layer 331 may be disposed on the first horizontal data link line HLIA1 . Specifically, the first planarization layer 331 may be disposed on the first horizontal data link line HLIA1 and a portion of the second interlayer insulating layer 323 .

[0310] The first vertical data link line VLIA1 and the first vertical power line VLIA1_P may be disposed to be spaced apart from each other on the first planarization layer 331 .

[0311] The first vertical data link line VLIA1 may be connected to the first horizontal data link line HLIA1 through a hole passing through the first planarization layer 331 .

[0312] A second planarization layer 332 may be disposed on the first vertical data link line VLIA1 and the first vertical power line VLIA1_P. A bank 333 may be disposed on the second planarization layer 332. Specifically, the second planarization layer 332 may be disposed on the first vertical data link line VLIA1 and the first vertical power line VLIA1_P, and a portion of the first planarization layer 331. The first vertical data link line VLIA1 and the first vertical power line VLIA1_P may be spaced apart from each other.

[0313] The first vertical power line VLIA1_P may be disposed in the second metal layer ML2 together with the first vertical data link line VLIA1 .

[0314] A separation space between the first vertical data link line VLIA1 and the first vertical power line VLIA1_P in the second metal layer ML2 may be referred to as a second open area OA2 of the second metal layer ML2 .

[0315] As described above, the common driving voltage required for display driving can be transmitted through the horizontal power lines HLIA1_P and HLIA2_P spaced apart from the horizontal data link lines HLIA1 and HLIA2 and the vertical power lines VLIA1_P and VLIA2_P spaced apart from the vertical data link lines VLIA1 and VLIA2. For example, the common driving voltage can be the base voltage VSS.

[0316] Therefore, the path for transmitting the common driving voltage can be configured in a grid form, thereby increasing the area for transmitting the common driving voltage and greatly improving the transmission characteristics of the common driving voltage.

[0317] In the following, reference is made to Figures 11 to 20 The power line structure for transmitting the power voltage input to the display panel 110 through the power circuit to the display driving electrode is described in more detail. In the following description, an example is described in which the display driving electrode is a common electrode CE and the power voltage is a second common driving voltage VSS applied to the common electrode CE. However, exemplary embodiments of the present disclosure are not limited thereto.

[0318] Figure 11 is a plan view illustrating an active area AA of a display panel 110 having a power line structure associated with a data link structure according to an exemplary embodiment of the present disclosure.

[0319] Reference Figure 11 , in the display panel 110 according to the exemplary embodiment of the present disclosure, the active area AA may include a data link structure with a reduced bezel.

[0320] The data link structure with reduced bezel may include a plurality of data link lines LIA disposed in the active area AA. The plurality of data link lines LIA may be electrically connected to the plurality of data lines DL and may transmit a data voltage VDATA to the plurality of data lines DL.

[0321] The plurality of data link lines LIA may include a plurality of vertical data link lines VLIA and a plurality of horizontal data link lines HLIA. Each of the plurality of vertical data link lines VLIA may extend in a column direction, and each of the plurality of horizontal data link lines HLIA may extend in a row direction.

[0322] The horizontal data link line HLIA and the vertical data link line VLIA may be electrically connected in the link line connection hole CNT_LIA, and the horizontal data link line HLIA and the data line DL may be electrically connected in the data line connection hole CNT_DL.

[0323] The vertical data link line VLIA can electrically connect the data pad and the horizontal data link line HLIA. The horizontal data link line HLIA can electrically connect the vertical data link line VLIA and the data line DL. Therefore, the data voltage VDATA output from the data driving circuit 120 can be transmitted to the data line DL through the vertical data link line VLIA and the horizontal data link line HLIA.

[0324] At least one of the plurality of data lines DL may be directly supplied with the data voltage VDATA through the data link line LIN disposed in the non-active area NA without passing through the data link line LIA disposed in the active area AA.

[0325] Reference Figure 11 , in the display panel 110 according to an exemplary embodiment of the present disclosure, the active area AA may include a power line structure associated with a bezel-reduced data link structure.

[0326] The power line structure may include a plurality of power lines LIA_P disposed in the active area AA and transmitting a power voltage to the plurality of sub-pixels SP. The power voltage may be a second common driving voltage VSS applied to the common electrode CE.

[0327] The plurality of power lines LIA_P may include a plurality of vertical power lines VLIA_P and a plurality of horizontal power lines HLIA_P. Each of the plurality of vertical power lines VLIA_P may extend in a column direction, and each of the plurality of horizontal power lines HLIA_P may extend in a row direction.

[0328] The plurality of vertical power lines VLIA_P and the plurality of horizontal power lines HLIA_P may be electrically connected to each other. At least one of the plurality of vertical power lines VLIA_P may be electrically connected to at least one horizontal power line HLIA_P through a power connection hole CNT_P. The power connection hole CNT_P may be a contact hole provided in the active area AA.

[0329] The power line structure according to the exemplary embodiment of the present disclosure may be configured in association with a bezel-reduced data link structure.

[0330] The plurality of horizontal power lines HLIA_P and the plurality of horizontal data link lines HLIA may be provided on the same metal layer (eg, Figure 9 and Figure 10The plurality of vertical power lines VLIA_P and the plurality of vertical data link lines VLIA may be disposed on the same metal layer (eg, Figure 9 and Figure 10 On the second metal layer ML2).

[0331] Multiple horizontal power lines HLIA_P may be formed together with multiple horizontal data link lines HLIA, and multiple vertical power lines VLIA_P may be formed together with multiple vertical data link lines VLIA. At least one of the multiple horizontal power lines HLIA_P may be spaced apart from the corresponding horizontal data link line HLIA in the same row. The horizontal power lines HLIA_P and horizontal data link lines HLIA spaced apart from each other in the same row may be first metal patterns that are disconnected in the first metal layer ML1. For example, a first opening region may be provided between the horizontal data link line HLIA and the horizontal power lines HLIA_P.

[0332] At least one of the plurality of vertical power lines VLIA_P may be arranged in the same row and spaced apart from the corresponding vertical data link line VLIA. The vertical power line VLIA_P and the vertical data link line VLIA spaced apart from each other in the same row may be a second metal pattern that is disconnected in the second metal layer ML2. For example, a second open region may be provided between the vertical data link line VLIA and the vertical power line VLIA_P.

[0333] Reference Figure 11 The active area AA may include multiple wiring areas, such as a first wiring area WA1, a second wiring area WA2, and a third wiring area WA3. The third wiring area WA3 may be located between the first wiring area WA1 and the second wiring area WA2. Alternatively, the active area AA may include multiple areas, such as the first wiring area WA1 and the second wiring area WA2.

[0334] The first and second wiring areas WA1 and WA2 may have the same wiring arrangement structure, and the third wiring area WA3 may have a wiring arrangement structure different from those of the first and second wiring areas WA1 and WA2, but is not limited thereto.

[0335] The first and second wiring areas WA1 and WA2 may be areas where the data lines DL and the data link lines LIA are disposed.

[0336] Each of the first wiring area WA1 and the second wiring area WA2 may include a first area A, a second area B, and a third area C in the active area AA. The first area A may be an area where the horizontal data link line HLIA and the vertical data link line VLIA are not disposed, the second area B may be an area where the horizontal data link line HLIA is disposed, and the third area C may be an area where the vertical data link line VLIA is disposed.

[0337] The third line area WA3 may be an area in which the data line DL is disposed but the data link line LIA is not disposed.

[0338] The third wiring area WA3 may include the first area A among the first area A, the second area B, and the third area C in the active area AA.

[0339] The first wiring area WA1 may include a first sub-wiring area WA1a and a second sub-wiring area WA1b.

[0340] The first sub-line area WA1a may include a data line DL, a data link line LIA, and a power line LIA_P.

[0341] The data link lines LIA disposed in the first sub-line area WA1a may include horizontal data link lines HLIA.

[0342] The horizontal data link line HLIA disposed in the first sub-wire area WA1a may be connected to the vertical data link line VLIA in the second sub-wire area WA1b to extend to the first sub-wire area WA1a.

[0343] The data line DL disposed in the first sub-line area WA1a may receive the data voltage VDATA through the horizontal data link line HLIA.

[0344] The power lines LIA_P disposed in the first sub-wire area WA1a may include at least one vertical power line VLIA_P and at least one horizontal power line HLIA_P.

[0345] The vertical power line VLIA_P disposed in the first sub-wire area WA1 a may have a length corresponding to a length of the active area AA in the column direction.

[0346] The horizontal power line HLIA_P disposed in the first sub-wiring area WA1a may be disposed to be disconnected from the corresponding horizontal data link line HLIA disposed in the same row. Therefore, the horizontal power line HLIA_P disposed in the first sub-wiring area WA1a may have a length shorter than the length of the active area AA in the row direction.

[0347] The second sub-line area WA1b may include a data line DL, a data link line LIA, and a power line LIA_P.

[0348] The data link lines LIA disposed in the second sub-wire area WA1b may include vertical data link lines VLIA and horizontal data link lines HLIA. In the second sub-wire area WA1b, the vertical data link lines VLIA and the horizontal data link lines HLIA may be connected to each other.

[0349] The data line DL disposed in the second sub-line area WA1b may be directly supplied with the data voltage VDATA through the data link line LIN disposed in the non-active area NA without passing through the horizontal data link line HLIA. The data line DL disposed in the second sub-line area WA1b may have a length corresponding to the length of the active area AA in the column direction.

[0350] The power lines LIA_P disposed in the second sub-wiring area WA1b may include vertical power lines VLIA_P and horizontal power lines HLIA_P.

[0351] The vertical power lines VLIA_P disposed in the second sub-wiring area WA1b can be disposed so as to be disconnected from the vertical data link lines VLIA disposed in the same column. Therefore, the vertical power lines VLIA_P disposed in the second sub-wiring area WA1b can have a length shorter than the length of the active area AA in the column direction. The vertical power lines VLIA_P disposed in the second sub-wiring area WA1b can have different lengths.

[0352] The horizontal power lines HLIA_P disposed in the second sub-wiring area WA1b can be disposed so as to be disconnected from the corresponding horizontal data link lines HLIA disposed in the same row. Therefore, the horizontal power lines HLIA_P disposed in the second sub-wiring area WA1b can have a length shorter than the length of the active area AA in the row direction. The horizontal power lines HLIA_P disposed in the second sub-wiring area WA1b can have different lengths.

[0353] The second wiring area WA2 may include a third sub-wiring area WA2a and a fourth sub-wiring area WA2b.

[0354] The third sub-wiring area WA2a may include data lines DL, data link lines LIA, and power lines LIA_P. The third sub-wiring area WA2a may have the same wiring structure (wiring arrangement) as the first sub-wiring area WA1a. The wiring structure (wiring arrangement) of the third sub-wiring area WA2a may be symmetrical to that of the first sub-wiring area WA1a.

[0355] The fourth sub-wiring area WA2b may include data lines DL, data link lines LIA, and power lines LIA_P. The fourth sub-wiring area WA2b may have the same wiring structure (wiring arrangement structure) as the second sub-wiring area WA1b. The wiring structure (wiring arrangement structure) of the fourth sub-wiring area WA2b may be symmetrical to the wiring structure (wiring arrangement structure) of the second sub-wiring area WA1b.

[0356] The third wiring area WA3 may include the data line DL and the power line LIA_P, and may not include the data link line LIA.

[0357] Since the data link line LIA is not provided in the third wiring area WA3, the data line DL provided in the third wiring area WA3 can be directly supplied with the data voltage VDATA through the data link line LIN provided in the non-active area NA without passing through the data link line LIA. The data line DL provided in the third wiring area WA3 can have a length corresponding to the length of the active area AA in the column direction.

[0358] The power lines LIA_P disposed in the third wiring area WA3 may include vertical power lines VLIA_P and horizontal power lines HLIA_P.

[0359] The vertical power line VLIA_P disposed in the third wiring area WA3 may have a length corresponding to a length of the active area AA in the column direction.

[0360] The horizontal power lines HLIA_P disposed in the third wiring area WA3 may be disposed so as to be disconnected from the horizontal data link lines HLIA disposed in the same row. Therefore, the horizontal power lines HLIA_P disposed in the third wiring area WA3 may have a length shorter than the length of the active area AA in the row direction. The horizontal power lines HLIA_P disposed in the third wiring area WA3 may have different lengths.

[0361] Hereinafter, a power line structure associated with a bezel-reduced data link structure in the display panel 110 according to an exemplary embodiment of the present disclosure is described in more detail.

[0362] Figure 12 A power line structure of the display panel 110 according to an exemplary embodiment of the present disclosure is shown. Figure 12 This is a diagram about the power line structure, and for the convenience of description, the data link structure is omitted. Figure 11 Can also be used to describe the structure of power lines in relation to data link structures.

[0363] Reference Figure 12According to an exemplary embodiment of the present disclosure, a display panel 110 may include a substrate 111 including an active area AA and a non-active area NA, a plurality of data lines DL, and a plurality of data link lines LIA. The active area AA may include a plurality of sub-pixels SP. The non-active area NA may be located outside or around the active area AA. Each of the plurality of data lines DL may extend in a column direction within the active area AA. The plurality of data link lines LIA may be electrically connected to the plurality of data lines DL within the active area AA.

[0364] Reference Figure 12 , the power line structure in the display panel 110 according to an exemplary embodiment of the present disclosure may include a plurality of power lines LIA_P disposed in the active area AA.

[0365] The plurality of power lines LIA_P may be electrically connected to each other.

[0366] The plurality of power lines LIA_P may be disposed in the same metal layer (eg, the first metal layer ML1 and the second metal layer ML2 ) as at least one of the plurality of data link lines LIA.

[0367] The power line structure in the display panel 110 according to an exemplary embodiment of the present disclosure may include a plurality of power lines LIA_P arranged in a grid form.

[0368] The plurality of power lines LIA_P may include a plurality of horizontal power lines HLIA_P and a plurality of vertical power lines VLIA_P that intersect each other. The plurality of horizontal power lines HLIA_P may each extend in a row direction within the active area AA. The plurality of vertical power lines VLIA_P may each extend in a column direction within the active area AA and may be electrically connected to the plurality of horizontal power lines HLIA_P.

[0369] Reference Figure 12 The power line structure in the display panel 110 according to an exemplary embodiment of the present disclosure may be provided in the non-active area NA. A power pattern 1200 electrically connected to at least one of the plurality of power lines LIA_P may also be included. For example, the power pattern may be provided in the non-active area NA and electrically connected to at least one of the plurality of power lines LIA_P.

[0370] For example, the power pattern 1200 may be connected to all or part of the plurality of horizontal power lines HLIA_P among the plurality of power lines LIA_P. As another example, the power pattern 1200 may be connected to all or part of the plurality of vertical power lines VLIA_P among the plurality of power lines LIA_P. As another example, the power pattern 1200 may be connected to all or part of the plurality of horizontal power lines HLIA_P and may be connected to all or part of the plurality of vertical power lines VLIA_P.

[0371] A power voltage may be applied to the power pattern 1200 .

[0372] For example, the power voltage applied to the power pattern 1200 may be the second common driving voltage VSS corresponding to the base voltage. Therefore, the power voltage applied to the common electrode CE may be applied to the power pattern 1200. The power pattern 1200 may be electrically connected to the common electrode CE.

[0373] In order to describe the power line structure according to the exemplary embodiment of the present disclosure in more detail, a data link structure with reduced bezel associated with the power line structure according to the exemplary embodiment of the present disclosure is further briefly described.

[0374] The data link structure of the display panel 110 with reduced bezel according to an exemplary embodiment of the present disclosure may include a plurality of data link lines LIA disposed in the active area AA. The plurality of data link lines LIA may be electrically connected to the plurality of data lines DL and may transmit the data voltage VDATA to the plurality of data lines DL.

[0375] The plurality of data link lines LIA disposed in the active area AA may include a plurality of vertical data link lines VLIA each extending in a column direction in the active area AA, and a plurality of horizontal data link lines HLIA each extending in a row direction in the active area AA.

[0376] A metal layer having multiple power lines LIA_P can be connected to a metal layer having multiple data link lines LIA. For example, multiple horizontal power lines HLIA_P can be arranged in a first metal layer ML1 having multiple horizontal data link lines HLIA, and multiple vertical power lines VLIA_P can be arranged in a second metal layer ML2 having multiple vertical data link lines VLIA. However, this is not limiting, and various modifications can be made to the metal layer having multiple power lines LIA_P associated with the metal layer having multiple data link lines LIA. Furthermore, the multiple horizontal power lines HLIA_P and the multiple horizontal data link lines HLIA can be spaced apart from each other, and the multiple vertical power lines VLIA_P and the multiple vertical data link lines VLIA can be spaced apart from each other.

[0377] The active area AA may include a first area A where the plurality of vertical data link lines VLIA and the plurality of horizontal data link lines HLIA are not disposed, a second area B where the plurality of horizontal data link lines HLIA are disposed, and a third area C where the plurality of vertical data link lines VLIA are disposed. Figure 12 , the first region A is not shown to prevent confusion in the drawing, but the remaining regions except the second region B and the third region C may be the first region A.

[0378] The first portion of the first region A may be located at the upper end (or upper side) of the two second regions B, the second portion of the first region A may be located between the two third regions C, or the third portion of the first region A may be located outside each of the two second regions B.

[0379] The plurality of power lines LIA_P may extend from the first area A to at least a portion of the second area B or the third area C. At least some of the plurality of power lines LIA_P may have a different length from the remaining power lines. Figure 11 What is described is basically the same, so the description thereof is omitted.

[0380] The plurality of vertical data link lines VLIA and the plurality of horizontal data link lines HLIA may be electrically connected in a boundary area between the second region B and the third region C. The plurality of horizontal data link lines HLIA and the plurality of data lines DL may be electrically connected at a boundary between the second region B and the first region A.

[0381] For example, the plurality of vertical data link lines VLIA may include a first vertical data link line VLIA1 and a second vertical data link line VLIA2 disposed further outward than the first vertical data link line VLIA1. The plurality of horizontal data link lines HLIA may include a first horizontal data link line HLIA1 electrically connected to the first vertical data link line VLIA1 and a second horizontal data link line HLIA2 electrically connected to the second vertical data link line VLIA2. In this case, the first vertical data link line VLIA1 may be longer than the second vertical data link line VLIA2, or the first horizontal data link line HLIA1 may be longer than the second horizontal data link line HLIA2.

[0382] Reference Figure 12 The power line structure of the display panel 110 according to an exemplary embodiment of the present disclosure may further include a merging electrode 1250 electrically connected to at least one of the plurality of power lines LIA_P. For example, the merging electrode 1250 may be electrically connected to a plurality of vertical power lines VLIA_P.

[0383] The merged electrode 1250 may be disposed in the non-active area NA. For example, the merged electrode 1250 may be disposed in the non-active area NA, but may be disposed on the opposite side of the pad area PA relative to the active area AA ( Figure 4 However, the position of the merged electrode 1250 is not limited thereto and may be variously modified.

[0384] Reference Figure 12In the power line structure of the display panel 110 according to an exemplary embodiment of the present disclosure, the power pattern 1200 may include a first power pattern 1210 electrically connected to the plurality of horizontal power lines HLIA_P and disposed to surround the outer periphery of the active area AA.

[0385] Reference Figure 12 In the power line structure of the display panel 110 according to an exemplary embodiment of the present disclosure, the power pattern 1200 may further include a second power pattern 1220 disposed outside the first power pattern 1210, and a plurality of connection patterns 1240 electrically connecting the first power pattern 1210 and the second power pattern 1220.

[0386] For example, the second power pattern 1220 may be configured as a grid-type electrode having at least one opening, but the embodiments of the present disclosure are not limited thereto. As another example, the second power pattern 1220 may be configured as a plate electrode without an opening, but the embodiments of the present disclosure are not limited thereto.

[0387] Reference Figure 12 In the power line structure of the display panel 110 according to the exemplary embodiment of the present disclosure, the power pattern 1200 may further include a third power pattern 1230. The third power pattern 1230 may be disposed outside the second power pattern 1220. The third power pattern 1230 may be electrically connected to the second power pattern 1220.

[0388] For example, the third power pattern 1230 may be formed of one electrode, but embodiments of the present disclosure are not limited thereto.

[0389] As another example, the third power pattern 1230 may be formed of two or more electrodes disposed on different metal layers. For example, the third power pattern 1230 may include a lower power pattern 1230a and an upper power pattern 1230b electrically connected to each other. The lower power pattern 1230a and the upper power pattern 1230b may be disposed in different metal layers and electrically connected via contact holes.

[0390] For example, lower power pattern 1230a may be disposed in first metal layer ML1, upper power pattern 1230b may be disposed in second metal layer ML2, and upper power pattern 1230b may be electrically connected to lower power pattern 1230a disposed in first metal layer ML1 through a hole of first planarization layer 331 between first metal layer ML1 and second metal layer ML2.

[0391] A display device 100 according to an exemplary embodiment of the present disclosure may include a substrate 111 including an active area AA and a non-active area NA for displaying an image; a plurality of data lines DL; a plurality of pixel electrodes PE; and a common electrode CE. The non-active area NA may be located outside or around the active area AA. The plurality of data lines DL may transmit data signals for displaying an image. The plurality of pixel electrodes PE may be disposed in the active area AA. The common electrode CE may overlap with the plurality of pixel electrodes PE.

[0392] The display device 100 according to an exemplary embodiment of the present disclosure may include a plurality of data link lines LIA electrically connected to the plurality of data lines DL and disposed in the active area AA as a bezel-reduced data link structure.

[0393] The display device 100 according to an exemplary embodiment of the present disclosure may include a plurality of power lines LIA_P arranged in a grid form in the active area AA and electrically connected to the common electrode CE or to which a power voltage applied to the common electrode CE is applied, as a power line structure associated with a bezel-reduced data link structure.

[0394] Based on the display device 100 according to the exemplary embodiment of the present disclosure, the plurality of power lines LIA_P may be disposed in the same metal layer as the plurality of data link lines LIA.

[0395] The display device 100 according to the exemplary embodiment of the present disclosure may further include a merged electrode 1250 electrically connected to the plurality of power lines LIA_P.

[0396] The display device 100 according to the exemplary embodiment of the present disclosure may further include a power pattern 1200 electrically connected to at least one of the plurality of power lines LIA_P or electrically connected to the merged electrode 1250 and disposed in the non-active area NA.

[0397] Based on the display device 100 according to the exemplary embodiment of the present disclosure, the power pattern 1200 may include a first power pattern 1210 disposed in the same metal layer as at least some of the plurality of data link lines LIA and disposed outside the active area AA.

[0398] Based on the display device 100 according to the exemplary embodiment of the present disclosure, the power pattern 1200 may include a second power pattern 1220 disposed in the same metal layer as the plurality of pixel electrodes PE and disposed outside the active area AA.

[0399] Based on the display device 100 according to the exemplary embodiment of the present disclosure, the power pattern 1200 may further include a third power pattern 1230 disposed outside the second power pattern 1220 and electrically connected to the second power pattern 1220 .

[0400] Based on the display device 100 according to the exemplary embodiment of the present disclosure, the power pattern 1200 may further include a plurality of connection patterns 1240 electrically connecting the first power pattern 1210 and the second power pattern 1220 .

[0401] A plurality of horizontal power lines HLIA_P may be disposed in the first metal layer ML1 .

[0402] A plurality of vertical power lines VLIA_P may be disposed in the second metal layer ML2 .

[0403] The merged electrode 1250 may be provided in the first metal layer ML1 or the second metal layer ML2, but the embodiments of the present disclosure are not limited thereto. Alternatively, the merged electrode 1250 may have a multilayer electrode structure provided on both the first metal layer ML1 and the second metal layer ML2, but the embodiments of the present disclosure are not limited thereto.

[0404] The first power pattern 1210 may be disposed in the second metal layer ML2. The second metal layer ML2 may be a metal layer different from the first metal layer ML1.

[0405] The second power pattern 1220 may be disposed in the third metal layer ML3. The third metal layer ML3 may be a metal layer different from the first metal layer ML1 and the second metal layer ML2.

[0406] The lower power pattern 1230 a and the upper power pattern 1230 b included in the third power pattern 1230 may be provided in different metal layers and electrically connected through a contact hole.

[0407] The lower power pattern 1230 a of the third power pattern 1230 may be disposed in the first metal layer ML1 together with the plurality of horizontal power lines HLIA_P, but is not limited thereto.

[0408] The upper power pattern 1230 b of the third power pattern 1230 may be disposed in the second metal layer ML2 together with the plurality of vertical power lines VLIA_P, but is not limited thereto.

[0409] As an example, the upper power pattern 1230 b of the third power pattern 1230 may be electrically connected to the lower power pattern 1230 a of the third power pattern 1230 through a hole passing through the first planarization layer 331 .

[0410] The upper power pattern 1230 b of the third power pattern 1230 may be electrically connected to the lower power pattern 1230 a of the third power pattern 1230 through a hole of the first planarization layer 331 , which is a first insulating layer between the first metal layer ML1 and the second metal layer ML2 .

[0411] As an example, the second power pattern 1220 may be electrically connected to the upper power pattern 1230 b of the third power pattern 1230 through a hole passing through the second planarization layer 332 .

[0412] The second power pattern 1220 may be electrically connected to the upper power pattern 1230 b of the third power pattern 1230 through a hole of the second planarization layer 332 , which is a second insulating layer between the second metal layer ML2 and the third metal layer ML3 .

[0413] Reference Figure 12 The display panel 110 according to an exemplary embodiment of the present disclosure may further include an intra-panel gate circuit GIPC disposed in the non-active area NA. The intra-panel gate circuit GIPC may be a gate intra-panel (GIP) type gate driving circuit 130, but is not limited thereto.

[0414] The intra-panel gate circuit GIPC may overlap at least one of the second power pattern 1220 and the connection pattern 1240 .

[0415] The intra-panel gate circuit GIPC may be disposed inside the third power pattern 1230. For example, the intra-panel gate circuit GIPC may not overlap with the third power pattern 1230.

[0416] Based on the power line structure according to the exemplary embodiment of the present disclosure, the power supply voltage can be distributed and supplied through the power line structure. Therefore, the heat concentration that occurs when the power supply voltage is concentrated at a specific location can be reduced or prevented. For example, since the supply path of the power supply voltage is increased, the heat generated by the power supply voltage being concentrated in the corner area of ​​the display panel can be reduced or prevented. For example, since the four surfaces of the power pattern 1220 are configured in a grid form by connecting multiple power lines LIA_P to the power pattern 1220, the heat generated in the corner area below the display panel can be reduced or prevented.

[0417] In addition, based on the power line structure according to the exemplary embodiment of the present disclosure, an undesirable drop in the power voltage can be reduced. Therefore, even if the power voltage input to the display panel 110 is not increased in consideration of the voltage drop, the power voltage can be normally supplied to the entire area of ​​the display panel 110 (e.g., the entire common electrode CE).

[0418] Hereinafter, the power line structure according to the exemplary embodiment of the present disclosure described above is briefly described with respect to each of main areas A, B, and C. FIG.

[0419] Figure 13 A first area A of the display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0420] Reference Figure 13 , the first area A in the active area AA of the display panel 110 according to an exemplary embodiment of the present disclosure may be an area where the data link line LIA is not disposed.

[0421] In the first region A, a horizontal power line HLIA_P and a vertical power line VLIA_P may be provided by using metal layers ML1 and ML2 where the data link line LIA is provided.

[0422] In the first region A, the horizontal power lines HLIA_P may be arranged to extend along the row direction. In the first region A, the vertical power lines VLIA_P may be arranged to extend along the column direction, but the present invention is not limited thereto.

[0423] In a portion of the first region A, the horizontal power line HLIA_P and the vertical power line VLIA_P may intersect each other. In a portion of the first region A, the horizontal power line HLIA_P and the vertical power line VLIA_P may overlap each other. In a portion of the first region A, the horizontal power line HLIA_P and the vertical power line VLIA_P may be electrically connected to each other.

[0424] The horizontal power line HLIA_P and the vertical power line VLIA_P may be electrically connected to each other through the first power connection hole CNT_P1 in a partial area of ​​the first area A. The first power connection hole CNT_P1 may be a contact hole provided in the active area AA.

[0425] The horizontal power line HLIA_P and the vertical power line VLIA_P may be provided in different metal layers. The horizontal power line HLIA_P may be provided in the first metal layer ML1, and the vertical power line VLIA_P may be provided in the second metal layer ML2, but is not limited thereto.

[0426] Figure 14 The second region B of the display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0427] Reference Figure 14 , in the second area B of the active area AA of the display panel 110 according to an exemplary embodiment of the present disclosure, a horizontal data link line HLIA among the data link lines LIA may be disposed, and a vertical power line VLIA_P may be disposed.

[0428] In the second region B, the horizontal data link lines HLIA may be arranged to extend along the row direction. In the second region B, the vertical power lines VLIA_P may be arranged to extend along the column direction, but the present invention is not limited thereto.

[0429] The horizontal data link line HLIA and the vertical power line VLIA_P may cross each other in a partial area of ​​the second area B. In the second area B, the horizontal data link line HLIA and the vertical power line VLIA_P may overlap each other.

[0430] In a portion of the second region B, the horizontal data link line HLIA and the vertical power line VLIA_P may be disposed in different metal layers. In a portion of the second region B, the horizontal data link line HLIA may be disposed in the first metal layer ML1, and the vertical power line VLIA_P may be disposed in the second metal layer ML2, but is not limited thereto.

[0431] Figure 15 The third region C of the display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0432] Reference Figure 15 , in the third area C of the active area AA of the display panel 110 according to an exemplary embodiment of the present disclosure, a vertical data link line VLIA among the data link lines LIA may be disposed, and a horizontal power line HLIA_P may be disposed.

[0433] In the third region C, the vertical data link lines VLIA may be arranged to extend in a column direction, and the horizontal power lines HLIA_P may be arranged to extend in a row direction, but the present invention is not limited thereto.

[0434] The vertical data link line VLIA and the horizontal power line HLIA_P may cross each other in a partial area of ​​the third area C. The vertical data link line VLIA and the horizontal power line HLIA_P may overlap each other in a partial area of ​​the third area C.

[0435] The vertical data link line VLIA and the horizontal power line HLIA_P may be disposed in different metal layers in a portion of the third region C. In a portion of the third region C, the vertical data link line VLIA may be disposed in the second metal layer ML2, and the horizontal power line HLIA_P may be disposed in the first metal layer ML1.

[0436] Figure 16 A boundary area between the second area B and the third area C of the display panel 110 according to an exemplary embodiment of the present disclosure is shown.

[0437] Reference Figure 16 , a boundary area between the second area B and the third area C may be an area where the vertical data link line VLIA and the horizontal data link line HLIA are electrically connected.

[0438] The vertical power lines VLIA_P, the vertical data link lines VLIA, and the data lines DL may be arranged to extend in a column direction, and the horizontal data link lines HLIA and the horizontal power lines HLIA_P may be arranged to extend in a row direction, but are not limited thereto.

[0439] The vertical data link line VLIA and the horizontal data link line HLIA may be electrically connected through the link line connection hole CNT_LIA. The horizontal data link line HLIA may be electrically connected to the corresponding data line DL through the data line connection hole CNT_DL.

[0440] A horizontal power line HLIA_P disposed in the same row as the horizontal data link line HLIA may be disposed in a boundary region between the second region B and the third region C. The horizontal power line HLIA_P may be disposed to be disconnected from the horizontal data link line HLIA disposed in the same row.

[0441] A vertical power line VLIA_P disposed in the same column as the vertical data link line VLIA may be disposed in a boundary region between the second region B and the third region C. The vertical power line VLIA_P may be disposed to be disconnected from the vertical data link line VLIA disposed in the same column.

[0442] In the following, reference is made to Figure 17 and Figure 18 describe Figure 12 The power line structure in the non-corner area NCA and the power line structure in the corner area CA. Figure 19 and Figure 20 Describe the structure or vertical structure of the power line structure.

[0443] Figure 17 is a plan view illustrating a non-corner area NCA in the display panel 110 according to an exemplary embodiment of the present disclosure. Figure 18 is a plan view illustrating a corner area CA in the display panel 110 according to an exemplary embodiment of the present disclosure. Figure 19 It is along Figure 17 A cross-sectional view taken along line X1-X1'. Figure 20 It is along Figure 17 A cross-sectional view taken along line X2-X2'.

[0444] Reference Figure 17 and Figure 18 The power line structure of the display panel 110 according to an exemplary embodiment of the present disclosure may include a plurality of power lines LIA_P including a horizontal power line HLIA_P and a vertical power line VLIA_P, a first power pattern 1210 , a second power pattern 1220 , and a third power pattern 1230 .

[0445] Reference Figure 17 , the power line structure of the display panel 110 according to the exemplary embodiment of the present disclosure may further include a connection pattern 1240 connecting the first power pattern 1210 and the second power pattern 1220 .

[0446] Reference Figure 17 and Figure 18 A plurality of power lines LIA_P including horizontal power lines HLIA_P and vertical power lines VLIA_P may be disposed in the active area AA, and a first power pattern 1210 , a connection pattern 1240 , a second power pattern 1220 , and a third power pattern 1230 may be disposed in the non-active area NA.

[0447] like Figure 17 and Figure 18 As shown, all of the horizontal power line HLIA_P, the vertical power line VLIA_P, the first power pattern 1210, the second power pattern 1220, and the third power pattern 1230 may be disposed in each of the non-corner area NCA and the corner area CA.

[0448] like Figure 17 and Figure 18 As shown, the plurality of connection patterns 1240 may be provided in the non-corner area NCA but may not be provided in the corner area CA, but embodiments of the present disclosure are not limited thereto. As another example, the plurality of connection patterns 1240 may be provided in both the non-corner area NCA and the corner area CA, but embodiments of the present disclosure are not limited thereto.

[0449] The presence or absence of the plurality of connection patterns 1240 in the corner area CA may vary depending on whether there is a pattern or line to be provided in the second metal layer ML2 in which the plurality of connection patterns 1240 are provided between the first power pattern 1210 and the second power pattern 1220 in the corner area CA.

[0450] When a pattern or line in the second metal layer ML2 to be disposed between the first power pattern 1210 and the second power pattern 1220 exists in the corner area CA, the connection pattern 1240 may exist in the corner area CA.

[0451] If a pattern or line in the second metal layer ML2 to be disposed between the first power pattern 1210 and the second power pattern 1220 necessarily exists in the corner area CA, the connection pattern 1240 may not exist in the corner area CA.

[0452] In the corner area CA, when a pattern or line disposed in a region between the first power pattern 1210 and the second power pattern 1220 must be disposed in the second metal layer ML2 , the connection pattern 1240 may not exist in the corner area CA.

[0453] In the corner area CA, when the pattern or line may not be configured as a skip structure in the area between the first power pattern 1210 and the second power pattern 1220 , the connection pattern 1240 may not exist in the corner area CA.

[0454] Reference Figure 17 and Figure 18 In the non-corner area NCA and the corner area CA, the horizontal power line HLIA_P may extend from the active area AA to the non-active area NA to connect to the first power pattern 1210 disposed in the non-active area NA. In the active area AA, the horizontal power line HLIA_P and the vertical power line VLIA_P may be electrically connected to each other through the first power connection hole CNT_P1. In the active area AA, the light-emitting elements ED1, ED2, and ED3 may be disposed around the horizontal power line HLIA_P and the vertical power line VLIA_P.

[0455] The horizontal power line HLIA_P may be electrically connected to the first power pattern 1210 through the second power connection hole CNT_P2. The second power connection hole CNT_P2 may be a contact hole present in the non-active area NA.

[0456] Reference Figure 17 In the non-corner area NCA, the first power pattern 1210 may be electrically connected to the second power pattern 1220 through the connection pattern 1240. The second power pattern 1220 and the connection pattern 1240 may be electrically connected through the third power connection hole CNT_P3.

[0457] Reference Figure 17 , each of the plurality of connection patterns 1240 may correspond to a protrusion protruding in a row direction from the first power pattern 1210. For example, each of the plurality of connection patterns 1240 may be integrated with the first power pattern 1210.

[0458] Reference Figure 17 and Figure 18 , the second power pattern 1220 may be configured as a mesh-type electrode having at least one opening. However, exemplary embodiments of the present disclosure are not limited thereto.

[0459] Reference Figure 17 and Figure 18 The display panel 110 according to the exemplary embodiment of the present disclosure may further include a plurality of signal lines 1710 and 1720 disposed between the first power pattern 1210 and the second power pattern 1220 .

[0460] Reference Figure 17 and Figure 18, the plurality of signal lines 1710 and 1720 may include a first signal line 1710 for transmitting a first signal and a second signal line 1720 for transmitting a second signal.

[0461] For example, the driving signal may include two or more of an initialization voltage, a bias voltage, a reference voltage, a first pixel electrode reset voltage (a first anode reset voltage), and a second pixel electrode reset voltage (a second anode reset voltage), but the embodiments of the present disclosure are not limited thereto. The driving signal may be a voltage having a constant voltage level (a direct current voltage) or a voltage having a variable voltage level (an alternating current voltage).

[0462] Reference Figure 17 , the plurality of signal lines 1710 and 1720 disposed between the first power pattern 1210 and the second power pattern 1220 may extend in a column direction and may cross at least one of the plurality of connection patterns 1240 .

[0463] Reference Figure 17 , each of the plurality of signal lines 1710 and 1720 may include intersection portions CP1 and CP2 that intersect and overlap with the at least one connection pattern 1240, and non-intersection portions NCP1 and NCP2 that do not intersect and overlap with the at least one connection pattern 1240. In each of the plurality of signal lines 1710 and 1720, the non-intersection portions NCP1 and NCP2 may be portions other than the intersection portions CP1 and CP2.

[0464] Reference Figure 17 , the intersection portions CP1 and CP2 in each of the plurality of signal lines 1710 and 1720 may be disposed in a first metal layer ML1 different from the second metal layer ML2 in which the connection pattern 1240 is disposed. In each of the plurality of signal lines 1710 and 1720, the non-intersection portions NCP1 and NCP2 may be disposed in the same second metal layer ML2 as the connection pattern 1240.

[0465] In each of the plurality of signal lines 1710 and 1720 , a structure in which intersection portions CP1 and CP2 overlapping (intersecting) the connection pattern 1240 and non-intersection portions NCP1 and NCP2 not overlapping (intersecting) the connection pattern 1240 are provided in different metal layers may be referred to as a jumping structure.

[0466] Reference Figure 17 and Figure 18The plurality of signal lines disposed between the first power pattern 1210 and the second power pattern 1220 may further include a gate drive-related signal line 1750 for transmitting gate drive-related signals. For example, the gate drive-related signals may include a gate clock signal, a high-level gate voltage, and a low-level gate voltage, but the embodiments of the present disclosure are not limited thereto. The gate drive-related signals may also include various control signals for gate drive (e.g., a reset signal, a start signal, etc.).

[0467] For example, the gate driving related signal line 1750 may be disposed in a different metal layer (eg, the first metal layer ML1 ) from the connection pattern 1240 .

[0468] As another example, each of the gate drive-related signal lines 1750 may include a portion disposed in the same metal layer as the connection pattern 1240. In this case, the gate drive-related signal line 1750 may have a skipping structure. For example, the gate drive-related signal line 1750 may include an intersection portion that intersects and overlaps with at least one connection pattern 1240 and a non-intersection portion that does not intersect or overlap with at least one connection pattern 1240. In the gate drive-related signal line 1750, the non-intersection portion may be a portion other than the intersection portion. The intersection portion of the gate drive-related signal line 1750 may be disposed in the first metal layer ML1. In the gate drive-related signal line 1750, the non-intersection portion may be electrically connected to the intersection portion and may be disposed in the same second metal layer ML2 as the connection pattern 1240.

[0469] Reference Figure 17 and Figure 18 , the display panel 110 according to the exemplary embodiment of the present disclosure may further include a plurality of signal lines 1730 and 1740 disposed between the active area AA and the first power pattern 1210 .

[0470] Reference Figure 17 and Figure 18 The plurality of signal lines 1730 and 1740 disposed between the active area AA and the first power pattern 1210 may further include a third signal line 1730 for transmitting a third signal and a fourth signal line 1740 for transmitting a fourth signal.

[0471] The third signal and the fourth signal may be drive signals necessary to drive the plurality of sub-pixels SP. For example, the drive signal may include two or more of an initialization voltage, a bias voltage, a reference voltage, a first pixel electrode reset voltage (a first anode reset voltage), and a second pixel electrode reset voltage (a second anode reset voltage), but the embodiments of the present disclosure are not limited thereto. The drive signal may be a voltage having a constant voltage level (a direct current voltage) or a voltage having a variable voltage level (an alternating current voltage).

[0472] Reference Figure 17 and Figure 18 , a bank opening region 1760 , in which an opening of the bank 333 is formed, may exist outside the third power pattern 1230 .

[0473] Reference Figure 19 and Figure 20 The display panel 110 according to an exemplary embodiment of the present disclosure may include: an insulating layer including a second interlayer insulating layer 323, a first planarizing layer 331, and a second planarizing layer 332; and a metal layer including a first metal layer ML1, a second metal layer ML2, and a third metal layer ML3 for a power line structure, but the embodiments of the present disclosure are not limited thereto.

[0474] The first metal layer ML1 may be disposed on the second interlayer insulating layer 323. Specifically, the first metal layer ML1 may be disposed on a portion of the second interlayer insulating layer 323. The first metal layer ML1 may be disposed between the second interlayer insulating layer 323 and the first planarization layer 331.

[0475] The second metal layer ML2 may be disposed on the first planarization layer 331. Specifically, the second metal layer ML2 may be disposed on a portion of the first planarization layer 331. The second metal layer ML2 may be disposed between the first planarization layer 331 and the second planarization layer 332.

[0476] The third metal layer ML3 may be disposed on the second planarization layer 332. Specifically, the third metal layer ML3 may be disposed on a portion of the second planarization layer 332.

[0477] The horizontal power line HLIA_P may be disposed in the first metal layer ML1 , and the vertical power line VLIA_P connected to the horizontal power line HLIA_P in the active area AA may be disposed in the second metal layer ML2 .

[0478] The merged electrode 1250 connected to the vertical power line VLIA_P may be provided in the first metal layer ML1 or the second metal layer ML2. Alternatively, the merged electrode 1250 may have a multilayer electrode structure provided on both the first metal layer ML1 and the second metal layer ML2, but the embodiments of the present disclosure are not limited thereto.

[0479] The first power pattern 1210 may be disposed in the second metal layer ML2 .

[0480] The first power pattern 1210 may be electrically connected to the horizontal power line HLIA_P extending from the active area AA to the non-active area NA through a hole passing through the first planarization layer 331. The hole of the first planarization layer 331 may correspond to the second power connection hole CNT_P2.

[0481] The first power pattern 1210 may include a connection pattern 1240. The connection pattern 1240 may protrude outward.

[0482] The second power pattern 1220 may be disposed in the third metal layer ML3 .

[0483] The second power pattern 1220 may be electrically connected to the connection pattern 1240 protruding from the first power pattern 1210 through the hole of the second planarization layer 332. The hole of the second planarization layer 332 may correspond to the third power connection hole CNT_P3.

[0484] The third signal line 1730 and the fourth signal line 1740 may be disposed in the second metal layer ML2 .

[0485] In the first and second signal lines 1710 and 1720 , intersections CP1 and CP2 overlapping the connection pattern 1240 may be disposed in the first metal layer ML1 , and non-intersections NCP1 and NCP2 not overlapping the connection pattern 1240 may be disposed in the second metal layer ML2 .

[0486] The gate driving related signal line 1750 may overlap with the connection pattern 1240 .

[0487] The gate driving related signal line 1750 may be disposed in a first metal layer ML1 different from the connection pattern 1240 .

[0488] Hereinafter, the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 used in the power line structure according to the exemplary embodiment of the present disclosure are described. Figure 3 .

[0489] Each of the plurality of sub-pixels SP may include: a light emitting element ED including a pixel electrode PE, an intermediate layer EL, and a common electrode CE; and a transistor ( ) for driving the light emitting element ED. Figure 3 The second transistor TFT2 in the circuit).

[0490] The first metal layer ML1 may be a metal layer for setting a source electrode or a drain electrode of a transistor. The second metal layer ML2 may be a metal layer between the source electrode or the drain electrode of the transistor and the pixel electrode PE. The third metal layer ML3 may be a metal layer for setting a pixel electrode PE.

[0491] For example, the source electrode or drain electrode of the transistor may be provided in the first metal layer ML1. The relay electrode RE electrically connecting the source electrode or drain electrode of the transistor with the pixel electrode PE may be provided in the second metal layer ML2. The pixel electrode PE may be provided in the third metal layer ML3.

[0492] Various embodiments of the present disclosure described above are described below.

[0493] According to various embodiments of the present disclosure, a display device may include: a substrate, the substrate including an active area including a plurality of sub-pixels and an inactive area outside the active area; a plurality of data lines, the plurality of data lines being connected to the plurality of sub-pixels; a plurality of data link lines, the plurality of data link lines being electrically connected to the plurality of data lines in the active area; a plurality of power lines, the plurality of power lines being arranged in the active area and being arranged in the same metal layer as at least one of the plurality of data lines; and a power pattern, the power pattern being arranged in the inactive area and electrically connected to at least one of the plurality of power lines.

[0494] According to various embodiments of the present disclosure, the plurality of data link lines may include a plurality of first data link lines (a plurality of horizontal data link lines) each extending along a first direction (row direction) in the active area, and a plurality of second data link lines (a plurality of vertical data link lines) each extending along a second direction (column direction) different from the first direction in the active area.

[0495] According to various embodiments of the present disclosure, the plurality of power lines may include a plurality of first power lines (a plurality of horizontal power lines) extending along a first direction (row direction) in the active area, and a plurality of second power lines (a plurality of vertical power lines) each extending along a second direction (column direction) in the active area and electrically connected to the plurality of first power lines.

[0496] According to various embodiments of the present disclosure, the plurality of first power lines may be arranged in parallel with the plurality of first data link lines in the active region. The plurality of second power lines may be arranged in parallel with the plurality of second data link lines in the active region.

[0497] According to various embodiments of the present disclosure, the plurality of first power lines and the plurality of second power lines may be arranged in a grid form.

[0498] The display device according to various embodiments of the present disclosure may further include a merged electrode electrically connected to at least one second power line of the plurality of second power lines and disposed in the inactive region.

[0499] According to various embodiments of the present disclosure, at least one first power line among the plurality of first power lines can be arranged in the same row as at least one first data link line among the plurality of first data link lines, and at least one second power line among the plurality of second power lines can be arranged in the same column as at least one second data link line among the plurality of second data link lines.

[0500] According to various embodiments of the present disclosure, the plurality of first power lines may be disposed in a first metal layer in which the plurality of first data link lines are disposed, and the plurality of second power lines may be disposed in a second metal layer in which the plurality of second data link lines are disposed.

[0501] According to various embodiments of the present disclosure, the active area may include: a first area, in which the multiple second data link lines and the multiple first data link lines are not set; a second area, in which the multiple first data link lines are set; and a third area, in which the multiple second data link lines are set.

[0502] According to various embodiments of the present disclosure, the plurality of power lines may extend from the first area to at least a portion of the second area or the third area, and at least some of the plurality of power lines may have a different length from the remaining power lines.

[0503] According to various embodiments of the present disclosure, the plurality of second data link lines and the plurality of first data link lines may be electrically connected in a boundary region between the second region and the third region.

[0504] According to various embodiments of the present disclosure, the power pattern may include a first power pattern electrically connected to the plurality of first power lines and disposed outside the active area.

[0505] According to various embodiments of the present disclosure, the power pattern may further include: a second power pattern disposed outside the first power pattern; and a plurality of connection patterns electrically connected to the first power pattern and the second power pattern.

[0506] According to various embodiments of the present disclosure, the plurality of first power lines may be provided in a first metal layer, the first power pattern may be provided in a second metal layer different from the first metal layer, and the second power pattern may be provided in a third metal layer different from the first and second metal layers.

[0507] According to various embodiments of the present disclosure, each of the plurality of sub-pixels may include: a light-emitting element including a pixel electrode, an intermediate layer, and a common electrode; and a transistor for driving the light-emitting element. The first metal layer may be a metal layer on which a source electrode or a drain electrode of the transistor is provided. The second metal layer may be a metal layer between the source electrode or the drain electrode of the transistor and the pixel electrode. The third metal layer may be a metal layer on which the pixel electrode is provided.

[0508] According to various embodiments of the present disclosure, the plurality of connection patterns may be provided to protrude from the first power pattern in the first direction (row direction).

[0509] According to various embodiments of the present disclosure, the second power pattern may be configured as a mesh-type electrode having at least one opening.

[0510] According to various embodiments of the present disclosure, the power pattern may further include a third power pattern disposed outside the second power pattern and electrically connected to the second power pattern.

[0511] According to various embodiments of the present disclosure, the third power pattern may include a lower power pattern and an upper power pattern electrically connected to each other. The lower power pattern may be provided in the first metal layer together with the plurality of first power lines. The upper power pattern may be provided in the second metal layer together with the plurality of second power lines.

[0512] According to various embodiments of the present disclosure, the upper power pattern may be electrically connected to the lower power pattern provided in the first metal layer through a hole of the first insulating layer between the first metal layer and the second metal layer.

[0513] According to various embodiments of the present disclosure, the second power pattern may be electrically connected to the upper power pattern through a hole of the second insulating layer between the second metal layer and the third metal layer.

[0514] The display device according to various embodiments of the present disclosure may further include a plurality of signal lines disposed between the first power pattern and the second power pattern, extending along the second direction (column direction), and overlapping at least one connection pattern of the plurality of connection patterns.

[0515] According to various embodiments of the present disclosure, each of the plurality of signal lines may include an intersection portion intersecting at least one of the plurality of connection patterns and a non-intersection portion not intersecting at least one of the plurality of connection patterns.

[0516] According to various embodiments of the present disclosure, the intersection portion may be provided in a metal layer different from a metal layer provided with the connection pattern, and the non-intersection portion may be provided in the same metal layer as the connection pattern.

[0517] According to various embodiments of the present disclosure, the plurality of connection patterns may be provided in a non-corner region of the substrate, but may not be provided in a corner region of the substrate.

[0518] The display device according to various embodiments of the present disclosure may further include a plurality of pixel electrodes, an intermediate layer on the plurality of pixel electrodes, and a common electrode on the intermediate layer. The power supply voltage applied to the common electrode may be applied to a power supply pattern.

[0519] According to various embodiments of the present disclosure, a display device may include: a substrate, the substrate including an active area for displaying an image and an inactive area outside the active area; a plurality of data link lines, the plurality of data link lines being electrically connected to a plurality of data lines and being arranged in the active area; a plurality of pixel electrodes, the plurality of pixel electrodes being arranged in the active area; a common electrode, the common electrode overlapping with the plurality of pixel electrodes; and a plurality of power lines, the plurality of power lines being arranged in a grid form in the active area and being electrically connected to the common electrodes or receiving a power supply voltage applied to the common electrodes.

[0520] According to various embodiments of the present disclosure, the plurality of power lines may be provided in the same metal layer as the plurality of data link lines.

[0521] The display device according to various embodiments of the present disclosure may further include: a merged electrode electrically connected to the plurality of power lines; and a power pattern electrically connected to at least one of the plurality of power lines or electrically connected to the merged electrode and disposed in the inactive area.

[0522] According to various embodiments of the present disclosure, the power pattern may include a first power pattern disposed in the same metal layer as at least some of the plurality of data link lines and disposed outside the active area.

[0523] According to various embodiments of the present disclosure, the power supply pattern may include a second power supply pattern disposed in the same metal layer as the plurality of pixel electrodes and disposed outside the active area.

[0524] According to various embodiments of the present disclosure, a display device may include: a substrate including an active area including a plurality of sub-pixels and an inactive area outside the active area; a plurality of data lines connected to the plurality of sub-pixels; and a plurality of data link lines electrically connecting a plurality of pads in the inactive area and the plurality of data lines in the active area.

[0525] According to various embodiments of the present disclosure, the plurality of data link lines may include a plurality of first data link lines each extending along a first direction in the active region and a plurality of second data link lines each extending along a second direction different from the first direction in the active region.

[0526] According to various embodiments of the present disclosure, the plurality of second data link lines may electrically connect the plurality of pads and the plurality of first data link lines, and the plurality of first data link lines may electrically connect the plurality of second data link lines and the plurality of data lines.

[0527] A vehicle according to various embodiments of the present disclosure may include at least one display device.

[0528] According to various embodiments of the present disclosure, a display device may include: a plurality of data lines, which are arranged in the active area; a plurality of pads, which are arranged in the non-active area; and a plurality of data link lines, which are arranged in the active area and the non-active area and are configured to electrically connect the plurality of pads and the plurality of data lines, wherein the plurality of data link lines include a plurality of first data link lines each extending along a first direction in the active area and a plurality of second data link lines each extending along a second direction different from the first direction in the active area, and wherein the plurality of second data link lines electrically connect the plurality of pads and the plurality of first data link lines, and the plurality of first data link lines electrically connect the plurality of second data link lines and the plurality of data lines.

[0529] According to exemplary embodiments of the present disclosure, a display device having a data link structure capable of reducing a bezel may be provided.

[0530] According to exemplary embodiments of the present disclosure, a display device having a power line structure capable of stably transmitting a power voltage may be provided.

[0531] According to exemplary embodiments of the present disclosure, a display device having a power line structure suitable for a data link structure capable of reducing a bezel may be provided.

[0532] According to exemplary embodiments of the present disclosure, a display device having a power line structure capable of distributively supplying a power voltage may be provided.

[0533] According to exemplary embodiments of the present disclosure, a display device capable of alleviating or preventing heat concentration due to a power supply voltage may be provided.

[0534] According to exemplary embodiments of the present disclosure, a display device having a power line structure capable of reducing an undesirable voltage drop of a power voltage may be provided.

[0535] According to the exemplary embodiments of the present disclosure, the weight of the display device may be reduced by reducing the bezel through the data link structure capable of reducing the bezel.

[0536] According to exemplary embodiments of the present disclosure, the need to increase the power supply voltage to be input to the display panel in consideration of the voltage drop can be eliminated by reducing the voltage drop of the power supply voltage, thereby ensuring additional voltage usage margin and achieving low power consumption design.

[0537] The display device according to various embodiments of the present disclosure can be applied to mobile devices, video phones, smart watches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, slidable devices, deformable devices, electronic notebooks, electronic books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, notebook computers, workstations, navigation devices, car navigations, vehicle displays, vehicle devices, theater devices, theater displays, televisions, wallpaper devices, signage devices, game consoles, laptop computers, monitors, cameras, camcorders, and home appliances, etc.

[0538] The above embodiments are merely examples, and those skilled in the art will appreciate that various modifications may be made thereto without departing from the scope of the present disclosure. Therefore, the embodiments described herein are provided for illustrative purposes only and are not intended to limit the scope of the present disclosure, and it should be understood that the scope of the present disclosure is not limited by the embodiments.

[0539] CROSS-REFERENCE TO RELATED APPLICATIONS

[0540] This application claims priority to Korean Patent Application No. 10-2024-0025252, filed on February 21, 2024, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a substrate comprising an active area including a plurality of sub-pixels and an inactive area outside the active area; a plurality of data lines connected to the plurality of sub-pixels; a plurality of data link lines electrically connected to the plurality of data lines in the active area; a plurality of power lines, the plurality of power lines being disposed in the active area and being disposed in the same metal layer as at least one data line of the plurality of data lines; as well as A power pattern is provided in the inactive region and is electrically connected to at least one power line of the plurality of power lines.

2. The display device according to claim 1, wherein The plurality of data link lines include a plurality of first data link lines each extending along a first direction in the active area and a plurality of second data link lines each extending along a second direction different from the first direction in the active area, and The plurality of power lines include a plurality of first power lines arranged in parallel with the first data link lines in the active area and a plurality of second power lines arranged in parallel with the plurality of second data link lines in the active area.

3. The display device according to claim 2, wherein: The plurality of first power lines and the plurality of second power lines are arranged in a grid form. 4 . The display device according to claim 2 , further comprising a merged electrode electrically connected to at least one second power supply line of the plurality of second power supply lines and disposed in the inactive region.

5. The display device according to claim 2, wherein At least one first power line among the plurality of first power lines and at least one first data link line among the plurality of first data link lines are arranged in the same row, and at least one second power line among the plurality of second power lines and at least one second data link line among the plurality of second data link lines are arranged in the same column. The display device according to claim 2 , wherein: The active area includes: a first area, in which the plurality of second data link lines and the plurality of first data link lines are not arranged; a second area, in which the plurality of first data link lines are arranged; and a third area, in which the plurality of second data link lines are arranged; The plurality of power lines extend from the first area to at least a portion of the second area or the third area, and at least some of the plurality of power lines have a different length from the remaining power lines.

7. The display device according to claim 6, wherein: The plurality of second data link lines and the plurality of first data link lines are electrically connected in a boundary region between the second region and the third region.

8. The display device according to claim 2, wherein: The power pattern includes a first power pattern electrically connected to the plurality of first power lines and disposed outside the active area.

9. The display device according to claim 8, wherein The power pattern further includes: a second power pattern disposed outside the first power pattern; and A plurality of connection patterns are electrically connected to the first power pattern and the second power pattern.

10. The display device according to claim 9, wherein The plurality of first power lines are provided in the first metal layer where the plurality of first data link lines are provided, The plurality of second power lines are provided in a second metal layer provided with the plurality of second data link lines, and the second metal layer is different from the first metal layer. wherein the first power pattern is provided in the second metal layer, and The second power supply pattern is provided in a third metal layer different from the first metal layer and the second metal layer.

11. The display device according to claim 10, wherein: Each of the plurality of sub-pixels includes: a light emitting element including a pixel electrode, an intermediate layer, and a common electrode; and a transistor for driving the light emitting element. The first metal layer is a metal layer provided with a source electrode or a drain electrode of the transistor. The second metal layer is a metal layer between the source electrode or the drain electrode of the transistor and the pixel electrode, and The third metal layer is a metal layer on which the pixel electrode is provided.

12. The display device according to claim 9, wherein The plurality of connection patterns are provided to protrude from the first power pattern in the first direction.

13. The display device according to claim 9, wherein: The second power pattern is configured as a mesh type electrode having at least one opening.

14. The display device according to claim 9, wherein The power pattern further includes a third power pattern disposed outside the second power pattern and electrically connected to the second power pattern.

15. The display device according to claim 14, wherein The third power pattern includes a lower power pattern and an upper power pattern electrically connected to each other, wherein the lower power pattern and the plurality of first power lines are disposed in a first metal layer, and the upper power pattern and the plurality of second power lines are disposed in a second metal layer, and The upper power pattern is electrically connected to the lower power pattern disposed in the first metal layer through a hole of the first insulating layer between the first metal layer and the second metal layer.

16. The display device according to claim 15, wherein The second power pattern is electrically connected to the upper power pattern through a hole of the second insulating layer between the second metal layer and the third metal layer. 17 . The display device according to claim 9 , further comprising a plurality of signal lines disposed between the first power pattern and the second power pattern, extending along the second direction, and overlapping at least one connection pattern of the plurality of connection patterns.

18. The display device according to claim 17, wherein: Each of the plurality of signal lines includes an intersection portion intersecting at least one connection pattern among the plurality of connection patterns and a non-intersection portion not intersecting at least one connection pattern among the plurality of connection patterns, and The intersection portion is provided in a metal layer different from a metal layer provided with the connection pattern, and the non-intersection portion is provided in the same metal layer as the connection pattern.

19. The display device according to claim 9, wherein The plurality of connection patterns are disposed in a non-corner region of the substrate, but are not disposed in a corner region of the substrate.

20. The display device according to claim 1, further comprising: a plurality of pixel electrodes; an intermediate layer, the intermediate layer being on the plurality of pixel electrodes; as well as a common electrode, the common electrode being on the intermediate layer, The power voltage applied to the common electrode is applied to the power pattern.

21. A display device, comprising: a substrate comprising an active area for displaying an image and an inactive area outside the active area; a plurality of data link lines electrically connected to the plurality of data lines and disposed in the active area; a plurality of pixel electrodes, wherein the plurality of pixel electrodes are arranged in the active area; a common electrode, the common electrode overlapping the plurality of pixel electrodes; as well as A plurality of power supply lines are provided in a grid form in the active area and are electrically connected to the common electrode or receive a power supply voltage applied to the common electrode.

22. The display device according to claim 21, further comprising: a merging electrode, the merging electrode being electrically connected to the plurality of power lines; as well as A power pattern is electrically connected to at least one of the plurality of power lines or to the merged electrode and is disposed in the inactive region.

23. The display device according to claim 22, wherein: The power supply pattern includes a first power supply pattern disposed in a same metal layer as at least some of the plurality of data link lines and disposed outside the active area.

24. The display device according to claim 22, wherein: The power supply pattern includes a second power supply pattern disposed in the same metal layer as the plurality of pixel electrodes and disposed outside the active area.

25. A display device, comprising: a substrate comprising an active area including a plurality of sub-pixels and an inactive area outside the active area; a plurality of data lines connected to the plurality of sub-pixels; a plurality of data link lines electrically connecting the plurality of pads in the non-active area and the plurality of data lines in the active area; The plurality of data link lines include a plurality of first data link lines each extending along a first direction in the active area and a plurality of second data link lines each extending along a second direction different from the first direction in the active area, and The plurality of second data link lines electrically connect the plurality of pads and the plurality of first data link lines, and the plurality of first data link lines electrically connect the plurality of second data link lines and the plurality of data lines.

26. A vehicle, comprising: At least one display device according to any one of claims 1 to 25.

27. A display panel, comprising an active area and an inactive area, the display panel comprising: a plurality of data lines, wherein the plurality of data lines are arranged in the active area; a plurality of pads, the plurality of pads being arranged in the inactive area; as well as a plurality of data link lines, the plurality of data link lines being disposed in the active area and the inactive area and configured to electrically connect the plurality of pads and the plurality of data lines, The plurality of data link lines include a plurality of first data link lines each extending along a first direction in the active area and a plurality of second data link lines each extending along a second direction different from the first direction in the active area, and The plurality of second data link lines electrically connect the plurality of pads and the plurality of first data link lines, and the plurality of first data link lines electrically connect the plurality of second data link lines and the plurality of data lines.

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