System and method for manufacturing printed circuit board

Abstract

Systems and methods for overcoming technical issues associated with processing and manufacturing printed circuit boards are provided. In some embodiments, the systems and methods include a process of removing or reducing defects in an initially generated printed circuit board (PCB) trace. For example, a method may include a process of removing or reducing burrs of laser micromachined PCB traces (which may be electrically insulated from each other). In some cases, a material is deposited on the PCB traces, and the deposition causes the conductive layer to electrically connect all or a majority of the PCB traces and provide electrical connections for removing or reducing defects in the PCB traces.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 436,971, filed on January 4, 2023, entitled “METHOD FOR MANUFACTURING ULTRA-HIGH-DENSITY MINIATURIZED PRINTED CIRCUITBOARDS,” which is also incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the technical field of processing and manufacturing printed circuit boards (PCBs). Background Art

[0004] Printed circuit boards, or PCBs, are commonly used in electronic products. The trend toward miniaturization of electronic devices has led to the miniaturization of printed circuit boards, reducing trace widths and spacing. Furthermore, the significant slowdown of Moore's Law over the past decade has led to a shift in chip manufacturing toward alternative methods, such as heterogeneous integration of chiplets and advanced packaging. This has further created a need to reduce the trace widths and spacing of printed circuit boards (PCBs).

[0005] Traditional PCB manufacturing processes may have reached their limits in reducing the width and spacing of PCB traces. State-of-the-art PCB manufacturing processes can use photolithography and wet chemical etching to create PCB traces. The wet chemical etching process is an isotropic etching process and typically etches the material at the same rate vertically and laterally, limiting the aspect ratio of the etched trenches to a ratio of less than 1:2. Typically, etching 18μm thick copper to create PCB traces results in gaps of 50μm or more between traces. In addition, PCB traces have a trapezoidal cross-section, which causes signal distortion in high-speed RF applications. In addition, many known PCB manufacturing processes may cause contamination due to the use of various toxic chemicals (e.g., resists, developers, and etchants).

[0006] Although laser micromachining can be used in PCB manufacturing and offers a technical solution to the aforementioned issues, its application is limited to PCBs with large trace widths and spacings due to the burrs generated during the process. These burrs typically range in size from a few microns to approximately 50μm. When the trace width and spacing are much larger than the burrs, they do not cause any short circuits between traces. Furthermore, because the burrs can be much smaller than the PCB traces, they can be removed using wet etching without completely etching the traces. However, as the trace spacing decreases below approximately 50μm, the burr size becomes comparable to the trace spacing, and burrs can cause short circuits between traces. Furthermore, when multi-layer PCBs are built by laminating multiple PCB trace layers, burrs can pierce the insulating layers separating the conductive trace layers, causing short circuits between them. Sharp burrs can also cause electrical discharges, leading to dielectric breakdown in the conductive layers or the insulating layers between the traces.

[0007] As trace widths and spacing decrease, burr removal becomes difficult, and burr size becomes comparable to the PCB trace width and spacing. Using wet etching to remove burrs also etches away the PCB traces, while using physical polishing can damage fragile PCB traces. Therefore, the burrs generated during laser micromachining limit the smaller PCB trace widths and spacings that can be produced using laser micromachining.

[0008] Electrodeburring, electropolishing, and plasma electropolishing (PeP) can be used to remove burrs from microstructures without etching away the microstructures. However, these processes may require making electrical connections to the microstructures (e.g., PCB traces) that need to be deburred. Furthermore, in PCBs, there are many (often hundreds) of electrically isolated traces (or island structures). Using a probe array to make electrical connections to hundreds of high-density PCB traces is impractical.

[0009] If known electro-deburring, electro-polishing or PeP processes are used to remove burrs from a PCB, the burrs are removed only from the traces where electrical connections are made (see, for example, Figure 1D ), while other electrically insulated traces still have burrs (see, for example, Figures 1D to 1F ). Therefore, in a practical sense, the known electrodeburring, electropolishing and PeP processes cannot be used to remove burrs from smaller size laser micromachined PCB traces. Summary of the Invention

[0010] Described herein are systems and methods for overcoming technical problems associated with processing and manufacturing printed circuit boards, or PCBs. In some embodiments, these systems and methods include a process for removing or reducing defects in initially generated printed circuit board, PCB, traces. For example, a method may include a process for removing or reducing burrs from laser micromachined PCB traces (wherein the traces may be electrically insulated from one another). In some embodiments, a material is deposited on the initially generated PCB traces, and the deposition results in a conductive layer electrically connecting all or most of the PCB traces and providing an electrical connection for removing or reducing defects in the PCB traces (e.g., reducing or eliminating burrs formed during laser micromachining). With respect to some embodiments, disclosed herein is an electrical island deburring (EID) process for removing burrs from laser micromachined PCB traces, for example, removing burrs from traces that are electrically insulated from one another.

[0011] Furthermore, with respect to some embodiments, disclosed herein are processes for improving the processing and manufacturing of multi-layer PCBs. Each layer in a set of layers of the multi-layer PCB can undergo a cycle of depositing material on the PCB traces and removing or reducing defects in the deposited material in that layer, thereby providing a conductive layer that electrically connects all or most of the PCB traces and an electrical connection that removes or reduces defects in the PCB traces (e.g., reducing or eliminating burrs formed during laser micromachining of the layers of the multi-layer PCB).

[0012] In some embodiments, an example method includes depositing a conductive layer on traces formed on a PCB, the traces being electrically insulated from one another, and after depositing the conductive layer, the conductive layer electrically connecting at least some of the traces. The example method may also include applying a current to the conductive layer to reduce or eliminate defects on or in the traces. In some examples, the PCB is micromachined using laser micromachining. In some examples, at least some of the defects are formed by laser micromachining. And in some cases, at least some of the defects include burrs. Therefore, in some embodiments, an example method includes depositing a conductive layer on traces formed on a laser micromachined PCB, the traces being electrically insulated from one another, and after depositing the conductive layer, the conductive layer electrically connecting at least some of the traces. This method may also include applying a current to the conductive layer to reduce or eliminate burrs on the traces.

[0013] In some cases, example methods may include the generation of traces. For example, the method may include laser micromachining of PCB traces. In some cases, at least some of the traces are not connected by a deposited conductive layer. In some such cases, at least some of the traces are electrically connected in another manner known or foreseeable to one of ordinary skill in the art. In such examples where a conductive layer is not deposited, defects or burrs may or may not be reduced or eliminated by the method.

[0014] In some embodiments, one or more steps of the example method may be repeated to produce a multilayer PCB. For example, in some cases, the example method includes, for each of the multiple layers of the multilayer PCB, repeating the laser micromachining of the PCB traces. In some embodiments, for each of the multiple layers of the multilayer PCB, the example method includes repeatedly depositing a conductive layer on the traces formed on the laser micromachining PCB. In addition, in some cases, for each of the multiple layers of the multilayer PCB, the example method includes applying a current to the conductive layer to reduce or eliminate burrs on the traces. In some cases, the example method includes repeating an EID process (e.g., a process including the aforementioned sub-process of depositing a conductive layer on the traces and applying a current to the conductive layer to reduce or eliminate burrs on the traces). And, in some cases, the example method includes forming through-holes between the multiple layers of the multilayer PCB after repeating the laser micromachining and EID processes of the PCB traces.

[0015] For example, in some embodiments, an example method includes reducing or eliminating burrs that appear on printed PCB traces using an EID process, wherein the PCB traces are electrically isolated from each other prior to performing the EID process. As a first sub-process, the EID process may include depositing a conductive layer on the PCB traces, causing the conductive layer to electrically connect at least some of the PCB traces. Furthermore, as a second sub-process, the EID process may include applying a current or voltage to the conductive layer to reduce or eliminate the burrs.

[0016] In some cases, the reduction or elimination of burrs depends on the voltage and electrolyte used to apply current to the conductive layer. Furthermore, in some examples, using the aforementioned second sub-process, the reduction or elimination of burrs by the second sub-process depends on the voltage and electrolyte used in the second sub-process. In some embodiments, the voltage used in the second sub-process or a similar process is determined based on the composition of the trace, the conductive layer, or a combination thereof. In some embodiments, the second sub-process or a similar process includes applying electropolishing to the trace. In some embodiments, the second sub-process or a similar process includes applying electrodeburring to the trace. In some embodiments, the second sub-process or a similar process includes plasma electropolishing the trace.

[0017] In some embodiments, the first sub-process includes using PVD, CVD, ALD, or any combination thereof. In some embodiments, the first sub-process includes using electroless plating. In some embodiments, the first sub-process includes using liquid metal ink. In some embodiments, the first sub-process includes using electroplating to increase the thickness of the conductive layer.

[0018] In some embodiments, the exemplary method includes, after an EID process or similar process, removing the conductive layer using chemical etching. In some embodiments, the conductive layer includes a thin film conductive layer. In some embodiments, the exemplary method includes forming PCB traces on an insulating substrate. In some embodiments, the conductive layer is deposited on the PCB traces such that the conductive layer electrically connects all of the PCB traces.

[0019] In summary, the systems and methods (or technologies) disclosed herein can provide specific technical solutions to at least overcome the technical problems mentioned herein and other technical problems that are not described herein but are recognized by those skilled in the art.

[0020] These and other important aspects of the present disclosure are described more fully in the detailed description below. The present disclosure is not limited to the methods and systems described herein. Other embodiments may be used, and changes may be made to the described embodiments, without departing from the scope of the claims that follow the detailed description. It is understood that the various aspects, embodiments, examples, and alternatives set forth herein, and their individual features, may be employed independently or in any possible and compatible combination within the scope of this application. Where features are described with reference to a single aspect or embodiment, it is understood that these features apply to all aspects and embodiments unless otherwise stated or the features are incompatible. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure can be more fully understood from the detailed description given below and the accompanying drawings of various exemplary embodiments of the present disclosure.

[0022] Figures 1A to 1F The individual and known process steps for the electrical deburring process are shown and follow the Figure 1A Steps from start to Figure 1F The steps in the sequence of operations are provided.

[0023] Figures 2A to 2K The individual process steps for the electrical island deburring process according to some embodiments of the present disclosure are shown and are as follows: Figure 2A Steps from start to Figure 2K The steps in the sequence of operations are provided.

[0024] Figures 3A to 3O The individual process steps for manufacturing a PCB by laminating conductive and dielectric laminates and defining PCB traces using laser micromachining (followed by electrical island deburring) according to some embodiments of the present disclosure are shown, and are as follows: Figure 3A Steps from start to Figure 3O The steps in the sequence of operations are provided.

[0025] Figure 4A multilayer PCB with air gaps between traces for various applications (eg, high-speed applications) is shown according to some embodiments of the present disclosure.

[0026] Figure 5 PCB layers formed on both sides of a PCB core are shown, wherein the air gap is filled with a dielectric material, according to some embodiments of the present disclosure.

[0027] Figures 6A to 6M The individual process steps for fabricating a PCB by depositing conductive and dielectric layers and using laser micromachining (followed by electrical island deburring) to define PCB traces on the conductive layers according to some embodiments of the present disclosure are shown, and are described in detail. Figure 6A Steps from start to Figure 6M The steps in the sequence of operations are provided.

[0028] Figure 7 PCB layers are shown formed on both sides of a core according to some embodiments of the present disclosure.

[0029] Figures 8A to 8F The individual process steps for manufacturing a double-sided PCB according to some embodiments of the present disclosure are shown. Figure 8A Steps from start to Figure 8F The steps in the sequence of operations are provided.

[0030] Figures 9A to 9G The individual process steps for manufacturing a multi-layer PCB by laminating double-sided PCB laminates according to some embodiments of the present disclosure are shown, and are as follows: Figure 9A Steps from start to Figure 9G The steps in the sequence of operations are provided. DETAILED DESCRIPTION

[0031] The following detailed description is of the best currently contemplated mode of carrying out exemplary embodiments of the invention. This description is not limiting but merely illustrative of the general principles of the invention, as the scope of the invention is best defined by the appended claims.

[0032] In summary, embodiments of the present invention provide improved systems, apparatus, and methods for manufacturing printed circuit boards (PCBs), and the PCBs.

[0033] With reference to the accompanying drawings, details of exemplary embodiments of the present invention are described in the following detailed description. Although the detailed description provides reference to exemplary embodiments, it should be understood that the invention disclosed herein is not limited to such exemplary embodiments. On the contrary, the invention disclosed herein includes many alternatives, modifications, and equivalents, which will become apparent by considering the following detailed description and other portions of this disclosure.

[0034] Described herein are systems and methods for overcoming technical problems associated with processing and manufacturing circuit boards (see, for example, Figures 2A to 2K 、 Figures 3A to 3O 、 Figure 4 、 Figure 5 、 Figures 6A to 6M 、 Figure 7 、 Figures 8A to 8F and Figures 9A to 9G . In some embodiments, these systems and methods include a process for removing or reducing defects in initially created printed circuit board (PCB) traces. For example, a method may include a process for removing or reducing burrs from laser micromachined PCB traces (wherein the traces may be electrically insulated from one another). In some embodiments, a material is deposited on the initially created PCB traces, and the deposition results in a conductive layer electrically connecting all or most of the PCB traces and providing electrical connections for removing or reducing defects in the PCB traces (e.g., reducing or eliminating burrs formed during laser micromachining). With respect to some embodiments, disclosed herein is an electrical island deburring (EID) process for removing burrs from laser micromachined PCB traces, e.g., removing burrs from traces that are electrically insulated from one another. For example, see Figures 2A to 2K .

[0035] Furthermore, with respect to some embodiments, processes for improving the processing and manufacturing of multi-layer PCBs are disclosed herein. For example, see Figures 3A to 3O Each layer in a set of layers of a multilayer PCB may undergo a round of depositing material on the PCB traces and removing or reducing defects in that layer from the deposited material, thereby providing a conductive layer that electrically connects all or most of the PCB traces and electrical connections that remove or reduce defects in the PCB traces (e.g., reducing or eliminating burrs formed in laser micromachining of layers of the multilayer PCB).

[0036] In some embodiments, methods, and other embodiments described herein, thin film conductors are deposited on laser micromachined PCB traces. For example, see Figure 2B The deposition results in a conductive layer electrically connecting all or most of the insulated PCB traces of the laser micromachined PCB traces and providing an electrical connection (or current flow) for electrical deburring. In some cases, the deposition results in a conductive layer electrically connecting all or most of the insulated PCB traces of the laser micromachined PCB traces and providing an electrical connection (or current flow) for electrical deburring all or most of the generated burrs. For example, see Figure 2D .

[0037] For the purposes of this disclosure, electrical island deburring is the process of deburring insulating structures (e.g., structures that are not electronically connected). Alternatively, or in addition to electrical island deburring, electrical deburring, electropolishing, or PeP can be used to remove burrs from electrically connected or monolithic conductive structures (or continuous structures). However, in printed circuit boards, there are many electrically insulating island traces (e.g., PCB traces can be conductive island structures on an insulating substrate), and when the traces are very small, electrical deburring, electropolishing, or plasma electrolytic polishing cannot be used to remove burrs from such PCB traces. Instead, electrical island deburring can be used to remove burrs from very small electrically insulating island traces.

[0038] With respect to some examples, this document discloses a new technology, referred to herein as electrical island deburring, which overcomes the limitations of the aforementioned electrical deburring, electropolishing, and plasma electropolishing, and is capable of deburring island PCB traces. In addition, with respect to some examples, this document describes an electrical deburring process for removing burrs from a plurality of electrically insulated island PCB traces (e.g., wires) formed on an insulating substrate. In this process, a thin film conductive layer is deposited on the island (or island) traces to electrically bridge most or all of the traces, and the conductive layer electrically connecting the traces serves as an electrode of an electrochemical cell. The conductive layers are electrically connected, and a suitable cell voltage waveform is applied to deburr the PCB traces. Various mechanisms are used to perform deburring at the electrodes, such as electropolishing, electrical deburring, and plasma electropolishing, while the conductive film is periodically regenerated by reversing the voltage and performing electroplating. For example, see Figure 2H The conductive layer is then etched away to electrically isolate the PCB traces.

[0039] In some examples, electrodeburring, electropolishing, and plasma electropolishing involve an anode (usually the part being deburred), a cathode, and an electrolyte. The difference lies in the mechanism of the electrodes used to remove the burrs, and this mechanism depends on the voltage and electrolyte used.

[0040] For the purposes of this disclosure, electropolishing is an electrochemical and reverse electroplating process for smoothing surfaces. In this process, a metal part with a smooth surface is used as the anode of an electrochemical cell. A suitable cell voltage is applied to produce a high-resistance viscous layer or polishing film around the anode. The polishing layer creates a high-resistance path between the anode and the electrolyte; however, the "peaks" or "hills" present on the anode surface protrude through the polishing film, resulting in localized low-resistance paths. The low resistance at the peaks results in high current density compared to recessed or flat areas, and causes the metal to dissolve faster at the peaks, thereby smoothing the surface. If the burrs are small and comparable to the surface roughness of the part, the electropolishing process can be used to remove the burrs.

[0041] For the purposes of this disclosure, electrodeburring is an electrochemical and reverse electroplating process used to remove burrs from metal parts. In this process, the metal part to be deburred is used as the anode of an electrochemical cell. A suitable cell voltage (usually higher than the electropolishing voltage) is applied, resulting in a current density proportional to the electric field. Due to the spike structure of the burr, the electric field is concentrated at the burr, resulting in a higher current density. The high current density at the peak causes the metal to dissolve faster at the peak compared to the flat area, thereby removing the burr. The electrodeburring process is used when the burr is much larger than the surface roughness of the part. In electropolishing and electrodeburring, the high current density at the burr (or peak) causes the metal to dissolve faster at the peak compared to the recessed or flat area, thereby removing the burr. However, the mechanism that leads to the high current density at the burr (or peak) is different for electropolishing and electrodeburring. During electropolishing, the current density at burrs (peaks or hills) is higher because these burrs protrude through the high-resistance polishing film and have a thinner film overlying them, resulting in low resistance and high current density. During electrodeburring, the high current density at burrs is due to the high electric field concentrated at the burrs. The sharp structure of the burrs causes the electric field to concentrate.

[0042] For the purposes of this disclosure, plasma electropolishing (PEP) is a process used to smooth surfaces. In this process, a smooth-surfaced metal part serves as the anode of an electrochemical cell. A high cell voltage is used to generate an electrical discharge and plasma at the site of a sharp burr. Due to the evaporation of the electrolyte and the ionization of the vapor, an electrical discharge or plasma forms at the burr. The generated plasma causes plasma etching of the burr, thereby removing the burr.

[0043] In some embodiments, during the EID process, a thin film layer of a conductive coating is deposited on a laser micromachined PCB. Typically, the thin film conductive layer is much thinner than the PCB traces so that the conductive layer can be etched away without significantly etching the PCB traces. Typically, the conductive layer thickness is 1 / 10 to 1 / 1000 of the PCB trace thickness (depending on the PCB trace thickness). For example, a 100 nm thick conductive layer can be used for a 25 micron thick PCB trace. The thickness of the conductive layer should be balanced, large enough to ensure an effective conductive path for the deburring current, but not too thick so that subsequent etching in the process does not significantly change the dimensions of the PCB traces. As described below, the thickness of the conductive layer depends on multiple parameters.

[0044] For a given PCB board design, the number of burrs generated during laser micromachining of PCB traces depends on the board design, trace thickness, and the laser micromachining parameters used. The number of burrs on the PCB trace determines the deburring current required to completely remove these burrs during the electrical island deburring process.

[0045] The deburring current depends on the effective conductance between the burr on the conductive layer and the electrode contact and has two components: 1) conductance through the deposited thin film conductive layer, and 2) conductance through the PCB trace.

[0046] The conductance through a PCB trace is determined by the board design (trace layout, trace thickness, etc.) and determines the thickness of the conductive layer to achieve sufficient deburring current. In summary, the number of burrs present on the trace determines the deburring current, which in turn determines the PCB trace layout and the thickness of the thin-film conductive layer. The following table summarizes the relationship between thickness t and other parameters: 1) tα / number of burrs, 2) tα1 / deburring time, 3) tα / trace spacing, and 4) tα1 / trace width.

[0047] Next, the thin film conductive layer is electrically connected to the anode (see, for example, Figure 2D ) and remove the burrs using electrodeburring, electropolishing (e.g., for small burrs), or plasma electropolishing. Because the conductive layer electrically connects all or most of the PCB traces, burrs can be removed from most or all of the PCB traces (e.g., see Figure 2E ).

[0048] In some embodiments, for certain conductive layer materials, the conductive coating may be partially removed due to electrolytic deburring (e.g., electrodeburring, electropolishing, or plasma electropolishing). For such materials, the thickness of the conductive layer may be increased by reversing the electrochemical cell voltage and electroplating on the conductive film (e.g., see Figure 2G ). During the plating cycle, the cell parameters are set to maximize uniform plating, while during the deburring cycle, the parameters are set to maximize selective electrochemical etching of the burrs. Following the deburring process, the thin film conductive coating is etched away using a rapid wet chemical etch, plasma etch, or similar method to electrically insulate the PCB traces (e.g., see Figure 2I Since the conductive coating is much thinner than the thickness of the PCB traces, it can be removed without etching away the PCB traces.

[0049] In some embodiments, one or more of the aforementioned techniques are used to manufacture a multi-layer PCB (e.g., a multi-layer ultra-high density PCB). In this process, laser micromachining is used to form PCB traces on a metal-insulator laminate substrate, followed by a disclosed electrical island deburring process (e.g., see Figure 3B ). Subsequently, a second metal-insulator layer is stacked on the substrate layer (for example, see Figure 3D ). Thereafter, a laser via is formed in the second metal-insulator layer (eg, by drilling) (eg, see Figure 3E ) and uses electroless plating followed by electroplating to fill and electrically connect the two laminate layers (see, for example, Figure 3F). Subsequently, laser micromachining and subsequent electrical island deburring are used to create PCB traces on the second metal laminate layer (see, for example, Figure 3G ). Can be repeated Figures 3D to 3G The process steps shown are used to produce a multilayer stack up to the selected number of PCB layers. Figure 3H A schematic diagram of the completed multi-layer PCB is shown.

[0050] For some embodiments, the disclosed PCB manufacturing process has the following advantages over known PCB manufacturing processes: 1) ultra-high density PCB routing, 2) vertical walls of PCB traces resulting in better signal integrity, 3) tight control of trace impedance for high data transmission applications, 4) use of various materials such as metals, alloys, conductive polymers, etc. to manufacture PCBs with traces, 5) PCBs with air gaps between traces for high data transmission applications, and 6) high aspect ratio PCB traces for high density and high current applications.

[0051] In some embodiments, ultra-high-density and miniaturized PCBs can be used as substrates for advanced semiconductor packaging, space-constrained mobile and wearable devices, applications with strict impedance control (e.g., 5G or 6G applications), and ultra-high-density wiring in high-density flexible cables. Furthermore, the disclosed electrical island deburring process can also be used to remove burrs from other island structures found in other applications, such as microelectromechanical systems (MEMS) and microfluidics.

[0052] Specifically, Figures 1A to 1F The individual known process steps of the electrical deburring process are shown and follow the Figure 1A Steps from start to Figure 1F The steps in the sequence of operations are provided. Figures 1A to 1F The steps in are known prior art processes, and many technical problems associated with known prior art processes have been overcome by the solutions provided herein. Figures 1A to 1F One or more of the steps shown in can be combined with novel aspects of some embodiments of the present disclosure, and in some cases, the combination is novel when combined with some aspects of some embodiments of the present disclosure. Figure 1A A PCB is shown having a laser micromachined trace 102, showing a burr 104 that appears on the trace as a result of the laser micromachining process. As shown, the laser micromachined trace 102 is located on an insulating substrate 106 that is part of the PCB. Figure 1B The setup of a known electro-deburring process is shown. It includes a laser micro-machined PCB comprising an anode 108 and a cathode 110. In addition, it also includes an electrolyte 112, a power supply 114 and electrical connections 116. Figure 1C1. It is shown that electrical connection 116a is formed only with outer edge trace 102a, while island traces 102b are electrically disconnected from each other and from the outer edge traces. Figure 1C As shown schematically in Figure 1C , the power supply 114 is on and current is shown flowing to the outer edge trace 102a, which makes the trace the anode 108. Figure 1D and Figure 1E It is shown that when electrodeburring, electropolishing, or PeP is performed by applying voltage, only burrs 104a present on outer edge traces 102a of the laser micromachined PCB traces are deburred, while burrs 104b present on island traces 102b are not deburred. Figure 1F It is shown that the conventional electrical deburring process is not suitable for deburring laser micromachined PCB traces because the island traces 102b cannot be deburred using this process, and only the outer edge traces 102a are deburred.

[0053] In some embodiments, a new method for deburring laser-etched or laser-micromachined PCB traces (eg, deburring electrically insulating PCB traces) is provided.

[0054] In some embodiments, the method includes the following steps.

[0055] In the first step, PCB traces are formed on the insulating layer 206 as a metal-insulator laminate by patterning the top metal layer using a laser micromachining process. The trace width 203 is determined by the laser tool path, and the trace spacing 205 is determined by the laser spot size used in the laser micromachining process. By varying the spot size in real time, a smaller spot size can be used to achieve a smaller trace spacing, while a larger spot size can be used to achieve a higher etch rate. Using laser etching or laser micromachining processes, PCB traces 202 can be formed on a variety of insulating layer 206 substrates, such as FR4, polyimide, glass, ceramic, silicon, and others.

[0056] In a second step, a thin film conductive layer 207 is deposited on the laser micromachined PCB, such as Figure 2BAs shown. Thin film conductive layer 207 can be selected from any suitable conductive material, selected from copper, liquid metal ink, graphite, etc. Thin film conductive layer 207 can be deposited on PCB traces 202 and insulating layer 206 substrate using a deposition process selected from electroless plating, physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, spray coating, dip coating, or similar methods. Thin film conductive layer 207 can be made of the same material as PCB traces 202, or can be selected from a different conductive material. Thin film conductive layer 207 electrically connects all or most of the insulated PCB traces 202b and provides electrical connection (or current flow) for electrolytic deburring. If there is sufficient conductive material coverage to provide electrical connection to all or most of the traces 202 (especially the insulated PCB traces 202b), the deposited thin film conductive layer 207 may not need to be evenly coated on the laser micromachined PCB.

[0057] In a third step, the method includes making an anodic electrical connection to the thin film conductive layer 207 for electrolytic deburring (see, for example, Figure 2C An array of electrodes spanning the PCB area may be used to make electrical connections to thin film conductive layer 207 at multiple points to ensure uniform voltage is applied across thin film conductive layer 207 and to provide low resistance electrical connections to trace 202 and insulated PCB trace 202b.

[0058] In the fourth step, the electro-deburring process, plasma electrolytic polishing (see, for example, Figure 2F ) or electropolishing to perform electrolytic deburring (see, for example, Figure 2D When thin film conductive layer 207 is made of the same material as PCB trace 202, either electro-deburring or electro-polishing processes may be used. When burrs 204 are large, electro-deburring may be used, while when the surface roughness of burrs 204 is comparable to that of PCB trace 202, electro-polishing may be used.

[0059] In some embodiments, plasma electropolishing is used when the material of thin-film conductive layer 207 is different from the material of PCB trace 202, or when the resistance of thin-film conductive layer 207 or PCB trace 202 is higher than that of electrodeburring or electropolishing processes. Plasma electropolishing uses higher voltages than electrodeburring or electropolishing and is less sensitive to changes in the resistance of thin-film conductive layer 207 than electrodeburring and electropolishing processes. Plasma electropolishing also provides high selectivity for removing burrs 204 without etching away thin-film conductive layer 207 because there is no anodic dissolution of the anode (e.g., PCB trace) in plasma electropolishing. Plasma electropolishing also uses an environmentally friendly electrolyte 212.

[0060] In some embodiments of the method, an island deglitching voltage waveform is used.

[0061] For some conductive coating materials, the thin film conductive layer 207 may be partially removed due to a chemical reaction between the thin film conductive layer 207 and the electrolyte 212 used for deburring, or due to anodic dissolution caused by the electro-deburring or electro-polishing process (see, for example, Figure 2G ). The reduction in thickness of the thin film conductive layer 207 can be estimated by measuring the resistance of the thin film conductive layer 207 or using optical inspection.

[0062] For such materials, the thickness of the thin film conductive layer 207 can be increased by reversing the electrochemical cell voltage and electroplating on the thin film conductive layer 207, e.g. Figure 2H As shown. During the electroplating cycle, cell parameters such as voltage, current, duration, electrode configuration, and electrolyte flow rate are set to maximize uniform electroplating of the thin film conductive layer 207, while during the deburring cycle, these parameters are set to maximize selective electrochemical etching of the burrs 204 without etching away the thin film conductive layer 207. For example, during the electroplating cycle, a low voltage and a larger spacing between electrodes can be used to perform uniform electroplating, while during the electrical island deburring, a high voltage and a shorter spacing between electrodes can be used to perform plasma electrolytic polishing and selectively remove the burrs 204. Electroplating can also be performed in a separate electrochemical cell using an electrolyte 212 different from the deburring electrolyte 212.

[0063] The deburring current is monitored to determine when the burrs 204 are removed. When more burrs 204 are present, the deburring current is larger and slowly decreases as the burrs 204 are removed. When all or most of the burrs 204 are removed, the deburring current saturates to a low value. Alternatively or additionally, an optical inspection system inside the electrochemical cell can also be used to determine when all or most of the burrs 204 are removed. After deburring, the burrs 204 can also be inspected using other inspection techniques and devices, such as an optical profilometer, a scanning electron microscope, x-rays, etc., to ensure that all or most of the burrs 204 are removed. If some burrs 204 remain, the PCB substrate can be deburred again.

[0064] In a fifth step, once all or most of the burrs 204 are removed (see, for example, Figure 2I ), a rapid wet chemical etch, plasma etch, or similar method is used to remove the thin film conductive layer 207 so that the PCB trace 202 is electrically isolated (e.g., see Figure 2J Because thin film conductive layer 207 is much thinner than the thickness of PCB trace 202, thin film conductive layer 207 is etched away more quickly without significantly affecting PCB trace 202. Additionally, uniform anodic dissolution can be used to reduce the thickness of thin film conductive layer 207 prior to etching. Figure 2K Shown are electrically island deburred PCB traces 222. Additionally, the gaps G between the PCB traces may be filled with an insulating material.

[0065] In some embodiments, for certain conductive materials or deposition processes, the deposited thin film conductive layer 207 may not be uniformly coated on the laser micromachined PCB, and some PCB traces 202 may remain electrically isolated. In such cases, multiple cycles of applying the thin film conductive layer 207 material, followed by electrical island deburring, may be performed to cover all or most of the PCB traces 202.

[0066] In some embodiments, in the fourth step, the burrs 204 are removed using an electrical deburring process.

[0067] In some embodiments, in the fourth step, the burrs 204 are removed using an electropolishing process.

[0068] In some embodiments, in the fourth step, the burrs 204 are removed using a PeP process (eg, see Figure 2F The voltage used for PeP is higher than that used in electrodeburring or electropolishing processes. The high voltage creates a plasma skin around burrs 204, resulting in plasma etching of the burrs. Burrs 204 have sharp edges and generate a higher plasma discharge than smooth areas of PCB traces 202, and are therefore selectively etched.

[0069] In some embodiments, a combination of plasma electropolishing, electrodeburring, and electropolishing is used to remove burrs 204 from laser etched or laser micromachined PCB traces 202 .

[0070] In some embodiments, for certain thin film conductive layer 207 materials, the thin film conductive layer 207 may be partially removed due to a chemical reaction between the thin film conductive layer 207 and the electrolyte 212 used for deburring, or due to anodic dissolution caused by the electrolytic deburring process. For such materials, the thickness of the thin film conductive layer 207 can be increased by reversing the electrochemical cell voltage and performing electroplating on the thin film conductive layer 207.

[0071] During positive cycles of the power supply 214 voltage, the PCB trace 202 is deburred, while during negative cycles of the power supply 214 voltage, electroplating material is uniformly deposited on the thin film conductive layer 207. Note that deburring uses selective etching of the burrs 204, while electroplating uses uniform deposition of thin film conductive material.

[0072] During the island deburring cycle, the electrochemical cell parameters (e.g., voltage, current, pulse duration, voltage or current waveform, electrode configuration, electrolyte flow rate, electrolyte concentration, bath temperature, etc.) are set to maximize deburring (e.g., selectively remove burrs 204 without etching other portions of trace 202). During the electroplating cycle, these parameters are set to ensure uniform electroplating. An example of such parameter variation is to use high voltage and electrodes close together to perform deburring, and use low voltage and electrodes far apart to perform uniform electroplating.

[0073] In some embodiments, the laser micromachined PCB can be moved to a different electroplating cell if the electrolyte 212 used for deburring is different from the electrolyte 212 used for electroplating. After electroplating, the PCB is moved back to the deburring cell for the electro-island deburring process.

[0074] Figures 2A to 2K An example implementation of the steps is shown. Figure 2A A PCB having a laser micromachined trace 202 is shown, showing burrs 204 present at the trace 202 due to laser micromachining, according to some embodiments of the present disclosure. The laser micromachined trace 202 includes an outer edge trace 202a and an electrically insulating island trace 202b. The PCB includes an insulating layer 206.

[0075] Figure 2B Thin film conductive layer 207 is shown deposited on laser micromachined PCB 200, including on traces 202, burrs 204, and insulating layer 206. According to some embodiments of the present disclosure, thin film conductive layer 207 may be deposited using PVD, CVD, ALD, electroless copper, liquid metal ink, or similar methods.

[0076] Figure 2C The method for increasing the thickness of the thin film conductive layer 207 or Figure 2B Electroplating of different conductive coatings on a medium deposit layer.

[0077] Figure 2D Electrodeburring is shown by applying a positive voltage at the PCB trace 202 (as the anode) and a negative voltage at the cathode according to some embodiments of the present disclosure. The voltage value depends on the selected deburring material and electrolyte 212. The thin film conductive coating 207 provides electrical connection to all or most of the insulated trace 202b for electrodeburring, electropolishing or PeP processing.

[0078] Figure 2E Schematic diagram showing deburring of all or most of the PCB traces 202 using electro-deburring or electro-polishing according to some embodiments of the present disclosure.

[0079] Figure 2FSome embodiments of the present disclosure are shown Figure 2E As an alternative to or in combination with the illustrated process, a plasma electrolytic polishing process can also be used to remove burrs 204. A high voltage power supply 215 provides a voltage for PeP that is higher than the voltage used for electrodeburring or electropolishing processes. The burrs have sharp edges, and the high voltage generates a plasma discharge 217 around the burrs 204, resulting in plasma etching of the burrs.

[0080] Figure 2G The electrolytic deburring process according to some embodiments of the present disclosure selectively etches the burrs 204 without significantly affecting other components. For some conductive coating materials, the electrolytic deburring process can reduce the thickness of the conductive coating of the thin film conductive layer 207, such as Figure 2G Shown schematically. Figure 2G A partially etched away burr 204a is shown, along with reduced conductive coating material 207a.

[0081] Figure 2H The voltage at power supply 214 is reversed to perform electroplating and increase the coating thickness, thereby producing a thickened coating 207b or a regenerated conductive coating. Note that according to some embodiments of the present disclosure, the voltage, current, and other electrochemical cell parameter values ​​used for electroplating differ from those used for island deburring. In this example, trace 202 or coating 207b becomes the cathode and PCB 210 becomes the anode.

[0082] Figure 2I A schematic diagram of a completed electrical island deburring process according to some embodiments of the present disclosure is shown. In this process, the voltage and polarity of the electrode deburring, electropolishing, or plasma electropolishing are varied. Furthermore, the trace 202 is nearly completely deburred or completely deburred.

[0083] Figure 2J It is shown that after the electrical island deburring process, the thin film conductive layer 207 is removed using chemical etching (including using an etchant 220 ), according to some embodiments of the present disclosure.

[0084] Figure 2K A schematic diagram of an electrode island deburred PCB 222 with deburred traces 202 is shown, according to some embodiments of the present disclosure.

[0085] In some embodiments, a multilayer PCB is manufactured using the above process. In some embodiments, a multilayer PCB is manufactured using the above laser micromachining and electrical island deburring process.

[0086] For example, according to Figures 3A to 3O The steps shown are for manufacturing a multi-layer PCB.

[0087] Figure 3AA first conductor-insulator laminate is shown as a layer-by-layer substrate for a PCB. According to some embodiments of the present disclosure, the first conductor-insulator laminate includes a first conductive layer 302. The first conductive layer 302 can be a conductive metal (e.g., copper), a conductive polymer, or the like, deposited on an insulating material 304. The insulating material 304 can be selected from ceramic, FR4, and glass.

[0088] Figure 3B PCB traces 306 and alignment marks 308 are shown formed on conductive layer 302 using laser micromachining (followed by an electrical island deburring process) according to some embodiments of the present disclosure. A PCB layer is a composition of conductive layer 302, insulating material 304, and PCB traces 306, and may be referred to herein as a first PCB layer.

[0089] Figure 3C The gaps G between the PCB traces 306 are shown filled with one or more dielectrics 310 and / or insulating materials 310 .

[0090] Figure 3D An overlying conductor-insulator layer (second PCB layer) is shown formed on top of a first or preceding conductor-insulator layer. The second PCB layer includes an overlying conductive layer 302', an overlying insulating layer 304', and an overlying cutout 312 positioned to cover an alignment mark 308 of the underlying conductor-insulator laminate. The overlying conductor-insulator layer is laminated onto the underlying conductor-insulator layer. In this case, according to some embodiments of the present disclosure, the second PCB layer is laminated onto the first PCB layer.

[0091] Figure 3E A through-hole 314 is shown that can be drilled using a laser micromachining process according to some embodiments of the present disclosure. Through-hole 314 stops at conductive layer 302 of the first PCB layer and is used to make an electrical connection between the overlying conductor-insulator layer and the underlying conductor-insulator layer. In the embodiment shown, through-hole 314 provides a conductive path between overlying conductive layer 302' and underlying conductive layer 302. An electrolytic deburring process can also be used to remove burrs (not shown) from through-hole 314.

[0092] Figure 3F A thin conductive seed layer 318 is shown deposited to cover via walls 314, underlying conductive layer 302, and overlying conductive layer 302' according to some embodiments of the present disclosure. Thin conductive seed layer 318 may be deposited using electroless plating, atomic layer deposition (ALD), or other deposition methods.

[0093] Figure 3GThe diagram shows a thicker conductive layer 320 applied to the initial thin conductive seed layer 318 using electroplating to increase electrical conductance according to some embodiments of the present disclosure. The metal of the thicker conductive layer 320 is deposited on the through-hole walls, providing an electrical connection between the underlying first PCB layer and the overlying second PCB layer.

[0094] Figure 3H Overlying traces 306 ′ are shown formed using laser micromachining (followed by electrical island deburring) according to some embodiments of the present disclosure, as previously described.

[0095] Figure 3I The gaps G' between the overlying PCB traces 306' are shown filled with dielectric and insulator material 324 according to some embodiments of the present disclosure.

[0096] Figures 3J to 3N Shows that by repeating Figures 3D to 3H According to some embodiments of the present disclosure, through holes 314 may also be drilled between multiple PCB layers, such as Figure 3K shown.

[0097] Figure 3O The completed multi-layer PCB is shown after removing excess areas containing alignment marks 308 and cover cutouts 312 according to some embodiments of the present disclosure.

[0098] In some embodiments, layer-by-layer PCB build-up using laser micromachining and electrical island deburring processes includes the following steps.

[0099] In a first step, the method starts with a conductor-insulator dielectric rigid or flexible substrate (see, for example, Figure 3A Conductive layer 302 and insulating layer 304 are shown. As previously mentioned, conductive layer 302 can be copper or other conductive material, and insulating layer 304 can be glass, FR4, ceramic, or other insulating material. Conductive layer 302 can be used to create traces 306 using laser micromachining (followed by electrical island deburring).

[0100] The second step includes using laser micromachining to machine alignment marks 308 and to machine traces 306 on the conductive layer 302. Next, an electrical island deburring process is used to remove burrs from the laser micromachined PCB traces 306 (e.g., see Figure 3B ). This layer is hereafter referred to as the first PCB layer.

[0101] The third step includes filling the gaps G between the PCB traces 306 with a dielectric material 310 (see, for example, Figure 3C 3. Dielectric material 310 is shown. Additionally, this step can be omitted to create PCB traces 306 with air gaps therebetween.

[0102] The fourth step includes laminating the conductor-insulator laminate layer (second PCB layer) with the cutout window 312 for the alignment mark on the first PCB layer (e.g., as shown in FIG. Figure 3D shown).

[0103] The fifth step includes aligning the second PCB layer design with the first PCB layer using alignment marks 308 in the first PCB layer visible through cutouts 312 in the second PCB layer. Next, a laser micromachining process is used to form one or more vias 314 in the second PCB layer that stop at the conductive layer of the first PCB layer, as shown in FIG. Figure 3E Schematically shown (eg, see hole stop 316).

[0104] The sixth step includes applying a thin conductive layer 318 over the second PCB layer and the through-holes 314 while masking the alignment marks 308 on the first PCB layer (see, for example, Figure 3F ). Thin conductive layer 318 can have any conductive material (e.g., copper, liquid metal ink, conductive polymer, etc.) and can be deposited using various deposition processes, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, dip coating, or the like. In addition, electroplating can be used to apply a thicker conductive layer 320 over thin conductive layer 318 (see Figure 3G ) to increase the electrical conductance of the one or more through-holes 314. The metal deposited at the one or more through-hole walls creates an electrical connection between the first PCB layer and the second PCB layer (eg, see via fill 322).

[0105] The seventh step includes machining trace 306' on the overlying conductive layer 320 of the second PCB layer using laser micromachining and removing burrs (not shown) from the laser micromachined PCB trace using the disclosed electrical island deburring process (e.g., see Figure 3H ). In addition, the gaps G between the traces may be filled with a dielectric material 324, such as Figure 3I By repeating Figures 3J to 3N Note that during layer buildup, one or more through holes 314 may be formed between multiple layers, such as Figure 3K shown. Figure 3N The layer stackup of a four-layer PCB is shown schematically. Figure 3N Also shown in FIG. 3 is a PCB having deburred traces 326 .

[0106] An eighth step involves cutting the PCB to size and removing the area containing the alignment marks 308 once the layer build-up is complete. Figure 3O The completed ultra high density multilayer PCB is shown after the PCB has been cut to size and the area containing the alignment marks 308 has been removed.

[0107] In conventional PCB layer buildup processes, new overlying layers are aligned with the alignment mark located on the top layer of the PCB layer buildup. Consequently, layer alignment errors increase with the number of layers. However, in the disclosed method, each layer can be aligned with respect to the same alignment mark 308 located in the first layer. Therefore, errors do not accumulate as the number of layers increases.

[0108] In some embodiments, PCB traces 306, 306', ... 306 with air gaps are used. n .

[0109] In some embodiments, the Figure 3C , thereby producing PCB traces 404, 404', ... 404 n , with an air gap 402 therebetween (see, for example, Figure 4 ). This example eliminates the need for populating the PCB traces 404, 404', ... 404. n The gap 402 between the dielectric material 310 and the thermal and electrical problems associated with the gap 402. In addition, since the dielectric constant of air is the lowest, it is possible to n These are traces 404, 404', ... 404 n PCBs with air gaps between them are suitable for high-density interconnection in heterogeneous integration of chiplets.

[0110] In some embodiments, layer-by-layer buildup on both sides of the core sheet is used (see Figure 5 ).

[0111] In some embodiments, the through holes 314 are drilled in the conductive-insulator laminate prior to lamination, which allows for the processing of through holes 314 of different shapes. Figure 3D In the embodiment, the conductive-insulator laminates (302', 304') are first laminated, and then Figure 3E , the through hole is drilled. This method only allows the through hole to be drilled from the top, resulting in a through hole that is wider at the top and narrower as it goes deeper (not shown in the figure). The through hole shown in the image has vertical walls. However, if the through hole 314 is first drilled in the conductive-insulator laminate 302', 304', this allows drilling from both the top and the bottom, and can be used to produce a through hole 314 that is 1) wide at the top and narrow at the bottom, or 2) narrow at the bottom and wide at the top. After the through hole 314 is drilled, it is laminated. In summary, in one embodiment, the steps Figure 3D (Laminate first) in step Figure 3E (and then drilling the through holes), while in other embodiments, the step Figure 3E (First, drill the through hole) in step Figure 3D(and then laminating) before.

[0112] In some embodiments, the disclosed laser etching or laser micromachining (followed by electrical island deburring) is used in conjunction with conventional wet chemical etching or semi-additive processes. First, large trace width and spacing PCB traces 404, 404', ... 404 n Formed using conventional wet chemical etching or semi-additive processes. For traces that are too small to be manufactured using conventional PCB manufacturing processes, the traces remain connected and laser micromachining (followed by electrical island deburring) is then used to form these small traces. This allows the use of conventional PCB manufacturing processes to create large traces and then utilize the laser micromachining process of the present invention to create small traces. This allows the high throughput provided by existing technologies with the benefits of small trace widths and spacing provided by aspects of the present invention.

[0113] Furthermore, using laser micromachining, traces 404, 404', ... 404 having smaller trace widths and spacings are formed. n It can be machined and deburred using the electric island deburring process.

[0114] Furthermore, multi-layer PCBs may be manufactured using some of the methods disclosed herein or using standard PCB manufacturing processes.

[0115] For example, Figure 4 A multilayer PCB with air gaps 404 between traces 402 for high-speed applications is shown according to some embodiments of the present disclosure. Figure 4 A multilayer PCB with air gaps 404 between traces 402 according to some embodiments of the present disclosure is shown. Since air has the lowest dielectric constant, fast data propagation speeds can be achieved in PCB traces. These PCBs are suitable for high-density interconnection in heterogeneous integration of small chips. In addition, Figure 4 Shown are vias 406 connecting the traces, an insulating layer 408 between the traces, and a core 410 of the PCB.

[0116] In addition, for example, Figure 5 5 shows a PCB layer stack-up on both sides of a PCB core, wherein the air gap is filled with dielectric material 502, according to some embodiments of the present disclosure. Figure 5 In the example of FIG. 5 , the vias include a machined via 504 that provides conduction through a core 510 and a laser micromachined via 506 that provides conduction through an insulating layer 508 .

[0117] An advantage of the process described in the example embodiments is that conventional processes can be used for low-density PCB traces and layers, while the disclosed PCB manufacturing process can be used to manufacture high-density traces and layers. For example, one use case is in the manufacture of PCB substrates for mounting circuit components with or without high-density ball grid array (BGA) fan-outs. Conventional PCB manufacturing processes can be used to pattern low-density PCB traces and layers, while laser micromachining can be used to pattern BGA pads and high-density traces and layers.

[0118] For example, Figures 6A to 6M The individual process steps for fabricating a PCB by depositing dielectric and conductive layers and defining PCB traces using laser micromachining (followed by electrical island deburring) according to some embodiments of the present disclosure are shown, and are described in detail. Figure 6A Steps from start to Figure 6M The steps in the sequence of operations are provided.

[0119] Figure 6A A conductor-insulator laminate used as a layer-by-layer buildup substrate for a PCB according to some embodiments of the present disclosure is shown. The conductor-insulator laminate includes a conductive layer 602, which can be formed of a metal (e.g., copper), a conductive polymer, etc., deposited on an insulating material 604. The insulating material can be formed of ceramic, FR4, glass, etc.

[0120] Figure 6B The fabrication of PCB traces 606 and alignment marks 608 on a conductor-insulator of a rigid or flexible substrate using laser micromachining (followed by island deburring) is shown in accordance with some embodiments of the present disclosure.

[0121] Figure 6C A dielectric material is shown deposited to define a dielectric layer 610 (e.g., liquid polyimide, etc.) on a previous layer (a PCB trace) while masking an alignment mark area 608, which includes a window 612 provided for exposing the alignment mark 608. When constructing a PCB stack, an insulating (also referred to as dielectric) layer 610 is deposited over the previous trace to separate the trace from the previous layer of conductive layer traces that will be applied to the dielectric layer 610 in a subsequent layer of the PCB stack.

[0122] Figure 6D The through hole 614 is shown drilled using laser micromachining according to some embodiments of the present disclosure, ensuring that the hole stops at the underlying PCB trace 606 where electrical connection is required. Alignment marks 608 in the first layer visible through a window 612 in the dielectric layer 610 are used to align the through hole 614 with the bottom layer and determine the location of the through hole 614 in the overlying conductive layer 610.

[0123] Figure 6EA thin film conductive layer 616 (or seed layer) is shown deposited over the dielectric layer 610 and the vias 614 while masking the area of ​​the alignment marks 608. The conductive layer 618 may be deposited using various deposition methods, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, dip coating, or other deposition methods.

[0124] Figure 6F Conductive material 618 is shown electroplated on seed layer 616 using an electroplating process to increase the thickness of thin film conductive layer 616 , in accordance with some embodiments of the present disclosure.

[0125] Figure 6G PCB traces 620 are shown fabricated using laser micromachining (followed by electrical island deburring) on ​​the conductive layer 618 deposited in the previous step.

[0126] Figures 6H to 6L It shows that according to some embodiments of the present disclosure, Figures 6C to 6G The steps shown are used to stack up subsequent PCB layers.

[0127] Figure 6H A dielectric material 622 (eg, liquid polyimide, etc.) is shown deposited on a previous layer (the PCB trace layer) while masking the alignment mark 608 area.

[0128] Figure 6I The through hole 624 is shown drilled using laser micromachining. Note that according to some embodiments of the present disclosure, such as Figure 6I As shown, during layer buildup, vias 624 may be formed between multiple layers.

[0129] Figure 6J Deposition of a thin film conductive layer 626 (or seed layer) over the dielectric layer 626 and vias 624 while masking the alignment mark areas is shown, in accordance with some embodiments of the present disclosure.

[0130] Figure 6K Conductive material 628 is shown electroplated on seed layer 626 using an electroplating process to increase the thickness of the conductive layer, in accordance with some embodiments of the present disclosure. Figure 6L The layer stackup of a three-layer PCB is shown schematically.

[0131] Figure 6M It is shown that once the layer build-up is complete, the process may include cutting the PCB to size and removing the area containing the alignment mark 608 and the overlying alignment cutout 612 . Figure 6M A completed ultra-high density multi-layer PCB according to some embodiments of the present disclosure is schematically illustrated.

[0132] In some embodiments, a PCB can be provided with a liquid polymer as a dielectric layer and an electrodeposited conductive material on one or more PCB trace layers. In this example, the conductive layer is the electrodeposited conductive material, and the insulating layer is the liquid polymer. The process of building a multilayer PCB includes the following steps.

[0133] First, the process involves using laser micromachining (followed by electrical island deburring) to create PCB traces 606 and alignment marks 608 on a conductive insulator that forms a rigid or flexible substrate, such as Figure 6B shown.

[0134] Second, the process includes depositing a thin film 610 of polymer insulator and dielectric material (e.g., liquid polyimide, etc.) on the previous layer while masking the alignment mark 608 area, e.g. Figure 6C shown.

[0135] Third, the process includes drilling one or more vias 614 using laser micromachining, ensuring that the vias 614 terminate at the desired PCB trace layer where electrical connection is required (e.g., see Figure 6D ). Using the alignment marks in the first layer visible through the cutouts 612 in the dielectric layer 610, the via design file is aligned with the alignment marks 608 on the bottom layer of the PCB structure and the location of the via 614 is determined.

[0136] Fourth, the process includes depositing a thin film conductive layer 616 (or seed layer) over the dielectric layer 610 and the vias 614 while masking the alignment mark 608 area, as shown in FIG. Figure 6E As previously mentioned, various deposition methods (e.g., electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, dip coating, or other deposition methods) can be used to deposit the conductive layer. In some cases, such as Figure 6F As shown, a conductive material 618 is electroplated on the seed layer 616 using an electroplating process to increase the thickness of the conductive layer. Figure 6G As shown, in some examples, PCB traces 620 can be fabricated using laser micromachining (followed by electrical island deburring) on ​​the conductive layer deposited in the previous step. To build up subsequent PCB layers, the process is repeated. Figures 6C to 6G Note that during layer stacking, vias 614 may be formed between multiple layers, as shown in FIG. Figure 6G shown.

[0137] Figure 6L The schematic diagram shows the layer stacking of a three-layer PCB. Once the layer stacking is completed, the PCB is cut to size and the area containing the alignment mark 608 is removed. Figure 6M It should be understood that this process can also be used to build up PCB layers on both sides of the core of a high-density multi-layer PCB, such as Figure 7In this case, for a single-sided PCB structure, the core 700 can be a single thickness or double thickness of the insulating material 604.

[0138] In some embodiments, a double-sided printed circuit board is used. For example, Figure 7 PCB layer stack-up on both sides of core 710 is shown according to some embodiments of the present disclosure. The PCB layers include traces 702, laser micromachined vias 704, machined vias 706, dielectric material 708, and core 710. In addition, Figure 7 PCB layer buildup on both sides of a core 710 is shown by depositing dielectric and conductive layers and using laser micromachining (followed by electrical island deburring) to define PCB traces 702 in accordance with some embodiments of the present disclosure.

[0139] Figures 8A to 8F are separate process steps for manufacturing a high-density double-sided PCB 800, and are Figure 8A Steps from start to Figure 8F The steps in the sequence of operations are provided.

[0140] Figure 8A The diagram shows a process of starting with a double-sided conductor-insulator-conductor rigid or flexible laminate according to some embodiments of the present disclosure. The double-sided conductor-insulator-conductor laminate includes a first conductive layer 802, a second conductive layer 804, and an insulating layer 806 between the conductive layers. The first conductive layer 802 is deposited on a first side of the insulating layer 806. The second conductive layer 804 is deposited on a second side of the insulating layer, opposite the first side of the insulating layer 806.

[0141] Figure 8B Laser micromachining is shown drilling through via 808. As previously described in other embodiments, electrical island deburring is used to remove burrs (not shown) from via 808.

[0142] Figure 8C A thin film conductive layer 810 (or seed layer) is shown deposited over the first conductive layer 802, the second conductive layer 804, and the vias 808. The thin film conductive layer 810 may be deposited using various deposition methods, such as electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, dip coating, or other deposition methods.

[0143] Figure 8D Conductive material 812 is shown being plated onto thin film conductive layer 810 using an electroplating process to increase the thickness of thin film conductive layer 810 and fill via 808 .

[0144] Figure 8E The fabrication of PCB traces 814 and alignment marks 816 in a double-sided PCB 800 using laser micromachining (followed by electrical island deburring) is shown.

[0145] Figure 8F The PCB is shown cut to size and the area containing the alignment marks 816 is removed. Figure 8F A completed ultra-high density double-layer PCB 800 according to some embodiments of the present disclosure is schematically illustrated.

[0146] In some embodiments, the Figures 8A to 8F The following process shown in FIG. 8 is used to manufacture a high-density double-layer PCB 800. First, as shown in FIG. Figure 8B As shown, laser micromachining is used to drill a through hole 808 in a conductor-insulator-conductor rigid or flexible laminate. As previously described, electrical island deburring is used to remove burrs (not shown) from the through hole 808. Second, the method includes depositing a thin film conductive layer (or seed layer) 810, such as Figure 8C As shown. Various deposition methods (e.g., electroless plating, PVD, sputtering, CVD, ALD, spin coating, spray coating, dip coating or other deposition methods) can be used to deposit the thin film conductive layer 810. In addition, as shown Figure 8D As shown, electrodeposition can then be applied to plate additional conductive material 812 onto the seed layer 810, thereby increasing the thickness of the conductive seed layer 810 and filling the via 808. The via 808 electrically connects the two conductive layers 802, 804 of the conductor-insulator-conductor laminate 800. Next, as previously described, laser micromachining (followed by electrical island deburring) is used to create PCB traces 814 and alignment marks 816 on the first conductive layer 802 and the second conductive layer 804, as shown. Figure 8E Finally, the PCB 800 is cut to size and the area containing the alignment mark 816 is removed. Figure 8F The completed ultra-high density double-layer PCB 800 is shown.

[0147] In some embodiments, a multilayer PCB with mechanical or laser vias 808 is used.

[0148] For example, double-sided PCBs are Figures 8A to 8F The double-sided PCB 800 is laminated to produce a multi-layer PCB. Through holes 808 are created to electrically connect the various PCB layers.

[0149] Figures 9A to 9G The individual process steps for manufacturing a multilayer PCB 900 by laminating double-sided PCB laminates are shown, and are as follows: Figure 9A Steps from start to Figure 9G The steps in the sequence of operations are provided.

[0150] Figure 9AAn alternative process step for manufacturing a double-sided PCB 900 as described in FIG8 and filling the gaps between traces 902 with dielectric material 904 is shown. For layers using low-density PCB traces 902, the traces 902 can also be manufactured using conventional PCB manufacturing processes. Figure 9A shown.

[0151] Figure 9B A four-layer PCB 900 is shown, produced by laminating two double-sided PCBs, with one of an insulating layer 906 or a dielectric layer 906 interposed between the first and second PCBs. An adhesive layer (not shown) may be applied to one of the insulating layer 806 and the dielectric layer 906 to bond the first and second PCBs.

[0152] Figure 9C The step of applying a protective coating or film 910 to both sides of a joined first and second PCBs (PCB stack-up) is shown. The protective coating or film 910 is applied to mask selected areas of one or more exterior surfaces of the PCB stack-up to selectively apply thin film conductors 916, as further described below.

[0153] Figure 9D One or more through-holes 912, 912' are shown drilled using laser micromachining or mechanical milling, as previously described. It should be understood that one or more through-holes 912, 914 can extend into the PCB buildup to provide conductivity between conductive layers on a first PCB layer, or can extend through the PCB buildup to provide conductivity between a first PCB layer and a second PCB layer.

[0154] Figure 9E Deposition of a thin film conductive layer (or seed layer) 916 is shown. According to some embodiments of the present disclosure, the deposited thin film conductive layer 916 covers the walls of one or more through-holes 912, 912' and the protective coating 920.

[0155] Figure 9F The diagram shows the electroplating of conductive material onto seed layer 916 using an electrodeposition process to fill vias 912, 912', according to some embodiments of the present disclosure. Next, protective coating 920 is removed, leaving only the conductive material in vias 912, 912'. Vias 912, 912' provide electrical connections between PCB trace layers 904.

[0156] Figure 9G The PCB is shown cut to size and the area containing the alignment marks 816 is removed, in accordance with some embodiments of the present disclosure. Figure 9G The completed ultra-high-density double-layer PCB 900 is schematically shown.

[0157] In this embodiment, first, use Figures 8A to 8F The process steps described in the previous embodiment shown in the figure are used to manufacture multiple double-sided PCBs 800, and the gaps between the traces are filled with dielectric material 906. For layers using low-density PCB traces 902, the traces 902 can also be manufactured using conventional PCB manufacturing processes. Next, the double-sided PCBs 800 including dielectric material 904 and using dielectric and adhesive layers 906 are laminated together, as shown in FIG. Figure 9A shown. Figure 9B 800 is laminated together to create a four-layer PCB 900. Figure 9C As shown, a protective coating 910 or film is applied to both sides of the PCB buildup. Third, through holes 912, 912' are drilled using laser micromachining (e.g., see laser micromachined through hole 912) or mechanical milling (e.g., see mechanical milled through hole 912'), as shown. Figure 9D Fourth, a thin film conductive layer 916 is deposited on the opposite outer surface of the PCB stack. Figure 9E As shown, a thin film conductive layer 916 can cover the via walls as well as the protective coating 910. As previously described, this embodiment can also use electrodeposition to plate additional conductive material over the seed layer and filled vias 912, 912'. Next, the protective coating 920 is removed, leaving only the conductive material in the vias 912, 912', as shown. Figure 9F The through holes 912, 912' provide electrical connections between selected PCB trace layers 902. Finally, the PCB 900 is cut into selected sizes and the area containing the alignment mark 920 is removed. Figure 9G The completed ultra high density four layer PCB 900 is shown after the PCB has been cut to selected dimensions and the area containing the alignment marks 920 has been cut away.

[0158] In some embodiments, PCBs may also be manufactured with three-dimensional traces.

[0159] For example, a PCB with three-dimensional traces is described. First, a thin film layer of conductive material 916 is embossed to create the desired three-dimensional shape. Second, a sheet of conductive material with the three-dimensional structure is attached or laminated to an insulating substrate. Finally, laser micromachining is used to machine the PCB traces over the embossed shape to create the three-dimensional PCB traces, and electrical island deburring is used to remove burrs generated during the laser micromachining process.

[0160] Conventional PCB manufacturing processes are limited to producing two-dimensional PCB traces. However, the PCB manufacturing process disclosed in the examples can be used to produce PCBs with three-dimensional traces. Such PCBs can be used to interconnect small chips in 3D space.

[0161] In some embodiments, high-density and high-current-carrying PCBs are used. For example, a process for manufacturing PCBs with trace thickness greater than 100 μm is described. In this process, a thick (greater than 100 μm) laminate is formed on an insulating substrate, such as FR4, glass, or ceramic. Next, laser micromachining is used to create high-aspect ratio (10:1 to 20:1) gaps between the traces. A similar process can be used to manufacture multi-layer PCBs.

[0162] In traditional PC manufacturing processes using wet chemical etching, etching 250μm-thick PCB traces also results in 250μm gaps between traces, resulting in low trace density. However, using the process described in the example, it is possible to laser micromachine PCB traces with thicknesses of 100μm to 250μm, but with spacing of only 5μm to 10μm, thereby achieving high-density and high-current-carrying PCBs. These PCBs are particularly suitable for ASIC applications that use high-density routing and high-current-carrying traces.

[0163] It is important to understand that burrs are a major obstacle to reducing the trace width and spacing of PCB traces formed using laser micromachining. The methods and systems disclosed herein are capable of removing burrs, thereby enabling laser micromachining to produce PCB traces with fine line widths and spacings. By enhancing the laser micromachining process and using the disclosed electrical island deburring process, trace widths and spacings below sub-micron can be readily achieved.

[0164] In some embodiments, ultra-high-density and miniaturized PCBs can be used as substrates for advanced semiconductor packaging, such as system-in-package (SiP), heterogeneous integration of chiplets, and fan-out packaging. Furthermore, our miniaturized PCBs can be used in space-constrained devices, such as mobile and wearable devices, for applications using controlled impedance traces, such as 5G or 6G applications, modules, and high-density PCB flex cables.

[0165] The electrical island deburring process disclosed herein can be used to deburr island structures found in other applications, such as MEMS devices, microfluidics, and other microstructures fabricated using other microfabrication processes (e.g., micromilling, EDM, etc.).

[0166] Some advantages of some embodiments include the following advantages of the disclosed PCB manufacturing process compared to known PCB manufacturing processes. In addition, the disclosed PCB manufacturing process can be used to manufacture ultra-high density PCBs, which have a wiring density ten times or more that PCBs manufactured using traditional processes. In addition, the disclosed PCB manufacturing process can be used to manufacture PCB traces with vertical walls, thereby allowing for better signal integrity. Traditional PCB manufacturing processes cause PCB traces to have a trapezoidal cross-section, which leads to signal loss during high-speed signal propagation. In addition, the disclosed PCB manufacturing process provides tighter manufacturing tolerances than current technologies, thereby enabling better control of the impedance of traces used in high data transmission applications such as 5G or 6G.

[0167] Furthermore, the disclosed PCB manufacturing process can be used to manufacture PCBs made of a variety of materials (e.g., metals, alloys, conductive polymers, etc.). Conventional PCB manufacturing processes use wet chemical etching to manufacture PCB traces and are currently limited to manufacturing PCBs using only copper. Furthermore, the disclosed PCB manufacturing process can produce PCBs with air gaps between traces. Air has the lowest dielectric constant and can transmit data through PCB traces at the fastest speed. Furthermore, the disclosed PCB manufacturing process can manufacture PCB traces with high aspect ratios (10:1 to 20:1), enabling the manufacture of PCBs with high density and high current-carrying capacity. Furthermore, the disclosed PCB manufacturing process is chemical-free and environmentally friendly, producing no hazardous chemical waste and significantly reducing water consumption. Conventional PCB manufacturing processes use photolithography and wet chemical etching to manufacture PCB traces, using various chemicals such as photoresists, developers, and etchants, generating hazardous chemical waste and consuming large amounts of water and energy.

[0168] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. The description and drawings are, therefore, to be regarded as illustrative rather than restrictive.

Claims

1. A method of reducing one or more defects from a plurality of traces of a printed circuit board (PCB), comprising: depositing a thin film conductive layer on at least some of the plurality of traces formed on the PCB, the plurality of traces being electrically insulated from one another, wherein after depositing the thin film conductive layer, the thin film conductive layer electrically connects at least some of the one or more defects on the traces; as well as An electric current is applied to the thin film conductive layer at a first polarity to reduce or eliminate the one or more defects on the plurality of traces.

2. The method according to claim 1, further comprising: The current is applied to the thin film conductive layer with a second polarity to achieve electroplating of the thin film conductive layer, thereby increasing the thickness of the thin film conductive layer.

3. The method according to claim 2, further comprising: The current is applied to the thin film conductive layer at the first polarity to further reduce or eliminate the one or more defects on the plurality of traces.

4. The method according to claim 1, further comprising: The thin film conductive layer is removed by one or more of etching or stripping.

5. The method according to claim 3, wherein At least some of the one or more defects include burrs.

6. An electrical island deburring (EID) process for reducing or eliminating one or more defects present on one or more traces carried on a substrate of a printed circuit board (PCB), the one or more traces including at least some island traces electrically isolated from each other, the EID comprising: depositing a conductive layer on the one or more PCB traces, the conductive layer electrically connecting at least some of the one or more PCB traces and at least some of the one or more defects; as well as An electric current is applied to the conductive layer to reduce or eliminate one or more defects in the one or more PCB traces.

7. The electrical island deburring (EID) process according to claim 6, wherein the step of applying current further comprises: connecting a power source between a first contact on the PCB and a second contact on the PCB; applying an electrolytic composition between the first contact, the one or more PCB traces, and the one or more defects to define an electrolytic cell; as well as The current is applied to the electrolytic cell at a first polarity to reduce or eliminate the one or more defects in the one or more PCB traces.

8. The electrical island deburring (EID) process according to claim 7, further comprising: The current is applied to the electrolytic cell at a second polarity to provide electroplating of the conductive layer.

9. The electrical island deburring (EID) process according to claim 6, wherein: The voltage of the current is determined by the composition of the PCB trace, the conductive layer, or a combination thereof.

10. The electrical island deburring (EID) process according to claim 6, further comprising: Applying an electropolish to the PCB traces, comprising: applying a voltage to an anode contact of the electrolytic cell to form a high resistance path between the anode contact, the electrolyte, and the peaks of the one or more defects of the one or more PCB traces; and A high current density is induced at the peaks of the one or more defects, dissolving the one or more defects at a higher rate than the one or more PCB traces.

11. The electrical island deburring (EID) process according to claim 10, further comprising: The electropolishing is applied to the PCB trace when the size of the one or more defects is comparable to the surface roughness of the PCB trace.

12. The electrical island deburring (EID) process according to claim 6, further comprising: applying electrical deburring to the PCB trace when the one or more defects are burrs; as well as A suitable voltage is applied to the anode contact of the electrolytic cell to induce a high current density at the sharp peaks of the one or more burrs, thereby dissolving or reducing the one or more burrs at a higher rate than the one or more PCB traces.

13. The electrical island deburring (EID) process according to claim 12, further comprising: The electrical deburring is applied to the one or more PCB traces when the size of the one or more burrs is comparable to or larger than the surface roughness of the one or more PCB traces.

14. The electrical island deburring (EID) process according to claim 6, further comprising: applying plasma electropolishing (PeP) to the one or more PCB traces; as well as A high voltage is applied to the electrolytic cell to generate a discharge as a plasma arc at the sharp peak of the one or more burrs.

15. The electrical island deburring (EID) process according to claim 6, wherein: The step of depositing the conductive layer is selected from: physical vapor deposition (PVD), sputtering, chemical vapor deposition (CVD), atomic layer deposition (ALD), spin coating, spray coating, dip coating, electroless copper plating, liquid metal ink or a combination thereof.

16. The electrical island deburring (EID) process according to claim 6, further comprising: The one or more PCB traces are formed on an insulating substrate.

17. The electrical island deburring (EID) process according to claim 6, further comprising: generating the PCB traces; as well as For each layer in a multi-layer PCB: repeatedly generating the one or more PCB traces; as well as After repeatedly creating the PCB traces, vias are formed between the multiple layers.

18. A method comprising: Applying an electrical island deburring (EID) process to reduce or eliminate burrs present on laser micromachined printed circuit board (PCB) traces, at least some of the PCB traces being electrically isolated from each other, the EID process comprising: depositing a conductive layer on the PCB traces, causing the conductive layer to electrically connect at least some of the PCB traces; and A current or voltage is applied to the conductive layer to reduce or eliminate the burrs.

19. The method according to claim 18, further comprising: Laser micromachining the PCB traces.

20. The method according to claim 19, comprising: Repeating the laser micromachining PCB traces and the EID process for each of the multiple layers of the multi-layer PCB; as well as After repeatedly laser micromachining the PCB traces, vias are formed between at least some of the multiple layers.

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