Pixel circuit, driving method and display device

Abstract

The invention provides a pixel circuit, a driving method and a display device. The pixel circuit comprises N sub-pixels, N first initial voltage ends and N second initial voltage ends, wherein N is an integer greater than 1; n is a positive integer smaller than or equal to N; the nth sub-pixel comprises an nth driving circuit, an nth light-emitting element, an nth first initialization circuit, an nth second initialization circuit and an nth first light-emitting control circuit; the nth first initialization circuit writes the nth first initial voltage into the nth third node under the control of a first reset control signal; the nth second initialization circuit writes the nth second initial voltage into the nth second node under the control of a second reset control signal; the at least two first initial voltages are different from each other, and / or the at least two second initial voltages are different from each other. According to the invention, the nodes in the sub-pixels of different colors are reset through different initial voltages, so that higher-precision image display under high frequency is realized.

Description

Pixel circuit, driving method and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, and a display device. Background Art

[0002] In the related art, the red sub-pixel, the green sub-pixel and the blue sub-pixel are reset with the same initial voltage. For the first node (the first node is the node electrically connected to the control end of the driving circuit), since the pixel current of the blue sub-pixel is relatively large, the data voltage corresponding to the blue sub-pixel is different from the data voltages of the other color sub-pixels. Therefore, using the same initial voltage to reset the first node will cause display deviations caused by different charging rates; for the third node (the third node is the node electrically connected to the second end of the driving circuit), the pixel current of the blue sub-pixel is greater than the pixel current of the red sub-pixel, the pixel current of the blue pixel is greater than the pixel current of the green sub-pixel, the hysteresis of the driving transistor in the blue sub-pixel is greater than the hysteresis of the driving transistor in the red sub-pixel, and the hysteresis of the driving transistor in the blue sub-pixel is greater than the hysteresis of the driving transistor in the blue sub-pixel. Therefore, using the same initial voltage to reset the second node is likely to cause display deviations.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a pixel circuit comprising N sub-pixels, N first initial voltage terminals, and N second initial voltage terminals, where N is an integer greater than 1; and n is a positive integer less than or equal to N.

[0005] The nth sub-pixel includes an nth driving circuit, an nth light-emitting element, an nth first initialization circuit, an nth second initialization circuit and an nth first light-emitting control circuit;

[0006] The control terminal of the nth driving circuit is electrically connected to the nth first node, the first terminal of the nth driving circuit is electrically connected to the nth second node, and the second terminal of the nth driving circuit is electrically connected to the nth third node, and the nth driving circuit is configured to generate a driving current for driving the nth light-emitting element under the control of the potential of the nth first node;

[0007] The nth first light-emitting control circuit is electrically connected to the light-emitting control terminal, the nth third node, and the first electrode of the nth light-emitting element, respectively, and is configured to control the connection between the nth third node and the first electrode of the nth light-emitting element under the control of a light-emitting control signal provided by the light-emitting control terminal; and the second electrode of the nth light-emitting element is electrically connected to the second voltage terminal;

[0008] The nth first initialization circuit is electrically connected to the first reset control terminal, the nth first initial voltage terminal, and the nth third node, respectively, and is configured to write the nth first initial voltage provided by the nth first initial voltage terminal into the nth third node under the control of a first reset control signal provided by the first reset control terminal;

[0009] The nth second initialization circuit is electrically connected to the second reset control terminal, the nth second initial voltage terminal, and the nth second node, respectively, and is configured to write the nth second initial voltage provided by the nth second initial voltage terminal into the nth second node under the control of a second reset control signal provided by the second reset control terminal;

[0010] The first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other.

[0011] Optionally, the pixel circuit includes three sub-pixels, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel;

[0012] The first first initial voltage is different from the third first initial voltage, and the second first initial voltage is different from the third first initial voltage.

[0013] Optionally, the driving transistor included in each driving circuit is a p-type transistor, the first first initial voltage is greater than the third first initial voltage, and the second first initial voltage is greater than the third first initial voltage; or,

[0014] The driving transistor included in each driving circuit is an n-type transistor, the first first initial voltage is smaller than the third first initial voltage, and the second first initial voltage is smaller than the third first initial voltage.

[0015] Optionally, the first first initial voltage is equal to the second first initial voltage.

[0016] Optionally, the driving transistor is a p-type transistor, and the first initial voltage is smaller than the second initial voltage; or

[0017] The driving transistor is a p-type transistor, and the first first initial voltage is greater than the second first initial voltage.

[0018] Optionally, the pixel circuit includes three sub-pixels, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel;

[0019] The first second initial voltage is different from the third second initial voltage, and the second second initial voltage is different from the third second initial voltage.

[0020] Optionally, the driving transistor included in each driving circuit is a p-type transistor, the first second initial voltage is greater than the third second initial voltage, and the second second initial voltage is greater than the third second initial voltage; or,

[0021] The driving transistor included in each driving circuit is an n-type transistor, the first second initial voltage is smaller than the third second initial voltage, and the second second initial voltage is smaller than the third second initial voltage.

[0022] Optionally, the first second initial voltage is equal to the second second initial voltage.

[0023] Optionally, the driving transistor is a p-type transistor, and the first second initial voltage is smaller than the second second initial voltage; or

[0024] The driving transistor is an n-type transistor, and the first second initial voltage is greater than the second second initial voltage.

[0025] Optionally, the pixel circuit further includes N third initial voltage terminals; the nth sub-pixel further includes an nth third initialization circuit;

[0026] The nth third initialization circuit is electrically connected to the third reset control terminal, the nth third initial voltage terminal and the first electrode of the nth light-emitting element, respectively, and is used to write the nth third initial voltage provided by the nth third initial voltage terminal into the first electrode of the nth light-emitting element under the control of a third reset control signal provided by the third reset control terminal.

[0027] Optionally, the third initial voltages provided by the N third initial voltage terminals are the same.

[0028] Optionally, the nth sub-pixel further includes an nth energy storage circuit, an nth compensation control circuit and an nth data writing circuit;

[0029] The first end of the nth energy storage circuit is electrically connected to the nth first node, the second end of the nth energy storage circuit is electrically connected to the DC voltage terminal, and the nth energy storage circuit is used to store electrical energy;

[0030] The nth compensation control circuit is electrically connected to the compensation control terminal, the nth first node, and the nth third node, respectively, and is used to control the communication between the nth first node and the nth third node under the control of the compensation control signal provided by the compensation control terminal;

[0031] The nth data writing circuit is electrically connected to the write control terminal, the nth data line and the nth second node respectively, and is used to write the nth data voltage provided by the nth data line into the nth second node under the control of the write control signal provided by the write control terminal.

[0032] Optionally, the nth sub-pixel further includes an nth second light emitting control circuit;

[0033] The nth second light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal and the nth second node respectively, and is used to control the connection between the first voltage terminal and the nth second node under the control of the light-emitting control signal.

[0034] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned pixel circuit. The driving method includes:

[0035] The nth driving circuit generates a driving current for driving the nth light-emitting element under the control of the potential of the nth first node;

[0036] The nth first light emitting control circuit controls the connection between the nth third node and the first electrode of the nth light emitting element under the control of the light emitting control signal;

[0037] The nth first initialization circuit writes the nth first initial voltage provided by the nth first initial voltage terminal into the nth third node under the control of the first reset control signal;

[0038] The nth second initialization circuit writes the nth second initial voltage provided by the nth second initial voltage terminal into the nth second node under the control of the second reset control signal;

[0039] The first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other;

[0040] N is an integer greater than 1; n is a positive integer less than or equal to N.

[0041] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0043] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0044] FIG3 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0045] FIG4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0046] FIG5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0047] FIG6 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0048] FIG. 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0050] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0051] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0052] The pixel circuit according to the embodiment of the present disclosure includes N sub-pixels, N first initial voltage terminals, and N second initial voltage terminals, where N is an integer greater than 1; and n is a positive integer less than or equal to N.

[0053] The nth sub-pixel includes an nth driving circuit, an nth light-emitting element, an nth first initialization circuit, an nth second initialization circuit and an nth first light-emitting control circuit;

[0054] The control terminal of the nth driving circuit is electrically connected to the nth first node, the first terminal of the nth driving circuit is electrically connected to the nth second node, and the second terminal of the nth driving circuit is electrically connected to the nth third node, and the nth driving circuit is configured to generate a driving current for driving the nth light-emitting element under the control of the potential of the nth first node;

[0055] The nth first light-emitting control circuit is electrically connected to the light-emitting control terminal, the nth third node, and the first electrode of the nth light-emitting element, respectively, and is configured to control the connection between the nth third node and the first electrode of the nth light-emitting element under the control of a light-emitting control signal provided by the light-emitting control terminal to perform light-emitting control; the second electrode of the nth light-emitting element is electrically connected to the second voltage terminal;

[0056] The nth first initialization circuit is electrically connected to the first reset control terminal, the nth first initial voltage terminal, and the nth third node, respectively, and is configured to write the nth first initial voltage provided by the nth first initial voltage terminal into the nth third node under the control of a first reset control signal provided by the first reset control terminal, thereby initializing the potential of the nth third node;

[0057] The nth second initialization circuit is electrically connected to the second reset control terminal, the nth second initial voltage terminal, and the nth second node, respectively, and is configured to write the nth second initial voltage provided by the nth second initial voltage terminal into the nth second node under the control of a second reset control signal provided by the second reset control terminal, so as to initialize the potential of the nth second node;

[0058] The first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other.

[0059] In the related art, the red sub-pixel, the green sub-pixel and the blue sub-pixel are reset with the same initial voltage. For the first node (the first node is the node electrically connected to the control end of the driving circuit), since the pixel current of the blue sub-pixel is relatively large, when the driving transistor included in the n-th driving circuit is a p-type transistor, the required data voltage is more negative, and the initial voltage corresponding to the blue sub-pixel should be lower. When the driving transistor included in the n-th driving circuit is an n-type transistor, the required data voltage is more positive, and the initial voltage corresponding to the blue sub-pixel should be higher to improve the charging rate. For the second node (the second node is the node electrically connected to the first end of the driving circuit), the pixel current of the blue sub-pixel is greater than the pixel current of the red sub-pixel, the pixel current of the blue sub-pixel is greater than the pixel current of the green sub-pixel, the hysteresis of the driving transistor in the blue sub-pixel is greater than the hysteresis of the driving transistor in the red sub-pixel, and the hysteresis of the driving transistor in the blue sub-pixel is greater than the hysteresis of the driving transistor in the blue sub-pixel. Therefore, using the same initial voltage to reset the second node can easily cause display deviation.

[0060] In at least one embodiment of the present disclosure, the first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other. The first nodes in each color sub-pixel can be reset by different initial voltages, and the second nodes in each color sub-pixel can be reset by different initial voltages. Multiple initial voltages are adjusted together to achieve higher precision image display at high frequency.

[0061] When the driving transistor is a p-type transistor, the data voltage corresponding to the blue sub-pixel is the smallest. If the first initial voltages corresponding to the red sub-pixel, the green sub-pixel, and the blue sub-pixel are the same, then for the blue sub-pixel, the voltage difference between the data voltage and the first initial voltage is smaller, and the charging rate is smaller. Therefore, in at least one embodiment of the present disclosure, when the driving transistor is a p-type transistor, the third first initial voltage is set to be smaller so that the charging rates of the corresponding red sub-pixels, the green sub-pixels, and the blue sub-pixels are substantially the same.

[0062] When the driving transistor is an n-type transistor, the data voltage corresponding to the blue sub-pixel is the largest. If the first initial voltages corresponding to the red sub-pixel, the green sub-pixel, and the blue sub-pixel are the same, then for the blue sub-pixel, the voltage difference between the data voltage and the first initial voltage is larger, and the charging rate is larger. Therefore, in at least one embodiment of the present disclosure, when the driving transistor is a p-type transistor, the third first initial voltage is set to be larger so that the charging rates corresponding to the red sub-pixel, the green sub-pixel, and the blue sub-pixel are approximately the same.

[0063] In at least one embodiment of the present disclosure, when the driving transistor is a p-type transistor, the voltage value of each first initial voltage can be greater than or equal to -5V and less than or equal to -3V, and the voltage value of each second initial voltage can be greater than or equal to 5V and less than or equal to 8V, but the present invention is not limited thereto. In specific implementations, the first initial voltage and the second initial voltage can be selected based on actual conditions.

[0064] The following description takes N equal to 3 as an example.

[0065] As shown in FIG1 , the pixel circuit according to the embodiment of the present disclosure includes a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, a first first initial voltage terminal I11, a second first initial voltage terminal I21, a third first initial voltage terminal I31, a first second initial voltage terminal I12, a second second initial voltage terminal I22, and a third second initial voltage terminal I32;

[0066] The first sub-pixel P1 includes a first driving circuit 10, a first light-emitting element E1, a first first initialization circuit 11, a first second initialization circuit 12 and a first first light-emitting control circuit 13;

[0067] The control end of the first driving circuit 10 is electrically connected to a first first node N11, the first end of the first driving circuit 10 is electrically connected to a first second node N12, and the second end of the first driving circuit 10 is electrically connected to a first third node N13. The first driving circuit is configured to generate a driving current for driving the first light-emitting element E1 under the control of the potential of the first first node N11.

[0068] The first first light-emitting control circuit 13 is electrically connected to the light-emitting control terminal EM, the first third node N13, and the first electrode of the first light-emitting element E1, respectively, and is configured to control the first third node N13 to be connected to the first electrode of the first light-emitting element E1 under the control of a light-emitting control signal provided by the light-emitting control terminal EM; and the second electrode of the first light-emitting element E1 is electrically connected to the second voltage terminal V2;

[0069] The first first initialization circuit 11 is electrically connected to the first reset control terminal RP, the first first initial voltage terminal I11, and the first third node N13, respectively, and is configured to write the first first initial voltage provided by the first first initial voltage terminal I11 into the first third node N13 under the control of the first reset control signal provided by the first reset control terminal RP1;

[0070] The first second initialization circuit 12 is electrically connected to the second reset control terminal RH, the first second initial voltage terminal I12 and the first second node N12 respectively, and is used to write the first second initial voltage provided by the first second initial voltage terminal I12 into the first second node N12 under the control of the second reset control signal provided by the second reset control terminal RH;

[0071] The second sub-pixel P2 includes a second driving circuit 20, a second light-emitting element E2, a second first initialization circuit 21, a second second initialization circuit 22 and a second first light-emitting control circuit 23;

[0072] The control end of the second driving circuit 20 is electrically connected to the second first node N21, the first end of the second driving circuit 20 is electrically connected to the second second node N22, and the second end of the second driving circuit 20 is electrically connected to the second third node N23. The second driving circuit 20 is configured to generate a driving current for driving the second light-emitting element E2 under the control of the potential of the second first node N21.

[0073] The second first light-emitting control circuit 23 is electrically connected to the light-emitting control terminal EM, the second third node N23, and the first electrode of the second light-emitting element E2, respectively, and is configured to control the second third node N23 to be connected to the first electrode of the second light-emitting element E2 under the control of a light-emitting control signal provided by the light-emitting control terminal EM; and the second electrode of the second light-emitting element E2 is electrically connected to the second voltage terminal V2;

[0074] The second first initialization circuit 21 is electrically connected to the first reset control terminal RP, the second first initial voltage terminal I21, and the second third node N23, respectively, and is configured to write the second first initial voltage provided by the second first initial voltage terminal I21 into the second third node N23 under the control of the first reset control signal provided by the first reset control terminal RP;

[0075] The second second initialization circuit 22 is electrically connected to the second reset control terminal RH, the second second initial voltage terminal I22 and the second second node N22, respectively, and is configured to write the second second initial voltage provided by the second second initial voltage terminal I22 into the second second node N12 under the control of the second reset control signal provided by the second reset control terminal RH;

[0076] The third sub-pixel P3 includes a third driving circuit 30, a third light-emitting element E3, a third first initialization circuit 31, a third second initialization circuit 32 and a third first light-emitting control circuit 33;

[0077] The control terminal of the third driving circuit 30 is electrically connected to the third first node N31, the first terminal of the third driving circuit 30 is electrically connected to the third second node N32, and the second terminal of the third driving circuit 20 is electrically connected to the third third node N33. The third driving circuit 20 is configured to generate a driving current for driving the third light-emitting element E3 under the control of the potential of the third first node N31.

[0078] The third first light-emitting control circuit 33 is electrically connected to the light-emitting control terminal EM, the third third node N33, and the first electrode of the third light-emitting element E3, respectively, and is configured to control the third third node N33 to be connected to the first electrode of the third light-emitting element E3 under the control of a light-emitting control signal provided by the light-emitting control terminal EM; and the second electrode of the third light-emitting element E3 is electrically connected to the second voltage terminal V2.

[0079] The third first initialization circuit 31 is electrically connected to the first reset control terminal RP, the third first initial voltage terminal I31, and the third third node N33, respectively, and is configured to write the third first initial voltage provided by the third first initial voltage terminal I31 into the third third node N33 under the control of the first reset control signal provided by the first reset control terminal RP;

[0080] The third second initialization circuit 32 is electrically connected to the second reset control terminal RH, the third second initial voltage terminal I32 and the third second node N32, respectively, and is configured to write the second second initial voltage provided by the second second initial voltage terminal I22 into the third second node N32 under the control of the second reset control signal provided by the second reset control terminal RH;

[0081] Optionally, the pixel circuit includes three sub-pixels, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel;

[0082] The first first initial voltage is different from the third first initial voltage, and the second first initial voltage is different from the third first initial voltage.

[0083] In at least one embodiment of the present disclosure, the first first initial voltage is the first initial voltage provided to the first sub-pixel, the second first initial voltage is the first initial voltage provided to the second sub-pixel, and the third first initial voltage is the first initial voltage provided to the third sub-pixel.

[0084] In a specific implementation, since the pixel current of the blue sub-pixel is relatively large and the required data voltage is more negative, the third first initial voltage corresponding to the blue sub-pixel is set to be different from the first initial voltages corresponding to the other two sub-pixels to avoid display deviation caused by using the same first initial voltage.

[0085] In at least one embodiment of the present disclosure, when the driving transistor included in each driving circuit is a p-type transistor, the first first initial voltage is greater than the third first initial voltage, and the second first initial voltage is greater than the third first initial voltage;

[0086] When each driving transistor is an n-type transistor, the first first initial voltage is smaller than the third first initial voltage, and the second first initial voltage is smaller than the third first initial voltage.

[0087] In a specific implementation, when the driving transistor is a p-type transistor, the voltage value of the third first initial voltage can be set to be relatively small;

[0088] When the driving transistor is an n-type transistor, the voltage value of the third first initial voltage can be set to be relatively large.

[0089] Optionally, the first first initial voltage is equal to the second first initial voltage.

[0090] In a specific implementation, the first initial voltage may be equal to the second first initial voltage.

[0091] In at least one embodiment of the present disclosure, when the driving transistor is a p-type transistor, the first first initial voltage is less than the second first initial voltage; when the driving transistor is an n-type transistor, the first first initial voltage is greater than the second first initial voltage.

[0092] In a specific implementation, since the pixel current of the red sub-pixel is greater than the pixel current of the green sub-pixel, when the driving transistor is a p-type transistor, the first first initial voltage can be set to be less than the second first initial voltage so that the charging rate of the red sub-pixel and the charging rate of the green sub-pixel are approximately the same; when the driving transistor is an n-transistor, the first first initial voltage can be set to be greater than the second first initial voltage so that the charging rate of the red sub-pixel and the charging rate of the green sub-pixel are approximately the same.

[0093] In at least one embodiment of the present disclosure, the pixel circuit includes three sub-pixels, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel;

[0094] The first second initial voltage is different from the third second initial voltage, and the second second initial voltage is different from the third second initial voltage.

[0095] In specific implementation, since the pixel current of the blue sub-pixel is relatively large, the required data voltage is more negative.

[0096] Therefore, the third second initial voltage corresponding to the blue sub-pixel is set to be different from the second initial voltages corresponding to the other two sub-pixels, so as to avoid display deviation caused by using the same second initial voltage.

[0097] Optionally, when the driving transistor included in each driving circuit is a p-type transistor, the first second initial voltage is greater than the third second initial voltage, and the second second initial voltage is greater than the third second initial voltage;

[0098] When each driving transistor is an n-type transistor, the first second initial voltage is smaller than the third second initial voltage, and the second second initial voltage is smaller than the third second initial voltage.

[0099] In at least one embodiment of the present disclosure, the first second initial voltage is the second initial voltage provided to the first sub-pixel, the second second initial voltage is the second initial voltage provided to the second sub-pixel, and the third second initial voltage is the second initial voltage provided to the third sub-pixel; the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a green sub-pixel, and the third sub-pixel can be a blue sub-pixel.

[0100] In a specific implementation, when the driving transistor is a p-type transistor, the data voltage corresponding to the blue sub-pixel is more negative. When resetting the potential of each second node through each eighth transistor, by setting the third second initial voltage corresponding to the blue sub-pixel to a smaller value, the gate-source voltage of the red sub-pixel, the gate-source voltage of the green sub-pixel, and the gate-source voltage of the blue sub-pixel are substantially the same when resetting the potential of each second node through each eighth transistor. This provides the driving transistors in each sub-pixel with a substantially identical bias state, thereby improving the display effect.

[0101] When the driving transistor is an n-type transistor, the data voltage corresponding to the blue sub-pixel is corrected, and when the potential of each second node is reset through each eighth transistor, by setting the third second initial voltage corresponding to the blue sub-pixel to a larger value, it is possible to make the gate-source voltage of the red sub-pixel, the gate-source voltage of the green sub-pixel and the gate-source voltage of the blue sub-pixel be roughly the same when the potential of each second node is reset through each eighth transistor, and the driving transistors in each sub-pixel have a roughly the same bias state, thereby improving the display effect.

[0102] In a specific implementation, when the driving transistor is a p-type transistor, the voltage value of the third second initial voltage can be set to be relatively small;

[0103] When the driving transistor is a p-type transistor, the voltage value of the third second initial voltage can be set to be relatively large.

[0104] Optionally, the first second initial voltage is equal to the second second initial voltage; or,

[0105] When the driving transistor is a p-type transistor, the first second initial voltage is less than the second second initial voltage; when the driving transistor is an n-type transistor, the first second initial voltage is greater than the second second initial voltage.

[0106] In a specific implementation, since the pixel current of the red sub-pixel is greater than the pixel current of the green sub-pixel, when the driving transistor is a p-type transistor, the first second initial voltage can be set to be less than the second second initial voltage, and when the driving transistor is an n-type transistor, the first second initial voltage can be set to be greater than the second second initial voltage, so as to give the driving transistor in the red sub-pixel and the driving transistor in the green sub-pixel a roughly identical bias state, thereby improving the display effect.

[0107] In at least one embodiment of the present disclosure, the pixel circuit further includes N third initial voltage terminals; the nth sub-pixel further includes an nth third initialization circuit;

[0108] The nth third initialization circuit is electrically connected to the third reset control terminal, the nth third initial voltage terminal and the first electrode of the nth light-emitting element, respectively, and is used to write the nth third initial voltage provided by the nth third initial voltage terminal into the first electrode of the nth light-emitting element under the control of a third reset control signal provided by the third reset control terminal.

[0109] In a specific implementation, the nth sub-pixel may further include an nth third initialization circuit, which, under the control of a third reset control signal, writes the nth third initial voltage provided by the nth third initial voltage terminal into the first electrode of the nth light-emitting element to clear the residual charge in the first electrode of the nth light-emitting element.

[0110] Optionally, the third initial voltages provided by the N third initial voltage terminals are the same, but not limited thereto; in actual operation, the third initial voltages provided by at least two third initial voltage terminals may be different from each other.

[0111] In actual operation, when the third initial voltages provided by the N third initial voltage terminals are the same, the number of initial voltage lines used to provide the third initial voltage can be reduced.

[0112] In at least one embodiment of the present disclosure, the second reset control terminal and the third reset control terminal may be the same control terminal, but the present invention is not limited thereto.

[0113] In at least one embodiment of the present disclosure, the nth sub-pixel further includes an nth energy storage circuit, an nth compensation control circuit, and an nth data writing circuit;

[0114] The first end of the nth energy storage circuit is electrically connected to the nth first node, the second end of the nth energy storage circuit is electrically connected to the DC voltage terminal, and the nth energy storage circuit is used to store electrical energy;

[0115] The nth compensation control circuit is electrically connected to the compensation control terminal, the nth first node, and the nth third node, respectively, and is used to control the communication between the nth first node and the nth third node under the control of the compensation control signal provided by the compensation control terminal;

[0116] The nth data writing circuit is electrically connected to the write control terminal, the nth data line and the nth second node respectively, and is used to write the nth data voltage provided by the nth data line into the nth second node under the control of the write control signal provided by the write control terminal.

[0117] In a specific implementation, the nth sub-pixel may further include an nth energy storage circuit, an nth compensation control circuit and an nth data writing circuit; the nth energy storage circuit maintains the potential of the nth first node; the nth compensation control circuit, under the control of a compensation control signal, controls the connection between the nth first node and the nth third node to perform threshold voltage compensation; the nth data writing circuit, under the control of the write control signal, writes the nth data voltage provided by the nth data line into the nth second node to perform data voltage writing.

[0118] Optionally, the nth sub-pixel further includes an nth second light emitting control circuit;

[0119] The nth second light-emitting control circuit is electrically connected to the light-emitting control terminal, the first voltage terminal and the nth second node respectively, and is used to control the connection between the first voltage terminal and the nth second node under the control of the light-emitting control signal.

[0120] In a specific implementation, the nth sub-pixel may further include an nth second light-emitting control circuit, which controls the connection between the first voltage terminal and the nth second node under the control of the light-emitting control signal to perform light-emitting control.

[0121] As shown in FIG2 , based on at least one embodiment of the pixel circuit shown in FIG1 , the pixel circuit further includes a first third initial voltage terminal I13 , a second third initial voltage terminal I23 , and a third third initial voltage terminal I33 ; the first sub-pixel further includes a first third initialization circuit 14 ;

[0122] The first third initialization circuit 14 is electrically connected to the second reset control terminal RH, the first third initial voltage terminal I13, and the first electrode of the first light-emitting element E1, respectively, and is configured to write the first third initial voltage provided by the first third initial voltage terminal I13 into the first electrode of the first light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal RH;

[0123] The first sub-pixel may further include a first energy storage circuit 15, a first compensation control circuit 16 and a first data writing circuit 17;

[0124] A first end of the first energy storage circuit 15 is electrically connected to the first first node N11, a second end of the first energy storage circuit 15 is electrically connected to the first voltage terminal V1, and the first energy storage circuit 15 is used to store electrical energy;

[0125] The first compensation control circuit 16 is electrically connected to the compensation control terminal GN, the first first node N11, and the first third node N13, respectively, and is configured to control the communication between the first first node N11 and the first third node N13 under the control of a compensation control signal provided by the compensation control terminal GN;

[0126] The first data writing circuit 17 is electrically connected to the write control terminal GP, the first data line DT1 and the first second node N12, respectively, and is configured to write the first data voltage provided by the first data line DT1 into the first second node N12 under the control of the write control signal provided by the write control terminal GP;

[0127] The first sub-pixel further includes a first second light emitting control circuit 18;

[0128] The first and second light emitting control circuits 18 are electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the first second node N12, respectively, and are used to control the connection between the first voltage terminal V1 and the first second node N12 under the control of the light emitting control signal;

[0129] The second sub-pixel further includes a second third initialization circuit 24;

[0130] The second third initialization circuit 24 is electrically connected to the second reset control terminal RH, the second third initial voltage terminal I23, and the first electrode of the second light-emitting element E2, respectively, and is configured to write the second third initial voltage provided by the second third initial voltage terminal I23 into the first electrode of the second light-emitting element E2 under the control of the second reset control signal provided by the second reset control terminal RH;

[0131] The second sub-pixel may further include a second energy storage circuit 25, a second compensation control circuit 26 and a first data writing circuit 27;

[0132] A first end of the second energy storage circuit 25 is electrically connected to the second first node N21, a second end of the second energy storage circuit 25 is electrically connected to the first voltage terminal V1, and the second energy storage circuit 25 is used to store electrical energy;

[0133] The second compensation control circuit 26 is electrically connected to the compensation control terminal GN, the second first node N21, and the second third node N23, respectively, and is configured to control the communication between the second first node N21 and the second third node N23 under the control of the compensation control signal provided by the compensation control terminal GN;

[0134] The second write circuit 27 is electrically connected to the write control terminal GP, the second data line DT2 and the second second node N22, respectively, and is used to write the second data voltage provided by the second data line DT2 into the second second node N22 under the control of the write control signal provided by the write control terminal GP;

[0135] The second sub-pixel further includes a second second light emitting control circuit 28;

[0136] The second second light emitting control circuit 28 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the second second node N22 respectively, and is used to control the connection between the first voltage terminal V1 and the second second node N22 under the control of the light emitting control signal;

[0137] The third sub-pixel may further include a second energy storage circuit 35, a third compensation control circuit 36 ​​and a third data writing circuit 37;

[0138] A first end of the third energy storage circuit 35 is electrically connected to the third first node N31, a second end of the third energy storage circuit 35 is electrically connected to the first voltage terminal V1, and the third energy storage circuit 35 is used to store electrical energy;

[0139] The third compensation control circuit 26 is electrically connected to the compensation control terminal GN, the third first node N31, and the third third node N33, respectively, and is configured to control the communication between the third first node N31 and the third third node N33 under the control of the compensation control signal provided by the compensation control terminal GN;

[0140] The third write circuit 37 is electrically connected to the write control terminal GP, the third data line DT3 and the third second node N32, respectively, and is configured to write the third data voltage provided by the third data line DT3 into the third second node N32 under the control of the write control signal provided by the write control terminal GP;

[0141] The third sub-pixel further includes a third second light emitting control circuit 38;

[0142] The third second light emitting control circuit 38 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the third second node N32 respectively, and is used to control the connection between the first voltage terminal V1 and the third second node N32 under the control of the light emitting control signal.

[0143] Optionally, the first voltage terminal may be a high voltage terminal, and the second voltage terminal may be a low voltage terminal.

[0144] As shown in FIG3 , in at least one embodiment of the pixel circuit shown in FIG2 , the first driving circuit 10 may include a first driving transistor T13, the first light-emitting element is a first organic light-emitting diode O1; the first first initialization circuit includes a first first initialization transistor T11, the first second initialization circuit includes a first second initialization transistor T18, and the first first light-emitting control circuit includes a first first light-emitting control transistor T16;

[0145] The gate of the first driving transistor T13 is electrically connected to the first first node N11, the source of the first driving transistor T13 is electrically connected to the first second node N12, and the drain of the first driving transistor T13 is electrically connected to the first third node N13;

[0146] The gate of the first first emission control transistor T16 is electrically connected to the emission control terminal EM, the source of the first first emission control transistor T16 is electrically connected to the first third node N13, the drain of the first first emission control transistor T16 is electrically connected to the anode of the first organic light emitting diode O1; and the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0147] The gate of the first first initialization transistor T11 is electrically connected to the first reset control terminal RP, the source of the first first initialization transistor T11 is electrically connected to the first first initial voltage terminal I11, and the drain of the first first initialization transistor T11 is electrically connected to the first third node N13;

[0148] The gate of the first second initialization transistor T18 is electrically connected to the second reset control terminal RH, the source of the first second initialization transistor T18 is electrically connected to the first second initial voltage terminal I12, and the drain of the first second initialization transistor T18 is electrically connected to the first second node N12;

[0149] The first third initialization circuit 14 includes a first third initialization transistor T17;

[0150] The gate of the first third initialization transistor T17 is electrically connected to the second reset control terminal RH, the source of the first third initialization transistor T17 is electrically connected to the first third initial voltage terminal I13, and the drain of the first third initialization transistor T17 is electrically connected to the anode of the first organic light emitting diode O1;

[0151] The first energy storage circuit includes a first storage capacitor Cst1, the first compensation control circuit includes a first compensation control transistor T12, and the first data writing circuit includes a first data writing transistor T14;

[0152] A first end of the first storage capacitor Cst1 is electrically connected to the first first node N11, and a second end of the first storage capacitor Cst1 is electrically connected to the high voltage terminal VDD;

[0153] The gate of the first compensation control transistor T12 is electrically connected to the compensation control terminal GN, the source of the first compensation control transistor T12 is electrically connected to the first first node N11, and the drain of the first compensation control transistor T12 is electrically connected to the first third node N13;

[0154] The gate of the first data writing transistor T14 is electrically connected to the writing control terminal GP, the source of the first data writing transistor T14 is electrically connected to the first data line DT1, and the drain of the first data writing transistor T14 is electrically connected to the first second node N12;

[0155] The first second light emitting control circuit includes a first second light emitting control transistor T15;

[0156] The gate of the first second light emitting control transistor T15 is electrically connected to the light emitting control terminal EM, the source of the first second light emitting control transistor T15 is electrically connected to the high voltage terminal VDD, and the drain of the first second light emitting control transistor T15 is electrically connected to the first second node N12;

[0157] The second driving circuit may include a second driving transistor T2, and the second light-emitting element is a second organic light-emitting diode O2; the second first initialization circuit includes a second first initialization transistor T21, the second second initialization circuit includes a second second initialization transistor T28, and the second first light-emitting control circuit includes a second first light-emitting control transistor T26;

[0158] The gate of the second driving transistor T23 is electrically connected to the second first node N21, the source of the second driving transistor T23 is electrically connected to the second second node N22, and the drain of the second driving transistor T23 is electrically connected to the second third node N23;

[0159] a gate of the second first emission control transistor T26 electrically connected to the emission control terminal EM, a source of the second first emission control transistor T26 electrically connected to the second third node N23, and a drain of the second first emission control transistor T26 electrically connected to the anode of the second organic light emitting diode O2;

[0160] The gate of the second first initialization transistor T21 is electrically connected to the first reset control terminal RP, the source of the second first initialization transistor T21 is electrically connected to the second first initial voltage terminal I21, and the drain of the second first initialization transistor T21 is electrically connected to the second third node N23;

[0161] The gate of the second second initialization transistor T28 is electrically connected to the second reset control terminal RH, the source of the second second initialization transistor T28 is electrically connected to the second second initial voltage terminal I22, and the drain of the second second initialization transistor T28 is electrically connected to the second second node N22;

[0162] The second third initialization circuit includes a second third initialization transistor T27;

[0163] The gate of the second third initialization transistor T27 is electrically connected to the second reset control terminal RH, the source of the second third initialization transistor T27 is electrically connected to the second third initial voltage terminal I23, the drain of the second third initialization transistor T27 is electrically connected to the anode of the second organic light emitting diode O2; the cathode of O2 is electrically connected to the low voltage terminal VSS;

[0164] The second energy storage circuit includes a second storage capacitor Cst2, the second compensation control circuit includes a second compensation control transistor T22, and the second data writing circuit includes a second data writing transistor T24;

[0165] A first end of the second storage capacitor Cst2 is electrically connected to the second first node N21, and a second end of the second storage capacitor Cst2 is electrically connected to the high voltage terminal VDD;

[0166] The gate of the second compensation control transistor T22 is electrically connected to the compensation control terminal GN, the source of the second compensation control transistor T22 is electrically connected to the second first node N21, and the drain of the second compensation control transistor T22 is electrically connected to the second third node N23;

[0167] The gate of the second data writing transistor T24 is electrically connected to the writing control terminal GP, the source of the second data writing transistor T24 is electrically connected to the second data line DT2, and the drain of the second data writing transistor T24 is electrically connected to the second second node N22;

[0168] The second second light emitting control circuit includes a second second light emitting control transistor T25;

[0169] The gate of the second second light emitting control transistor T25 is electrically connected to the light emitting control terminal EM, the source of the second second light emitting control transistor T25 is electrically connected to the high voltage terminal VDD, and the drain of the second second light emitting control transistor T25 is electrically connected to the second second node N22;

[0170] The third driving circuit may include a third driving transistor T3, and the third light-emitting element is a third organic light-emitting diode O3; the third first initialization circuit includes a third first initialization transistor T31, the third second initialization circuit includes a third second initialization transistor T38, and the third first light-emitting control circuit includes a third first light-emitting control transistor T36;

[0171] The gate of the third driving transistor T33 is electrically connected to the third first node N31, the source of the third driving transistor T33 is electrically connected to the third second node N32, and the drain of the third driving transistor T33 is electrically connected to the third node N33;

[0172] a gate of the third first light emitting control transistor T36 electrically connected to the light emitting control terminal EM, a source of the third first light emitting control transistor T36 electrically connected to the third third node N33, and a drain of the third first light emitting control transistor T36 electrically connected to the anode of the third organic light emitting diode O3;

[0173] The gate of the third first initialization transistor T31 is electrically connected to the first reset control terminal RP, the source of the third first initialization transistor T31 is electrically connected to the third first initial voltage terminal I31, and the drain of the third first initialization transistor T31 is electrically connected to the third third node N33;

[0174] The gate of the third second initialization transistor T38 is electrically connected to the second reset control terminal RH, the source of the third second initialization transistor T38 is electrically connected to the third second initial voltage terminal I32, and the drain of the third second initialization transistor T38 is electrically connected to the third second node N32;

[0175] The third initialization circuit includes a third initialization transistor T37;

[0176] The gate of the third initialization transistor T37 is electrically connected to the second reset control terminal RH, the source of the third initialization transistor T37 is electrically connected to the third third initial voltage terminal I33, the drain of the third initialization transistor T37 is electrically connected to the anode of the third organic light emitting diode O3; the cathode of O3 is electrically connected to the low voltage terminal VSS;

[0177] The third energy storage circuit includes a third storage capacitor Cst3, the third compensation control circuit includes a third compensation control transistor T32, and the third data writing circuit includes a third data writing transistor T34;

[0178] A first end of the third storage capacitor Cst3 is electrically connected to the third first node N31, and a second end of the third storage capacitor Cst3 is electrically connected to the high voltage terminal VDD;

[0179] The gate of the third compensation control transistor T32 is electrically connected to the compensation control terminal GN, the source of the third compensation control transistor T32 is electrically connected to the third first node N31, and the drain of the third compensation control transistor T32 is electrically connected to the third third node N33;

[0180] The gate of the third data writing transistor T34 is electrically connected to the writing control terminal GP, the source of the third data writing transistor T34 is electrically connected to the third data line DT3, and the drain of the third data writing transistor T34 is electrically connected to the third second node N32;

[0181] The third second light emitting control circuit includes a third second light emitting control transistor T35;

[0182] The gate of the third second light emitting control transistor T35 is electrically connected to the light emitting control terminal EM, the source of the third second light emitting control transistor T35 is electrically connected to the high voltage terminal VDD, and the drain of the third second light emitting control transistor T35 is electrically connected to the third second node N32.

[0183] In at least one embodiment of the pixel circuit shown in FIG. 3 , T12 , T22 , and T32 are n-type transistors, and the other transistors are p-type transistors, but the present invention is not limited thereto.

[0184] When at least one embodiment of the pixel circuit shown in FIG3 of the present disclosure is in operation, a display cycle may include a first reset phase, a second reset phase, a data writing phase, a third reset phase, and a light emitting phase, which are arranged in sequence;

[0185] In the first reset stage, RH provides a low voltage signal, T18, T28, T38, T17, T27, and T37 are turned on, I12 provides a first second initial voltage to N12, I22 provides a second second initial voltage to N22, and I32 provides a third second initial voltage to N32; I13 provides a first third initial voltage to the anode of O1, I23 provides a second third initial voltage to the anode of O2, and I33 provides a third third initial voltage to the anode of O3, so as to clear the residual charge on the anodes of O1, O2, and O3;

[0186] In the second reset phase, RH provides a high voltage signal, RP provides a low voltage signal, GN provides a high voltage signal, T11 and T12 are turned on, I11 provides a first first initial voltage to N11, so that T13 can be turned on when the data write phase starts; T21 and T22 are turned on, I21 provides a second first initial voltage to N21, so that T23 can be turned on when the data write phase starts; T31 and T32 are turned on, I31 provides a third first initial voltage to N31, so that T33 can be turned on when the data write phase starts;

[0187] In the data writing phase, GN provides a high voltage signal, GP provides a low voltage signal, RH provides a low voltage signal, RP provides a high voltage signal, T14 and T12 are turned on; DT1 writes the first data voltage Vdata1 into N12, DT2 writes the second data voltage Vdata2 into N22, and DT3 writes the third data voltage Vdata3 into N32;

[0188] At the beginning of the data write phase, T13, T23, and T33 are turned on, Vdata1 charges Cst1 to change the potential of N11 until the potential of N11 becomes Vdata1+Vth1, and T13 is turned off; Vdata2 charges Cst2 to change the potential of N21 until the potential of N21 becomes Vdata2+Vth2, and T23 is turned off; Vdata3 charges Cst3 to change the potential of N31 until the potential of N31 becomes Vdata3+Vth3, and T33 is turned off; Vth1 is the threshold voltage of T13, Vth2 is the threshold voltage of T23, and Vth3 is the threshold voltage of T33;

[0189] In the third reset stage, RH provides a low voltage signal, T17 and T18 are turned on, I13 provides a first third initial voltage to the anode of O1 to clear the residual charge at the anode of O1, I12 provides a first second initial voltage to N12 to improve the hysteresis phenomenon; I23 provides a second third initial voltage to the anode of O2 to clear the residual charge at the anode of O2, I22 provides a second second initial voltage to N22 to improve the hysteresis phenomenon; I33 provides a third third initial voltage to the anode of O3 to clear the residual charge at the anode of O3, I32 provides a third second initial voltage to N13 to improve the hysteresis phenomenon.

[0190] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG3 , I11 and I21 are both electrically connected to the first initial voltage line LI1 and receive the initial voltage from the first initial voltage line LI1 ;

[0191] I31 is electrically connected to the second initial voltage line LI2 and receives the initial voltage from the second initial voltage line LI2.

[0192] In at least one embodiment shown in FIG. 4 , the first first initial voltage is greater than the third first initial voltage, the second first initial voltage is greater than the third first initial voltage, and the first first initial voltage is equal to the second first initial voltage.

[0193] In at least one embodiment shown in FIG4 , the first second initial voltage provided by I12 , the second second initial voltage provided by I22 , and the third second initial voltage provided by I32 may be equal;

[0194] The first third initial voltage provided by I13, the second third initial voltage provided by I23, and the third third initial voltage provided by I33 may be equal;

[0195] But it is not limited to this.

[0196] In at least one embodiment of the present disclosure, the added initial voltage trace can overlap with other circuit traces, without causing additional layout space issues.

[0197] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG3 , I11 is electrically connected to the first initial voltage line LI1 , I21 is electrically connected to the second initial voltage line LI2 , and I31 is electrically connected to the third initial voltage line LI3 ;

[0198] I11 receives an initial voltage from a first initial voltage line LI1 , I21 receives an initial voltage from a second initial voltage line LI2 , and I31 receives an initial voltage from a third initial voltage line LI3 .

[0199] In at least one embodiment shown in FIG. 5 , the first first initial voltage is greater than the third first initial voltage, the second first initial voltage is greater than the third first initial voltage, and the first first initial voltage is less than the second first initial voltage.

[0200] In at least one embodiment of the pixel circuit shown in Figure 5, in the first sub-pixel, the second sub-pixel and the third sub-pixel, the first initial voltages connected to the first initialization transistors are different. During high-frequency display, different pixel node voltages can be reset in a targeted manner to give the driving transistors the same bias state. By controlling multiple first initial voltage terminals, higher-precision image display at high frequencies can be achieved.

[0201] As shown in FIG6 , based on at least one embodiment of the pixel circuit shown in FIG3 , I12 is electrically connected to the fourth initial voltage line LI4 , I22 is electrically connected to the fourth initial voltage line LI4 , and I32 is electrically connected to the fifth initial voltage line LI5 ;

[0202] I12 and I22 receive an initial voltage from the fourth initial voltage line LI4, and I32 receives an initial voltage from the fifth initial voltage line LI5.

[0203] In at least one embodiment shown in FIG. 6 , the first second initial voltage is equal to the second second initial voltage; and the first second initial voltage is greater than the third second initial voltage.

[0204] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG3 , I12 is electrically connected to the fourth initial voltage line LI4 , I22 is electrically connected to the fifth initial voltage line LI5 , and I32 is electrically connected to the sixth initial voltage line LI6 ;

[0205] I12 receives an initial voltage from the fourth initial voltage line LI4 , I22 receives an initial voltage from the fifth initial voltage line LI5 , and I32 receives an initial voltage from the sixth initial voltage line LI6 .

[0206] In at least one embodiment shown in FIG. 7 , the first second initial voltage is smaller than the second second initial voltage, and the first second initial voltage is larger than the third second initial voltage.

[0207] In at least one embodiment of the pixel circuit shown in Figure 7, in the first sub-pixel, the second sub-pixel and the third sub-pixel, the second initial voltage connected to each second initialization transistor is different. During high-frequency display, different pixel node voltages can be reset in a targeted manner to give the driving transistor the same bias state. Through the control of multiple second initial voltage terminals, higher-precision image display at high frequency can be achieved.

[0208] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, and the driving method includes:

[0209] The nth driving circuit generates a driving current for driving the nth light-emitting element under the control of the potential of the nth first node;

[0210] The nth first light emitting control circuit controls the connection between the nth third node and the first electrode of the nth light emitting element under the control of the light emitting control signal;

[0211] The nth first initialization circuit writes the nth first initial voltage provided by the nth first initial voltage terminal into the nth third node under the control of the first reset control signal;

[0212] The nth second initialization circuit writes the nth second initial voltage provided by the nth second initial voltage terminal into the nth second node under the control of the second reset control signal;

[0213] The first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other;

[0214] N is an integer greater than 1; n is a positive integer less than or equal to N.

[0215] The display device described in the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0216] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit includes N sub-pixels, N first initial voltage terminals, and N second initial voltage terminals, where N is an integer greater than 1; n is a positive integer less than or equal to N; The nth sub-pixel includes an nth driving circuit, an nth light-emitting element, an nth first initialization circuit, an nth second initialization circuit, and an nth first light-emitting control circuit; A control terminal of the nth driving circuit is electrically connected to an nth first node, a first terminal of the nth driving circuit is electrically connected to an nth second node, a second terminal of the nth driving circuit is electrically connected to an nth third node, and the nth driving circuit is configured to generate a driving current for driving the nth light-emitting element under the control of the potential of the nth first node; The nth first light-emitting control circuit is respectively electrically connected to a light-emitting control terminal, the nth third node, and a first pole of the nth light-emitting element, and is configured to control the connection between the nth third node and the first pole of the nth light-emitting element under the control of a light-emitting control signal provided by the light-emitting control terminal; a second pole of the nth light-emitting element is electrically connected to a second voltage terminal; The nth first initialization circuit is respectively electrically connected to a first reset control terminal, the nth first initial voltage terminal, and the nth third node, and is configured to write an nth first initial voltage provided by the nth first initial voltage terminal into the nth third node under the control of a first reset control signal provided by the first reset control terminal; The nth second initialization circuit is respectively electrically connected to a second reset control terminal, the nth second initial voltage terminal, and the nth second node, and is configured to write an nth second initial voltage provided by the nth second initial voltage terminal into the nth second node under the control of a second reset control signal provided by the second reset control terminal; The first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other.

2. The pixel circuit according to claim 1, wherein, The pixel circuit includes three sub-pixels, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel; The first first initial voltage is different from the third first initial voltage, and the second first initial voltage is different from the third first initial voltage.

3. The pixel circuit according to claim 2, wherein, The driving transistors included in each driving circuit are p-type transistors, the first first initial voltage is greater than the third first initial voltage, and the second first initial voltage is greater than the third first initial voltage; or, The driving transistors included in each driving circuit are n-type transistors, the first first initial voltage is less than the third first initial voltage, and the second first initial voltage is less than the third first initial voltage.

4. The pixel circuit according to claim 3, wherein, The first first initial voltage is equal to the second first initial voltage.

5. The pixel circuit according to claim 3, wherein, The driving transistor is a p-type transistor, and the first first initial voltage is less than the second first initial voltage; or, The driving transistor is a p-type transistor, and the first first initial voltage is greater than the second first initial voltage.

6. The pixel circuit according to claim 1, wherein, The pixel circuit includes three sub-pixels, where the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel; The first second initial voltage is different from the third second initial voltage, and the second second initial voltage is different from the third second initial voltage.

7. The pixel circuit according to claim 6, wherein, The driving transistors included in each driving circuit are p-type transistors, the first second initial voltage is greater than the third second initial voltage, and the second second initial voltage is greater than the third second initial voltage; or, The driving transistors included in each driving circuit are n-type transistors, the first second initial voltage is less than the third second initial voltage, and the second second initial voltage is less than the third second initial voltage.

8. The pixel circuit according to claim 7, wherein, The first second initial voltage is equal to the second second initial voltage.

9. The pixel circuit according to claim 7, wherein, The driving transistor is a p-type transistor, and the first second initial voltage is less than the second second initial voltage; or, The driving transistor is an n-type transistor, and the first second initial voltage is greater than the second second initial voltage.

10. The pixel circuit according to any one of claims 1 to 9, wherein, The pixel circuit further includes N third initial voltage terminals; the nth sub-pixel further includes the nth third initialization circuit; The nth third initialization circuit is respectively electrically connected to the third reset control terminal, the nth third initial voltage terminal, and the first pole of the nth light-emitting element, and is configured to write the nth third initial voltage provided by the nth third initial voltage terminal into the first pole of the nth light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

11. The pixel circuit according to claim 10, wherein, The third initial voltages provided by the N third initial voltage terminals are the same.

12. The pixel circuit according to any one of claims 1 to 9, wherein, The nth sub-pixel further includes the nth energy storage circuit, the nth compensation control circuit, and the nth data writing circuit; The first end of the nth energy storage circuit is electrically connected to the nth first node, the second end of the nth energy storage circuit is electrically connected to the DC voltage terminal, and the nth energy storage circuit is used for storing electrical energy; The nth compensation control circuit is respectively electrically connected to the compensation control terminal, the nth first node, and the nth third node, and is configured to control the connection between the nth first node and the nth third node under the control of the compensation control signal provided by the compensation control terminal; The nth data writing circuit is respectively electrically connected to the writing control terminal, the nth data line, and the nth second node, and is configured to write the nth data voltage provided by the nth data line into the nth second node under the control of the writing control signal provided by the writing control terminal.

13. The pixel circuit according to any one of claims 1 to 9, wherein, The nth sub-pixel further includes the nth second light-emitting control circuit; The nth second light-emitting control circuit is respectively electrically connected to the light-emitting control terminal, the first voltage terminal, and the nth second node, and is configured to control the connection between the first voltage terminal and the nth second node under the control of the light-emitting control signal.

14. A driving method, applied to the pixel circuit according to any one of claims 1 to 13, the driving method includes: The nth driving circuit generates a driving current for driving the nth light-emitting element under the control of the potential of the nth first node; Under the control of the light emission control signal, the nth first light emission control circuit controls the connection between the nth third node and the first pole of the nth light emitting element; The nth first initialization circuit writes the nth first initial voltage provided by the nth first initial voltage terminal into the nth third node under the control of the first reset control signal; The nth second initialization circuit writes the nth second initial voltage provided by the nth second initial voltage terminal into the nth second node under the control of the second reset control signal; The first initial voltages provided by at least two of the first initial voltage terminals are different from each other, and / or the second initial voltages provided by at least two of the second initial voltage terminals are different from each other; N is an integer greater than 1; n is a positive integer less than or equal to N.

15. A display device, comprising the pixel circuit according to any one of claims 1 to 13. ​

Images