Communication method, circuit and integrated circuit chip

Abstract

The embodiment of the invention provides a communication method, a communication circuit and an integrated circuit chip. The method comprises the following steps: receiving a first data signal and a first clock signal sent by a first device through a cJTAG interface; the first data signal and the first clock signal are both signals with a cJTAG protocol format; synchronizing the first data signal and the first clock signal based on a synchronous clock signal with the first device; sampling the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and generating a second clock signal based on the synchronized first clock signal; wherein the second data signal and the second clock signal are both signals with a JTAG protocol format; and sending the second data signal and the second clock signal to the second equipment through the debugging interface. The first data signal and the first clock signal are synchronized through the synchronous clock signal, uncertainty and potential errors caused by non-clock rising edge behaviors can be effectively avoided, and then the stability of the system is improved.

Description

Technical Field

[0001] The present application relates to the field of communications, and in particular to a communication method, circuit, and integrated circuit chip. Background Art

[0002] The JTAG interface is primarily used for internal testing of chip systems. The standard JTAG interface is a four-wire interface consisting of: TMS (mode select signal), TCK (clock signal), TDI (data input), and TDO (data output). While the JTAG interface is suitable for most applications, its large number of pins results in a larger chip package size. To reduce the number of pins required for the JTAG interface, a 4-pin to 2-pin conversion is implemented using the cJTAG interface.

[0003] The cJTAG interface is a two-wire interface consisting of TMSC (cJTAG mode select) and TCKC (cJTAG clock). TMSC is a bidirectional port. The cJTAG protocol requires escape sequence detection, which specifically counts the total number of rising and falling edges of TMSC when TCKC is high. During debug packet transmission, the debug module samples TMSC on the rising edge of TCKC and transmits the TDO data in TMSC on the falling edge of TCKC. However, the TMSC and TCKC signals of the cJTAG interface operate at different clock frequencies. If a circuit module includes circuits that do not rely on rising clock edges, this will complicate circuit simulation verification, design-for-fit (DFT), and other design processes, and reduce system reliability. Summary of the Invention

[0004] The embodiments of the present application provide a communication method, circuit, and integrated circuit chip for achieving a synchronous clock frequency, avoiding difficulties in circuit simulation verification and design fault tolerance, and improving system reliability.

[0005] In a first aspect, an embodiment of the present application provides a communication method, the method comprising:

[0006] Receiving a first data signal and a first clock signal sent by a first device through a cJTAG interface; the first data signal and the first clock signal are both signals in a cJTAG protocol format;

[0007] Synchronize the first data signal and the first clock signal based on the synchronization clock signal between the first device and the first device;

[0008] Based on the synchronized first clock signal, sampling the synchronized first data signal to generate a second data signal, and generating a second clock signal based on the synchronized first clock signal; wherein the second data signal and the second clock signal are both signals in a JTAG protocol format;

[0009] A second data signal and a second clock signal are sent to a second device via a debugging interface; the second device has a debugging interface.

[0010] In one embodiment, synchronizing the first data signal and the first clock signal based on a synchronization clock signal with the first device specifically includes:

[0011] synchronizing the first data signal and the first clock signal based on the synchronization clock signal by a synchronizer;

[0012] Converting the rising edge and the falling edge of the synchronized first data signal into pulse signals respectively;

[0013] The rising edge and the falling edge of the synchronized first clock signal are converted into pulse signals respectively.

[0014] In one embodiment, synchronizing the first data signal and the first clock signal based on the synchronization clock signal by a synchronizer specifically includes:

[0015] Synchronize the first clock signal to a high-frequency clock domain based on the synchronization clock signal using an N-level synchronizer;

[0016] An N+1-level synchronizer is used to synchronize the first data signal to a high-frequency clock domain based on the synchronization clock signal, so as to ensure synchronization between the clock signal and the data input signal.

[0017] In one embodiment, sampling the first data signal based on the synchronized first clock signal to generate the second data signal, and generating the second clock signal based on the synchronized first clock signal specifically includes:

[0018] When the rising edge pulse signal of the synchronized first clock signal is at a high level and the synchronization clock signal is at a rising edge, sampling the synchronized first data signal to generate a second data signal and a test mode selection signal;

[0019] The second clock signal is generated based on the synchronized first clock signal; wherein the second data signal, the test mode selection signal and the second clock signal are all signals in a JTAG protocol format.

[0020] In one embodiment, the method further comprises:

[0021] receiving a third data signal sent by the second device;

[0022] When the first clock signal is at a low level, a third data signal is sent to the first device.

[0023] In one embodiment, sending the third data signal to the first device specifically includes:

[0024] If the first clock signal is synchronized using an N-level synchronizer, the frequency of the synchronized clock signal is 2(N+2) times higher than the frequency of the first clock signal to ensure that the first device can receive it.

[0025] In a second aspect, an embodiment of the present application further provides a communication circuit, comprising: a cJTAG interface, a conversion module, and a JTAG module; a first end of the conversion module is connected to a first device via the cJTAG interface, a second end of the conversion module is connected to a first end of the JTAG module, and a second end of the JTAG module is connected to a second device;

[0026] The conversion module is configured to receive a first data signal and a first clock signal sent by a first device via a cJTAG interface; synchronize the first data signal and the first clock signal based on a synchronous clock signal with the first device, sample the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and generate a second clock signal based on the synchronized first clock signal; the first data signal and the first clock signal are both signals in a cJTAG protocol format; and the second data signal and the second clock signal are both signals in a JTAG protocol format;

[0027] The JTAG module is used to receive the second data signal and the second clock signal, and send the second data signal and the second clock signal to the second device through the debugging interface.

[0028] In one embodiment, the conversion module includes a synchronization unit and a communication unit, wherein a first end of the synchronization unit is connected to the first device via a cJTAG interface, a second end of the synchronization unit is connected to a first end of the communication unit, and a second end of the communication unit is connected to the JTAG module;

[0029] The synchronization unit is configured to synchronize the first data signal and the first clock signal based on the synchronization clock signal between the first device and the first device, sample the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and generate a second clock signal based on the synchronized first clock signal;

[0030] The communication unit is used to send the second clock signal and the second data signal to the JTAG module.

[0031] In one embodiment, the cJTAG interface includes a bidirectional data signal pin and a clock signal pin; the conversion module further includes a tri-state gate, a first end of the tri-state gate is connected to the bidirectional data signal pin and the synchronization unit, and a second end of the tri-state gate is connected to the communication unit;

[0032] The tri-state gate is used to, when in a closed state, allow the first device to send a first data signal to the synchronization unit; and when in an open state, allow the third data signal sent by the JTAG module to be output from the first end of the tri-state gate.

[0033] In one embodiment, the synchronization unit includes a first synchronization subunit and a second synchronization subunit;

[0034] A first end of the first synchronization subunit is connected to the clock signal pin, and a second end of the first synchronization subunit is connected to the communication unit; the first synchronization subunit is used to synchronize the first clock signal to the high-frequency clock domain based on the synchronization clock signal, and convert the clock signal into a pulse signal;

[0035] The first end of the second synchronization subunit is connected to the bidirectional data signal pin, and the second end of the second synchronization subunit is connected to the communication unit. The second synchronization unit is used to synchronize the first data signal to the high-frequency clock domain based on the synchronization clock signal, and convert the first data signal into a pulse signal.

[0036] In one embodiment, the synchronous clock signal is one of a high frequency clock, a CPU clock, and a bus clock.

[0037] In one embodiment, the first synchronization subunit includes an N-stage synchronizer and a first edge detection circuit;

[0038] The second synchronization subunit includes an N+1-stage synchronizer and a second edge detection circuit.

[0039] In a third aspect, an embodiment of the present application provides an integrated circuit chip, comprising any of the above-mentioned communication circuits.

[0040] The communication method, circuit, and integrated circuit chip provided by the embodiments of the present application include: receiving a first data signal and a first clock signal sent by a first device via a cJTAG interface; the first data signal and the first clock signal are both signals in the cJTAG protocol format; synchronizing the first data signal and the first clock signal based on a synchronous clock signal with the first device; sampling the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and generating a second clock signal based on the synchronized first clock signal; wherein the second data signal and the second clock signal are both signals in the JTAG protocol format; sending the second data signal and the second clock signal to a second device via a debug interface; the second device has a debug interface. Synchronizing the first data signal and the first clock signal via a synchronous clock signal can effectively avoid uncertainty and potential errors caused by non-clock rising edge behavior, thereby improving the stability of the entire system; secondly, the cJTAG interface has a small number of pins and a small package size. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0042] Figure 1 A schematic diagram of the structure of a communication circuit provided in one embodiment of the present application;

[0043] Figure 2 A schematic structural diagram of a communication circuit provided in another embodiment of the present application;

[0044] Figure 3 A flowchart of a communication method provided in one embodiment of the present application;

[0045] Figure 4 A schematic structural diagram of a first synchronization subunit provided in one embodiment of the present application;

[0046] Figure 5 A schematic structural diagram of a second synchronization subunit provided in one embodiment of the present application;

[0047] Figure 6 A timing diagram of each signal provided in an embodiment of the present application;

[0048] Figure 7 A schematic diagram of the structure of an integrated circuit chip provided in one embodiment of the present application;

[0049] Figure 8 Schematic diagram of the JTAG interface provided for this application.

[0050] Reference numerals:

[0051] 2100, first device; 110, cJTAG interface; 120, conversion module; 130, JTAG module; 2200, second device; 401, first edge detection circuit; 402, second edge detection circuit.

[0052] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0053] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0054] First, let’s explain the terms involved in this application:

[0055] An escape sequence is a special signal or character sequence used to identify or trigger a specific operation or state transition. In the cJTAG protocol, an escape sequence may be used to switch between different operating modes or to initialize and configure the link state. This sequence typically consists of a set of specific signal changes (such as a series of high and low level transitions). The receiver detects these changes to identify and execute the corresponding operation.

[0056] JTAG (Joint Test Action Group) interface: refers to a standard interface for testing and debugging integrated circuits, usually composed of the following four main signals, such as Figure 8 As shown, Figure 8 Schematic diagram of the JTAG interface provided for this application: TDI (Test Data In) is the test data input signal, which is used to shift data into the JTAG scan chain, and the test data is input to the target device through TDI; TDO (Test Data Out) is the test data output signal, which is used to shift data out of the JTAG scan chain, and the tested data is output from the target device through TDO; TCK (Test Clock) is the test clock signal, which is used to synchronize JTAG operations. TCK controls the shifting of data and the updating of registers; TMS (Test Mode Select) is the test mode select signal, which is used to control the operation of the JTAG state machine. Different test modes and operations can be selected through the TMS signal.

[0057] The JTAG interface has four pins, which increases the package size. Therefore, a cJTAG interface adapter is used to convert received cJTAG-compliant signals into JTAG-compliant signals. However, the cJTAG interface is a two-wire interface consisting of TMSC (cJTAG mode select) and TCKC (cJTAG clock). TMSC is a bidirectional port. The cJTAG protocol requires escape sequence detection, which specifically counts the total number of rising and falling edges of TMSC when TCKC is high. During debug packet transmission, the debug module samples TMSC on the rising edge of TCKC and transmits the TDO data in TMSC on the falling edge of TCKC. However, the TMSC and TCKC signals of the cJTAG interface operate at different clock frequencies. If a circuit module includes circuits that do not use rising-edge behavior, this can complicate circuit simulation verification, design-for-fit (DFT), and other design processes, reducing system reliability.

[0058] Based on the above scenario, it can be seen that in the existing technology, conversion through the cJTAG interface will cause the problem of input signal asynchrony, which will cause difficulties in other design processes such as circuit simulation verification and DFT, and will also reduce system reliability.

[0059] A communication method provided by the present application synchronizes a first data signal and a first clock signal by means of a synchronous clock signal, which can effectively avoid the uncertainty and potential errors caused by non-clock rising edge behavior, thereby improving the stability of the entire system; secondly, the cJTAG interface has a small number of pins and a small package size.

[0060] The following specific embodiments describe in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0061] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a communication circuit provided in one embodiment of the present application. The communication circuit includes: a cJTAG interface 110, a conversion module 120, and a JTAG module 130; a first end of the conversion module 120 is connected to a first device 2100 via the cJTAG interface 110, a second end of the conversion module 120 is connected to a first end of the JTAG module 130, and a second end of the JTAG module 130 is connected to a second device 2200; the conversion module 120 is configured to receive a first data signal (TMSC) and a first clock signal (TCKC) sent by the first device 2100 via the cJTAG interface 110; based on a synchronous clock signal with the first device 2100, The first data signal and the first clock signal are synchronized, and the synchronized first data signal is sampled based on the synchronized first clock signal to generate a second data signal, and a second clock signal (sync_tckc) is generated based on the synchronized first clock signal; the first data signal and the first clock signal are both signals having a cJTAG protocol format; the second data signal and the second clock signal are both signals having a JTAG protocol format; the JTAG module 130 is used to receive the second data signal and the second clock signal, and send the second data signal and the second clock signal to the second device 2200 through the debug interface.

[0062] Specifically, the first device 2100 is a debugger, and the second device 2200 is a debugged device. The first device 2100 is connected to the communication circuit via the cJTAG interface 110. The debug interface of the JTAG module 130 is typically used to send debug information to the second device 2200, facilitating debugging of the second device 2200. The present application synchronizes the first data signal with the first clock signal via a synchronous clock signal, effectively avoiding the uncertainty and potential errors caused by non-clock rising edge behavior, thereby improving the stability of the entire system. Furthermore, communication with the second device 2200 is achieved through conversion via the cJTAG interface 110, which has a small number of pins and a small package size.

[0063] In one embodiment, Figure 2 As shown, Figure 2 A schematic diagram of the structure of a communication circuit provided in another embodiment of the present application. The conversion module 120 includes a synchronization unit (not shown) and a communication unit. The first end of the synchronization unit is connected to the first device 2100 via the cJTAG interface 110, the second end of the synchronization unit is connected to the first end of the communication unit, and the second end of the communication unit is connected to the JTAG module 130 of the second device 2200. The synchronization unit is used to synchronize the first data signal and the first clock signal based on the synchronization clock signal between the synchronization unit and the first device 2100, and to sample the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and to generate a second clock signal based on the synchronized first clock signal. The communication unit is used to send the second clock signal and the second data signal to the JTAG module 130.

[0064] In one embodiment, the synchronous clock signal is one of a high frequency clock, a CPU clock, and a bus clock.

[0065] Specifically, in this embodiment, taking the synchronous clock signal as a high-frequency clock signal as an example, the synchronization unit synchronizes the first data signal and the first clock signal to the high-frequency clock domain based on the high-frequency clock signal, thereby solving the uncertainty and potential errors caused by the non-clock rising edge behavior of the first data signal and the first clock signal in the prior art. The behavior of all registers inside the module is driven by the rising edge of the high-frequency clock signal, avoiding the use of the rising edge or falling edge of the first clock signal to directly drive the logic circuit in the adapter module. The use of this solution brings great convenience to circuit design, verification, DFT and other links.

[0066] In one embodiment, see Figure 2The cJTAG interface 110 includes a bidirectional data signal pin and a clock signal pin; the conversion circuit also includes a three-state gate, a first end of the three-state gate is connected to the bidirectional data signal pin and the synchronization unit, and a second end of the three-state gate is connected to the communication unit; when the three-state gate is in a closed state, the first device 2100 sends a first data signal to the synchronization unit; when it is in an open state, the third data signal sent by the JTAG module 130 is output from the first end of the three-state gate.

[0067] The bidirectional data signal pin can be used as both an input pin and an output pin.

[0068] Specifically, a tri-state gate is a logic gate circuit whose output can be in three different states: high, low, and high-impedance. The high-impedance state indicates a disconnection between the output and input, equivalent to an open circuit in a circuit. A tri-state gate typically consists of an input terminal, an output terminal, and a control terminal. When the control terminal is active, the input signal of the tri-state gate is transmitted to the output terminal; when the control terminal is inactive, the output terminal enters a high-impedance state, i.e., an open circuit. In this embodiment, when the tri-state gate receives an enable signal from the communication unit (i.e., when the control terminal is active), the tri-state gate opens, the bidirectional data signal pin enters an output state, and the second terminal of the tri-state gate transmits a third data signal to the bidirectional data signal pin. When the control terminal is inactive, the first terminal of the tri-state gate enters a high-impedance state, the tri-state gate closes, and the bidirectional data signal pin enters an input state, transmitting the first data signal to the synchronization unit. The bidirectional data signal pin can either input or output signals depending on the state of the tri-state gate's control terminal. In practical applications, using TMS as a bidirectional data signal pin is a requirement of the cJTAG protocol specification.

[0069] like Figure 3 As shown, Figure 3 This is a flowchart of a communication method provided in one embodiment of the present application. The communication method includes the following steps:

[0070] Step S302: Receive a first data signal and a first clock signal sent by the first device 2100 through the cJTAG interface 110; both the first data signal and the first clock signal are signals in the cJTAG protocol format.

[0071] Specifically, the communication circuit receives signals from the first device 2100, which are transmitted through the cJTAG interface 110 and include a first data signal and a first clock signal. The cJTAG protocol is a protocol used for testing and debugging.

[0072] Step S304: Synchronize the first data signal and the first clock signal based on the synchronization clock signal between the first device 2100.

[0073] Specifically, the received signal needs to be synchronized with the synchronous clock signal to ensure that the first data signal and the first clock signal are consistent with the timing of the first device 2100 for subsequent processing.

[0074] Step S306: Based on the synchronized first clock signal, sample the synchronized first data signal to generate a second data signal, and generate a second clock signal based on the synchronized first clock signal; wherein the second data signal and the second clock signal are both signals in the JTAG protocol format.

[0075] Specifically, after synchronization, the system samples the first data signal using the synchronized first clock signal to generate a second data signal. Simultaneously, the system generates a second clock signal based on the synchronized first clock signal. The second clock signal and the second data signal conform to the JTAG protocol format for easy recognition by the second device 2200.

[0076] Step S308: Send the second data signal and the second clock signal to the second device 2200 through the debugging interface; the second device 2200 has a debugging interface.

[0077] Specifically, the JTAG module 130 sends the converted second data signal and the second clock signal to the second device 2200 through the debug interface. The second device 2200 has a debug interface for receiving and processing these signals. Optionally, the debug interface is a debug interface.

[0078] In one embodiment, step S304 specifically includes the following steps:

[0079] The first data signal and the first clock signal are synchronized by the synchronizer based on the synchronization clock signal.

[0080] The rising edge and the falling edge of the synchronized first data signal are converted into pulse signals respectively.

[0081] The rising edge and the falling edge of the synchronized first clock signal are converted into pulse signals respectively.

[0082] Specifically, in the high-frequency clock domain, corresponding pulse signals drive various events required by the cJTAG protocol, including the conversion of cJTAG to JTAG logic.

[0083] In one embodiment, see Figure 2The synchronization unit includes a first synchronization sub-unit and a second synchronization sub-unit; the first end of the first synchronization sub-unit is connected to the clock signal pin, and the second end of the first synchronization sub-unit is connected to the communication unit; the first synchronization sub-unit is used to synchronize the first clock signal to the high-frequency clock domain based on the synchronization clock signal, and convert the clock signal into a pulse signal; the first end of the second synchronization sub-unit is connected to the bidirectional data signal pin, and the second end of the second synchronization sub-unit is connected to the communication unit, and the second synchronization unit is used to synchronize the first data signal to the high-frequency clock domain based on the synchronization clock signal, and convert the first data signal into a pulse signal.

[0084] In one embodiment, the first synchronization sub-unit includes an N-stage synchronizer and a first edge detection circuit 401 .

[0085] In one embodiment, the second synchronization sub-unit includes an N+1-stage synchronizer and a second edge detection circuit 402 .

[0086] Specifically, the first edge detection circuit 401 is used to detect the rising edge and falling edge of the synchronized clock signal and generate a rising edge pulse signal and a falling edge pulse signal. Similarly, the second edge detection circuit 402 is used to detect the rising edge and falling edge of the synchronized first data signal and generate a rising edge pulse signal and a falling edge pulse signal.

[0087] In one embodiment, synchronizing the first data signal and the first clock signal based on the synchronization clock signal by a synchronizer specifically includes the following steps:

[0088] The first clock signal is synchronized to a high-frequency clock domain based on the synchronization clock signal using an N-stage synchronizer.

[0089] An N+1-level synchronizer is used to synchronize the first data signal to a high-frequency clock domain based on the synchronization clock signal, so as to ensure synchronization between the clock signal and the data input signal.

[0090] Specifically, if Figure 4 As shown, Figure 4 This is a structural diagram of the first synchronization subunit provided in one embodiment of the present application. Figure 5 As shown, Figure 5A schematic structural diagram of a second synchronization subunit provided for an embodiment of the present application. Take the first synchronization subunit as an example of a three-level synchronizer, and the second synchronization subunit as an example of a four-level synchronizer. The first clock signal is synchronized to obtain a second clock signal. The first edge detection circuit 401 generates two pulse signals at the rising and falling edges of the second clock signal by identifying the edge of the synchronized second clock signal. The first data signal is also processed in the same way to generate a second data signal. The second edge detection circuit 402 identifies the edge of the second data signal and generates two pulse signals according to the rising and falling edges of the second data signal. The difference between the first data signal and the first clock signal in signal processing is that the first data signal needs to be synchronized one more level. Therefore, the generated synchronized second data signal and the corresponding pulse signal are both delayed by one cycle compared to the second clock signal and the corresponding pulse signal.

[0091] In one embodiment, sampling a first data signal based on a synchronized first clock signal to generate a second data signal, and generating a second clock signal based on the synchronized first clock signal specifically includes the following steps:

[0092] When the rising edge pulse signal of the synchronized first clock signal is at a high level and the synchronization clock signal is at a rising edge, the synchronized first data signal is sampled to generate a second data signal and a test mode selection signal.

[0093] The second clock signal is generated based on the synchronized first clock signal; wherein the second data signal, the test mode selection signal and the second clock signal are all signals in a JTAG protocol format.

[0094] In one embodiment, the method further comprises the following steps:

[0095] Receive a third data signal sent by the second device 2200.

[0096] When the first clock signal is at a low level, the third data signal is sent to the first device 2100 .

[0097] Specifically, if Figure 6 As shown, Figure 6 This is a timing diagram of the various signals provided in one embodiment of the present application. During the initialization phase of the communication circuit, the cJTAG protocol requires the identification of an escape sequence. When the second clock signal is at a high level, the total number of rising edge pulse signals and falling edge pulse signals of the second data signal is counted to identify the escape sequence. During the data packet transmission phase of the communication circuit, when the rising edge pulse signal of the second clock signal is at a high level and the high-frequency clock signal is at a rising edge, the second data signal and the test mode selection signal are sampled. In this way, the second device 2200 can receive and identify the second data signal and the test mode selection signal.

[0098] When the second device 2200 needs to return data to the first device 2100, a state machine is designed to control the signal routing in the process of converting cJTAG to JTAG signal. The state of the cJTAG protocol parsing state machine is switched by the falling edge pulse of the second clock signal. At this time, the three-state gate is in the valid state, and the third data signal of the second device 2200 can be output to the first device 2100.

[0099] The first clock signal serves as the clock line of the cJTAG protocol, and the first data signal serves as the signal line of the cJTAG protocol. The cJTAG protocol requires that the value of the first data signal be sampled at the rising edge of the first clock signal, that is, the value of the first data signal at time p is sampled at time r on the first clock signal. Figure 6 The position indicated by ori_trigger is the time r on the first clock signal, and the value of the first data signal at time p is sampled. In this solution, the value of the second data signal at time d needs to be sampled at time c on the rising edge pulse signal of the second clock signal. Figure 6 It can be seen from the figure that the second clock signal is delayed by 3T compared to the first clock signal, that is, after the first clock signal is synchronized by the synchronizer, it is delayed by 3T compared to the first clock signal. Figure 6 It can be seen that the time at point f is delayed by 3T compared to the time at point e. If the first data signal is sampled at the rising edge of the second clock signal, the sampling time will be delayed by 3T compared to the original time. However, because it is driven by the synchronous clock signal, Figure 6 Points b and h indicate a 4T delay between the first and second data signals. Therefore, the actual sampling time occurs at the new_trigger point (i.e., time c on the rising edge of the second clock signal), which is 4T later than the original time. Therefore, when synchronizing the first data signal, a synchronizer with one more stage than the first clock signal is used, causing the synchronization signal of the first data signal to lag by one cycle behind the first clock signal to compensate. Therefore, the value of the second data signal sampled at time d on the rising edge of the second clock signal, sampled at time c, is equivalent to the value of the original first data signal sampled at time p, ensuring that the first data signal is sampled midway between two transitions of the first data signal. Considering that in actual debugging, the first data signal and the first clock signal at the JTAG port may not be strictly aligned and may even differ by several high-frequency clock signal cycles after synchronization, sampling midway between two transitions of the first data signal provides maximum time margin for both advances and delays in the first data signal, thereby improving system reliability.

[0100] In one embodiment, sending the third data signal to the first device 2100 specifically includes:

[0101] If the first clock signal is synchronized using an N-level synchronizer, the frequency of the synchronized clock signal is higher than 2(N+2) times the frequency of the first clock signal to ensure that the first device 2100 can receive it.

[0102] Specifically, the third data signal output from cJTAG interface 110 must occur before the rising edge of the first clock signal. That is, the rising edge of the second clock signal controlling the output of the third data signal must occur before the rising edge of the first clock signal. Therefore, if an n-stage synchronizer is used to synchronize the first clock signal, the sampling high-frequency clock frequency must be higher than 2(n+2) times the frequency of the first clock signal to ensure that the first device 2100 can sample the third data signal output by the second device 2200 at the rising edge of the first clock signal.

[0103] The embodiment of the present application provides an integrated circuit chip, including any of the above-mentioned communication circuits. Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of an integrated circuit chip provided in one embodiment of the present application. The integrated circuit chip includes a conversion module 120 and a JTAG module 130. The integrated circuit chip is connected to a first device 2100 via a cJTAG interface 110 and to a second device 2200 via a debug interface. The conversion module 120 converts signals received by the cJTAG interface 110 into signals that can be processed by the JTAG module 130.

[0104] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASICs), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the present invention may be directly executed by a hardware processor or by a combination of hardware and software modules within the processor.

[0105] The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage.

[0106] A bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, the buses in the drawings of this application are not limited to just one bus or just one type of bus.

[0107] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0108] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0109] The readable storage medium may be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The readable storage medium may be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0110] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be an integral part of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0111] The division of units is merely a logical functional division; actual implementations may employ alternative divisions, such as combining or integrating multiple units or components into another system, or omitting or disabling certain features. Furthermore, any direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between devices or units, either through an interface, electrical, mechanical, or other means.

[0112] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0113] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0114] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the method of the present invention. The aforementioned storage medium includes various media that can store program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0115] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0116] Finally, it should be noted that those skilled in the art will readily identify other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art not disclosed herein. The present invention is not limited to the precise structure described above and illustrated in the accompanying drawings, and various modifications and variations may be made without departing from the scope thereof. The scope of the present invention is limited solely by the appended claims.

Claims

1. A communication method, characterized in that: The method comprises: Receiving a first data signal and a first clock signal sent by a first device through a cJTAG interface; the first data signal and the first clock signal are both signals in a cJTAG protocol format; Synchronize the first data signal and the first clock signal based on a synchronization clock signal between the first device and the first device; Based on the synchronized first clock signal, sampling the synchronized first data signal to generate a second data signal, and generating a second clock signal based on the synchronized first clock signal; wherein the second data signal and the second clock signal are both signals in a JTAG protocol format; The second data signal and the second clock signal are sent to a second device through a debugging interface; the second device has a debugging interface.

2. The communication method according to claim 1, wherein: The synchronizing the first data signal and the first clock signal based on the synchronous clock signal between the first device specifically includes: synchronizing the first data signal and the first clock signal based on the synchronization clock signal through a synchronizer; Converting the rising edge and the falling edge of the synchronized first data signal into pulse signals respectively; The rising edge and the falling edge of the synchronized first clock signal are converted into pulse signals respectively.

3. The communication method according to claim 2, wherein: The step of synchronizing the first data signal and the first clock signal based on the synchronization clock signal by a synchronizer specifically includes: Synchronize the first clock signal to a high-frequency clock domain based on the synchronization clock signal using an N-level synchronizer; An N+1-level synchronizer is used to synchronize the first data signal to a high-frequency clock domain based on the synchronization clock signal, so as to ensure synchronization between the clock signal and the data input signal.

4. The communication method according to claim 2, wherein: The sampling of the first data signal based on the synchronized first clock signal to generate a second data signal, and generating a second clock signal based on the synchronized first clock signal specifically includes: When the rising edge pulse signal of the synchronized first clock signal is at a high level and the synchronization clock signal is at a rising edge, sampling the synchronized first data signal to generate a second data signal and a test mode selection signal; A second clock signal is generated based on the synchronized first clock signal; wherein the second data signal, the test mode selection signal and the second clock signal are all signals in a JTAG protocol format.

5. The communication method according to claim 4, wherein: The method further comprises: receiving a third data signal sent by the second device; When the first clock signal is at a low level, the third data signal is sent to the first device. The communication method according to claim 5 , wherein: The sending the third data signal to the first device when the first clock signal is at a low level specifically includes: If the first clock signal is synchronized using an N-level synchronizer, the frequency of the synchronized clock signal is higher than 2(N+2) times the frequency of the first clock signal to ensure that the first device can receive it.

7. A communication circuit, characterized in that: include: cJTAG interface, conversion module and JTAG module; a first end of the conversion module is connected to the first device via the cJTAG interface, a second end of the conversion module is connected to the first end of the JTAG module, and a second end of the JTAG module is connected to the second device; The conversion module is configured to receive a first data signal and a first clock signal sent by the first device through the cJTAG interface; synchronize the first data signal and the first clock signal based on a synchronous clock signal with the first device, sample the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and generate a second clock signal based on the synchronized first clock signal; the first data signal and the first clock signal are both signals in a cJTAG protocol format; and the second data signal and the second clock signal are both signals in a JTAG protocol format; The JTAG module is used to receive the second data signal and the second clock signal, and send the second data signal and the second clock signal to the second device through a debugging interface.

8. The communication circuit according to claim 7, wherein: The conversion module includes a synchronization unit and a communication unit, wherein a first end of the synchronization unit is connected to the first device via the cJTAG interface, a second end of the synchronization unit is connected to the first end of the communication unit, and a second end of the communication unit is connected to the JTAG module; The synchronization unit is configured to synchronize the first data signal and the first clock signal based on a synchronization clock signal between the first device and the first device, sample the synchronized first data signal based on the synchronized first clock signal to generate a second data signal, and generate a second clock signal based on the synchronized first clock signal; The communication unit is configured to send the second clock signal and the second data signal to the JTAG module.

9. The communication circuit according to claim 8, characterized in that The cJTAG interface includes a bidirectional data signal pin and a clock signal pin; the conversion module also includes a tri-state gate, a first end of the tri-state gate is connected to the bidirectional data signal pin and the synchronization unit, and a second end of the tri-state gate is connected to the communication unit; The tri-state gate is configured to, when in a closed state, enable the first device to send the first data signal to the synchronization unit; and when in an open state, enable the third data signal sent by the JTAG module to be output from the first end of the tri-state gate.

10. The communication circuit according to claim 9, wherein: The synchronization unit includes a first synchronization subunit and a second synchronization subunit; The first end of the first synchronization subunit is connected to the clock signal pin, and the second end of the first synchronization subunit is connected to the communication unit; the first synchronization subunit is used to synchronize the first clock signal to the high-frequency clock domain based on the synchronization clock signal, and convert the clock signal into a pulse signal; The first end of the second synchronization subunit is connected to the bidirectional data signal pin, and the second end of the second synchronization subunit is connected to the communication unit. The second synchronization unit is used to synchronize the first data signal to the high-frequency clock domain based on the synchronization clock signal, and convert the first data signal into a pulse signal.

11. The communication circuit according to claim 7, wherein: The synchronous clock signal is one of a high-frequency clock, a CPU clock, and a bus clock.

12. The communication circuit according to claim 10, wherein: The first synchronization subunit includes an N-level synchronizer and a first edge detection circuit; The second synchronization subunit includes an N+1-stage synchronizer and a second edge detection circuit.

13. An integrated circuit chip, characterized in that: The communication circuit comprises the communication circuit according to any one of claims 7 to 12.

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