Instruction fetching methods, devices, equipment, and storage media for branch instructions

Abstract

This application provides a method, apparatus, device, and storage medium for fetching branch instructions. The method includes: determining the jump address of the branch instruction; and, when the instruction corresponding to the jump address exists only in the branch optimization queue, fetching the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache. The method provided by this application, when the instruction corresponding to the jump address exists only in the branch optimization queue, fetches the instruction corresponding to the jump address and its subsequent instructions from the branch optimization queue. This ensures that during a branch jump, only the instruction corresponding to the jump address and its subsequent instructions need to be fetched from the branch optimization queue, eliminating the need to restart the sequential instruction fetching process, reducing processor power consumption, and improving execution efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, device, and storage medium for fetching branch instructions. Background Technology

[0002] In computer architecture, instruction execution can be divided into three stages: instruction fetch, instruction decoding, and instruction execution. In the instruction fetch stage, the processor retrieves the instruction from instruction memory based on its virtual address. In the instruction decoding stage, the fetched instruction is broken down and interpreted according to a predetermined instruction format, identifying different instruction categories and various methods for fetching operands. In the instruction execution stage, the processor performs the various operations specified by the instruction, specifically implementing the instruction's function. When the processor processes a branch instruction, a jump may occur depending on whether the condition is true or false.

[0003] When a processor with pipelined technology processes a branch instruction, it generates a jump based on the true / false condition. This jump interrupts the processing of instructions in the pipeline because the processor cannot determine the next instruction until the branch instruction is completed. The longer the pipeline, the longer the processor waits, because it must wait for the branch instruction to complete before determining the next instruction to enter the pipeline.

[0004] If a branch instruction requiring a jump is found during the instruction execution phase, the instruction fetching sequence needs to be restarted from the calculated jump address, wasting processor power and reducing execution efficiency. Summary of the Invention

[0005] To address one of the aforementioned technical deficiencies, this application provides a method, apparatus, device, and storage medium for fetching branch instructions.

[0006] The first aspect of this application provides a method for fetching branch instructions, the method comprising:

[0007] Determine the jump address for the branch instruction;

[0008] If the instruction corresponding to the jump address exists only in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue;

[0009] The branch optimization queue is initially empty; the instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is retrieved from the instruction cache.

[0010] Optionally, the jump address is determined when executing branch instructions in the sequential execution queue of the Fetch module; or, it is determined by branch prediction.

[0011] Optionally, after determining the jump address of the branch instruction, the method further includes:

[0012] Determine if the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module;

[0013] If the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

[0014] Optionally, after determining whether the Fetch module's sequential execution queue contains an instruction corresponding to the jump address, the method further includes:

[0015] If there is no instruction corresponding to the jump address in the sequential execution queue of the Fetch module, determine whether there is an instruction corresponding to the jump address in the branch optimization queue;

[0016] If the instruction corresponding to the jump address is not found in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the instruction cache, and store the instruction corresponding to the jump address and subsequent instructions into the sequential execution queue and branch optimization queue of the Fetch module; retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

[0017] Optionally, the instructions corresponding to the jump address and subsequent instructions are retrieved from the sequential execution queue of the Fetch module, including:

[0018] If the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

[0019] If the instruction corresponding to the jump address is not the head instruction of the sequential execution queue of the Fetch module, then pop the instruction preceding the instruction corresponding to the jump address from the sequential execution queue of the Fetch module; start fetching instructions sequentially from the head of the sequential execution queue of the Fetch module.

[0020] Optionally, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue, including:

[0021] If the branch optimization queue is empty, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue in sequence.

[0022] If the branch optimization queue is not empty, pop all instructions from the branch optimization queue and store the instruction corresponding to the jump address and subsequent instructions into the branch optimization queue in sequence.

[0023] Optionally, if there is only one candidate branch optimization queue, then the candidate branch optimization queue is determined as the branch optimization queue;

[0024] If there are multiple candidate branch optimization queues, then if there is an empty candidate branch optimization queue, the empty candidate branch optimization queue will be determined as the branch optimization queue; if there is no empty candidate branch optimization queue, the candidate branch optimization queue with the smallest value will be selected as the branch optimization queue.

[0025] The selection value of any candidate branch optimization queue is the sum of all elements in the corresponding row of the selection matrix for any candidate branch optimization queue.

[0026] The selection matrix is ​​an n×n matrix, where n is the total number of candidate branch optimization queues; each row in the selection matrix uniquely corresponds to a candidate branch optimization queue; the selection matrix is ​​initially a 0 matrix; when a candidate branch optimization queue i is determined as a branch optimization queue, the element in the i-th row of the selection matrix is ​​first updated to 1, and the element in the i-th column of the selection matrix is ​​then updated to 0, where the i-th row is the row corresponding to candidate branch optimization queue i in the selection matrix.

[0027] A second aspect of this application provides an instruction fetching device for branch instructions, the device comprising:

[0028] The determination module is used to determine the jump address of branch instructions;

[0029] The instruction fetch module is used to fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue when the instruction corresponding to the jump address determined by the determination module exists only in the branch optimization queue.

[0030] The branch optimization queue is initially empty; the instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is retrieved from the instruction cache.

[0031] A third aspect of this application provides an electronic device, comprising:

[0032] Memory;

[0033] Processor; and

[0034] Computer programs;

[0035] The computer program is stored in the memory and configured to be executed by the processor to implement the method described in the first aspect above.

[0036] In a fourth aspect, this application provides a computer-readable storage medium having a computer program stored thereon; the computer program is executed by a processor to implement the method described in the first aspect above.

[0037] This application provides a method, apparatus, device, and storage medium for fetching branch instructions. The method includes: determining the jump address of the branch instruction; and, when the instruction corresponding to the jump address exists only in the branch optimization queue, fetching the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache. The method provided by this application, when the instruction corresponding to the jump address exists only in the branch optimization queue, fetches the instruction corresponding to the jump address and its subsequent instructions from the branch optimization queue. This ensures that during a branch jump, only the instruction corresponding to the jump address and its subsequent instructions need to be fetched from the branch optimization queue, eliminating the need to restart the sequential instruction fetching process, reducing processor power consumption, and improving execution efficiency. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 A schematic diagram of sequential execution instructions provided in an embodiment of this application;

[0040] Figure 2 A flowchart illustrating a branch instruction fetching method provided in an embodiment of this application;

[0041] Figure 3 A queue diagram of a Fetch module provided in an embodiment of this application;

[0042] Figure 4 A schematic diagram of a queue for another Fetch module provided in an embodiment of this application;

[0043] Figure 5 A schematic diagram of instruction execution at time Clk0 provided in an embodiment of this application;

[0044] Figure 6 A schematic diagram of instruction execution at time step Clk1 provided in an embodiment of this application;

[0045] Figure 7 A schematic diagram of instruction execution at time step Clk2 is provided as an embodiment of this application;

[0046] Figure 8 A schematic diagram of instruction execution at time Clkx provided in an embodiment of this application;

[0047] Figure 9 A schematic diagram of instruction execution at time Clkx+1 provided for an embodiment of this application;

[0048] Figure 10 A schematic diagram of instruction execution at time Clkx+2 provided in this application embodiment;

[0049] Figure 11 A schematic diagram of instruction execution at time Clkx+3 provided for an embodiment of this application;

[0050] Figure 12 A schematic diagram of instruction execution at time Clkx+4 provided for an embodiment of this application;

[0051] Figure 13 A schematic diagram of instruction execution at time Clkx+5 provided for an embodiment of this application;

[0052] Figure 14 This is a schematic diagram illustrating a selection value determination process provided in an embodiment of this application;

[0053] Figure 15 This is a schematic diagram of a queue in the Fetch module provided in an embodiment of this application;

[0054] Figure 16 This is a schematic diagram of another queue in the Fetch module provided in the embodiments of this application;

[0055] Figure 17 A schematic diagram of the structure of an instruction fetching device for branch instructions provided in an embodiment of this application;

[0056] Figure 18 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0057] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0058] In the process of implementing this application, the inventors discovered that when a branch instruction requiring a jump is found during the instruction execution stage, the calculated jump address must be used as the starting address to start fetching instructions sequentially again, which wastes the processor's power consumption and reduces execution efficiency.

[0059] To address the aforementioned problems, this application provides a method, apparatus, device, and storage medium for fetching branch instructions. The method includes: determining the jump address of a branch instruction; and, when the instruction corresponding to the jump address exists only in the branch optimization queue, fetching the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache. The method provided in this application fetches the instruction corresponding to the jump address and its subsequent instructions from the branch optimization queue when the instruction corresponding to the jump address exists only in the queue. This ensures that during a branch jump, only the instruction corresponding to the jump address and its subsequent instructions need to be fetched from the branch optimization queue, eliminating the need to restart the sequential instruction fetching process, reducing processor power consumption, and improving execution efficiency.

[0060] This embodiment provides a method for fetching branch instructions. This method is used to fetch the instruction after a jump when a branch instruction is encountered during the sequential execution of instructions.

[0061] If the Fetch module's sequential execution queue is in Figure 1 As shown, PC0, PC1, ..., PCM, PCM+1, SEQ, PCN, PCN+1... are all instruction addresses. During sequential instruction execution, instructions are fetched sequentially starting from PC0. After fetching, the instruction is dispatched. If the instruction is not a branch instruction (such as PC0, PC1, ..., PCM, PCM+1, PCN, PCN+1, etc.), it is executed at the execution unit or waits for transmission in the FIFO. If the instruction is a branch instruction (such as SEQ), a jump address is determined and returned to the Fetch module. Then, the instruction corresponding to the jump address is fetched, and the instruction corresponding to the jump address and subsequent instructions are executed.

[0062] Each time a branch instruction is dispatched, the method provided in this embodiment is executed to fetch the instruction. In order to execute the instruction fetch method for branch instructions provided in this embodiment, a branch optimization queue is built in the Fetch module. The initial value of the branch optimization queue is empty, and the fields of the branch optimization queue are the same as those of the sequential execution queue of the Fetch module.

[0063] See Figure 2 The method provided in this embodiment is implemented as follows:

[0064] 201, Determine the jump address for the branch instruction.

[0065] Branch instructions that appear in the program flow (such as...) Figure 1The SEQ instruction in the code may be an upward jump, a downward jump, or an execution outside the jump sequence. Which case it is depends on the execution of the branch instruction, and only then can the jump address be determined. Therefore, branch instructions can be retrieved from the sequential execution queue of the Fetch module, and the jump address is determined when the branch instruction is executed.

[0066] In addition, current branch prediction technology can predict the jump direction of branch instructions in advance, speeding up the operation. Based on this, the jump address can also be determined through branch prediction.

[0067] In a specific implementation, the method provided in this embodiment can be executed by the Fetch module. That is, the Fetch module will obtain the returned jump address, which is determined when executing the branch instructions in the sequential execution queue of the Fetch module; or, it can be determined through branch prediction.

[0068] 202. When the instruction corresponding to the jump address exists only in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue.

[0069] If the instruction corresponding to the jump address exists only in the branch optimization queue, the instruction corresponding to the jump address and its subsequent instructions are retrieved from the branch optimization queue and written into the sequential execution queue of the Fetch module so that the instruction corresponding to the jump address and its subsequent instructions can be executed.

[0070] The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache.

[0071] like Figure 3 As shown, the Fetch module includes a branch optimization queue and a sequential execution queue. When the instruction corresponding to the jump address exists only in the branch optimization queue (i.e., the instruction corresponding to the jump address does not exist in the sequential execution queue included by the Fetch module, but exists in the branch optimization queue), the Fetch module will fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. In other words, when the instruction corresponding to the jump address does not exist in the branch optimization queue included by the Fetch module, it will not fetch instructions from the instruction cache, but will fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. This avoids the reduction in processor power consumption and execution efficiency caused by the prior art, where instructions are fetched from the instruction cache whenever the instruction corresponding to the jump address does not exist in the branch optimization queue included by the Fetch module.

[0072] Additionally, after executing step 201, it will be determined whether there is an instruction corresponding to the jump address in the sequential execution queue of the Fetch module.

[0073] ●The Fetch module's sequential execution queue contains instructions corresponding to the jump address.

[0074] If the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

[0075] In the actual implementation, if the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

[0076] If the instruction corresponding to the jump address is not the head instruction of the sequential execution queue of the Fetch module, then (1) pop the instruction before the instruction corresponding to the jump address from the sequential execution queue of the Fetch module. (2) Start fetching instructions sequentially from the head of the sequential execution queue of the Fetch module.

[0077] In other words, the instruction corresponding to the jump address will be executed as the first instruction at the head of the sequential execution queue of the Fetch module.

[0078] ● The Fetch module's sequential execution queue does not contain instructions corresponding to the jump address.

[0079] If the instruction corresponding to the jump address is not found in the sequential execution queue of the Fetch module, it will check whether the instruction corresponding to the jump address is found in the branch optimization queue.

[0080] The branch optimization queue contains instructions corresponding to the jump address.

[0081] If the instruction corresponding to the jump address exists only in the branch optimization queue, execute step 202, that is, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue.

[0082] The branch optimization queue does not contain the instruction corresponding to the jump address.

[0083] If the instruction corresponding to the jump address is not found in the branch optimization queue, 1) retrieve the instruction corresponding to the jump address and its subsequent instructions from the instruction cache, and store the instruction corresponding to the jump address and its subsequent instructions into the sequential execution queue and branch optimization queue of the Fetch module. 2) retrieve the instruction corresponding to the jump address and its subsequent instructions from the sequential execution queue of the Fetch module.

[0084] The implementation of 1) retrieving the instruction corresponding to the jump address and its subsequent instructions from the instruction cache, and storing the instruction corresponding to the jump address and its subsequent instructions into the sequential execution queue and branch optimization queue of the Fetch module is as follows:

[0085] A. The process of storing the instruction corresponding to the jump address and subsequent instructions into the sequential execution queue of the Fetch module.

[0086] If the sequential execution queue of the Fetch module is empty, the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the sequential execution queue of the Fetch module.

[0087] If the sequential execution queue of the Fetch module is not empty, all instructions in the sequential execution queue of the Fetch module are popped, and the instructions corresponding to the jump address and subsequent instructions are sequentially stored into the sequential execution queue of the Fetch module.

[0088] In other words, the instruction corresponding to the jump address is the first instruction at the head of the sequential execution queue of the Fetch module.

[0089] B. The process of storing the instruction corresponding to the jump address and subsequent instructions into the branch optimization queue.

[0090] If the branch optimization queue is empty, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue in sequence.

[0091] If the branch optimization queue is not empty, pop all instructions from the branch optimization queue and store the instruction corresponding to the jump address and subsequent instructions into the branch optimization queue in sequence.

[0092] In other words, the branch optimization queue only stores the instruction corresponding to the jump address and subsequent instructions.

[0093] The implementation of 2) retrieving the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module is as follows:

[0094] If the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

[0095] If the instruction corresponding to the jump address is not the head instruction of the sequential execution queue of the Fetch module, then (1) pop the instruction before the instruction corresponding to the jump address from the sequential execution queue of the Fetch module. (2) Start fetching instructions sequentially from the head of the sequential execution queue of the Fetch module.

[0096] In other words, if the Fetch module's sequential execution queue contains instructions corresponding to the jump address, the instructions corresponding to the jump address and subsequent instructions will be retrieved from the Fetch module's sequential execution queue, regardless of whether such instructions exist in the branch optimization queue. Only when the Fetch module's sequential execution queue does not contain instructions corresponding to the jump address, but the branch optimization queue does, will the branch optimization queue contain the instructions corresponding to the jump address and subsequent instructions.

[0097] In existing technologies, instructions are fetched from the instruction cache whenever the instruction corresponding to the jump address is not present in the sequential execution queue of the Fetch module. This embodiment provides a method that, even when the instruction corresponding to the jump address is not present in the sequential execution queue of the Fetch module, does not necessarily fetch from the instruction cache. Whether or not an instruction is fetched from the instruction cache depends on whether the instruction corresponding to the jump address is present in the branch optimization queue. If the instruction corresponding to the jump address is present in the branch optimization queue, the instruction cache will not be fetched; only if the instruction corresponding to the jump address is not present in the branch optimization queue will the instruction cache be fetched. This reduces the number of times instructions are fetched from the instruction cache during branch instruction execution, reduces processor power consumption, and improves execution efficiency.

[0098] The following example, which requires a branch instruction to jump upwards, will be used to illustrate the method provided in this embodiment in detail.

[0099] An upward jump refers to a branch instruction actually jumping to an address that is lower than the address of the instruction currently being executed by the program. This situation is usually a loop program. The instruction fetching method for branch instructions provided in this embodiment can store the instruction corresponding to the actual jump address and subsequent instructions in the branch optimization queue. When the program jumps, the instruction of that program segment can be directly fetched from the branch optimization queue, thereby covering the empty bubbles caused by re-initiating the instruction cache fetch request in the prior art.

[0100] like Figure 1 As shown, the program segment executes sequentially from PC0 to PCM and then to PCN+1. SEQ is a branch instruction. When this SEQ instruction is executed subsequently, it finds that the jump address is PCM and returns to the previously executed program segment. However, at this time, PCM and subsequent instructions have already left the sequential execution queue of the Fetch module (e.g., Figure 4 As shown), in the prior art, a new instruction fetch request for the jump address would be initiated at this time, and it takes 3 cycles from the issuance of the fetch request to the instruction entering the instruction queue. However, in the method provided in this embodiment, if the branch optimization queue contains these instructions (such as...), Figure 4As shown in the diagram, the sequential execution queue of the Fetch module stores instructions to be executed sequentially, which are instructions following SEQ. The branch optimization queue stores PCM and subsequent instructions, which are instructions preceding SEQ. When SEQ is executed, a jump occurs at the PCM address, and the instructions in the branch optimization queue can be directly dispatched to the next instruction. The process described in this embodiment only requires one cycle to execute the instruction, saving two cycles of idling.

[0101] The specific implementation process of the instruction fetching method for branch instructions provided in this embodiment is as follows: Figures 5 to 13 As shown. If the instructions in the sequential execution queue of the Fetch module are output from the InstrLatch register, after dispatch judgment, they are dispatched by the dispatch register, enter the Rename unit to output reg, and then output to other execution units / the issue FIFO to which the execution unit belongs, or SEQ execution.

[0102] Initially, the upward jump branch storage queue is empty;

[0103] like Figure 5 As shown, at time Clk0, the first instruction in the current Fetch module's sequential execution queue is the SEQ instruction, which is currently being dispatched. The PCM instruction has arrived at the execution unit for execution or is waiting to be sent in the FIFO. The PCM+1 instruction is dispatched.

[0104] like Figure 6 As shown, at time Clk1, the SEQ instruction is dispatched to the Rename unit to output reg, and the PCN instruction performs dispatch determination.

[0105] like Figure 7 As shown, at time Clk2, SEQ executes a discovery instruction jump, and the jump address is PCM. Simultaneously, the jump address is returned to the Fetch module. At this time, the branch optimization queue is empty, and there are no PCM instructions in the Fetch module's sequential execution queue, requiring an instruction fetch request to be initiated. Instructions located in dispatch and rename are invalidated. At this point, the Fetch module executes step 201 of the instruction fetch method for branch instructions shown in this embodiment to determine the jump address of the branch instruction.

[0106] like Figure 8As shown, at time Clkx, the instruction PCM enters the sequential execution queue of the Fetch module from the instruction cache (such as ICache), and simultaneously stores the instruction in the branch optimization queue. That is, the Fetch module executes the instruction fetching method for branch instructions shown in this embodiment, specifically the process of "if the instruction corresponding to the jump address does not exist in the branch optimization queue, fetching the instruction corresponding to the jump address and subsequent instructions from the instruction cache, and storing the instruction corresponding to the jump address and subsequent instructions into the sequential execution queue and branch optimization queue of the Fetch module."

[0107] like Figure 9 As shown, at time Clkx+1, the PCM+1 instruction enters two queues, and the PCM instruction is dispatched. That is, from time Clkx+1 onwards, the Fetch module executes the following process in the instruction fetching method for branch instructions shown in this embodiment: "If the instruction corresponding to the jump address does not exist in the branch optimization queue, fetch the instruction corresponding to the jump address and its subsequent instructions from the instruction cache, and store the instruction corresponding to the jump address and its subsequent instructions into the sequential execution queue and the branch optimization queue of the Fetch module," followed by "fetching the instruction corresponding to the jump address and its subsequent instructions from the sequential execution queue of the Fetch module."

[0108] like Figure 10 As shown, at time Clkx+2, the SEQ instruction enters two queues, the PCM+1 instruction is dispatched, and the PCM instruction re-enters the execution unit for execution or waits for transmission in the FIFO.

[0109] like Figure 11 As shown, at time Clkx+3, the PCN instruction enters the sequential fetch queue, and the SEQ instruction is dispatched.

[0110] like Figure 12 As shown, at time Clkx+4, SEQ executes the discovery jump instruction with the jump address being PCM. At this time, it returns to the Fetch module from the jump address, hitting the branch optimization queue. It is not necessary to re-initiate the PCM fetch request; only the PCN fetch request needs to be initiated.

[0111] like Figure 13 As shown, at time Clkx+5, the PCM and subsequent instructions are retrieved from the branch optimization queue. If the PCM and subsequent instructions are retrieved from the branch optimization queue, the instructions are then written into the sequential execution queue of the Fetch module. That is, the Fetch module executes step 202 of the instruction fetching method for branch instructions shown in this embodiment. When only the instruction corresponding to the jump address exists in the branch optimization queue, the instruction corresponding to the jump address and subsequent instructions are retrieved from the branch optimization queue.

[0112] At time Clkx+6, PCM is executed to perform dispatch judgment and other subsequent processes.

[0113] The following example, which requires a downward jump in a branch instruction, will be used to illustrate the method provided in this embodiment in detail.

[0114] A downward jump occurs when the address to which the branch instruction actually jumps is higher than the address of the instruction currently being executed. Since the sequential execution queue of the Fetch module has a limited size (e.g., it can hold 20 instructions), there's a possibility that the jump address already exists in the Fetch module's sequential execution queue (this can be called a short jump). Figure 1 As shown, the jump address obtained from SEQ is PCN+1, and PCN+1 is already in the sequential execution queue of the Fetch module. Therefore, the Fetch module will perform the process of "if there is an instruction corresponding to the jump address in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module". For example, (1) pop the instructions before PCN+1 from the sequential execution queue of the Fetch module (at this time, PCN+1 is the first instruction at the head of the Fetch module). (2) Start from the head of the sequential execution queue of the Fetch module and retrieve instructions sequentially.

[0115] If the jump address is not in the sequential execution queue of the Fetch module (this can be called a long jump), the Fetch module performs the process of "determining whether the instruction corresponding to the jump address exists in the branch optimization queue" of the instruction fetching method for branch instructions provided in this embodiment. When the instruction corresponding to the jump address exists only in the branch optimization queue, step 202 is executed, that is, retrieving the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. When the instruction corresponding to the jump address does not exist in the branch optimization queue, 1) the instruction corresponding to the jump address and subsequent instructions are retrieved from the instruction cache, and stored in the sequential execution queue and branch optimization queue of the Fetch module. 2) The instruction corresponding to the jump address and subsequent instructions are retrieved from the sequential execution queue of the Fetch module.

[0116] The Fetch module can save time lost due to instruction fetching by using the instruction fetching method for branch instructions provided in this embodiment.

[0117] Furthermore, in specific implementations, the Fetch module can have one or more candidate branch optimization queues. The method provided in this embodiment stores the relevant instructions of a branch instruction into a candidate branch optimization queue. In this case, the candidate branch optimization queue containing the relevant instructions of that branch is the branch optimization queue mentioned in this embodiment. That is, the branch optimization queue is related to the final branch of the branch instruction that needs to be stored. Specifically, the branch optimization queue mentioned in this embodiment is only for the current execution. Each time the method provided in this embodiment is executed, its branch optimization queue may be the same candidate branch optimization queue or a different candidate branch optimization queue.

[0118] If there is only one candidate branch optimization queue, whenever a branch instruction is encountered and the instruction fetching method for branch instructions provided in this embodiment is executed, the candidate branch optimization queue will be determined as the branch optimization queue.

[0119] If multiple candidate branch optimization queues exist, whenever a branch instruction is encountered and the instruction fetching method for branch instructions provided in this embodiment is executed, an empty candidate branch optimization queue (i.e., an empty candidate branch optimization queue) is preferentially determined as the branch optimization queue, meaning it is preferentially stored in an empty candidate branch optimization queue. In other words, when an empty candidate branch optimization queue exists, one of the empty candidate branch optimization queues is randomly selected as the branch optimization queue.

[0120] If there is no empty candidate branch optimization queue, and if there are two candidate branch optimization queues, then one of them is selected as the branch optimization queue through round-robin. For example, if the two candidate branch optimization queues are candidate branch optimization queue 0 and candidate branch optimization queue 1, if candidate branch optimization queue 0 was selected last time, then candidate branch optimization queue 1 will be selected this time. If candidate branch optimization queue 1 was selected last time, then candidate branch optimization queue 0 will be selected this time. If there are multiple candidate branch optimization queues, then the candidate branch optimization queue that has not been selected as a branch optimization queue for the longest time is selected, that is, the candidate branch optimization queue with the smallest selection value is selected as the branch optimization queue.

[0121] The selection value of any candidate branch optimization queue is the sum of all elements in the corresponding row of the selection matrix for any candidate branch optimization queue.

[0122] The selection matrix is ​​an n×n matrix, where n is the total number of candidate branch optimization queues. Each row in the selection matrix uniquely corresponds to a candidate branch optimization queue. The selection matrix is ​​initially a 0 matrix. When a candidate branch optimization queue i is determined as a branch optimization queue, the element in the i-th row of the selection matrix is ​​first updated to 1, and the element in the i-th column of the selection matrix is ​​then updated to 0, where the i-th row is the row corresponding to candidate branch optimization queue i in the selection matrix.

[0123] For example, if there are 3 candidate branches in the optimization queue, then n=3, and the selection matrix is ​​as follows: Figure 14 As shown, row 0 corresponds to candidate branch optimization queue 0, row 1 corresponds to candidate branch optimization queue 1, and row 2 corresponds to candidate branch optimization queue 2. If candidate branch optimization queue 0 was previously selected as the branch optimization queue, then the element in row 0 of the selection matrix will be updated to 1 first, and then the element in column 0 of the selection matrix will be updated to 0.

[0124] In this execution, the selection value for candidate branch optimization queue 0 is the sum of all elements in the 0th row of the selection matrix (i.e., 0+1+1=2), the selection value for candidate branch optimization queue 1 is the sum of all elements in the 1st row of the selection matrix (i.e., 0+0+0=0), and the selection value for candidate branch optimization queue 2 is the sum of all elements in the 2nd row of the selection matrix (i.e., 0+0+0=0). The candidate branch optimization queue with the smallest selection value is determined as the branch optimization queue. If there are multiple candidate branch optimization queues with the smallest selection value, one is randomly selected. For example, candidate branch optimization queue 2 is selected as the branch optimization queue in this execution.

[0125] Furthermore, in the specific implementation of the branch instruction fetching method provided in this embodiment, the branch optimization queue can be further subdivided, such as including at least one jump-up optimization queue and at least one branch prefetch optimization queue (e.g., Figure 15 (As shown). Alternatively, a branch optimization queue, comprising at least one upward jump optimization queue, at least one branch prefetch optimization queue, and at least one maneuver queue (e.g. Figure 16 (As shown).

[0126] The aforementioned candidate branch optimization queue can be an upward jump optimization queue, or it can be a branch prefetch optimization queue.

[0127] The branch optimization queue does not actively initiate instruction fetch requests; it only passively receives instructions. The jump-up optimization queue only stores the jump address instructions for the previous branch, and the branch prefetch optimization queue only stores the jump address instructions for the next and longest branches.

[0128] In practice, the configuration instructions of the program to which the instruction belongs can configure the jump initial value ini in the register. o For example, certain bit fields in the configuration directive store ini files.o The program needs to add this configuration instruction to inform the hardware of the number of jump-up optimization queues to use. The hardware stores the current configuration in a register and uses the queues according to the configuration. For example, the jump initial value ini is configured based on the loop state of the program to which the instruction belongs. o As inini o The maximum value is 5, and the minimum value is 1. If the program containing the instruction has many loops, and more than 5 different loops may be executed repeatedly within the same time period, the ini file can be modified accordingly. o Configure it to 5. If the number of loops in the program to which the instruction belongs is average, and more than 2 / 3 / 4 different loops may be executed repeatedly within the same period of time, the ini file can be configured to... o Configure it as 2 / 3 / 4. If loops are rarely encountered in the program containing the instruction, the ini file can be... o Configured to 1.

[0129] Before executing the method provided in this embodiment, the jump initial value ini is read from the register. o Among them, ini o The configuration is made in the register by the configuration instructions of the program to which the instruction belongs.

[0130] One of the multiple branch optimization queues is designated as the branch prefetch optimization queue. In other words, there must be at least one branch prefetch optimization queue.

[0131] If BO c -1≤ini o This indicates that the number of non-branch prefetch optimization queues in the branch optimization queue is insufficient, or that it is exactly equal to the jump initial value ini. o If this happens, then all other branch optimization queues will be designated as upward jump optimization queues. At this point, the branch optimization queues will contain only one upward jump optimization queue and at least one branch prefetch optimization queue.

[0132] Among them, BO c Optimize the total number of queues for branching.

[0133] If BO c -1>ini o This indicates that the number of non-branch prefetch optimization queues in the branch optimization queue is greater than the jump initial value ini. o Then the remaining branches will optimize random ini values ​​in the queue. o One queue is designated as the upward jump optimization queue, and the remaining branch optimization queue is designated as the maneuver queue. At this point, the branch optimization queue includes one upward jump optimization queue and one ini queue. o One branch prefetch optimization queue and at least one maneuver queue.

[0134] The above process ensures that the hardware resource usage of the branch optimization queue is adapted to the program to which the instruction belongs. Using more branch optimization queues is wasteful when the loop frequency is low; therefore, unnecessary hardware overhead can be reduced while making full use of existing resources. Each branch optimization queue is accessed in parallel.

[0135] Based on the aforementioned upward jump optimization queue and branch prefetch optimization queue, the instruction fetching method for branch instructions provided in this embodiment will obtain the branch optimization mode and jump address when executing step 201.

[0136] The branch optimization mode here refers to the branch optimization mode used in the Fetch module. For example, the Fetch module may use two branch optimization modes: jump-up optimization and branch prefetch optimization. Therefore, the branch optimization mode here is jump-up and / or branch prefetch. If the branch optimization mode is jump-up and the jump address is jump-up, then the method provided in this embodiment can achieve jump-up of the instruction address. If the branch optimization mode is branch prefetch and the jump address is jump-down, then the method provided in this embodiment can achieve prefetch of the instruction address. If the branch optimization mode is both jump-up and branch prefetch and the jump address is jump-up, then the method provided in this embodiment can achieve jump-up of the instruction address. If the branch optimization mode is both jump-up and branch prefetch and the jump address is jump-down, then the method provided in this embodiment can achieve prefetch of the instruction address.

[0137] In practice, the branch optimization mode used in the Fetch module can also include other modes, and the corresponding branch optimization mode is also other modes.

[0138] The optimization mode of the Fetch module is configurable and can be configured using specific commands.

[0139] After executing step 201, it will be determined whether the queue has been hit based on the branch optimization mode and the jump address.

[0140] Specifically: If the branch optimization mode is upward jump and the jump address is upward, then check if the upward jump optimization queue has been hit. If the branch optimization mode is branch prefetch and the jump address is downward, then check if the branch prefetch optimization queue has been hit. If the branch optimization mode is both upward jump and branch prefetch and the jump address is upward, then check if the upward jump optimization queue has been hit. If the branch optimization mode is both upward jump and branch prefetch and the jump address is downward, then check if the branch prefetch optimization queue has been hit.

[0141] Among them, the hit queue contains instructions corresponding to the jump address.

[0142] The hit queue, in the branch optimization queue corresponding to the branch optimization mode, is the queue containing the instructions corresponding to the jump address. If a hit queue exists, it means that the branch optimization queue contains a queue storing the instructions corresponding to the jump address. The instructions corresponding to the jump address and subsequent instructions can be directly retrieved from this queue for execution, achieving fast instruction fetching for branch instructions that require a jump during the instruction execution phase.

[0143] If no hit queue is found, it means that no queue in the branch optimization queue stores the instruction corresponding to the jump address. A queue (i.e., the replacement queue) will be selected, and the instruction corresponding to the jump address and subsequent instructions will be stored in the replacement queue. Then, when the same branch instruction is found during the instruction execution phase, the instruction can be fetched quickly.

[0144] Among them, (a) the process of selecting a queue (i.e., replacing the queue) is as follows:

[0145] If no hit queue exists, then if the branch optimization mode is an upward jump and the jump address is upward, the replacement queue is determined from the upward jump optimization queue. If the branch optimization mode is a branch prefetch and the jump address is downward, the replacement queue is determined from the branch prefetch optimization queue. If the branch optimization mode is both upward jump and branch prefetch and the jump address is upward, the replacement queue is determined from the upward jump optimization queue. If the branch optimization mode is both upward jump and branch prefetch and the jump address is downward, the replacement queue is determined from the branch prefetch optimization queue.

[0146] This process can determine the replacement queue from the branch optimization queue corresponding to the obtained branch optimization mode.

[0147] ●The process of determining the replacement queue in the upward jump optimization queue is as follows:

[0148] If an empty upward jump optimization queue exists, it means that an empty upward jump optimization queue exists. In this case, an empty upward jump optimization queue can be randomly selected as the replacement queue. That is, an empty upward jump optimization queue is preferred as the replacement queue.

[0149] If there is no empty jump-up optimization queue, then:

[0150] When there is only one queue for upward jump optimization, it is designated as the replacement queue.

[0151] When there are two upward jump optimization queues, the upward jump optimization queue that was not used as a replacement queue in the previous step is determined as the replacement queue.

[0152] When there are two or more upward jump optimization queues, the upward jump optimization queue with the smallest value will be selected as the replacement queue.

[0153] The selection value of any upward jump optimization queue is the sum of all elements in the corresponding row of the upward jump selection matrix for any upward jump optimization queue.

[0154] The upward jump selection matrix is ​​an n u ×n u Matrix, where n u The total number of upward jump optimization queues is determined. Each row in the upward jump selection matrix uniquely corresponds to an upward jump optimization queue. The upward jump selection matrix is ​​initially a 0-matrix. When a certain upward jump optimization queue i... u When a node is identified as part of the replacement queue, jump upwards to the i-th node of the selection matrix. u The elements of the first row are updated to 1, then the selection jumps up to the i-th element of the matrix. u The elements of the column are then updated to 0, where the i-th element... u Behavior-based upward jump optimization queue i u Jump up to select the corresponding row in the matrix.

[0155] Among them, the construction process of the upward jump selection matrix is ​​similar to... Figure 14 The process of constructing the selection matrix is ​​similar; please refer to the process of constructing the selection matrix. The process of determining the selection value for jumping up to the optimization queue is similar to the process of determining the selection value for the optimization queue; please refer to the process of determining the selection value for the optimization queue.

[0156] ●The process of determining the replacement queue in the branch prefetch optimization queue is as follows:

[0157] If an empty branch prefetch optimization queue exists, it means that an empty branch prefetch optimization queue exists, and in this case, an empty branch prefetch optimization queue can be designated as the replacement queue. That is, an empty branch prefetch optimization queue is preferentially selected as the replacement queue.

[0158] If there is no empty branch prefetch optimization queue, then:

[0159] When there is only one branch prefetch optimization queue, it is designated as the replacement queue.

[0160] When there are two branch prefetch optimization queues, the branch prefetch optimization queue that was not used as a replacement queue in the previous step is determined as the replacement queue.

[0161] When there are two or more branch prefetch optimization queues, the branch prefetch optimization queue with the smallest selection value is determined as the replacement queue.

[0162] The selection value of any branch prefetch optimization queue is the sum of all elements in the corresponding row of the branch prefetch selection matrix for any branch prefetch optimization queue.

[0163] The branch prefetch selection matrix is ​​an nd ×n d Matrix, where n d This represents the total number of branch prefetch optimization queues. Each row in the branch prefetch selection matrix uniquely corresponds to a branch prefetch optimization queue. The branch prefetch selection matrix is ​​initially a 0-matrix. When a certain branch prefetch optimization queue i... d When a node is identified as a replacement queue, the i-th node of the branch prefetch selection matrix is... d The elements of the row are first updated to 1, and the i-th element of the branch prefetch selection matrix is ​​then selected. d The elements of the column are then updated to 0, where the i-th element... d Behavior branch prefetch optimization queue i d The corresponding row in the branch prefetch selection matrix.

[0164] Among them, the construction process of the branch prefetch selection matrix is ​​similar to Figure 14 The process of constructing the selection matrix is ​​similar; please refer to the process of constructing the selection matrix. The process of determining the selection values ​​for the branch prefetch optimization queue is similar to the process of determining the selection values ​​for the optimization queue; please refer to the process of determining the selection values ​​for the optimization queue.

[0165] (b) The process of storing the instruction corresponding to the jump address and subsequent instructions into the replacement queue is as follows:

[0166] Retrieve the instruction and subsequent instructions corresponding to the jump address from the instruction cache, and store the instruction and subsequent instructions corresponding to the jump address into the replacement queue.

[0167] The process of storing the instruction corresponding to the jump address and subsequent instructions into the replacement queue is as follows:

[0168] If the replacement queue is empty, the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the replacement queue.

[0169] If the replacement queue is not empty, all instructions in the replacement queue are popped, and the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the replacement queue.

[0170] Alternatively, if a hit queue exists, step 202 is executed, in which case instructions are fetched sequentially starting from the head of the hit queue.

[0171] Since the maneuver queue can be used as an upward jump optimization queue when the upward jump optimization queue cannot meet the actual needs of upward jump optimization, and as a branch prefetch optimization queue when the branch prefetch optimization queue cannot meet the actual needs of branch prefetch optimization, the method provided in this embodiment can also periodically adjust the maneuver queue through the following supplementary process.

[0172] 1. Determine the total number of hit checks h for the upward jump optimization queue within a preset time period (e.g., the last 3 minutes). u (Including hit checks for branch optimization mode of upward jump, and hit checks in the upward jump optimization queue during branch prefetching, the total number of times the result is a hit in the upward jump optimization queue eh) u (Including hits in the upward jump optimization queue when the branch optimization mode is upward jump, and hits in the upward jump optimization queue when the branch optimization mode is upward jump and during branch prefetching), the total number of times h is performed to determine the hit of the branch prefetch optimization queue. d (Including the hit detection for branch prefetching in the branch optimization mode, and the hit detection for branch prefetching in the branch optimization mode of jumping upwards), the total number of times the detection result is that the branch prefetching optimization queue has been hit (eh). d (Including branch prefetch optimization queue hits when the branch optimization mode is branch prefetch, and branch prefetch optimization queue hits when the branch optimization mode is jump up and branch prefetch).

[0173] 2. If Then, one of the maneuver queues is designated as the upward jump optimization queue. If Then, a maneuver queue is determined as a branch prefetch optimization queue.

[0174] As can be seen from steps 301 to 304, when a branch instruction obtains both the branch optimization mode and the jump address, a hit check will be performed (i.e., step 302 will be executed once; if the branch optimization mode is an upward jump and the jump address is an upward jump, or if the branch optimization mode is an upward jump and branch prefetch and the jump address is an upward jump, then a hit check will be performed in the upward jump optimization queue in step 302; if the branch optimization mode is a branch prefetch and the jump address is a downward jump, or if the branch optimization mode is an upward jump and branch prefetch and the jump address is a downward jump, then a hit check will be performed in the branch prefetch optimization queue in step 302). u h represents the number of branches requiring upward jumps among all instructions executed by the program within a preset time period. d It represents the number of branch optimization requirements that generate branch prefetching among all instructions executed by the program to which the instruction belongs within a preset time period.

[0175] During the hit check, if the branch optimization mode is jump-up or branch prefetch, the result is either a hit or a miss. If the branch optimization mode is both jump-up and branch prefetch, the result is either a hit in the jump-up optimization queue, a hit in the branch prefetch optimization queue, or a miss in either queue. For misses, a replacement queue is created. Therefore, each branch instruction generates a hit result, a miss result, or a hit and / or miss result. Each miss result indicates a replacement queue has been performed. A hit result means the instruction corresponding to the jump address exists in the current branch optimization queue, meaning the jump-up optimization queue and / or branch prefetch optimization queue can meet the program's requirements. A miss result means the instruction corresponding to the jump address does not exist in the current branch optimization queue, meaning the jump-up optimization queue and / or branch prefetch optimization queue cannot meet the program's requirements.

[0176] Based on the above analysis, eh u This characterizes the number of times the upward jump optimization queue satisfies the branch instruction requirements within a preset time period (including hits in the upward jump optimization queue when the branch optimization mode is upward jump, and hits in the upward jump optimization queue when the branch optimization mode is upward jump and during branch prefetching), h u -eh u This represents the number of times the upward jump optimization queue fails to meet the branch instruction requirements within a preset time period. It represents the ratio of satisfaction to dissatisfaction. This indicates that within the preset time period, there are more cases where the upward jump optimization queue does not meet the branch instruction requirements. In this case, it is considered that the upward jump optimization queue is insufficient and the number of upward jump optimization queues needs to be increased. Therefore, a mobile queue is designated as the upward jump optimization queue.

[0177] eh d This characterizes the number of times the branch prefetch optimization queue satisfies the branch instruction requirement within a preset time period (including branch prefetch optimization queue hits when the branch optimization mode is branch prefetch, and branch prefetch optimization queue hits when the branch optimization mode is jump up and branch prefetch). d -eh d This represents the number of times the branch prefetch optimization queue fails to meet the branch instruction requirements within a preset time period. It represents the ratio of satisfaction to dissatisfaction. This indicates that within the preset time period, there are more cases where the branch prefetch optimization queue does not meet the requirements of branch instructions. In this case, it is considered that the number of branch prefetch optimization queues is insufficient and the number of branch prefetch optimization queues needs to be increased. Therefore, a mobile queue is determined as the branch prefetch optimization queue.

[0178] The above is a supplementary process for the maneuver queue to the jump optimization queue and the branch prefetch optimization queue. In the method provided in this embodiment, the jump optimization queue and / or the branch prefetch optimization queue can also be periodically adjusted through the following process.

[0179] 1. Determine the optimal queue size s for upward jumps from a stationary position. u Determine the number s of the prefetch optimization queue for the static branch. d .

[0180] Among them, the static upward jump optimization queue is the upward jump optimization queue that is neither a hit queue nor a replacement queue in the hit judgment of each upward jump optimization queue within a preset time period.

[0181] The static branch prefetch optimization queue is the branch prefetch optimization queue that is neither a hit queue nor a replacement queue in the hit judgment of each branch prefetch optimization queue within a preset time period.

[0182] 2. If h u <α u , and s u ≥β u Then, a static upward jump optimization queue is determined as a mobile queue. If h d <α d , and s d ≥β d Then, a static branch prefetch optimization queue is determined as a mobile queue.

[0183] Where, α u The threshold for optimizing the upward jump queue is a standard for determining the optimization requirement of upward jump branches within a preset time period. If the optimization requirement of upward jump branches within the preset time period is less than α, then... u If the value is positive, it indicates that there is relatively little need for upward branch optimization within the preset time period; otherwise, it indicates that there is relatively much need for upward branch optimization within the preset time period. β u The threshold for the static upward jump optimization queue is a standard based on the number of unused upward jump optimization queues within a preset time period. If the number of unused upward jump optimization queues within the preset time period is less than β... u If the number of unused upward jump optimization queues is relatively small within the preset time period, then it indicates that the number of unused upward jump optimization queues is relatively large within the preset time period.

[0184] αd A threshold is set for the branch prefetch optimization queue. This threshold is a standard for determining the branch optimization demand during branch prefetching within a preset time period. If the branch optimization demand during branch prefetching within the preset time period is less than α, then... d If the value is positive, it indicates that there are relatively few branch optimization needs during the preset time period; otherwise, it indicates that there are relatively many branch optimization needs during the preset time period. β d The threshold for the static branch prefetch optimization queue is a standard for the number of unused branch prefetch optimization queues within a preset time period. If the number of unused branch prefetch optimization queues within the preset time period is less than β, then the threshold is set. d If the number of unused branch prefetch optimization queues is small within the preset time period, then the number of unused branch prefetch optimization queues is large within the preset time period.

[0185] The static upward jump optimization queue actually consists of upward jump optimization queues that have not been hit or selected as replacement queues within a preset time period. The more of these queues there are, the more unused upward jump optimization queues there are, necessitating a reduction in the number of upward jump optimization queues to release the resources they occupy. That is, if h u <α u This indicates that there is relatively little need for upward branch optimization within the preset time period. If simultaneously s u ≥β u If there are a large number of unused upward jump optimization queues within a preset time period, then there are few upward jump branch optimization needs and a large number of upward jump optimization queues. Therefore, it is necessary to reduce the number of upward jump optimization queues. Thus, a static upward jump optimization queue is designated as a mobile queue.

[0186] The static branch prefetch optimization queue is actually a branch prefetch optimization queue that has not been hit or selected as a replacement queue within a preset time period. The more of this queue there is, the more unused branch prefetch optimization queues there are, necessitating a reduction in the number of branch prefetch optimization queues and consequently, the resources occupied by them. That is, if h d <α d This indicates that the branch optimization requirement for branch prefetching is relatively low within the preset time period. If simultaneously s d ≥β d If there are a large number of unused branch prefetch optimization queues within a preset time period, then the branch prefetch optimization needs are low and the number of branch prefetch optimization queues is large. Therefore, it is necessary to reduce the number of branch prefetch optimization queues. Thus, a static upward jump optimization queue is designated as a mobile queue.

[0187] Through the above process, the maneuver queue can dynamically adjust the number of the jump optimization queue and the branch prefetch optimization queue, which ensures fast instruction fetching while avoiding resource waste.

[0188] This embodiment provides a method for fetching branch instructions, determining the jump address of the branch instruction; when only the instruction corresponding to the jump address exists in the branch optimization queue, the instruction corresponding to the jump address and subsequent instructions are fetched from the branch optimization queue; wherein, the branch optimization queue is initially empty; the instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache. The method provided in this embodiment, when only the instruction corresponding to the jump address exists in the branch optimization queue, fetches the instruction corresponding to the jump address and its subsequent instructions from the branch optimization queue, so that when a branch jump occurs, only the instruction corresponding to the jump address and its subsequent instructions need to be fetched from the branch optimization queue, without having to start fetching instructions sequentially again, reducing processor power consumption and improving execution efficiency.

[0189] Based on the same inventive concept as the instruction fetching method for branch instructions, this embodiment provides an instruction fetching device for branch instructions, see [link to documentation]. Figure 17 The device includes:

[0190] The acquisition module 1701 is used to determine the jump address of the branch instruction.

[0191] The instruction fetch module 1702 is used to fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue when the instruction corresponding to the jump address determined by the fetch module 1701 exists only in the branch optimization queue.

[0192] The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache.

[0193] The jump address is determined when executing branch instructions in the sequential execution queue of the Fetch module. Alternatively, it can be determined through branch prediction.

[0194] The device further includes a first processing module, used to determine whether there is an instruction corresponding to the jump address in the sequential execution queue of the Fetch module.

[0195] If the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

[0196] The device further includes a first processing module, used to determine whether there is an instruction corresponding to the jump address in the branch optimization queue when there is no instruction corresponding to the jump address in the sequential execution queue of the Fetch module.

[0197] If the instruction corresponding to the jump address is not found in the branch optimization queue, the instruction corresponding to the jump address and its subsequent instructions are retrieved from the instruction cache, and then stored in the sequential execution queue and branch optimization queue of the Fetch module. The instruction corresponding to the jump address and its subsequent instructions are then retrieved from the sequential execution queue of the Fetch module.

[0198] This includes retrieving the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module, including:

[0199] If the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

[0200] If the instruction corresponding to the jump address is not at the head of the Fetch module's sequential execution queue, then the instruction preceding the instruction at the jump address is popped from the Fetch module's sequential execution queue. Instructions are then fetched sequentially, starting from the head of the Fetch module's sequential execution queue.

[0201] Specifically, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue, including:

[0202] If the branch optimization queue is empty, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue in sequence.

[0203] If the branch optimization queue is not empty, pop all instructions from the branch optimization queue and store the instruction corresponding to the jump address and subsequent instructions into the branch optimization queue in sequence.

[0204] If there is only one candidate branch optimization queue, then the candidate branch optimization queue is determined as the branch optimization queue.

[0205] If multiple candidate branch optimization queues exist, and one of them is empty, then that empty candidate branch optimization queue is selected as the branch optimization queue. If no candidate branch optimization queue is empty, then the candidate branch optimization queue with the smallest value is selected as the branch optimization queue.

[0206] The selection value of any candidate branch optimization queue is the sum of all elements in the corresponding row of the selection matrix for any candidate branch optimization queue.

[0207] The selection matrix is ​​an n×n matrix, where n is the total number of candidate branch optimization queues. Each row in the selection matrix uniquely corresponds to a candidate branch optimization queue. The selection matrix is ​​initially a 0 matrix. When a candidate branch optimization queue i is determined as a branch optimization queue, the element in the i-th row of the selection matrix is ​​first updated to 1, and the element in the i-th column of the selection matrix is ​​then updated to 0, where the i-th row is the row corresponding to candidate branch optimization queue i in the selection matrix.

[0208] The apparatus provided in this embodiment retrieves the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue when only the branch optimization queue contains the instruction corresponding to the jump address. This allows for branch jumps to be performed by retrieving only the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue, eliminating the need to start retrieving instructions sequentially again. This reduces processor power consumption and improves execution efficiency.

[0209] Based on the same inventive concept as the instruction fetching method for branch instructions, this embodiment provides an electronic device, which, as... Figure 18 As shown, it includes: a memory 1801, a processor 1802, and a computer program.

[0210] The computer program is stored in memory 1801 and configured to be executed by processor 1802 to implement the above-described instruction fetching method for branch instructions.

[0211] Specifically,

[0212] Determine the jump address for the branch instruction.

[0213] If the instruction corresponding to the jump address exists only in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue.

[0214] The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache.

[0215] Optionally, the jump address is determined when executing branch instructions in the sequential execution queue of the Fetch module. Alternatively, it can be determined through branch prediction.

[0216] Optionally, after determining the jump address of the branch instruction, the method further includes:

[0217] Determine if the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module.

[0218] If the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

[0219] Optionally, after determining whether the Fetch module's sequential execution queue contains an instruction corresponding to the jump address, the method further includes:

[0220] If there is no instruction corresponding to the jump address in the sequential execution queue of the Fetch module, determine whether there is an instruction corresponding to the jump address in the branch optimization queue.

[0221] If the instruction corresponding to the jump address is not found in the branch optimization queue, the instruction corresponding to the jump address and its subsequent instructions are retrieved from the instruction cache, and then stored in the sequential execution queue and branch optimization queue of the Fetch module. The instruction corresponding to the jump address and its subsequent instructions are then retrieved from the sequential execution queue of the Fetch module.

[0222] Optionally, the instructions corresponding to the jump address and subsequent instructions are retrieved from the sequential execution queue of the Fetch module, including:

[0223] If the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

[0224] If the instruction corresponding to the jump address is not at the head of the Fetch module's sequential execution queue, then the instruction preceding the instruction at the jump address is popped from the Fetch module's sequential execution queue. Instructions are then fetched sequentially, starting from the head of the Fetch module's sequential execution queue.

[0225] Optionally, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue, including:

[0226] If the branch optimization queue is empty, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue in sequence.

[0227] If the branch optimization queue is not empty, pop all instructions from the branch optimization queue and store the instruction corresponding to the jump address and subsequent instructions into the branch optimization queue in sequence.

[0228] Optionally, if there is only one candidate branch optimization queue, then the candidate branch optimization queue is determined as the branch optimization queue.

[0229] If multiple candidate branch optimization queues exist, and one of them is empty, then that empty candidate branch optimization queue is selected as the branch optimization queue. If no candidate branch optimization queue is empty, then the candidate branch optimization queue with the smallest value is selected as the branch optimization queue.

[0230] The selection value of any candidate branch optimization queue is the sum of all elements in the corresponding row of the selection matrix for any candidate branch optimization queue.

[0231] The selection matrix is ​​an n×n matrix, where n is the total number of candidate branch optimization queues. Each row in the selection matrix uniquely corresponds to a candidate branch optimization queue. The selection matrix is ​​initially a 0 matrix. When a candidate branch optimization queue i is determined as a branch optimization queue, the element in the i-th row of the selection matrix is ​​first updated to 1, and the element in the i-th column of the selection matrix is ​​then updated to 0, where the i-th row is the row corresponding to candidate branch optimization queue i in the selection matrix.

[0232] The electronic device provided in this embodiment has a computer program executed by a processor to retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue when only the instruction corresponding to the jump address exists in the branch optimization queue. This allows the processor to retrieve only the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue when a branch jump occurs, without having to start retrieving instructions sequentially again, thus reducing processor power consumption and improving execution efficiency.

[0233] Based on the same inventive concept as the instruction fetching method for branch instructions, this embodiment provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the above-described instruction fetching method for branch instructions.

[0234] Specifically,

[0235] Determine the jump address for the branch instruction.

[0236] If the instruction corresponding to the jump address exists only in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue.

[0237] The branch optimization queue is initially empty. The instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is fetched from the instruction cache.

[0238] Optionally, the jump address is determined when executing branch instructions in the sequential execution queue of the Fetch module. Alternatively, it can be determined through branch prediction.

[0239] Optionally, after determining the jump address of the branch instruction, the method further includes:

[0240] Determine if the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module.

[0241] If the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

[0242] Optionally, after determining whether the Fetch module's sequential execution queue contains an instruction corresponding to the jump address, the method further includes:

[0243] If there is no instruction corresponding to the jump address in the sequential execution queue of the Fetch module, determine whether there is an instruction corresponding to the jump address in the branch optimization queue.

[0244] If the instruction corresponding to the jump address is not found in the branch optimization queue, the instruction corresponding to the jump address and its subsequent instructions are retrieved from the instruction cache, and then stored in the sequential execution queue and branch optimization queue of the Fetch module. The instruction corresponding to the jump address and its subsequent instructions are then retrieved from the sequential execution queue of the Fetch module.

[0245] Optionally, the instructions corresponding to the jump address and subsequent instructions are retrieved from the sequential execution queue of the Fetch module, including:

[0246] If the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

[0247] If the instruction corresponding to the jump address is not at the head of the Fetch module's sequential execution queue, then the instruction preceding the instruction at the jump address is popped from the Fetch module's sequential execution queue. Instructions are then fetched sequentially, starting from the head of the Fetch module's sequential execution queue.

[0248] Optionally, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue, including:

[0249] If the branch optimization queue is empty, the instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue in sequence.

[0250] If the branch optimization queue is not empty, pop all instructions from the branch optimization queue and store the instruction corresponding to the jump address and subsequent instructions into the branch optimization queue in sequence.

[0251] Optionally, if there is only one candidate branch optimization queue, then the candidate branch optimization queue is determined as the branch optimization queue.

[0252] If multiple candidate branch optimization queues exist, and one of them is empty, then that empty candidate branch optimization queue is selected as the branch optimization queue. If no candidate branch optimization queue is empty, then the candidate branch optimization queue with the smallest value is selected as the branch optimization queue.

[0253] The selection value of any candidate branch optimization queue is the sum of all elements in the corresponding row of the selection matrix for any candidate branch optimization queue.

[0254] The selection matrix is ​​an n×n matrix, where n is the total number of candidate branch optimization queues. Each row in the selection matrix uniquely corresponds to a candidate branch optimization queue. The selection matrix is ​​initially a 0 matrix. When a candidate branch optimization queue i is determined as a branch optimization queue, the element in the i-th row of the selection matrix is ​​first updated to 1, and the element in the i-th column of the selection matrix is ​​then updated to 0, where the i-th row is the row corresponding to candidate branch optimization queue i in the selection matrix.

[0255] The computer-readable storage medium provided in this embodiment allows a computer program thereon to be executed by a processor. When only the instruction corresponding to the jump address exists in the branch optimization queue, the processor retrieves the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue. This ensures that when a branch jump occurs, only the instruction corresponding to the jump address and subsequent instructions need to be retrieved from the branch optimization queue, eliminating the need to start retrieving instructions sequentially again. This reduces the processor's power consumption and improves execution efficiency.

[0256] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0257] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0258] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0259] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0260] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0261] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for fetching branch instructions, characterized in that, The method includes: Determine the jump address of the branch instruction; where the jump address is determined when executing branch instructions in the sequential execution queue of the Fetch module; or, determined through branch prediction; Determine whether the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module; If the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, the instruction corresponding to the jump address and subsequent instructions are retrieved from the sequential execution queue of the Fetch module; the instruction corresponding to the jump address is executed as the first instruction at the head of the sequential execution queue of the Fetch module. If the instruction corresponding to the jump address exists only in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue; The branch optimization queue is initially empty; the instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is retrieved from the instruction cache.

2. The method according to claim 1, characterized in that, After determining whether the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, the method further includes: If the instruction corresponding to the jump address is not present in the sequential execution queue of the Fetch module, determine whether the instruction corresponding to the jump address is present in the branch optimization queue; If the instruction corresponding to the jump address is not found in the branch optimization queue, retrieve the instruction corresponding to the jump address and subsequent instructions from the instruction cache, and store the instruction corresponding to the jump address and subsequent instructions into the sequential execution queue and the branch optimization queue of the Fetch module; retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module.

3. The method according to claim 1 or 2, characterized in that, The step of retrieving the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module includes: If the instruction corresponding to the jump address is the head instruction of the sequential execution queue of the Fetch module, then the instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module. If the instruction corresponding to the jump address is not the head instruction of the sequential execution queue of the Fetch module, then the instruction preceding the instruction corresponding to the jump address in the sequential execution queue of the Fetch module is popped; and instructions are fetched sequentially starting from the head of the sequential execution queue of the Fetch module.

4. The method according to claim 2, characterized in that, The instruction corresponding to the jump address and subsequent instructions are stored in the branch optimization queue, including: If the branch optimization queue is empty, the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the branch optimization queue. If the branch optimization queue is not empty, then all instructions in the branch optimization queue are popped, and the instruction corresponding to the jump address and subsequent instructions are sequentially stored in the branch optimization queue.

5. The method according to claim 4, characterized in that, If there is only one candidate branch optimization queue, then the candidate branch optimization queue is determined as the branch optimization queue; If there are multiple candidate branch optimization queues, then if there is an empty candidate branch optimization queue, the empty candidate branch optimization queue will be determined as the branch optimization queue; if there is no empty candidate branch optimization queue, the candidate branch optimization queue with the smallest value will be selected as the branch optimization queue. The selection value of any candidate branch optimization queue is the sum of all elements in the corresponding row of the selection matrix for any candidate branch optimization queue. The selection matrix is ​​a Matrix, where, The total number of candidate branch optimization queues; each row in the selection matrix uniquely corresponds to a candidate branch optimization queue; the selection matrix is ​​initially a 0 matrix; when a certain candidate branch optimization queue... When a queue is selected for branch optimization, the matrix number is chosen. The elements of the first row are updated to 1, and then the matrix is ​​selected. The elements of the column are then updated to 0, where the first element is... Behavior candidate branch optimization queue Select the corresponding row in the matrix.

6. An instruction fetching device for branch instructions, characterized in that, The device includes: A determination module is used to determine the jump address of a branch instruction; determine whether the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module; if the instruction corresponding to the jump address exists in the sequential execution queue of the Fetch module, retrieve the instruction corresponding to the jump address and subsequent instructions from the sequential execution queue of the Fetch module; the instruction corresponding to the jump address is executed as the first instruction at the head of the sequential execution queue of the Fetch module; wherein, the jump address is determined when executing branch instructions in the sequential execution queue of the Fetch module; or, determined through branch prediction; The instruction fetching module is used to fetch the instruction corresponding to the jump address and subsequent instructions from the branch optimization queue when the instruction corresponding to the jump address determined by the determining module exists only in the branch optimization queue. The branch optimization queue is initially empty; the instruction corresponding to the jump address and its subsequent instructions are stored in the branch optimization queue when the branch instruction is retrieved from the instruction cache.

7. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the method as described in any one of claims 1-5.

8. A computer-readable storage medium, characterized in that, It stores a computer program thereon; the computer program is executed by a processor to implement the method as described in any one of claims 1-5.

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