Watchdog resetting method and device, equipment and storage medium

Abstract

The invention discloses a watchdog reset method, device and equipment and a storage medium, and relates to the technical field of signal control and processing.The watchdog reset method comprises the steps that after a watchdog function is started on a basic input and output system layer, a watchdog monitoring process of a software unit is initialized; periodically receiving a heartbeat detection flag bit of the watchdog monitoring process; determining the running state of the software unit according to the receiving result of the heartbeat detection flag bit; and determining a watchdog reset strategy according to the running state. According to the invention, an independent hardware chip is not needed, so that the watchdog resetting cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of signal control and processing technology, and in particular to a watchdog reset method, apparatus, device, and storage medium. Background Art

[0002] A watchdog reset is a mechanism used to monitor and ensure system stability, commonly found in embedded systems, microcontrollers, and computer hardware or software design. Currently, independent hardware watchdog chips are typically used, connected to the main CPU via a general-purpose input / output interface. Software watchdog resets are performed by inputting a watchdog pulse from the CPU. However, using a watchdog chip increases bill of materials and software development costs. Therefore, reducing the cost of watchdog resets remains an unresolved issue.

[0003] The above content is only used to assist in understanding the technical solution of this application and does not constitute an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a watchdog reset method, device, equipment and storage medium, aiming to solve the technical problem of how to reduce the cost of watchdog reset.

[0005] To achieve the above objectives, the present application proposes a watchdog reset method, the method comprising: After the watchdog function is started at the basic input and output system layer, the watchdog monitoring process of the software unit is initialized; Periodically receiving a heartbeat detection flag of the watchdog monitoring process; Determining the operating state of the software unit according to the reception result of the heartbeat detection flag; A watchdog reset strategy is determined according to the operating status.

[0006] In one embodiment, the step of determining the running status of the software unit according to the reception result of the heartbeat detection flag includes: If the heartbeat detection flag is received, determining that the running state of the software unit is normal; If the heartbeat detection flag is not received, it is determined that the running state of the software unit is a fault state.

[0007] In one embodiment, the step of determining a watchdog reset strategy according to the operating state includes: When the operating state is a fault state, obtaining a historical error level record of the heartbeat detection flag; A watchdog reset strategy is determined according to the historical error level record.

[0008] In one embodiment, the step of determining a watchdog reset strategy based on the historical error level record includes: When there is no historical error level record, generating an error log and restarting the software unit, and modifying the historical error level record of the heartbeat detection flag to a level 1 record; When the historical error level record is a level one record, an error log is generated and a hard restart is performed, and the historical error level record of the heartbeat detection flag is modified to a level two record; When the historical error level record is a level 2 record or a level 3 record, an error log is generated and a warning message is sent, and the historical error level record of the heartbeat detection flag is determined to be a level 3 record.

[0009] In one embodiment, the step of performing a hard restart includes: activating a hardware reset circuit via a timeout reset signal, wherein the timeout reset signal is generated by the basic input and output system layer; Transmitting the timeout reset signal to all peripheral chipsets; Receive a reset completion response returned by the peripheral chipset to complete the hard reset.

[0010] In one embodiment, after determining the watchdog reset strategy according to the operating state, the method further includes: determining a normal operation duration of the software unit according to the operation status; Obtaining historical error level records of the software unit; When the normal operation duration is longer than a preset duration, the historical error level record is downgraded and updated until the historical error level record is empty.

[0011] In one embodiment, after the periodic receiving of the heartbeat detection flag of the watchdog monitoring process, the method further includes: Obtaining a cyclic redundancy check code of the heartbeat detection flag, where the cyclic redundancy check code is added to the heartbeat detection flag by a basic input / output system layer; When the cyclic redundancy check code is detected to be abnormal, a hard restart is performed.

[0012] In addition, to achieve the above-mentioned purpose, the present application also proposes a watchdog reset device, which includes: A startup module, configured to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input and output system layer; A receiving module, configured to periodically receive a heartbeat detection flag of the watchdog monitoring process; A determination module, configured to determine the operating state of the software unit according to a reception result of the heartbeat detection flag; The reset module is used to determine the watchdog reset strategy according to the operating state.

[0013] In addition, to achieve the above-mentioned purpose, the present application also proposes a watchdog reset device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the watchdog reset method as described above.

[0014] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium and stores a computer program. When the computer program is executed by a processor, the steps of the watchdog reset method described above are implemented.

[0015] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the watchdog reset method described above are implemented.

[0016] The present application provides a watchdog reset method. After the watchdog function is started at the basic input and output system layer, the present application initializes the watchdog monitoring process of the software unit; periodically receives the heartbeat detection flag of the watchdog monitoring process; determines the operating status of the software unit based on the reception result of the heartbeat detection flag; and determines the watchdog reset strategy based on the operating status.

[0017] In summary, this application eliminates the use of a hardware watchdog chip, uses the built-in watchdog function in the hardware daughter board, adopts the shared library file provided by the basic input and output system, operates the input and output signals of the watchdog of the hardware daughter board to perform a hardware watchdog reset on the entire board, and reduces the cost of watchdog reset. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 A flowchart of the first embodiment of the watchdog reset method of the present application is provided; Figure 2 A flowchart of the second embodiment of the watchdog reset method of this application is provided; Figure 3 A schematic diagram of a brief flow chart of the watchdog reset method provided in Example 1 of the present application; Figure 4 This is a schematic diagram of the module structure of the watchdog reset device according to an embodiment of the present application; Figure 5 Schematic diagram of the device structure of the hardware operating environment involved in the watchdog reset method in the embodiment of the present application.

[0021] The purpose, features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0022] It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present application and are not intended to limit the present application.

[0023] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0024] The main solution of this application is to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input and output system layer; periodically receive the heartbeat detection flag of the watchdog monitoring process; determine the operating status of the software unit based on the reception result of the heartbeat detection flag; and determine the watchdog reset strategy based on the operating status.

[0025] Currently, independent hardware watchdog chips are typically used, connected to the main control CPU via a general-purpose input / output interface. Software watchdog resets are performed by inputting a watchdog pulse from the CPU. However, using a watchdog chip increases material costs and software development costs. Therefore, reducing the cost of watchdog resets remains an unresolved issue.

[0026] This application eliminates the use of a hardware watchdog chip, uses the built-in watchdog function in the hardware daughter board, adopts the shared library file provided by the basic input and output system, operates the input and output signals of the watchdog of the hardware daughter board to perform a hardware watchdog reset on the entire board, and reduces the cost of watchdog reset.

[0027] Based on this, the embodiment of the present application provides a watchdog reset method, referring to Figure 1 , Figure 1 This is a flowchart of the first embodiment of the watchdog reset method of the present application.

[0028] In this embodiment, the watchdog reset method includes steps S10 to S40: Step S10: After the watchdog function is started at the basic input and output system layer, the watchdog monitoring process of the software unit is initialized; It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, mobile phone, etc., or an electronic device capable of implementing the above functions, a watchdog reset device, etc. The following uses the watchdog reset device as an example to illustrate this embodiment and the following embodiments.

[0029] It should be noted that the Basic Input / Output System (BIOS) is a set of programs embedded in a computer's motherboard chip. It is responsible for hardware initialization and self-testing at startup, as well as providing an interface between the underlying hardware and the operating system. It is the first software to run after a computer boots up, providing the most basic hardware control support for the operating system. In this embodiment, the software unit refers to a container, a lightweight virtualization technology used to package an application and all its dependencies (such as the runtime environment, libraries, and configuration files) into a single, portable unit. This embodiment uses a shared library file provided by the BIOS to manipulate the input and output signals of the hardware daughterboard's watchdog to reset the hardware watchdog for the entire board. Therefore, after the watchdog function is enabled at the BIOS layer, the watchdog monitoring process within the container can be initialized.

[0030] Step S20: Periodically receiving the heartbeat detection flag of the watchdog monitoring process; It is understandable that the heartbeat detection flag represents the running status of the corresponding container. If the heartbeat detection flag is received, it means that the watchdog monitoring process of the container is running normally. If the heartbeat detection flag is not received, it means that the watchdog monitoring process is abnormal, which means that the container is abnormal.

[0031] In a feasible embodiment, after periodically receiving the heartbeat detection flag of the watchdog monitoring process, it also includes: obtaining a cyclic redundancy check code of the heartbeat detection flag, the cyclic redundancy check code is added to the heartbeat detection flag by the basic input and output system layer; when an abnormality is detected in the cyclic redundancy check code, a hard restart is performed.

[0032] It should be noted that the cyclic redundancy check code uses a cycle time count (CTC) mechanism, which embeds a count field that changes cyclically at a fixed period in continuous dog feeding pulses. When an abnormality in the cyclic redundancy check code is detected, it indicates that electromagnetic interference has caused pulse distortion or loss, and a hard restart is performed directly.

[0033] Step S30: determining the operating state of the software unit according to the reception result of the heartbeat detection flag; It is understandable that, by determining whether the heartbeat detection flag is received, it is possible to determine whether the watchdog monitoring process of the software unit is running normally, thereby determining the running status of the software unit.

[0034] In a feasible manner, the step of determining the running status of the software unit according to the reception result of the heartbeat detection flag includes: If the heartbeat detection flag is received, determining that the running state of the software unit is normal; If the heartbeat detection flag is not received, it is determined that the running state of the software unit is a fault state.

[0035] It is understood that when the heartbeat detection flag is detected, it indicates that the watchdog monitoring process of the software unit is running normally, thereby determining that the running state of the software unit is normal; when the heartbeat detection flag is not detected, it indicates that the watchdog monitoring process of the software unit is abnormal, thereby determining that the running state of the software unit is a fault state; Step S40: determining a watchdog reset strategy according to the operating status.

[0036] It's understandable that the watchdog reset strategy can be determined by the operating status. Specifically, when the operating status is a fault, a corresponding restart action is taken, including soft and hard restarts. A soft restart restarts only the software unit at the software level, affecting only that single software unit, while other software units continue to operate normally. A hard restart restarts the hardware, restarting all software units. Furthermore, if a hard restart is determined to be ineffective, an alarm message is generated to notify the administrator.

[0037] In this embodiment, after the watchdog function is started at the basic input and output system layer, the watchdog monitoring process of the software unit is initialized; the heartbeat detection flag of the watchdog monitoring process is periodically received; the operating status of the software unit is determined based on the reception result of the heartbeat detection flag; and the watchdog reset strategy is determined based on the operating status.

[0038] In summary, this embodiment eliminates the use of a hardware watchdog chip, uses the built-in watchdog function in the hardware daughter board, adopts the shared library file provided by the basic input and output system, operates the input and output signals of the watchdog of the hardware daughter board to perform a hardware watchdog reset on the entire board, and reduces the cost of watchdog reset.

[0039] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above embodiment 1 can be referred to the above introduction and will not be described in detail later. Figure 2 , step S40 further includes steps S401~S402: Step S401: when the operating state is a fault state, obtaining a historical error level record of the heartbeat detection flag; It's understandable that the historical error level record records the number of software unit failures. The greater the number of failures, the higher the level in the historical error level record. Therefore, when the operating state is faulty, it's necessary to obtain the historical error level record to determine whether the software unit has experienced its first or multiple failures, so that different response measures can be taken.

[0040] Step S402: determining a watchdog reset strategy according to the historical error level records.

[0041] In a feasible embodiment, the step of determining the watchdog reset strategy based on the historical error level record includes: when there is no historical error level record, generating an error log and restarting the software unit, and modifying the historical error level record of the heartbeat detection flag to a first-level record; when the historical error level record is a first-level record, generating an error log and performing a hard restart, and modifying the historical error level record of the heartbeat detection flag to a second-level record; when the historical error level record is a second-level record or a third-level record, generating an error log and sending a warning message, and determining the historical error level record of the heartbeat detection flag as a third-level record.

[0042] It should be noted that the specific steps of hard restart are to activate the hardware reset circuit through a timeout reset signal, and the timeout reset signal is generated by the basic input and output system layer; transmit the timeout reset signal to all peripheral chipsets; receive the reset completion response returned by the peripheral chipset to complete the hard restart.

[0043] It is understandable that when there is no record of the historical error level, it means that the software unit has failed for the first time in a period of time, which may be an occasional failure. In this case, an error log is generated and the software unit is restarted, and the historical error level record of the heartbeat detection flag is modified to a level one record. When the historical error level record is a level one record, it means that a soft restart has been performed but the failure still occurred, so it is necessary to generate an error log and perform a hard restart, and modify the historical error level record of the heartbeat detection flag to a level two record. When the historical error level record is a level two record or a level three record, it means that the restart method cannot solve the failure, and administrator intervention is required, so an error log is generated and a warning message is sent, which is handled by the administrator, and the historical error level record of the heartbeat detection flag is determined to be a level three record.

[0044] In a feasible embodiment, after determining the watchdog reset strategy according to the operating status, it also includes: determining the normal operating time of the software unit according to the operating status; obtaining the historical error level record of the software unit; when the normal operating time is greater than the preset time, downgrading and updating the historical error level record until the historical error level record is empty.

[0045] It is understandable that if the process disappears abnormally after restarting, the main monitoring program has an aging time record, and the flag level can be lowered step by step. The default aging time is 60 minutes, and users can also adjust it according to actual conditions.

[0046] In this embodiment, if the heartbeat detection flag is received, the running state of the software unit is determined to be a normal state; if the heartbeat detection flag is not received, the running state of the software unit is determined to be a fault state.

[0047] This embodiment determines the severity of the fault by querying historical error level records, thereby selecting a corresponding watchdog reset measure to meet the watchdog reset requirement.

[0048] For example, in order to help understand the implementation process of the watchdog reset method obtained by combining this embodiment with the above embodiment 1, please refer to Figure 3 , Figure 3 A simplified flowchart of a watchdog reset method is provided. Specifically, the system boots up and enters the BIOS to enable the watchdog function. After entering the sonic system, the main monitoring program initializes the watchdog, and each container initializes the watchdog monitoring process. The watchdog in each container returns a heartbeat flag to determine whether the program is abnormal. If so, the flag level record is checked. If no level record is found, the flag level is set to level one, a log is reported, and a soft reboot is performed. If a level record is found, the flag level is further determined to be level one. If so, the flag level is set to level two, a log is reported, and a hard reboot is performed. If not, the flag level is set to level three, an error log is reported, and the user is requested to conduct an inspection or the manufacturer is requested to provide technical support based on the error log. If the program is determined to be normal, an aging test is performed on the items with level records. If no trigger is triggered after the aging time, the flag level is lowered, and the main monitoring program outputs the watchdog to the BIOS shared library.

[0049] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the watchdog reset method of the present application. More simple transformations based on this technical concept are all within the scope of protection of the present application.

[0050] This application also provides a watchdog reset device, please refer to Figure 4 , the watchdog reset device comprises: The startup module 10 is used to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input and output system layer; A receiving module 20, configured to periodically receive a heartbeat detection flag of the watchdog monitoring process; A determination module 30, configured to determine the operating state of the software unit according to a reception result of the heartbeat detection flag; The reset module 40 is configured to determine a watchdog reset strategy according to the operating state.

[0051] In this embodiment, after the watchdog function is started at the basic input and output system layer, the watchdog monitoring process of the software unit is initialized; the heartbeat detection flag of the watchdog monitoring process is periodically received; the operating status of the software unit is determined based on the reception result of the heartbeat detection flag; and the watchdog reset strategy is determined based on the operating status.

[0052] In summary, this embodiment eliminates the use of a hardware watchdog chip, uses the built-in watchdog function in the hardware daughter board, adopts the shared library file provided by the basic input and output system, operates the input and output signals of the watchdog of the hardware daughter board to perform a hardware watchdog reset on the entire board, and reduces the cost of watchdog reset.

[0053] In one embodiment, the determination module 30 is further configured to determine that the running state of the software unit is normal if the heartbeat detection flag is received; and to determine that the running state of the software unit is faulty if the heartbeat detection flag is not received.

[0054] In one embodiment, the reset module 40 is further configured to obtain a historical error level record of the heartbeat detection flag when the operating state is a fault state; and determine a watchdog reset strategy according to the historical error level record.

[0055] In one embodiment, the reset module 40 is also used to generate an error log and restart the software unit when there is no historical error level record, and modify the historical error level record of the heartbeat detection flag to a first-level record; when the historical error level record is a first-level record, generate an error log and perform a hard restart, and modify the historical error level record of the heartbeat detection flag to a second-level record; when the historical error level record is a second-level record or a third-level record, generate an error log and send a warning message, and determine the historical error level record of the heartbeat detection flag as a third-level record.

[0056] In one embodiment, the reset module 40 is also used to activate the hardware reset circuit through a timeout reset signal, where the timeout reset signal is generated by the basic input and output system layer; transmit the timeout reset signal to all peripheral chipsets; receive a reset completion response returned by the peripheral chipset to complete the hard restart.

[0057] In one embodiment, the reset module 40 is further used to determine the normal operation duration of the software unit based on the operating status; obtain the historical error level record of the software unit; when the normal operation duration is greater than the preset duration, downgrade and update the historical error level record until the historical error level record is empty.

[0058] In one embodiment, the receiving module 20 is further configured to obtain a cyclic redundancy check code of the heartbeat detection flag, where the cyclic redundancy check code is added to the heartbeat detection flag by the basic input / output system layer; and perform a hard restart when an abnormality in the cyclic redundancy check code is detected.

[0059] The watchdog reset device provided in this application, employing the watchdog reset method of the aforementioned embodiment, can address the technical problem of reducing the cost of watchdog resets. Compared to the prior art, the watchdog reset device provided in this application has the same beneficial effects as the watchdog reset method of the aforementioned embodiment. Other technical features of the watchdog reset device are the same as those disclosed in the aforementioned embodiment and are not further described here.

[0060] The present application provides a watchdog reset device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the watchdog reset method in the above-mentioned embodiment 1.

[0061] Reference below Figure 5 , which shows a schematic diagram of the structure of a watchdog reset device suitable for implementing an embodiment of the present application. The watchdog reset device in the embodiment of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), in-vehicle terminals (such as in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5The watchdog reset device shown is merely an example and should not limit the functions and scope of use of the embodiments of the present application.

[0062] like Figure 5 As shown, the watchdog reset device may include a processing device 1001 (e.g., a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in ROM (Read Only Memory) 1002 or programs loaded from storage device 1003 into RAM (Random Access Memory) 1004. RAM 1004 also stores various programs and data required for the operation of the watchdog reset device. Processing device 1001, ROM 1002, and RAM 1004 are interconnected via bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input device 1007, such as a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; output device 1008, such as a liquid crystal display (LCD), speaker, vibrator, etc.; storage device 1003, such as a magnetic tape or hard disk; and communication device 1009. Communication device 1009 can allow the watchdog reset device to communicate with other devices wirelessly or wired to exchange data. Although the figure shows a watchdog reset device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0063] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program comprising program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0064] The watchdog reset device provided in this application, employing the watchdog reset method of the aforementioned embodiment, can solve the technical problem of reducing the cost of watchdog resets. Compared to the prior art, the beneficial effects of the watchdog reset device provided in this application are the same as those of the watchdog reset method provided in the aforementioned embodiment. Other technical features of the watchdog reset device are the same as those disclosed in the aforementioned embodiment and are not further described here.

[0065] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0066] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

[0067] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, a computer program) stored thereon, wherein the computer-readable program instructions are used to execute the watchdog reset method in the above embodiment.

[0068] The computer-readable storage medium provided herein may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems, or devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including, but not limited to, wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0069] The computer-readable storage medium may be included in the watchdog reset device; or may exist independently without being assembled into the watchdog reset device.

[0070] The above-mentioned computer-readable storage medium carries one or more programs. When the above-mentioned one or more programs are executed by the watchdog reset device, the watchdog reset device: after starting the watchdog function at the basic input and output system layer, initializes the watchdog monitoring process of the software unit; periodically receives the heartbeat detection flag of the watchdog monitoring process; determines the operating status of the software unit based on the reception result of the heartbeat detection flag; and determines the watchdog reset strategy based on the operating status.

[0071] Computer program code for performing the operations of the present application may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0072] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, program segment or a part of code, and the module, program segment or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or operation, or can be implemented by a combination of dedicated hardware and computer instructions.

[0073] The modules described in the embodiments of the present application may be implemented in software or hardware, wherein the name of a module does not necessarily limit the unit itself.

[0074] The computer-readable storage medium provided in this application stores computer-readable program instructions (i.e., a computer program) for executing the aforementioned watchdog reset method. This computer-readable storage medium can address the technical problem of reducing the cost of watchdog resets. Compared to the prior art, the beneficial effects of the computer-readable storage medium provided in this application are similar to those of the watchdog reset method provided in the aforementioned embodiments and are not further elaborated here.

[0075] The present application also provides a computer program product, comprising a computer program, which implements the steps of the above-mentioned watchdog reset method when executed by a processor.

[0076] The computer program product provided in this application can solve the technical problem of how to reduce the cost of watchdog reset. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the watchdog reset method provided in the above embodiment, and will not be repeated here.

[0077] The above description is only part of the embodiments of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made by using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A watchdog reset method, characterized in that: The method includes: After the watchdog function is started at the basic input and output system layer, the watchdog monitoring process of the software unit is initialized; Periodically receiving a heartbeat detection flag of the watchdog monitoring process; Determining the operating state of the software unit according to the reception result of the heartbeat detection flag; A watchdog reset strategy is determined according to the operating status.

2. The method according to claim 1, wherein The step of determining the operating state of the software unit according to the reception result of the heartbeat detection flag comprises: If the heartbeat detection flag is received, determining that the running state of the software unit is normal; If the heartbeat detection flag is not received, it is determined that the running state of the software unit is a fault state.

3. The method according to claim 1, wherein The step of determining the watchdog reset strategy according to the operating state comprises: When the operating state is a fault state, obtaining a historical error level record of the heartbeat detection flag; A watchdog reset strategy is determined according to the historical error level record.

4. The method according to claim 3, wherein The step of determining the watchdog reset strategy according to the historical error level record includes: When there is no historical error level record, generating an error log and restarting the software unit, and modifying the historical error level record of the heartbeat detection flag to a level 1 record; When the historical error level record is a level one record, an error log is generated and a hard restart is performed, and the historical error level record of the heartbeat detection flag is modified to a level two record; When the historical error level record is a level 2 record or a level 3 record, an error log is generated and a warning message is sent, and the historical error level record of the heartbeat detection flag is determined to be a level 3 record.

5. The method according to claim 4, wherein The steps of performing a hard restart include: activating a hardware reset circuit via a timeout reset signal, wherein the timeout reset signal is generated by the basic input and output system layer; Transmitting the timeout reset signal to all peripheral chipsets; Receive a reset completion response returned by the peripheral chipset to complete the hard reset.

6. The method according to claim 1, wherein After determining the watchdog reset strategy according to the operating state, the method further includes: determining a normal operation duration of the software unit according to the operation status; Obtaining historical error level records of the software unit; When the normal operation duration is longer than a preset duration, the historical error level record is downgraded and updated until the historical error level record is empty.

7. The method according to claim 1, wherein After the periodic reception of the heartbeat detection flag of the watchdog monitoring process, the method further includes: Obtaining a cyclic redundancy check code of the heartbeat detection flag, where the cyclic redundancy check code is added to the heartbeat detection flag by a basic input / output system layer; When the cyclic redundancy check code is detected to be abnormal, a hard restart is performed.

8. A watchdog reset device, characterized in that: The device comprises: A startup module, configured to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input and output system layer; A receiving module, configured to periodically receive a heartbeat detection flag of the watchdog monitoring process; A determination module, configured to determine the operating state of the software unit according to a reception result of the heartbeat detection flag; The reset module is used to determine the watchdog reset strategy according to the operating state.

9. A watchdog reset device, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the watchdog reset method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the watchdog reset method according to any one of claims 1 to 7 is implemented.

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