Gatekeeper reset method, apparatus, device, and storage medium

Abstract

The application discloses a watchdog reset method and device, equipment and storage medium, and relates to the technical field of signal control and processing. The watchdog reset method comprises the following steps: initializing a watchdog monitoring process of a software unit when starting a watchdog function at a basic input / output system layer; periodically receiving a heartbeat detection flag bit of the watchdog monitoring process; determining a running state of the software unit according to a receiving result of the heartbeat detection flag bit; and determining a watchdog reset strategy according to the running state. The application does not need an independent hardware chip, and thus the cost of the watchdog reset is reduced.

Description

Technical Field

[0001] This application relates to the field of signal control and processing technology, and in particular to a watchdog reset method, apparatus, device, and storage medium. Background Technology

[0002] Watchdog reset is a mechanism used to monitor and ensure system stability, commonly found in embedded systems, microcontrollers, and computer hardware or software design. Currently, a separate hardware watchdog chip is typically used, connected to the main control CPU via a general-purpose input / output interface. Software feeding is performed by inputting a feed pulse from the CPU. However, using a watchdog chip increases material costs and software development costs; therefore, reducing the cost of watchdog reset remains a problem to be solved.

[0003] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main objective of this application is to provide a watchdog reset method, apparatus, device, and storage medium, aiming to solve the technical problem of how to reduce the cost of watchdog reset.

[0005] To achieve the above objectives, this application proposes a watchdog reset method, the method comprising:

[0006] When the watchdog function is started at the basic input / output system layer, the watchdog monitoring process of the software unit is initialized.

[0007] The heartbeat detection flag of the watchdog monitoring process is received periodically;

[0008] The operating status of the software unit is determined based on the received result of the heartbeat detection flag.

[0009] The watchdog reset strategy is determined based on the described operating status.

[0010] In one embodiment, the step of determining the operating state of the software unit based on the received result of the heartbeat detection flag includes:

[0011] If the heartbeat detection flag is received, the operating state of the software unit is determined to be normal.

[0012] If the heartbeat detection flag is not received, the operating state of the software unit is determined to be faulty.

[0013] In one embodiment, the step of determining the watchdog reset strategy based on the operating state includes:

[0014] When the operating state is a fault state, obtain the historical error level record of the heartbeat detection flag bit;

[0015] The watchdog reset strategy is determined based on the historical error level record.

[0016] In one embodiment, the step of determining the watchdog reset strategy based on the historical error level record includes:

[0017] When there is no historical error level record, an error log is generated and the software unit is restarted, and the historical error level record of the heartbeat detection flag is modified to a level 1 record;

[0018] When the historical error level record is a Level 1 record, an error log is generated and a hard reboot is performed, and the historical error level record of the heartbeat detection flag is modified to a Level 2 record;

[0019] When the historical error level record is a level 2 or level 3 record, an error log is generated and a warning message is sent, and the historical error level record of the heartbeat detection flag is determined to be a level 3 record.

[0020] In one embodiment, the step of performing a hard reboot includes:

[0021] The hardware reset circuit is activated by a timeout reset signal, which is generated by the basic input / output system layer.

[0022] The timeout reset signal is transmitted to all peripheral chipsets;

[0023] The system receives a reset completion response from the peripheral chipset and completes a hard reboot.

[0024] In one embodiment, after determining the watchdog reset strategy based on the operating state, the method further includes:

[0025] The normal operating time of the software unit is determined based on the operating status;

[0026] Obtain the historical error level records of the software unit;

[0027] If the normal operation time exceeds the preset time, the historical error level record will be downgraded and updated until the historical error level record is empty.

[0028] In one embodiment, after periodically receiving the heartbeat detection flag of the watchdog monitoring process, the method further includes:

[0029] Obtain the cyclic redundancy check code of the heartbeat detection flag bit, wherein the cyclic redundancy check code is added to the heartbeat detection flag bit by the basic input / output system layer;

[0030] A hard reboot is performed when the cyclic redundancy check code is detected to be abnormal.

[0031] Furthermore, to achieve the above objectives, this application also proposes a watchdog reset device, which includes:

[0032] The startup module is used to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input / output system layer.

[0033] The receiving module is used to periodically receive the heartbeat detection flag of the watchdog monitoring process;

[0034] The determination module is used to determine the operating status of the software unit based on the received result of the heartbeat detection flag bit;

[0035] The reset module is used to determine the watchdog reset strategy based on the operating status.

[0036] In addition, to achieve the above objectives, this application also proposes a watchdog reset device, the device comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the watchdog reset method as described above.

[0037] In addition, to achieve the above objectives, this application also proposes a storage medium, which is a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the steps of the watchdog reset method described above.

[0038] In addition, to achieve the above objectives, this application also provides a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the watchdog reset method described above.

[0039] This application provides a watchdog reset method. After the watchdog function is started at the basic input / output system layer, the watchdog monitoring process of the software unit is initialized; the heartbeat detection flag of the watchdog monitoring process is periodically received; the running state of the software unit is determined according to the receiving result of the heartbeat detection flag; and a watchdog reset strategy is determined according to the running state.

[0040] In summary, this application eliminates the use of a hardware watchdog chip and utilizes the built-in watchdog function in the hardware daughterboard. It employs a shared library file provided by the Basic Input / Output System to operate the watchdog input / output signals of the hardware daughterboard to perform a hardware watchdog reset on the entire board, thereby reducing the cost of watchdog reset. Attached Figure Description

[0041] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 This is a flowchart illustrating an embodiment of the watchdog reset method of this application.

[0044] Figure 2 This is a flowchart illustrating Embodiment 2 of the watchdog reset method of this application;

[0045] Figure 3 This is a simplified flowchart illustrating the watchdog reset method provided in Embodiment 1 of this application.

[0046] Figure 4 This is a schematic diagram of the module structure of the watchdog reset device according to an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the device structure of the hardware operating environment involved in the watchdog reset method in the embodiments of this application.

[0048] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0050] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0051] The main solution of this application is to initialize the watchdog monitoring process of the software unit after starting the watchdog function at the basic input / output system layer; periodically receive the heartbeat detection flag of the watchdog monitoring process; determine the running state of the software unit based on the receiving result of the heartbeat detection flag; and determine the watchdog reset strategy based on the running state.

[0052] Currently, a separate hardware watchdog chip is typically used, connected to the main control CPU via a general-purpose input / output interface. The watchdog is fed via software input pulses from the CPU. However, using a watchdog chip increases both material and software development costs. Therefore, reducing the cost of watchdog resets remains a problem that needs to be solved.

[0053] This application eliminates the use of a hardware watchdog chip and instead uses the built-in watchdog function in the hardware daughterboard. It employs a shared library file provided by the Basic Input / Output System to operate the watchdog input / output signals of the hardware daughterboard to perform a hardware watchdog reset on the entire board, thereby reducing the cost of watchdog reset.

[0054] Based on this, the embodiments of this application provide a watchdog reset method, referring to... Figure 1 , Figure 1 This is a flowchart illustrating the first embodiment of the watchdog reset method of this application.

[0055] In this embodiment, the watchdog reset method includes steps S10 to S40:

[0056] Step S10: After the watchdog function is started at the basic input / output system layer, initialize the watchdog monitoring process of the software unit;

[0057] It should be noted that the executing entity in this embodiment can be a computing service device with data processing, network communication, and program execution functions, such as a tablet computer, personal computer, or mobile phone, or an electronic device or watchdog reset device capable of performing the above functions. The following description uses a watchdog reset device as an example to illustrate this embodiment and the subsequent embodiments.

[0058] It should be noted that the Basic Input Output System (BIOS) is a set of programs embedded in the computer motherboard chip. It is responsible for hardware initialization, self-test, and providing the interface between the underlying hardware and the operating system during startup. It is the first software to run after the computer boots up, providing the most basic hardware control support for the operating system. In this embodiment, the software unit refers to a container. A container is a lightweight virtualization technology used to package an application and all its dependencies (such as runtime environment, libraries, configuration files, etc.) into an independent, portable unit. This embodiment uses shared library files provided by the BIOS to manipulate the watchdog input / output signals of the hardware daughterboard to perform a hardware watchdog reset for the entire board. Therefore, after starting the watchdog function at the BIOS layer, the watchdog monitoring process within the container can be initialized.

[0059] Step S20: Periodically receive the heartbeat detection flag of the watchdog monitoring process;

[0060] Understandably, the heartbeat detection flag represents the running status of the corresponding container. Receiving the heartbeat detection flag indicates that the container's watchdog monitoring process is running normally, while not receiving the heartbeat detection flag indicates that the watchdog monitoring process is abnormal, which means that the container has encountered an abnormality.

[0061] In one feasible approach, after periodically receiving the heartbeat detection flag of the watchdog monitoring process, the method further includes: obtaining the cyclic redundancy check (CRC) code of the heartbeat detection flag, wherein the CRC code is added to the heartbeat detection flag by the basic input / output system layer; and performing a hard reboot when an abnormality of the CRC code is detected.

[0062] It should be noted that the Cyclic Redundancy Check (CRC) uses a Cyclic Time Counting (CTC) mechanism, embedding a count field that changes cyclically at a fixed period in the continuous dog feed pulses. When an abnormality of the CRC is detected, it indicates that there is electromagnetic interference causing pulse distortion or loss, and a hard reboot is performed directly.

[0063] Step S30: Determine the operating status of the software unit based on the received result of the heartbeat detection flag bit;

[0064] Understandably, by checking whether a heartbeat detection flag is received, it is possible to determine whether the watchdog monitoring process of the software unit is running normally, thereby determining the operating status of the software unit.

[0065] In one feasible approach, the step of determining the operating state of the software unit based on the received result of the heartbeat detection flag includes:

[0066] If the heartbeat detection flag is received, the operating state of the software unit is determined to be normal.

[0067] If the heartbeat detection flag is not received, the operating state of the software unit is determined to be faulty.

[0068] Understandably, when the heartbeat detection flag is detected, it indicates that the watchdog monitoring process of the software unit is running normally, thus determining that the operating state of the software unit is normal; when the heartbeat detection flag is not detected, it indicates that the watchdog monitoring process of the software unit is abnormal, thus determining that the operating state of the software unit is faulty.

[0069] Step S40: Determine the watchdog reset strategy based on the operating status.

[0070] Understandably, the watchdog reset strategy can be determined by the operating status. Specifically, when the operating status is in a fault state, a corresponding restart operation is performed, including both soft restart and hard restart. A soft restart only restarts the software unit at the software level, affecting only that single software unit, while other software units can still operate normally. A hard restart, on the other hand, restarts the hardware, in which case all software units will be restarted. Furthermore, if a hard restart is found to be ineffective, an alarm message needs to be generated to notify the administrator for handling.

[0071] In this embodiment, after the watchdog function is started at the basic input / output system layer, the watchdog monitoring process of the software unit is initialized; the heartbeat detection flag of the watchdog monitoring process is periodically received; the running state of the software unit is determined according to the receiving result of the heartbeat detection flag; and the watchdog reset strategy is determined according to the running state.

[0072] In summary, this embodiment eliminates the need for a hardware watchdog chip and utilizes the built-in watchdog function in the hardware daughterboard. It employs a shared library file provided by the Basic Input / Output System to operate the watchdog input / output signals of the hardware daughterboard to perform a hardware watchdog reset on the entire board, thereby reducing the cost of watchdog reset.

[0073] Based on the first embodiment of this application, in the second embodiment of this application, the content that is the same as or similar to that in the first embodiment described above can be referred to the above description, and will not be repeated hereafter. Based on this, please refer to... Figure 2 Step S40 also includes steps S401 to S402:

[0074] Step S401: When the operating state is a fault state, obtain the historical error level record of the heartbeat detection flag bit;

[0075] Understandably, historical error level records are a record of the number of software unit failures; the more failures, the higher the level in the historical error level record. Therefore, when the operating state is a fault state, it is necessary to retrieve the historical error level record to determine whether the software unit is experiencing its first failure or multiple failures, and thus take different countermeasures.

[0076] Step S402: Determine the watchdog reset strategy based on the historical error level record.

[0077] In one feasible approach, the step of determining the watchdog reset strategy based on the historical error level record includes: when there is no historical error level record, generating an error log and restarting the software unit, and modifying the historical error level record of the heartbeat detection flag to a level 1 record; when the historical error level record is a level 1 record, generating an error log and performing a hard reboot, and modifying the historical error level record of the heartbeat detection flag to a level 2 record; when the historical error level record is a level 2 or level 3 record, generating an error log and sending a warning message, and determining the historical error level record of the heartbeat detection flag to a level 3 record.

[0078] It should be noted that the specific steps of a hard reboot are as follows: activating the hardware reset circuit through a timeout reset signal generated by the basic input / output system layer; transmitting the timeout reset signal to all peripheral chipsets; and receiving the reset completion response returned by the peripheral chipsets to complete the hard reboot.

[0079] Understandably, when there is no historical error level record, it indicates that the software unit is experiencing its first failure within a certain period, which may be an intermittent failure. In this case, an error log is generated, the software unit is restarted, and the historical error level record of the heartbeat detection flag is modified to Level 1. When the historical error level record is Level 1, it indicates that a soft reboot has been performed but the failure still occurred. Therefore, an error log needs to be generated, a hard reboot is performed, and the historical error level record of the heartbeat detection flag is modified to Level 2. When the historical error level record is Level 2 or Level 3, it indicates that a reboot cannot resolve the failure. In this case, administrator intervention is required. Therefore, an error log is generated, a warning message is sent, and the administrator handles the issue, setting the historical error level record of the heartbeat detection flag to Level 3.

[0080] In one feasible approach, after determining the watchdog reset strategy based on the operating state, the method further includes: determining the normal operating time of the software unit based on the operating state; obtaining the historical error level record of the software unit; and when the normal operating time exceeds a preset time, downgrading and updating the historical error level record until the historical error level record is empty.

[0081] Understandably, if the process disappears abnormally after a restart, the main monitoring program has aging time records. The flag level can be gradually lowered. The default aging time is 60 minutes, and users can also adjust it according to the actual situation.

[0082] In this embodiment, if the heartbeat detection flag is received, the operating state of the software unit is determined to be normal; if the heartbeat detection flag is not received, the operating state of the software unit is determined to be faulty.

[0083] This embodiment determines the severity of the fault by querying historical error level records, and then selects the corresponding watchdog reset measure to meet the watchdog reset requirements.

[0084] For example, to help understand the implementation process of the watchdog reset method obtained in combination with the above embodiment one, please refer to... Figure 3 , Figure 3 A simplified flowchart of a watchdog reset method is provided. Specifically: The system boots into the BIOS and enables the watchdog function. After entering the sonic system, the main monitoring program initializes the watchdog, and each container initializes its watchdog monitoring process. The watchdog in each container returns a heartbeat flag to determine if the program is abnormal. If abnormal, the flag level record is checked. If no level record is found, the flag level is set to level one, the log is reported, and a soft reboot is performed. If a level record is found, it is checked again to see if it is level one. If so, the flag level is set to level two, the log is reported, and a hard reboot is performed. If not, the flag level is set to level three, an error log is reported, and the user is asked to check, or the original manufacturer is required to provide technical support based on the error log. If the program is determined to be normal, an aging test is performed on items with level records. If the test fails to trigger after the aging time, the flag level is lowered, and the main monitoring program feeds the watchdog with the shared library output from the BIOS.

[0085] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the watchdog reset method of this application. Any simple modifications based on this technical concept are within the protection scope of this application.

[0086] This application also provides a watchdog reset device, please refer to... Figure 4 The watchdog reset device includes:

[0087] Startup module 10 is used to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input / output system layer;

[0088] The receiving module 20 is used to periodically receive the heartbeat detection flag bit of the watchdog monitoring process;

[0089] The determination module 30 is used to determine the operating status of the software unit based on the received result of the heartbeat detection flag bit;

[0090] The reset module 40 is used to determine the watchdog reset strategy based on the operating status.

[0091] In this embodiment, after the watchdog function is started at the basic input / output system layer, the watchdog monitoring process of the software unit is initialized; the heartbeat detection flag of the watchdog monitoring process is periodically received; the running state of the software unit is determined according to the receiving result of the heartbeat detection flag; and the watchdog reset strategy is determined according to the running state.

[0092] In summary, this embodiment eliminates the need for a hardware watchdog chip and utilizes the built-in watchdog function in the hardware daughterboard. It employs a shared library file provided by the Basic Input / Output System to operate the watchdog input / output signals of the hardware daughterboard to perform a hardware watchdog reset on the entire board, thereby reducing the cost of watchdog reset.

[0093] In one embodiment, the determining module 30 is further configured to determine that the operating state of the software unit is normal if the heartbeat detection flag is received, and to determine that the operating state of the software unit is faulty if the heartbeat detection flag is not received.

[0094] In one embodiment, the reset module 40 is further configured to, when the operating state is a fault state, acquire the historical error level record of the heartbeat detection flag bit; and determine the watchdog reset strategy based on the historical error level record.

[0095] In one embodiment, the reset module 40 is further configured to generate an error log and restart the software unit when there is no historical error level record, and modify the historical error level record of the heartbeat detection flag to a level 1 record; when the historical error level record is a level 1 record, generate an error log and perform a hard reboot, and modify the historical error level record of the heartbeat detection flag to a level 2 record; when the historical error level record is a level 2 record or a level 3 record, generate an error log and send a warning message, and determine the historical error level record of the heartbeat detection flag to a level 3 record.

[0096] In one embodiment, the reset module 40 is further configured to activate the hardware reset circuit via a timeout reset signal generated by the basic input / output system layer; transmit the timeout reset signal to all peripheral chipsets; receive a reset completion response returned by the peripheral chipsets, and complete a hard reboot.

[0097] In one embodiment, the reset module 40 is further configured to determine the normal operating time of the software unit based on the operating state; obtain the historical error level record of the software unit; and when the normal operating time exceeds a preset time, downgrade and update the historical error level record until the historical error level record is empty.

[0098] In one embodiment, the receiving module 20 is further configured to obtain the cyclic redundancy check code of the heartbeat detection flag, wherein the cyclic redundancy check code is added to the heartbeat detection flag by the basic input / output system layer; and to perform a hard reboot when an abnormality of the cyclic redundancy check code is detected.

[0099] The watchdog reset device provided in this application, employing the watchdog reset method in the above embodiments, can solve the technical problem of how to reduce the cost of watchdog reset. Compared with the prior art, the beneficial effects of the watchdog reset device provided in this application are the same as those of the watchdog reset method provided in the above embodiments, and other technical features in the watchdog reset device are the same as those disclosed in the methods of the above embodiments, and will not be repeated here.

[0100] This application provides a watchdog reset device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the watchdog reset method in the first embodiment described above.

[0101] The following is for reference. Figure 5 The diagram illustrates a structural schematic suitable for implementing a watchdog reset device according to embodiments of this application. The watchdog reset device in embodiments of this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 5 The watchdog reset device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0102] like Figure 5As shown, the watchdog reset device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.) that can perform various appropriate actions and processes according to a program stored in ROM (Read Only Memory) 1002 or a program loaded from storage device 1003 into RAM (Random Access Memory) 1004. RAM 1004 also stores various programs and data required for the operation of the watchdog reset device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via bus 1005. Input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the watchdog reset device to communicate wirelessly or wiredly with other devices to exchange data. While watchdog reset devices with various systems are shown in the figures, it should be understood that implementation or possession of all the systems shown is not required. More or fewer systems may be implemented alternatively.

[0103] Specifically, according to the embodiments disclosed in this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments disclosed in this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from storage device 1003, or installed from ROM 1002. When the computer program is executed by processing device 1001, it performs the functions defined in the methods of the embodiments disclosed in this application.

[0104] The watchdog reset device provided in this application, employing the watchdog reset method in the above embodiments, can solve the technical problem of how to reduce the cost of watchdog reset. Compared with the prior art, the beneficial effects of the watchdog reset device provided in this application are the same as those of the watchdog reset method provided in the above embodiments, and other technical features in this watchdog reset device are the same as those disclosed in the previous embodiment method, and will not be repeated here.

[0105] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0106] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0107] This application provides a computer-readable storage medium having computer-readable program instructions (i.e., a computer program) stored thereon, the computer-readable program instructions being used to execute the watchdog reset method in the above embodiments.

[0108] The computer-readable storage medium provided in this application may be, for example, a USB flash drive, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, system, or device. The program code contained on the computer-readable storage medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (Radio Frequency), etc., or any suitable combination thereof.

[0109] The aforementioned computer-readable storage medium may be included in the watchdog reset device; or it may exist independently and not assembled into the watchdog reset device.

[0110] The aforementioned computer-readable storage medium carries one or more programs. When the one or more programs are executed by the watchdog reset device, the watchdog reset device: after starting the watchdog function at the basic input / output system layer, initializes the watchdog monitoring process of the software unit; periodically receives the heartbeat detection flag of the watchdog monitoring process; determines the running state of the software unit based on the receiving result of the heartbeat detection flag; and determines the watchdog reset strategy based on the running state.

[0111] Computer program code for performing the operations of this application can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a Local Area Network (LAN) or a Wide Area Network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0112] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0113] The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0114] The readable storage medium provided in this application is a computer-readable storage medium that stores computer-readable program instructions (i.e., a computer program) for executing the above-described watchdog reset method, thereby solving the technical problem of how to reduce the cost of watchdog reset. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided in this application are the same as those of the watchdog reset method provided in the above embodiments, and will not be repeated here.

[0115] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the watchdog reset method described above.

[0116] The computer program product provided in this application solves the technical problem of how to reduce the cost of watchdog reset. Compared with the prior art, the beneficial effects of the computer program product provided in this application are the same as those of the watchdog reset method provided in the above embodiments, and will not be repeated here.

[0117] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the technical concept of this application and using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included in the patent protection scope of this application.

Claims

1. A watchdog reset method, characterized in that, The method includes: When the watchdog function is started at the basic input / output system layer, the watchdog monitoring process of the software unit is initialized. The heartbeat detection flag of the watchdog monitoring process is received periodically; The operating status of the software unit is determined based on the received result of the heartbeat detection flag. Determine the watchdog reset strategy based on the described operating status; The step of determining the watchdog reset strategy based on the operating state includes: When the operating state is a fault state, obtain the historical error level record of the heartbeat detection flag bit; The watchdog reset strategy is determined based on the historical error level record. The step of determining the watchdog reset strategy based on the historical error level record includes: When there is no historical error level record, an error log is generated and the software unit is restarted, and the historical error level record of the heartbeat detection flag is modified to a level 1 record; When the historical error level record is a Level 1 record, an error log is generated and a hard reboot is performed, and the historical error level record of the heartbeat detection flag is modified to a Level 2 record; When the historical error level record is a level 2 or level 3 record, an error log is generated and a warning message is sent, and the historical error level record of the heartbeat detection flag is determined to be a level 3 record. The step of determining the watchdog reset strategy based on the operating state further includes: The normal operating time of the software unit is determined based on the operating status; Obtain the historical error level records of the software unit; If the normal operation time exceeds the preset time, the historical error level record will be downgraded and updated until the historical error level record is empty.

2. The method as described in claim 1, characterized in that, The step of determining the operating status of the software unit based on the received result of the heartbeat detection flag includes: If the heartbeat detection flag is received, the operating state of the software unit is determined to be normal. If the heartbeat detection flag is not received, the operating state of the software unit is determined to be faulty.

3. The method as described in claim 1, characterized in that, The steps for performing a hard reboot include: The hardware reset circuit is activated by a timeout reset signal, which is generated by the basic input / output system layer. The timeout reset signal is transmitted to all peripheral chipsets; The system receives a reset completion response from the peripheral chipset and completes a hard reboot.

4. The method as described in claim 1, characterized in that, After periodically receiving the heartbeat detection flag of the watchdog monitoring process, the method further includes: Obtain the cyclic redundancy check code of the heartbeat detection flag, wherein the cyclic redundancy check code is generated by the basic input / output system layer; A hard reboot is performed when the cyclic redundancy check code is detected to be abnormal.

5. A watchdog reset device, characterized in that, The device includes: The startup module is used to initialize the watchdog monitoring process of the software unit after the watchdog function is started at the basic input / output system layer. The receiving module is used to periodically receive the heartbeat detection flag of the watchdog monitoring process; The determination module is used to determine the operating status of the software unit based on the received result of the heartbeat detection flag bit; The reset module is used to determine the watchdog reset strategy based on the operating status. The step of determining the watchdog reset strategy based on the operating state includes: When the operating state is a fault state, obtain the historical error level record of the heartbeat detection flag bit; The watchdog reset strategy is determined based on the historical error level record. The step of determining the watchdog reset strategy based on the historical error level record includes: When there is no historical error level record, an error log is generated and the software unit is restarted, and the historical error level record of the heartbeat detection flag is modified to a level 1 record; When the historical error level record is a Level 1 record, an error log is generated and a hard reboot is performed, and the historical error level record of the heartbeat detection flag is modified to a Level 2 record; When the historical error level record is a level 2 or level 3 record, an error log is generated and a warning message is sent, and the historical error level record of the heartbeat detection flag is determined to be a level 3 record. The step of determining the watchdog reset strategy based on the operating state further includes: The normal operating time of the software unit is determined based on the operating status; Obtain the historical error level records of the software unit; If the normal operation time exceeds the preset time, the historical error level record will be downgraded and updated until the historical error level record is empty.

6. A watchdog reset device, characterized in that, The device includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the watchdog reset method as described in any one of claims 1 to 4.

7. A storage medium, characterized in that, The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, it implements the watchdog reset method as described in any one of claims 1 to 4.

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