Physical unclonable function generation system and method based on memristor array

Abstract

The invention discloses a physical unclonable function generation system and method based on a memristor array. The system comprises an entropy source module, a delay amplification module, a CRP screening module and a delay judgment module. The entropy source module is used for providing an entropy source and comprises a read-write module, a memristor array and a current multiplexer; the delay amplification module comprises a resistance-voltage mapping module, a current hunger buffer and a path switching unit, the resistance-voltage mapping module converts the resistance value of the memristor into voltage and inputs the voltage into the current hunger buffer, and the current hunger buffer generates an adjustable delay signal according to the voltage; the path switching unit is used for switching a signal propagation path in the delay path according to an input signal; the delay amplification module is used for controlling path exchange times by amplifying a preset configuration signal; the CRP screening module is used for applying programmable delay bias to the delay signal; and the delay judgment module is used for outputting a digital response signal by comparing the time difference of arrival of the two paths of delay signals.

Description

Technical Field

[0001] The present invention relates to the field of information security, and in particular to a system and method for generating a physical unclonable function based on a memristor array. Background Art

[0002] The proliferation of mobile and embedded devices is driving a growing demand for secure device authentication and the protection of private information. Traditional security measures, such as storing keys in non-volatile electrically erasable programmable read-only memory (EEPROM) or battery-backed static random-access memory (SRAM), and using hardware-based cryptographic operations (such as digital signatures or encryption), are costly in terms of design area and power consumption and are vulnerable to invasive attacks. PUFs exploit the physical properties of integrated circuits to derive secret information. These properties include natural variability in the manufacturing process, such as gate delays, SRAM power-up state, and threshold voltage. Due to this manufacturing variability, each IC has unique physical characteristics, enabling PUFs to generate unique "silicon biometrics."

[0003] The Chinese invention patent application with application number 202211413186.4, titled "A Multifunctional PUF Circuit Based on Memristors and Its Use Method," describes a technical solution: This invention adds a shift register circuit and a mode control circuit to an existing memristor-based arbiter PUF circuit, resulting in both PUF and TRNG functions. When used as a PUF, it exhibits excellent performance; when used as a TRNG, it can feed back the output result as an excitation signal applied to the terminals of the delay circuit. The excitation signal can then randomly increase or decrease the resistance of the first and second memristors in each delay unit, thereby generating a randomly varying output signal. Summary of the Invention

[0004] In order to solve the technical problems of high power consumption and vulnerability to invasive attacks in the existing technology, the present invention provides a physical unclonable function generation system and method based on a memristor array, which can continuously generate random signals as key information.

[0005] To achieve the above object, the technical solution adopted by the present invention is: A first aspect of the present invention provides a physical unclonable function generation system based on a memristor array, comprising an entropy source module, a delay amplification module, a CRP screening module, and a delay decision module connected in sequence; The entropy source module is used to provide an entropy source, and the entropy source module includes a read-write module, a memristor array, and a current multiplexer; The delay amplification module includes a resistance-voltage mapping module, a current-starved buffer, and a path switching unit. The resistance-voltage mapping module converts the resistance of the memristor into a voltage and inputs it into the current-starved buffer. The current-starved buffer generates an adjustable delay signal based on the voltage. The path switching unit is used to switch the signal propagation path in the delay path according to the input signal. The delay amplification module is used to control the number of path switches by amplifying a preset configuration signal. The resistance-voltage mapping module includes upper and lower current mirrors and transistors. The CRP screening module is used to apply a programmable delay bias to the delayed signal; The delay decision module includes a D flip-flop, which is used to output a digital response signal by comparing the arrival time difference of two delayed signals.

[0006] As a preferred solution, the read / write module is used to sequentially select individual memristor units in the memristor array module through input signals C0-C41 during the initialization phase, and apply voltage pulses thereto to set the memristor units to a high-resistance state.

[0007] As a preferred solution, the memristor array is used to generate different memristor combinations by inputting signals C0-C41, and to generate current by an external voltage.

[0008] As a preferred solution, the current multiplexer is used to select different parallel paths of memristors according to a selection signal, and distribute the current flowing through the memristors to the upper and lower current mirrors. The input end of the current multiplexer is electrically connected to the output end of the selected memristor combination in the memristor array module.

[0009] As a preferred solution, the memristor array is a matrix structure, comprising: Multiple word lines WL0-WL31 are connected to input signals C0-C31 to enable the memristor; A plurality of bit lines BL0 - BL31 and source lines SL0 - SL31 are connected to the read / write module, and the current multiplexer receives current from the source lines and outputs the current to the resistance-voltage mapping module.

[0010] As a preferred solution, the upper and lower current mirrors are used to receive the memristor current and output the mirror current; the body electrode and source of the transistor are connected to the power supply voltage, the drain is connected to the output end of the current mirror, and its gate voltage is output to the current-starved buffer as a control voltage. The transistor is used to convert the mirror current into a voltage and input it into the current-starved buffer.

[0011] As a preferred solution, the current starving buffer has a multi-stage cascade structure, wherein the output end of each stage of the current starving buffer is connected to the input end of the next stage buffer, forming a cascade structure; each stage of the current starving buffer includes a first-stage inverter and a second-stage inverter; the first-stage inverter includes an NMOS transistor M5, and the second-stage inverter includes an NMOS transistor M6, and the gates of the NMOS transistor M5 and the PMOS transistor M6 are connected to the control voltage in common; The first-stage inverter is used to reverse the input signal and dynamically adjust the gate opening degree of the NMOS tube M5 by controlling the voltage to achieve nonlinear adjustment of the delay; The second-stage inverter is used to invert the output signal of the first-stage inverter and dynamically adjust the gate opening degree of the NMOS tube M6 by controlling the voltage to achieve nonlinear adjustment of the delay; Single-level descent delayed gratification:

[0012] in For a single-stage drop delay, and are the on-resistances of the NMOS transistor M5 and the NMOS transistor M6 respectively.

[0013] As a preferred solution, the CRP screening module includes several buffers BF0-BF2. The CRP screening module implements unstable output screening by configuring signals F0-F1. The buffer delay satisfies:

[0014]

[0015] in Indicates the delay between BF0 and BF2. represents the setup time of the D flip-flop, express The length of the filtering interval.

[0016] A second aspect of the present invention provides a method for generating a physical unclonable function based on a memristor array, the method comprising: At least two memristors in the memristor array are selected by input signals C0-C41; Convert the resistance of the selected memristor into a read current I ᴿᴱᴬᴰ , which is converted into a control voltage V through a transistor after being mirrored by a current mirror. CTL ; Inputting the control voltage into a current starvation buffer to generate two original delay signals corresponding to the nonlinearity of the resistance value; The two original delayed signals are input into the cascaded delay chain, which includes a multi-stage path switching unit; the delay path is dynamically switched according to the configuration signal A0-A18 of the CLK delay amplification path, so that the path delay difference Δ Dᵢ satisfy:

[0017] Where δ is the inherent delay difference between the upper and lower single-stage current starvation buffers; The reliability of the two delayed signals is screened, and the screened two delayed signals are input into the D flip-flop, and the digital response signal is output by comparing the arrival time difference.

[0018] As a preferred solution, the method for reliability screening of two delayed signals includes: (a) Setting the initial magnification to 2x by controlling AFS (b) Execute two responses to the same Challenge signal to obtain the Response: First: Set the screening signals F0 and F1 to 0 and 1 respectively, and move the decision line down to the lower boundary of the unstable decision interval; Second time: Set the screening signals F0 and F1 to 1 and 1 respectively, and move the decision line to the upper boundary of the unstable decision interval; (c) If the two responses are the same, increase the amplification factor by controlling the AFS and repeat step (b) until the maximum amplification factor is reached and the CRP is still the same, then discard the CRP; (d) If any two responses are different, the Challenge, Response, and AFS signals are retained.

[0019] Compared with the prior art, the present invention has the following beneficial effects: The present invention adopts a controllable delay link to accumulate and amplify the resistance difference of the memristor into a delay difference, thereby improving the stability of the PUF unit and expanding the challenge-response pair (CRP) space in the actual PUF. The present invention introduces a low-cost screening strategy. By introducing a delay bias, it filters out possible unstable outputs, making the PUF output stable under different environments and enhancing the robustness of the PUF. The present invention has a built-in reliability self-detection mechanism, which quantifies the reliability level of CRP by the amplification factor of the memristor resistance difference; The circuit structure proposed by the present invention has good symmetry, better stability, and is not easily affected by interference and aging; The present invention nonlinearly maps the resistance value to the delay on the delay chain and performs controllable amplification, thereby realizing the extraction of circuit characteristics; The present invention has an exponential CRP space, and the proposed circuit is a nonlinear system that is not vulnerable to machine learning attacks; In the present invention, the selection of the resistor and the selection of the delay path simultaneously determine the output of the circuit, thereby improving the safety of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the module connections of a physical unclonable function generation system based on a memristor array provided in this embodiment; Figure 2 A schematic diagram of the circuit structure of a physical unclonable function generation system based on a memristor array provided in this embodiment; Figure 3 A schematic diagram of the structure of the memristor array module provided in this embodiment; Figure 4 A schematic diagram of the resistance-voltage mapping module structure provided in this embodiment; Figure 5 A schematic diagram of the structure of a current starvation buffer provided in this embodiment; Figure 6 The path delay difference provided in this embodiment is Statistical distribution graphs; Figure 7 This is a CRP screening flow chart provided in this embodiment. DETAILED DESCRIPTION

[0021] The accompanying drawings are for illustrative purposes only and are not to be construed as limiting the present invention; It should be clear that the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the embodiments of the present application.

[0022] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present application. The singular forms "a," "the," and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0023] When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0024] In addition, in the description of this application, unless otherwise specified, "plurality" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship. The present invention is further described below with reference to the accompanying drawings and examples.

[0025] The present invention is further described below with reference to the accompanying drawings and embodiments.

[0026] Example 1 Please refer to Figure 1 as well as Figure 2 , this embodiment provides a physical unclonable function generation system based on a memristor array, comprising an entropy source module 1, a delay amplification module 2, a CRP screening module 3 and a delay decision module 4 connected in sequence; The entropy source module 1 is used to provide an entropy source, and the entropy source module 1 includes a read-write module, a memristor array, and a current multiplexer; The delay amplification module 2 includes a resistance-voltage mapping module, a current-starved buffer, and a path switching unit. The resistance-voltage mapping module converts the resistance of the memristor into a voltage and inputs it into the current-starved buffer. The current-starved buffer generates an adjustable delay signal according to the voltage. The path switching unit is used to switch the signal propagation path in the delay path according to the input signal. The delay amplification module 2 is used to control the number of path switches by amplifying a preset configuration signal. The resistance-voltage mapping module includes upper and lower current mirrors and transistors. The CRP screening module 3 is used to apply a programmable delay bias to the delay signal; The delay decision module 4 includes a D flip-flop, which is used to output a digital response signal by comparing the arrival time difference between two delayed signals.

[0027] In a specific embodiment, the read / write module is used to sequentially select individual memristor units in the memristor array module through input signals C0-C41 during the initialization phase, and apply voltage pulses thereto to set the memristor units to a high-resistance state.

[0028] In a specific embodiment, the memristor array is used to generate different memristor combinations by inputting signals C0-C41, and to generate current by an external voltage.

[0029] In a specific embodiment, the current multiplexer is used to select different parallel paths of memristors according to a selection signal and distribute the current flowing through the memristors to the upper and lower current mirrors. The input end of the current multiplexer is electrically connected to the output end of the selected memristor combination in the memristor array module.

[0030] In a specific embodiment, please refer to Figure 3 , the memristor array is a matrix structure, comprising: Multiple word lines WL0-WL31 are connected to input signals C0-C31 to enable the memristor; A plurality of bit lines BL0 - BL31 and source lines SL0 - SL31 are connected to the read / write module, and the current multiplexer receives current from the source lines and outputs the current to the resistance-voltage mapping module.

[0031] In a specific embodiment, the upper and lower current mirrors are used to receive the memristor current and output the mirror current; the body electrode and source of the transistor are connected to the power supply voltage, the drain is connected to the output end of the current mirror, and its gate voltage is output to the current-starved buffer as a control voltage, and the transistor is used to convert the mirror current into a voltage and input it into the current-starved buffer.

[0032] In a specific embodiment, please refer to Figure 5 The current starving buffer is a multi-stage cascade structure, wherein the output end of each stage of the current starving buffer is connected to the input end of the next stage buffer to form a cascade structure; each stage of the current starving buffer includes a first-stage inverter and a second-stage inverter; the first-stage inverter includes an NMOS transistor M5, and the second-stage inverter includes an NMOS transistor M6, and the gates of the MOS transistor M5 and the PMOS transistor M6 are connected to the control voltage in common; The first-stage inverter is used to reverse the input signal and dynamically adjust the gate opening degree of the NMOS tube M5 by controlling the voltage to achieve nonlinear adjustment of the delay; The second-stage inverter is used to invert the output signal of the first-stage inverter and dynamically adjust the gate opening degree of the NMOS tube M6 by controlling the voltage to achieve nonlinear adjustment of the delay; Single-level descent delayed gratification:

[0033] in For a single-stage drop delay, and are the on-resistances of the NMOS transistor M5 and the NMOS transistor M6 respectively.

[0034] In a specific embodiment, the CRP screening module 3 includes several buffers BF0-BF2. The CRP screening module implements unstable output screening by configuring signals F0-F1. The buffer delay satisfies:

[0035]

[0036] in Indicates the delay between BF0 and BF2. represents the setup time of the D flip-flop, express The length of the filtering interval.

[0037] Example 2 Please refer to Figure 1 as well as Figure 2 This embodiment can be regarded as an improvement or extension of the embodiment 1, specifically: A physical unclonable function generation system based on a memristor array comprises an entropy source module 1, a delay amplification module 2, a CRP screening module 3 and a delay judgment module 4 connected in sequence; The entropy source module 1 is used to provide an entropy source, and the entropy source module 1 includes a read-write module, a memristor array, and a current multiplexer; The delay amplification module 2 includes a resistance-voltage mapping module, a current-starved buffer, and a path switching unit. The resistance-voltage mapping module converts the resistance of the memristor into a voltage and inputs it into the current-starved buffer. The current-starved buffer generates an adjustable delay signal according to the voltage. The path switching unit is used to switch the signal propagation path in the delay path according to the input signal. The delay amplification module 2 is used to control the number of path switches through a preset configuration signal to amplify the delay difference between the upper and lower signals. The resistance-voltage mapping module includes upper and lower current mirrors and transistors. The CRP screening module 3 is used to apply a programmable delay bias to the delay signal; The delay decision module 4 includes a D flip-flop, which is used to output a digital response signal by comparing the arrival time difference between two delayed signals.

[0038] Please refer to Figure 2 ,in: Module0: Entropy source module, consisting of R / W Module, RRAM Array, Current Mux, provides entropy source for PUF.

[0039] Module 1: Delay amplifier module, consisting of 40 SC buffers, 19 switch blocks, and two RVMs. Every two SC buffers and a switch block form a stage, and the last two SC buffers form a stage, for a total of 20 stages in cascade forming a delay chain.

[0040] Module 2: CRP screening module, consisting of two switch blocks and three buffers. It screens unstable CRP.

[0041] Module 3: Delay difference judgment module, composed of a D trigger, outputs a digital signal according to the delay difference between the two delayed signals in the delay path.

[0042] R / W Module: Read / write module of the memristor array.

[0043] Current Mux: Current multiplexer, which realizes the function of selecting 2 from 32.

[0044] CLK: Delay signal used for delay circuit.

[0045] SC Buffer: Used to generate different delays in the delay circuit according to the input voltage.

[0046] RVM: Please refer to Figure 4 The resistance-voltage mapping module multiplies the input current by a certain factor and then converts it into a voltage output through a transistor. This allows different resistance values ​​to be converted into voltage values.

[0047] BF0-BF2: Used to generate a certain delay to achieve self-detection and filter output functions.

[0048] Switch Block: Used to swap signals in the delay path based on the input signal.

[0049] C0-C41: Circuit input, PUF challenge signal, used to select the memristors in the memristor array.

[0050] A0-A18: Configuration signal of CLK delay amplification path (Amplification Control Signal, ACS).

[0051] F0, F1: Filter Control Signal (FCS) of the filter module, which configures different delay offsets for the two signals output by the delay path to implement the filtering function.

[0052] D flip-flop: determines the speed of the signal in the delay circuit and generates output at the Q terminal.

[0053] RRAM Array: Memristor array: provides different resistance options. The structure is as follows Figure 3 As shown, BL0-BL31, SL0-SL31 are connected to the R / W Module, SL0-SL31 are connected to the Current Mux, and WL0-WL31 are connected to C0-C31.

[0054] Example 3 This embodiment provides a method for generating a physical unclonable function based on a memristor array, the method comprising: At least two memristors in the memristor array are selected by input signals C0-C41; Please refer to Figure 4 , converting the resistance of the selected memristor into a read current I ᴿᴱᴬᴰ , which is converted into a control voltage V through a transistor after being mirrored by a current mirror. CTL ; Inputting the control voltage into a current starvation buffer to generate two original delay signals corresponding to the nonlinearity of the resistance value; The two original delayed signals are input into the cascaded delay chain, which includes a multi-stage path switching unit; the delay path is dynamically switched according to the configuration signal A0-A18 of the CLK delay amplification path, so that the path delay difference Δ Dᵢ satisfy:

[0055] Where δ is the inherent delay difference between the upper and lower single-stage current starvation buffers; The two delayed signals are screened for reliability, and the screened two delayed signals are input into a D flip-flop, which outputs a digital response signal by comparing the arrival time difference; In a specific embodiment, the method for performing reliability screening on two delayed signals includes: (a) Setting the initial magnification to 2x by controlling AFS (b) Execute two responses to the same Challenge signal to obtain the Response: First: Set the screening signals F0 and F1 to 0 and 1 respectively, and move the decision line down to the lower boundary of the unstable decision interval; Second time: Set the screening signals F0 and F1 to 1 and 1 respectively, and move the decision line to the upper boundary of the unstable decision interval; (c) If the two responses are the same, increase the amplification factor by controlling the AFS and repeat step (b) until the maximum amplification factor is reached and the CRP is still the same, then discard the CRP; (d) If any two responses are different, the Challenge, Response, and AFS signals are retained.

[0056] Specifically, during the initialization phase, by setting all C0-C31 to 1, the R / W Module performs a RESET operation on the RRAM array through BL and SL, setting all RRAMs in the array to a high-resistance state (HRS).

[0057] In the input stage, input is applied to C0-C41, A0-A18, F0-F1 of the PUF security circuit, such as Figure 3 As shown, the input controls the opening or closing of the transistor gate in the memristor array to select different memristor combinations. The selected resistor will be applied with voltage by the read / write module, and the generated current I READ The current is input to the upper and lower current mirrors through the current multiplexer. The output of the current mirror is then connected to a transistor to convert the output of the current mirror into a voltage. The structure is as follows Figure 4 shown.

[0058] This voltage value is applied to the current hungry buffer, Figure 5 V in CTL The magnitude of the applied voltage affects the delay of the current-starved buffer, V CTL The larger the value, the smaller the on-resistance of M5 and M6. When the on-resistance of M5 is When , the falling delay of the first-stage inverter is:

[0059] The second stage inverter is similar. CTL , realizing the adjustment of the falling delay of the single-stage inverter, thereby realizing the delay adjustment of the delay unit. The gate voltage of M6 and M5 are connected together to keep the rising delay and the falling delay the same to prevent the pulse from being shortened in the delay chain.

[0060] pass Figure 4 and Figure 5 The structure shown converts the resistance of the memristor in the circuit into the delay of the circuit.

[0061] exist Figure 2 In the delay circuit, the inputs A0-A18 determine the number of times the signal switches as it propagates along the delay path.

[0062] For stage i, represents the intrinsic delay difference per stage resulting from the resistance variation of the selected RRAM combination, is the input applied to the delay circuit. Then the difference in total delay at the end of the circuit is for:

[0063] Where δ is the inherent delay difference between the upper and lower single-stage current starvation buffers; During the response phase, the delay circuit is connected to a D-type flip-flop to determine the arrival speed of the two delayed signals. When the D-terminal signal arrives first, the Q-terminal output is 1. When the CLK-terminal signal arrives first, the Q-terminal output is 0. The output of 0 or 1 represents the resistance characteristics of some memristors in the circuit. A 42-bit challenge input results in a 1-bit output.

[0064] During the screening phase, CRPs and their ACS data need to be entered into a database. Under standard working conditions, for RDMPUF, challenges are randomly generated, each challenge is screened, and the minimum magnification factor that allows the challenge to pass the screening is found. The corresponding CRP and ACS data are then entered into the database.

[0065] This design is passed Figure 2 In the example, BF0-BF2 applies a delay bias to the signal output from the delay path, simulating the upper and lower boundaries of the delay difference ΔD between the two input signals of the D-type flip-flop and the CLK terminal when unstable output occurs. After the rising edge of the delayed signal arrives at the CLK terminal of the D-type flip-flop, the D-type flip-flop will determine the output based on the size of ΔD. The dividing line between 0 and 1 is the Arbite Line (AL). Figure 6 As shown, when ΔD is in the red area, the D flip-flop produces an unstable output.

[0066] Design the delay size of BF0-BF2 to meet the relationship:

[0067]

[0068] in Indicates the delay between BF0 and BF2. represents the setup time of the D flip-flop, express The length of the filtering interval.

[0069] The specific screening steps are to set the ACS amplification factor to 2 and let the PUF respond twice. In the first response, F0 and F1 are set to 01, and the CLK end of the D flip-flop is additionally delayed by Tsetup + Tfilter, which is equivalent to setting AL to the lower limit of the fluctuation ( Figure 6 The lower boundary of the shaded part in the middle), in the second response, F0, F1 are set to 11, which is equivalent to setting AL to the upper boundary of the fluctuation ( Figure 6 The upper boundary of the shaded part in the middle). If the results of the two responses are the same, the ACS amplification factor is increased by one level, and the above two responses are repeated until the ACS amplification factor is set to the maximum. If it still fails to pass the screening, the Challenge is discarded. If they are not the same, the corresponding CRP is retained. In this way, the unstable output of the PUF is screened out, and the minimum amplification factor corresponding to each Challenge is found. The size of the amplification factor represents the reliability level of the CRP. The smaller the amplification factor required to pass the screening, the higher the reliability level of the CRP. Different amplification factors are represented by ACS in the database, which quantifies the reliability level of each CRP. The screening process is as follows Figure 7 shown.

[0070] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A physical unclonable function generation system based on a memristor array, characterized in that: It includes an entropy source module (1), a delay amplification module (2), a CRP screening module (3) and a delay judgment module (4) connected in sequence; The entropy source module (1) is used to provide an entropy source, and the entropy source module (1) includes a read / write module, a memristor array, and a current multiplexer; The delay amplification module (2) includes a resistance-voltage mapping module, a current hungry buffer and a path switching unit. The resistance-voltage mapping module converts the resistance of the memristor into a voltage and inputs the voltage into the current hungry buffer. The current hungry buffer generates an adjustable delay signal according to the voltage. The path switching unit is used to switch the signal propagation path in the delay path according to the input signal. The delay amplification module (2) is used to control the number of path exchanges through a preset configuration signal to amplify the delay difference between the upper and lower signals. The resistance-voltage mapping module includes upper and lower current mirrors and transistors. The CRP screening module (3) is used to apply a programmable delay bias to the delay signal; The delay decision module (4) comprises a D trigger, which is used to output a digital response signal by comparing the arrival time difference of two delayed signals.

2. A physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The read / write module is used to sequentially select individual memristor units in the memristor array module through input signals C0-C41 during the initialization phase, and apply voltage pulses thereto to set the memristor units to a high-resistance state.

3. A physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The memristor array is used to generate different memristor combinations by inputting signals C0-C41, and to generate current by an external voltage.

4. A physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The current multiplexer is used to select different parallel paths of memristors according to the selection signal and distribute the current flowing through the memristors to the upper and lower current mirrors. The input end of the current multiplexer is electrically connected to the output end of the selected memristor combination in the memristor array module.

5. The physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The memristor array is a matrix structure, comprising: Multiple word lines WL0-WL31 are connected to input signals C0-C31 to enable the memristor; A plurality of bit lines BL0 - BL31 and source lines SL0 - SL31 are connected to the read / write module, and the current multiplexer receives current from the source lines and outputs the current to the resistance-voltage mapping module.

6. The physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The upper and lower current mirrors are used to receive the memristor current and output the mirror current; the body electrode and source of the transistor are connected to the power supply voltage, the drain is connected to the output end of the current mirror, and its gate voltage is output to the current-starved buffer as a control voltage. The transistor is used to convert the mirror current into a voltage and input it into the current-starved buffer.

7. The physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The current starving buffer is a multi-stage cascade structure, wherein the output end of each stage current starving buffer is connected to the input end of the next stage buffer to form a cascade structure; each stage current starving buffer includes a first-stage inverter and a second-stage inverter; the first-stage inverter includes an NMOS transistor M5, and the second-stage inverter includes an NMOS transistor M6, and the gates of the NMOS transistor M5 and the PMOS transistor M6 are connected to the control voltage in common; The first-stage inverter is used to reverse the input signal and dynamically adjust the gate opening degree of the NMOS tube M5 by controlling the voltage to achieve nonlinear adjustment of the delay; The second-stage inverter is used to invert the output signal of the first-stage inverter and dynamically adjust the gate opening degree of the NMOS tube M6 by controlling the voltage to achieve nonlinear adjustment of the delay; Single-level descent delayed gratification: in For a single-stage drop delay, and are the on-resistances of the NMOS transistor M5 and the NMOS transistor M6 respectively.

8. The physical unclonable function generation system based on a memristor array according to claim 1, characterized in that: The CRP screening module (3) includes several buffers BF0-BF2. The CRP screening module implements unstable output screening by configuring signals F0-F1. The buffer delay satisfies: in Indicates the delay between BF0 and BF2. represents the setup time of the D flip-flop, express The length of the filtering interval.

9. A method for generating a physical unclonable function based on a memristor array, characterized in that: The method comprises: At least two memristors in the memristor array are selected by input signals C0-C41; Convert the resistance of the selected memristor into a read current I ᴿᴱᴬᴰ , which is converted into a control voltage V through a transistor after being mirrored by a current mirror. CTL ; Inputting the control voltage into a current starvation buffer to generate two original delay signals corresponding to the nonlinearity of the resistance value; The two original delayed signals are input into the cascaded delay chain, which includes a multi-stage path switching unit; the delay path is dynamically switched according to the configuration signal A0-A18 of the CLK delay amplification path, so that the path delay difference Δ Dᵢ satisfy: Where δ is the inherent delay difference between the upper and lower single-stage current starvation buffers; The reliability of the two delayed signals is screened, and the screened two delayed signals are input into the D flip-flop, and the digital response signal is output by comparing the arrival time difference.

10. The method for generating a physical unclonable function based on a memristor array according to claim 1, characterized in that: Methods for reliability screening of two-path delayed signals include: (a) Setting the initial magnification to 2x by controlling AFS (b) Execute two responses to the same Challenge signal to obtain the Response: First: Set the screening signals F0 and F1 to 0 and 1 respectively, and move the decision line down to the lower boundary of the unstable decision interval; Second time: Set the screening signals F0 and F1 to 1 and 1 respectively, and move the decision line to the upper boundary of the unstable decision interval; (c) If the two responses are the same, increase the amplification factor by controlling the AFS and repeat step (b) until the maximum amplification factor is reached and the CRP is still the same, then discard the CRP; (d) If any two responses are different, the Challenge, Response, and AFS signals are retained.

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