Acceleration server system used in fields of cloud computing and AI

Abstract

The invention discloses an acceleration server system for the field of cloud computing and AI, which relates to the technical field of computer servers and comprises a server mainboard and an accelerator unit connected with the server mainboard. By integrating parallel computing units and optimizing resource scheduling, the computing performance is remarkably improved; the FPGA technology is adopted, and different calculation requirements are met; the intelligent cooling and power consumption management technology is adopted, and the unit operation cost is reduced; the modular design supports flexible expansion, and the calculation requirements of different scales are met; the multi-level cache and the efficient interconnection interface ensure low delay of data access and transmission; by integrating a calculation core module, a programmable logic module, a cache module, an interconnection interface module, an intelligent scheduling module and a cooling and energy consumption management module, the calculation performance, the flexibility and the energy efficiency ratio are remarkably improved; the acceleration unit can be widely applied to the fields of cloud computing, artificial intelligence, big data analysis, high-performance computing, edge computing and the like.

Description

Technical Field

[0001] The present invention relates to the field of computer server technology, and in particular to an acceleration server system for use in cloud computing and AI fields. Background Art

[0002] With the rapid development of cloud computing and artificial intelligence technologies, the demand for computing resources is growing exponentially. Traditional server architectures suffer from low computing efficiency, high energy consumption, and poor scalability when processing large-scale data and complex AI models. While existing acceleration technologies (such as GPUs and TPUs) can improve computing performance, there is still significant room for improvement in resource scheduling, energy efficiency, and system integration.

[0003] With the rapid development of cloud computing and AI technologies, traditional server systems are facing performance bottlenecks when processing large-scale data and complex computing tasks. Existing server systems typically use general-purpose processors (CPUs) for computing. However, when processing AI tasks such as deep learning and machine learning, CPUs have low computational efficiency and cannot meet the real-time and high-throughput requirements. While accelerators such as GPUs (graphics processing units) and TPUs (tensor processing units) have improved computing performance to a certain extent, their integration and optimization with server systems remain insufficient, leading to problems such as low resource utilization, high energy consumption, and poor scalability.

[0004] The rapid development of cloud computing and artificial intelligence technologies has placed higher demands on computing performance. Traditional CPUs face performance bottlenecks when processing large amounts of data and complex computing tasks. While accelerators such as GPUs and TPUs can improve performance, their integration, energy efficiency, and flexibility remain limited. Furthermore, existing acceleration units perform poorly in multi-task parallel processing, real-time computing, and edge computing scenarios. Therefore, there is an urgent need for efficient, flexible, and low-power acceleration units to meet the demands of cloud computing and AI. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an acceleration server system for cloud computing and AI fields in response to the shortcomings of the background technology. By optimizing the hardware architecture and resource scheduling mechanism, the data processing efficiency and computing performance can be significantly improved, while reducing energy consumption and costs.

[0006] The present invention adopts the following technical solutions to solve the above technical problems:

[0007] An acceleration server system for cloud computing and AI fields, comprising a server mainboard and an accelerator unit connected to the server mainboard; the server mainboard comprises a processor unit, a distributed storage unit, a first storage module, a USB interface module, a serial port module, a clock module, a heat dissipation module, a communication module, and a power management module; the distributed storage unit, first storage module, USB interface module, serial port module, clock module, heat dissipation module, communication module, and power management module are respectively connected to the processor unit; the accelerator unit comprises an acceleration control unit, a programmable logic module, a cache unit, an interconnection interface module, an intelligent scheduling module, a temperature monitoring unit, and a power chip; the acceleration control unit is connected to the temperature monitoring unit, the temperature monitoring unit is connected to the programmable logic module, and the cache unit, interconnection interface module, intelligent scheduling module, and power chip are respectively connected to the programmable logic module.

[0008] As a further preferred embodiment of an acceleration server system for cloud computing and AI fields of the present invention, the processor unit includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a data reading unit, and a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit and a configuration SPI Flash circuit. The AD acquisition control unit is connected to the data processing and RAM read-write module unit, and the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the data reading unit, and the power supply circuit, the reset circuit, the crystal oscillator circuit, the download circuit and the configuration SPI Flash circuit are respectively connected to the data processing and RAM read-write module unit.

[0009] As a further preferred solution of the present invention for an acceleration server system in the field of cloud computing and AI, the programmable logic module includes a temperature reading module, a second storage module and an operation module; the temperature reading module is connected to the temperature monitoring chip; the second storage module is connected to the temperature reading module; the temperature reading module is connected to the operation module; the temperature reading module is used to read the temperature information of the acceleration unit and send it to the second storage module for storage; the operation module is connected to the power chip, and controls the power chip and the acceleration chip to be connected or disconnected according to the temperature information of the acceleration unit.

[0010] As a further preferred solution of the present invention for an acceleration server system used in the fields of cloud computing and AI, the acceleration unit integrates a GPU, TPU or FPGA dedicated accelerator for efficiently processing AI and deep learning tasks; the intelligent scheduling module dynamically allocates computing resources based on machine learning algorithms to optimize task execution efficiency.

[0011] As a further preferred embodiment of an acceleration server system for cloud computing and AI fields of the present invention, the communication module adopts a radio frequency switch circuit with a series-parallel structure, and the radio frequency switch circuit includes a radio frequency RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a radio frequency ANT terminal, a voltage VCTRL terminal, and a voltage VCTRI terminal.

[0012] The radio frequency RF end is respectively connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4. The other end of the fifth resistor R5 is respectively connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3. The other end of the third resistor R3 is respectively connected to the source of the second NMOS transistor Q2 of the first NMOS transistor Q1, the drain of the first NMOS transistor Q1, and one end of the first resistor R1. The other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and is grounded. The base of the first NMOS transistor Q1 is connected to the substrate of the first NMOS transistor Q1. The anode of the first diode is connected, the cathode of the first diode is respectively connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2, the other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the voltage terminal VCTRI, one end of the sixth resistor R6 and the other end of the fourth resistor R4 are respectively connected to the gate of the second NMOS transistor Q2 and the cathode of the second diode D2, the anode of the second diode D2 is connected to the base of the second NMOS transistor Q2; the other end of the sixth resistor R4 is respectively connected to the gate of the third NMOS transistor Q3 and the cathode of the third diode D3, and the anode of the third diode D3 is connected to the base of the third NMOS transistor Q3;

[0013] The gate of the fourth NMOS transistor Q4 is respectively connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is respectively connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and one end of the ninth resistor R9. The gate of the fifth NMOS transistor Q5 is respectively connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is respectively connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is respectively connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage terminal VCTRL. The source of the sixth NMOS transistor Q6 is respectively connected to the other end of the eleventh resistor R11 and the radio frequency ANT terminal.

[0014] As a further preferred solution of the present invention for an acceleration server system in the field of cloud computing and AI, the power management module includes a mains power module, a charging control module, and a rechargeable battery. The mains power module is connected to the processor unit, and the mains power module is connected to the processor unit in turn through the charging control module and the rechargeable battery.

[0015] As a further preferred solution of the acceleration server system for cloud computing and AI fields of the present invention, the charging control module includes a charging control circuit, a charging controller, an overcurrent protection circuit, a demodulation module, a full-bridge driver, and a voltage regulation module. The charging control circuit and the overcurrent protection circuit are respectively connected to the charging controller, and the charging controller is respectively connected to the full-bridge driver through the demodulation module and the voltage regulation module.

[0016] Wherein, the charging control circuit is connected to the rechargeable battery and is used for charging control of the rechargeable battery;

[0017] Overcurrent protection circuit, used for overcurrent protection during charging control of rechargeable batteries;

[0018] The voltage regulating module is connected to the full-bridge driver and is used to achieve automatic voltage regulation through the feedback pin;

[0019] The demodulation module is connected to the full-bridge driver and is used to transmit the demodulated data to the charging controller for processing;

[0020] The charging controller is connected to the voltage regulation module and the demodulation module respectively, and is used to control the voltage regulation accuracy and voltage regulation range of the voltage regulation module, and promptly process the received power request feedback from the demodulation module, and output a control signal to the voltage regulation module according to the demand, thereby realizing multi-speed voltage precision regulation.

[0021] As a further preferred solution of an acceleration server system for cloud computing and AI fields of the present invention, the demodulation module includes a voltage input VIN terminal, a resistor R1, a resistor R2, a resistor R3, a resistor R7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, an inductor L1, a chip FR9885, a voltage output VDCDC terminal, and a voltage output Vcontrol terminal; the voltage input VIN terminal is respectively connected to one end of the capacitor C1, one end of the capacitor C2 and the VIN terminal of the chip FR9885, the other end of the capacitor C1 is respectively connected to the other end of the capacitor C2, one end of the capacitor C3 and the GND terminal of the chip FR9885 and grounded, the other end of the capacitor C3 is connected to one end of the resistor R1, and the resistor R The other end of 1 is connected to the SHDN terminal of chip FR9885, the BST terminal of chip FR9885 is connected to one end of capacitor C9, the other end of capacitor C9 is respectively connected to the LX terminal of chip FR9885 and one end of inductor L1, the other end of inductor L1 is respectively connected to one end of resistor R2, one end of capacitor C5, one end of capacitor C6, one end of capacitor C7, one end of capacitor C8 and the voltage output VDCDC terminal, the other end of capacitor C5 is respectively connected to the other end of resistor R2, one end of resistor R3, one end of resistor R7 and the FB terminal of chip FR9885, the other end of resistor R7 is connected to the voltage output Vcontrol terminal, the other end of resistor R3 is grounded, and the other end of capacitor C6 is respectively connected to the other end of capacitor C7 and the other end of capacitor C8 and to ground.

[0022] As a further preferred embodiment of an acceleration server system for cloud computing and AI fields according to the present invention, the charging control circuit includes a signal control terminal, a charging power supply terminal, a device power supply terminal, a battery terminal, a transistor, a first MOS transistor, and a second MOS transistor; wherein the charging power supply terminal is grounded through a first resistor and a second resistor connected in series; the base of the transistor is respectively connected to the signal control terminal and the charging power supply terminal, the collector of the transistor is connected to the gate of the second MOS transistor through a fourth resistor, and is also connected to the source of the first MOS transistor through a third resistor, and the emitter of the transistor is grounded; the source of the second MOS transistor is connected to the charging power supply terminal through a first diode, and the drain is connected to the device power supply terminal; the source of the first MOS transistor is connected to the charging power supply terminal through a first diode, the gate is connected to the connection point of the first resistor and the second resistor, and the drain is connected to the battery terminal.

[0023] As a further preferred embodiment of an acceleration server system for cloud computing and AI fields of the present invention, the crystal oscillator circuit includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC terminal. The 8-interface of the control chip 7N10.000MBP is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C45, the 9-interface of the control chip 7N10.000MBP, one end of the resistor R23 and the voltage VCC terminal. The other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is grounded. The 10-interface of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded.

[0024] Compared with the prior art, the present invention adopts the above technical solution and has the following technical effects:

[0025] The present invention discloses an acceleration server system for cloud computing and AI fields, comprising a server mainboard and an accelerator unit connected to the server mainboard; the server mainboard comprises a processor unit, a distributed storage unit, a first storage module, a USB interface module, a serial port module, a clock module, a heat dissipation module, a communication module, and a power management module; the accelerator unit comprises an acceleration control unit, a programmable logic module, a cache unit, an interconnection interface module, an intelligent scheduling module, a temperature monitoring unit, and a power chip; the present invention significantly improves computing performance by integrating parallel computing units and optimizing resource scheduling; adopts FPGA technology to support dynamic reconstruction of hardware logic to adapt to different computing requirements; adopts intelligent cooling and power management technology to reduce unit operating costs; modular design supports flexible expansion to meet computing requirements of different scales; multi-level cache and efficient interconnection interfaces ensure low latency in data access and transmission; by integrating computing core modules, programmable logic modules, cache modules, interconnection interface modules, intelligent scheduling modules, and cooling and energy consumption management modules, computing performance, flexibility, and energy efficiency are significantly improved; the acceleration unit can be widely used in cloud computing, artificial intelligence, big data analysis, high-performance computing, edge computing, and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the structure of an acceleration server system for cloud computing and AI fields according to the present invention;

[0027] Figure 2 It is a structural principle diagram of the server motherboard of the present invention;

[0028] Figure 3 It is a structural principle diagram of the accelerator unit of the present invention;

[0029] Figure 4It is a structural principle diagram of the processor unit of the present invention;

[0030] Figure 5 It is a structural principle diagram of the programmable logic module of the present invention;

[0031] Figure 6 is a circuit diagram of the communication module of the present invention;

[0032] Figure 7 It is a structural principle diagram of the power management module of the present invention;

[0033] Figure 8 This is a schematic diagram of the structure of the charging control module of the present invention;

[0034] Figure 9 is a circuit diagram of a demodulation module of the present invention;

[0035] Figure 10 is a circuit diagram of a charging control circuit of the present invention;

[0036] Figure 11 It is a circuit diagram of the crystal oscillator circuit of the present invention. DETAILED DESCRIPTION

[0037] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings:

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0039] An acceleration server system for cloud computing and AI fields, such as Figure 1 As shown, the system includes a server motherboard and an accelerator unit connected to the server motherboard. During high-speed operation, the accelerator chip generates a large amount of heat due to the high computational workload and power consumption, causing the accelerator chip to overheat. However, the accelerator unit itself lacks heat dissipation, preventing it from dissipating the heat. The accelerator unit also lacks overtemperature protection, preventing the accelerator chip from shutting down when the temperature rises. This can cause the accelerator chip to burn out and damage the accelerator unit.

[0040] In the fields of cloud computing and artificial intelligence (AI), accelerators are hardware components specifically designed to efficiently handle compute-intensive tasks. They significantly improve computing performance through parallel computing and specialized architectures, particularly in scenarios such as deep learning, machine learning, big data analytics, and high-performance computing (HPC).

[0041] like Figure 2 As shown, the server motherboard includes a processor unit, a distributed storage unit, a first storage module, a USB interface module, a serial port module, a clock module, a heat dissipation module, a communication module, and a power management module; the distributed storage unit, the first storage module, the USB interface module, the serial port module, the clock module, the heat dissipation module, the communication module, and the power management module are respectively connected to the processor unit;

[0042] like Figure 3 As shown, the accelerator unit includes an acceleration control unit, a programmable logic module, a cache unit, an interconnection interface module, an intelligent scheduling module, a temperature monitoring unit and a power chip; the acceleration control unit is connected to the temperature monitoring unit, the temperature monitoring unit is connected to the programmable logic module, and the cache unit, the interconnection interface module, the intelligent scheduling module and the power chip are respectively connected to the programmable logic module.

[0043] High performance: Computing performance is significantly improved by integrating parallel computing units and optimizing resource scheduling.

[0044] High flexibility: Using FPGA technology, it supports dynamic reconstruction of hardware logic to adapt to different computing needs.

[0045] Low energy consumption: Adopts intelligent cooling and power management technologies to reduce unit operating costs.

[0046] High scalability: Modular design supports flexible expansion to meet computing needs of different scales.

[0047] Low latency: Multi-level cache and efficient interconnect interfaces ensure low latency in data access and transmission.

[0048] By integrating a computing core module, a programmable logic module, a cache module, an interconnect interface module, an intelligent scheduling module, and a cooling and energy management module, the present invention significantly improves computing performance, flexibility, and energy efficiency. This acceleration unit can be widely used in cloud computing, artificial intelligence, big data analysis, high-performance computing, and edge computing.

[0049] like Figure 4As shown, the processor unit includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command de-framing unit, a FIFO data cache unit, a data reading unit, as well as a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit and a configuration SPI Flash circuit. The AD acquisition control unit is connected to the data processing and RAM read-write module unit, and the port control unit, the synchronous clock control unit, the command de-framing unit, the FIFO data cache unit, the data reading unit, as well as the power supply circuit, the reset circuit, the crystal oscillator circuit, the download circuit and the configuration SPI Flash circuit are respectively connected to the data processing and RAM read-write module unit.

[0050] The present invention adopts Xilinx's Spartan6 series FPGA as the core control device, realizes the functions of data acquisition control, data caching, data processing, data storage, data transmission and synchronous clock control, and has the characteristics of high precision, fast speed, good reliability, strong real-time performance and low cost. The present invention uses FPGA as the main processor of the 16-channel real-time, high-speed and high-precision synchronous data acquisition system. The sampling frequency in the actual monitoring project is 200kHz. The FPGA is used to reasonably control and coordinate the transmission of data streams between various modules, thereby realizing the real-time, synchronous and high-speed acquisition functions required by the system.

[0051] The system's core control chip is the Xilinx Spartan 6 series chip, the XC6SLX45. Built on the recognized low-power 45nm, 9-metal copper layer, dual-gate oxide process technology, the sixth-generation Spartan 6 FPGA offers advanced power management technologies, 150,000 logic cells, hard-core DRAM memory, and a variety of IP. It is Xilinx's most widely used and technologically mature FPGA family. The FPGA master control module primarily handles camera configuration and video data acquisition, DDR3-SDRAM data access, and HDMI interface chip configuration and video data transmission. Its hardware circuitry also includes power supply circuitry, reset circuitry, crystal oscillator circuitry, download circuitry, and SPI Flash configuration circuitry.

[0052] To address the issue of caching high-speed, high-capacity video data, this system uses Micron's 4Gbit DDR3-SDRAM memory chip, the MT41J256M16HA-125, as the cache medium. A0-A14 are the address bus, and B0-B3 are the bank addresses. The FPGA controls the data storage location within the DDR3-SDRAM by manipulating the address bus and bank addresses. D0-D15 are the data bus, connected in parallel to the FPGA. CLK-N and CLK-P are differential clock input ports, with a clock frequency of 312.5MHz in this system. The FPGA controls the read and write operations of the DDR3-SDRAM using the column address select (CAS), row address select (RAS), and write enable (WE) signals. The ODT (Open Delay Time) enables on-chip resistors to optimize performance and prevent data line interruptions and reflections. DQS is a bidirectional synchronization signal between the DDR3-SDRAM and the controller, issued by the controller when writing data and by the memory when reading data. DM is the data mask signal. Since only Bank 1 and Bank 3 of the Spartan 6 series FPAG have MCB hard cores, in this system, Bank 3 in the FPGA is selected to connect to the DDR3-SDRAM, the port voltage standard is 1.5V, and in the FPAG UCF, the IO standard needs to be set to SSTL15_II.

[0053] After the system is powered on, it waits for the FPGA to initialize and enters the waiting state. When the relevant command parameters are input externally, the FPGA receives and parses the command. The system first controls the operation of the internal selector switch, connecting the selected device signal to the acquisition system. Control information is then sent to the device under test, while the acquisition system monitors the power supply status of the device under test in real time. The collected data is then cached in the FPGA's internal random access memory (RAM) for processing. Finally, the collected data is transmitted back to the external monitor via the FPGA's on-chip first-in, first-out queue (FIFO) for real-time display. It is then judged and stored according to the corresponding rules to form a test data report.

[0054] Storage circuit: After data acquisition is complete, the sampled data for the corresponding channel is sent to the monitor for real-time display and stored in Flash memory, awaiting a read command from an external controller. This system uses ST's S25FL128PFlash memory for real-time storage. This chip has a storage capacity of 128Mbits and communicates with the external controller via an SPI interface with a maximum clock frequency of 104MHz. This chip features a simple design, stable data storage, and a low price, making it widely applicable.

[0055] To address the inability of traditional data acquisition and processing systems to effectively achieve synchronization and real-time data transmission and storage, this system uses an FPGA to control the transmission of data read by the AD7609 during conversion, enabling the system to achieve a 200kHz sampling rate. By rationally utilizing the FPGA's internal resources and implementing a ping-pong data cache, this system achieves real-time data transmission and real-time Flash storage, enhancing the reliability, effectiveness, and stability of data transmission and storage, and fully leveraging the FPGA's high-speed data parallel processing and timing constraints. This system has been successfully applied in a real-world engineering monitoring project and demonstrates considerable application value.

[0056] like Figure 5 As shown, the programmable logic module includes a temperature reading module, a second storage module and an operation module; the temperature reading module is connected to the temperature monitoring chip; the second storage module is connected to the temperature reading module; the temperature reading module is connected to the operation module; the temperature reading module is used to read the temperature information of the acceleration unit and send it to the second storage module for storage; the operation module is connected to the power chip, and controls the power chip and the acceleration chip to be connected or disconnected according to the temperature information of the acceleration unit.

[0057] The temperature reading module on the programmable logic module uses the IIC protocol to read the temperature information of the acceleration unit collected by the temperature monitoring chip, including the internal temperature of the acceleration chip and the ambient temperature of the acceleration unit. The calculation module is connected to the temperature reading module and controls the operating mode between the power chip and the acceleration chip based on the acquired temperature information of the acceleration unit. The second storage module can also obtain the temperature information of the acceleration unit stored by the temperature reading module.

[0058] The computing module is internally configured with a temperature range within which the acceleration unit operates normally. When the acceleration unit's temperature information indicates that the current temperature exceeds a maximum temperature threshold, the computing module disconnects the power chip from the acceleration chip 11. The power chip stops supplying power to the acceleration chip, and the acceleration chip stops operating. This prevents the acceleration chip 11 from continuing to heat up and potentially burning the acceleration unit.

[0059] The acceleration unit integrates GPU, TPU or FPGA dedicated accelerators for efficiently processing AI and deep learning tasks; the intelligent scheduling module dynamically allocates computing resources based on machine learning algorithms to optimize task execution efficiency.

[0060] like Figure 6As shown, the communication module adopts a radio frequency switch circuit with a series-parallel structure, and the radio frequency switch circuit includes a radio frequency RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a radio frequency ANT terminal, and a voltage V CTRL Terminal and voltage V CTRI end,

[0061] The radio frequency RF end is respectively connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4; the other end of the fifth resistor R5 is respectively connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3; the other end of the third resistor R3 is respectively connected to the source of the second NMOS transistor Q2 of the first NMOS transistor Q1, the drain of the first NMOS transistor Q1, and one end of the first resistor R1; the other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and grounded; the base of the first NMOS transistor Q1 is connected to the anode of the first diode; the cathode of the first diode is respectively connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2; the other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the voltage V CTRI an end of the sixth resistor R6, one end of the fourth resistor R4, and the other end of the fourth resistor R4 are connected to the gate of the second NMOS transistor Q2 and the cathode of the second diode D2, respectively; an anode of the second diode D2 is connected to the base of the second NMOS transistor Q2; the other end of the sixth resistor R4 is connected to the gate of the third NMOS transistor Q3 and the cathode of the third diode D3, respectively; an anode of the third diode D3 is connected to the base of the third NMOS transistor Q3;

[0062] The gate of the fourth NMOS transistor Q4 is respectively connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is respectively connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and one end of the ninth resistor R9. The gate of the fifth NMOS transistor Q5 is respectively connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is respectively connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is respectively connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage V CTRL The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the radio frequency ANT terminal respectively.

[0063] The radio frequency switch circuit of the present invention can better meet the requirements of large voltage swing operation while ensuring insertion loss and isolation. It improves traditional stacking technology, weakens uneven voltage distribution, significantly improves branch voltage processing capability, and improves branch voltage tolerance, thereby better being used for antenna tuning and meeting the requirements of normal operation even in the case of antenna mismatch. The radio frequency switch part adopts a series-parallel structure, and the control signals of the two branches are complementary. When the series branch is turned on, it is equivalent to a small resistor, and the parallel branch is turned off, which is equivalent to a capacitor and a resistor in parallel.

[0064] The wireless RF chip uses the nRF905 wireless transceiver chip. This long-range wireless transceiver chip features multiple transmission points, a long transmission distance, and strong anti-interference capabilities. It operates in three ISM frequency bands: 433 / 868 / 915 MHz, and the switching time between transceiver modes is less than 650 μs. Ports such as TRX_CE, PWR_UP, TXEN, CSN, SCK, MISO, and MOSI are connected to the microcontroller, with CSN, SCK, MISO, and MOSI forming the SPI interface. When transmitting data, the nRF905 is set to transmit mode. The microcontroller writes the receiving point address and valid data to the chip buffer via the SPI interface, then generates a CRC and preamble based on the TRX_CE level, and transmits the data. When receiving data, the nRF905 is set to receive mode and waits for incoming data. Upon receiving the preamble, valid address, and CRC, the data is stored in a register, generating an interrupt to allow the microcontroller to read the data.

[0065] like Figure 7As shown, the power management module includes a mains module, a charging control module, and a rechargeable battery. The mains module is connected to the processor unit, and the mains module is connected to the processor unit through the charging control module and the rechargeable battery in turn.

[0066] like Figure 8 As shown, the charging control module includes a charging control circuit, a charging controller, an overcurrent protection circuit, a demodulation module, a full-bridge driver, and a voltage regulation module. The charging control circuit and the overcurrent protection circuit are respectively connected to the charging controller, and the charging controller is respectively connected to the full-bridge driver through the demodulation module and the voltage regulation module;

[0067] Wherein, the charging control circuit is connected to the rechargeable battery and is used for charging control of the rechargeable battery;

[0068] Overcurrent protection circuit, used for overcurrent protection during charging control of rechargeable batteries;

[0069] The voltage regulating module is connected to the full-bridge driver and is used to achieve automatic voltage regulation through the feedback pin;

[0070] The demodulation module is connected to the full-bridge driver and is used to transmit the demodulated data to the charging controller for processing;

[0071] The charging controller is connected to the voltage regulation module and the demodulation module respectively, and is used to control the voltage regulation accuracy and voltage regulation range of the voltage regulation module, and promptly process the received power request feedback from the demodulation module, and output a control signal to the voltage regulation module according to the demand, thereby realizing multi-speed voltage precision regulation.

[0072] like Figure 9 As shown, the demodulation module includes a voltage input VIN terminal, a resistor R1, a resistor R2, a resistor R3, a resistor R7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, an inductor L1, a chip FR9885, a voltage output V DCDC Terminal, voltage output V control The voltage input VIN terminal is connected to one end of the capacitor C1, one end of the capacitor C2 and the VIN terminal of the chip FR9885 respectively. The other end of the capacitor C1 is connected to the other end of the capacitor C2, one end of the capacitor C3 and the GND terminal of the chip FR9885 and grounded. The other end of the capacitor C3 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the SHDN terminal of the chip FR9885, the BST terminal of the chip FR9885 is connected to one end of the capacitor C9, the other end of the capacitor C9 is connected to the LX terminal of the chip FR9885 and one end of the inductor L1, and the other end of the inductor L1 is connected to one end of the resistor R2, one end of the capacitor C5, one end of the capacitor C6, one end of the capacitor C7, one end of the capacitor C8 and the voltage output V DCDCThe other end of capacitor C5 is connected to the other end of resistor R2, one end of resistor R3, one end of resistor R7 and the FB end of chip FR9885. The other end of resistor R7 is connected to the voltage output V control The other end of the resistor R3 is grounded, and the other end of the capacitor C6 is connected to the other end of the capacitor C7 and the other end of the capacitor C8 and is grounded.

[0073] By controlling the voltage regulation accuracy and voltage regulation range of the voltage regulation module and promptly processing the received power request fed back by the demodulation module, the control signal is output to the voltage regulation module according to the demand, thereby achieving multi-level voltage precise regulation; it does not require the use of a high-frequency MCU, but only needs to generate a control signal through the MCU to control the voltage regulation module to achieve accurate and reliable voltage regulation.

[0074] like Figure 10 As shown, the charging control circuit includes a signal control terminal, a charging power terminal, a device power terminal, a battery terminal, a transistor, a first MOS transistor, and a second MOS transistor; wherein the charging power terminal is grounded via a first resistor and a second resistor connected in series; the base of the transistor is connected to the signal control terminal and the charging power terminal respectively, the collector of the transistor is connected to the gate of the second MOS transistor via a fourth resistor, and is also connected to the source of the first MOS transistor via a third resistor, and the emitter of the transistor is grounded; the source of the second MOS transistor is connected to the charging power terminal via a first diode, and the drain is connected to the device power terminal; the source of the first MOS transistor is connected to the charging power terminal via a first diode, the gate is connected to the connection point of the first and second resistors, and the drain is connected to the battery terminal.

[0075] The present invention uses MOS tubes as power devices, which have high power efficiency. When the device battery is charging, the battery power supply can be cut off and the device is powered by the power supply instead, so as to protect the battery and extend the battery life. The device can be turned on and off by hardware and software, and can also be reset through the hardware reset port to shut down the device.

[0076] like Figure 11 As shown, the crystal oscillator circuit includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC terminal. The 8-port of the control chip 7N10.000MBP is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C45, the 9-port of the control chip 7N10.000MBP, one end of the resistor R23 and the voltage VCC terminal. The other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is grounded. The 10-port of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded.

[0077] The above description is merely illustrative of certain exemplary embodiments of the present invention. It goes without saying that those skilled in the art will be able to modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and description are illustrative in nature and should not be construed as limiting the scope of protection of the claims.

[0078] Finally, a few points should be explained: First, in the description of this application, it should be noted that, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense, and may refer to mechanical or electrical connections, internal communication between two components, or direct connection. "Up," "down," "left," and "right" are only used to indicate relative positional relationships. When the absolute positions of the objects being described change, the relative positional relationships may also change.

[0079] Secondly: The drawings of the embodiments disclosed in the present invention only involve structures related to the embodiments disclosed in the present invention. Other structures may refer to conventional designs. The same embodiment and different embodiments of the present invention may be combined with each other without conflict.

[0080] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An acceleration server system for cloud computing and AI, characterized by: The invention comprises a server mainboard and an accelerator unit connected to the server mainboard; the server mainboard comprises a processor unit, a distributed storage unit, a first storage module, a USB interface module, a serial port module, a clock module, a heat dissipation module, a communication module, and a power management module; the distributed storage unit, the first storage module, the USB interface module, the serial port module, the clock module, the heat dissipation module, the communication module, and the power management module are respectively connected to the processor unit; the accelerator unit comprises an acceleration control unit, a programmable logic module, a cache unit, an interconnection interface module, an intelligent scheduling module, a temperature monitoring unit, and a power chip; the acceleration control unit is connected to the temperature monitoring unit, the temperature monitoring unit is connected to the programmable logic module, and the cache unit, the interconnection interface module, the intelligent scheduling module, and the power chip are respectively connected to the programmable logic module.

2. The acceleration server system for cloud computing and AI according to claim 1, characterized in that: The processor unit includes an AD acquisition control unit, a data processing and RAM read-write module unit, a port control unit, a synchronous clock control unit, a command deframing unit, a FIFO data cache unit, a data reading unit, as well as a power supply circuit, a reset circuit, a crystal oscillator circuit, a download circuit and a configuration SPI Flash circuit. The AD acquisition control unit is connected to the data processing and RAM read-write module unit, and the port control unit, the synchronous clock control unit, the command deframing unit, the FIFO data cache unit, the data reading unit, as well as the power supply circuit, the reset circuit, the crystal oscillator circuit, the download circuit and the configuration SPI Flash circuit are respectively connected to the data processing and RAM read-write module unit.

3. The acceleration server system for cloud computing and AI according to claim 1, characterized in that: The programmable logic module includes a temperature reading module, a second storage module and an operation module; the temperature reading module is connected to the temperature monitoring chip; the second storage module is connected to the temperature reading module; the temperature reading module is connected to the operation module; the temperature reading module is used to read the temperature information of the acceleration unit and send it to the second storage module for storage; the operation module is connected to the power supply chip, and controls the power supply chip and the acceleration chip to be connected or disconnected according to the temperature information of the acceleration unit.

4. The acceleration server system for cloud computing and AI according to claim 1, characterized in that: The acceleration unit integrates GPU, TPU or FPGA dedicated accelerators for efficiently processing AI and deep learning tasks; the intelligent scheduling module dynamically allocates computing resources based on machine learning algorithms to optimize task execution efficiency.

5. The acceleration server system for cloud computing and AI according to claim 1, characterized in that: The communication module adopts a radio frequency switch circuit with a series-parallel structure, and the radio frequency switch circuit includes a radio frequency RF terminal, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, a sixth diode D6, a radio frequency ANT terminal, and a voltage V CTRL Terminal and voltage V CTRI end, The radio frequency RF end is respectively connected to one end of the fifth resistor R5, one end of the seventh resistor R7, the drain of the third NMOS transistor Q3, and the drain of the fourth NMOS transistor Q4; the other end of the fifth resistor R5 is respectively connected to the source of the third NMOS transistor Q3, the drain of the second NMOS transistor Q2, and one end of the third resistor R3; the other end of the third resistor R3 is respectively connected to the source of the second NMOS transistor Q2 of the first NMOS transistor Q1, the drain of the first NMOS transistor Q1, and one end of the first resistor R1; the other end of the first resistor R1 is connected to the source of the first NMOS transistor Q1 and grounded; the base of the first NMOS transistor Q1 is connected to the anode of the first diode; the cathode of the first diode is respectively connected to the gate of the first NMOS transistor Q1 and one end of the second resistor R2; the other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the voltage V CTRI an end of the sixth resistor R6, one end of the fourth resistor R4, and the other end of the fourth resistor R4 are connected to the gate of the second NMOS transistor Q2 and the cathode of the second diode D2, respectively; an anode of the second diode D2 is connected to the base of the second NMOS transistor Q2; the other end of the sixth resistor R4 is connected to the gate of the third NMOS transistor Q3 and the cathode of the third diode D3, respectively; an anode of the third diode D3 is connected to the base of the third NMOS transistor Q3; The gate of the fourth NMOS transistor Q4 is respectively connected to the cathode of the fourth diode D4 and one end of the eighth resistor R8. The other end of the seventh resistor R7 is respectively connected to the source of the fourth NMOS transistor Q4, the drain of the fifth NMOS transistor Q5, and one end of the ninth resistor R9. The gate of the fifth NMOS transistor Q5 is respectively connected to one end of the tenth resistor R10 and the cathode of the fifth diode D5. The anode of the fifth diode D5 is connected to the base of the fifth diode D5. The source of the fifth NMOS transistor Q5 is respectively connected to the other end of the ninth resistor R9, one end of the eleventh resistor R11, and the drain of the sixth NMOS transistor Q6. The gate of the sixth NMOS transistor Q6 is respectively connected to one end of the twelfth resistor R12 and the cathode of the sixth diode D6. The anode of the sixth diode D6 is connected to the base of the sixth diode D6. The other end of the twelfth resistor R12 is connected to the other end of the eighth resistor R8. The other end of the tenth resistor R10 is connected to the voltage V CTRL The source of the sixth NMOS transistor Q6 is connected to the other end of the eleventh resistor R11 and the radio frequency ANT terminal respectively.

6. The acceleration server system for cloud computing and AI according to claim 1, characterized in that: The power management module includes a mains module, a charging control module, and a rechargeable battery. The mains module is connected to the processor unit, and the mains module is connected to the processor unit through the charging control module and the rechargeable battery in turn.

7. The acceleration server system for cloud computing and AI according to claim 6, characterized in that: The charging control module includes a charging control circuit, a charging controller, an overcurrent protection circuit, a demodulation module, a full-bridge driver, and a voltage regulation module. The charging control circuit and the overcurrent protection circuit are respectively connected to the charging controller, and the charging controller is respectively connected to the full-bridge driver through the demodulation module and the voltage regulation module; Wherein, the charging control circuit is connected to the rechargeable battery and is used for charging control of the rechargeable battery; Overcurrent protection circuit, used for overcurrent protection during charging control of rechargeable batteries; The voltage regulating module is connected to the full-bridge driver and is used to achieve automatic voltage regulation through the feedback pin; The demodulation module is connected to the full-bridge driver and is used to transmit the demodulated data to the charging controller for processing; The charging controller is connected to the voltage regulation module and the demodulation module respectively, and is used to control the voltage regulation accuracy and voltage regulation range of the voltage regulation module, and promptly process the received power request feedback from the demodulation module, and output a control signal to the voltage regulation module according to the demand, thereby realizing multi-speed voltage precision regulation.

8. The acceleration server system for cloud computing and AI according to claim 7, characterized in that: The demodulation module includes a voltage input VIN terminal, a resistor R1, a resistor R2, a resistor R3, a resistor R7, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, a capacitor C9, an inductor L1, a chip FR9885, a voltage output V DCDC Terminal, voltage output V control The voltage input VIN terminal is connected to one end of the capacitor C1, one end of the capacitor C2 and the VIN terminal of the chip FR9885 respectively. The other end of the capacitor C1 is connected to the other end of the capacitor C2, one end of the capacitor C3 and the GND terminal of the chip FR9885 and grounded. The other end of the capacitor C3 is connected to one end of the resistor R1, the other end of the resistor R1 is connected to the SHDN terminal of the chip FR9885, the BST terminal of the chip FR9885 is connected to one end of the capacitor C9, the other end of the capacitor C9 is connected to the LX terminal of the chip FR9885 and one end of the inductor L1, and the other end of the inductor L1 is connected to one end of the resistor R2, one end of the capacitor C5, one end of the capacitor C6, one end of the capacitor C7, one end of the capacitor C8 and the voltage output V DCDC The other end of capacitor C5 is connected to the other end of resistor R2, one end of resistor R3, one end of resistor R7 and the FB end of chip FR9885. The other end of resistor R7 is connected to the voltage output V control The other end of the resistor R3 is grounded, and the other end of the capacitor C6 is connected to the other end of the capacitor C7 and the other end of the capacitor C8 and is grounded.

9. The acceleration server system for cloud computing and AI according to claim 7, characterized in that: The charging control circuit includes a signal control terminal, a charging power terminal, a device power terminal, a battery terminal, a transistor, a first MOS transistor, and a second MOS transistor; wherein the charging power terminal is grounded via a first resistor and a second resistor connected in series; the base of the transistor is connected to the signal control terminal and the charging power terminal respectively, the collector of the transistor is connected to the gate of the second MOS transistor via a fourth resistor, and is also connected to the source of the first MOS transistor via a third resistor, and the emitter of the transistor is grounded; the source of the second MOS transistor is connected to the charging power terminal via a first diode, and the drain is connected to the device power terminal; the source of the first MOS transistor is connected to the charging power terminal via a first diode, the gate is connected to the connection point of the first and second resistors, and the drain is connected to the battery terminal.

10. The acceleration server system for cloud computing and AI fields according to claim 1, characterized in that: The crystal oscillator circuit includes a control chip 7N10.000MBP, a capacitor C45, a resistor R22, a resistor R23, a resistor R24, a capacitor C69 and a voltage VCC terminal. The 8-interface of the control chip 7N10.000MBP is connected to one end of the resistor R22, and the other end of the resistor R22 is respectively connected to one end of the capacitor C45, the 9-interface of the control chip 7N10.000MBP, one end of the resistor R23 and the voltage VCC terminal. The other end of the capacitor C45 is grounded, the other end of the resistor R23 is connected to one end of the resistor R24, and the other end of the resistor R24 ​​is grounded. The 10-interface of the control chip 7N10.000MBP is connected to one end of the capacitor C69, and the other end of the capacitor C69 is grounded.

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