Display device

Abstract

A display device is provided. The display device includes a data driver, a distributor including a plurality of demultiplexers, a timing controller, and a plurality of pixels, the data driver supplies a reference voltage and a plurality of data signals to each of the plurality of output lines, the distributor supplies the reference voltage and the plurality of data signals supplied from each of the plurality of output lines to the plurality of data lines in response to a plurality of control signals, and the timing controller supplies the plurality of control signals, the plurality of pixels are connected to the plurality of scan lines and the plurality of data lines. Pixels located on at least two different horizontal lines are simultaneously supplied with a reference voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0023552 filed in the Korean Intellectual Property Office (KIPO) on February 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to a display device and a method of driving the display device and an electronic device. Background Art

[0004] With the development of information technology, the importance of display devices, which are a connecting medium between users and information, has increased. Therefore, display devices such as liquid crystal display devices and organic light emitting display devices are becoming increasingly popular.

[0005] Recently, head-mounted displays (HMDs) have been developed. HMDs are display devices that users wear in the form of glasses or helmets, thereby realizing virtual reality (VR) or augmented reality (AR) in which a focus is formed at a distance close to the eyes. Summary of the Invention

[0006] Embodiments provide a display device applicable to high resolution and a method of driving the display device.

[0007] According to an embodiment of the present disclosure, a display device may include a data driver, a distributor including multiple demultiplexers, a timing controller, and multiple pixels. The data driver supplies a reference voltage and multiple data signals to each of a plurality of output lines. The distributor supplies the reference voltage and multiple data signals supplied from each of the plurality of output lines to the plurality of data lines in response to multiple control signals. The timing controller supplies control signals. The plurality of pixels are connected to a plurality of scan lines and a plurality of data lines. Pixels located on at least two different horizontal lines can be supplied with the reference voltage simultaneously.

[0008] Each of the plurality of pixels may be driven separately in an initialization period, a threshold voltage compensation period, and a data writing period. The pixel may be supplied with a reference voltage during the initialization period and the threshold voltage compensation period.

[0009] The initialization period and the threshold voltage compensation period of pixels located on at least two different horizontal lines may overlap with each other.

[0010] Data writing periods of pixels located on at least two different horizontal lines may not overlap with each other.

[0011] Each of the plurality of demultiplexers may include a plurality of switches, each of the plurality of switches being connected to one of the plurality of data lines and being turned on or off in response to a control signal. The data driver may supply a reference voltage to the output line during an initialization period and a threshold voltage compensation period. The timing controller may simultaneously supply a plurality of control signals during the initialization period and the threshold voltage compensation period so that the plurality of switches can be turned on simultaneously.

[0012] The data driver may sequentially supply a plurality of data signals to each of the plurality of output lines during a data write period. The timing controller may sequentially supply a plurality of control signals during the data write period to sequentially turn on the plurality of switches.

[0013] Each of the plurality of demultiplexers may be connected to a plurality of data lines, and each of the plurality of data lines may be connected to a pixel emitting light of a different color.

[0014] Each of the plurality of demultiplexers may be connected to a plurality of data lines, and each of the plurality of data lines may be connected to pixels emitting light of the same color.

[0015] The display device may also include: a main line located between the timing controller and the distributor; a plurality of main buffers arranged at one side and the other side of the main line, the plurality of main buffers supplying at least one of a plurality of control signals supplied from the timing controller to the main line; a plurality of branch lines branching out from the main line; and a sub-buffer located on each of the plurality of branch lines, the sub-buffer being connected to at least one of the plurality of demultiplexers.

[0016] The channel of the data driver may include a first decoder that generates a plurality of data signals, a second decoder that generates a reference voltage, a first switch connected between a source amplifier and the first decoder, and a second switch connected between the source amplifier and the second decoder. An output terminal of the source amplifier may be connected to one of a plurality of output lines.

[0017] The first switch may be turned on during the data write period in response to a voltage control signal supplied from the timing controller. The second switch may be turned on during the initialization period and the threshold voltage compensation period in response to the voltage control signal.

[0018] Each of the multiple pixels may include: a first transistor including a gate electrode connected to a first node, a first electrode connected to a first power line, and a second electrode connected to a second node; a second transistor including a first electrode connected to one of a plurality of data lines and a gate electrode connected to a first scan line; a third transistor connected between the first node and the second node, the third transistor including a gate electrode connected to the second scan line; a light-emitting element including an anode electrode and a cathode electrode, the cathode electrode being connected to the second power line; a fourth transistor connected between the anode electrode of the light-emitting element and the second node, the fourth transistor including a gate electrode connected to a first emission control line; a fifth transistor connected between the anode electrode of the light-emitting element and the third power line, the fifth transistor including a gate electrode connected to the third scan line; a sixth transistor connected between the first electrode of the first transistor and the first power line, the sixth transistor including a gate electrode connected to the second emission control line; a first capacitor connected between the second electrode of the second transistor and the first node; and a second capacitor connected between the first power line and the first node.

[0019] According to another embodiment of the present disclosure, a method for driving a display device may include: supplying a reference voltage and a plurality of data signals to an output line; supplying the reference voltage and the plurality of data signals to a plurality of data lines using a demultiplexer connected to the output line; and supplying the reference voltage to the pixels during a first period in which the pixels are initialized and a second period in which a threshold voltage of a driving transistor included in each of the pixels is compensated. Pixels located on at least two different horizontal lines may be supplied with the reference voltage simultaneously during the first period and the second period.

[0020] The demultiplexer may include a plurality of switches, each of the plurality of switches being connected to one of the plurality of data lines. The plurality of switches may be set to be in an on state during the first period and the second period.

[0021] The pixels may be supplied with a plurality of data signals during a third period, and the third periods of pixels located on at least two different horizontal lines may not overlap with each other.

[0022] The plurality of switches may be sequentially turned on during the third period such that turn-on periods of the plurality of switches do not overlap with each other.

[0023] The method may also include supplying at least one control signal for controlling the on and off of a plurality of switches to the main line via a main buffer located at each of one side and the other side of the main line, and supplying at least one control signal to the demultiplexer via a sub-buffer connected to a branch line branching from the main line.

[0024] Each of the plurality of data lines connected to the demultiplexer may be connected to a pixel emitting light of a different color.

[0025] Each of the plurality of data lines connected to the demultiplexer may be connected to pixels emitting light of the same color.

[0026] A reference voltage and a plurality of data signals may be supplied to the output line via the same source amplifier.

[0027] According to an embodiment of the present disclosure, an electronic device may include: a processor that provides input image data; and a display device that displays an image based on the input image data. The display device also includes: a data driver that supplies a reference voltage and multiple data signals to each of a plurality of output lines; a distributor including multiple demultiplexers that supplies the reference voltage and multiple data signals supplied from each of the plurality of output lines to the plurality of data lines in response to multiple control signals; a timing controller that supplies multiple control signals; and a plurality of pixels connected to a plurality of scan lines and a plurality of data lines. Pixels located on at least two different horizontal lines are simultaneously supplied with the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0029] In the drawings, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intervening elements may be present. Like reference numerals refer to like elements throughout.

[0030] Figure 1 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure.

[0031] Figure 2 It shows Figure 1 Schematic diagram of an embodiment of a scan driver and an emission driver is shown in FIG.

[0032] Figure 3 It shows Figure 1 Schematic diagram of an embodiment of an equivalent circuit of a pixel shown in .

[0033] Figure 4 Is shown driving Figure 3 Schematic waveform diagram of an embodiment of the method for a pixel shown in FIG.

[0034] Figures 5A to 5F is a graph showing the pixel Figure 4 Schematic diagram of the operation process corresponding to the driving waveform shown in FIG.

[0035] Figure 6 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure.

[0036] Figure 7 and Figure 8 It shows Figure 6 A schematic diagram of an embodiment of a dispenser is shown in FIG.

[0037] Figure 9 is a schematic diagram showing pixels located on the (i-1)th horizontal line and the i-th horizontal line.

[0038] Figure 10 Is shown driving Figure 9 Schematic waveform diagram of the pixel method shown in FIG.

[0039] Figure 11 is a schematic diagram showing output channels of a data driver.

[0040] Figure 12 and Figure 13 is a schematic diagram illustrating a connection between a timing controller and a distributor according to an embodiment of the present disclosure.

[0041] Figure 14A is a schematic diagram illustrating a delay of a control signal according to a comparative example.

[0042] Figure 14B It shows that according to Figure 12 FIG. 4 is a schematic diagram of the delay of the control signal according to the embodiment of the present disclosure.

[0043] Figures 15 to 18 is a schematic diagram illustrating an electronic device according to various embodiments of the present disclosure.

[0044] Figure 19 is a schematic block diagram illustrating an electronic device including a display device according to an embodiment. DETAILED DESCRIPTION

[0045] Hereinafter, the embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described in the specification.

[0046] In order to clearly describe the present disclosure, parts not related to the description will be omitted, and the same or similar constituent elements will be represented by the same reference numerals throughout the specification. Therefore, the same reference numerals can be used to identify the same or similar elements in different drawings.

[0047] In the description, the expression "equal" may mean "substantially equal." For example, it may mean equal to the extent that a person skilled in the art can understand equality. Other expressions may be expressions in which "substantially" is omitted.

[0048] Some embodiments related to functional blocks, units and / or modules are described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically realized by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed by using semiconductor-based manufacturing techniques or other manufacturing techniques. When a block, unit and / or module is realized by a microprocessor or other similar hardware, the block, unit and / or module is programmed and controlled using software to perform the various functions discussed in this disclosure, and can be selectively driven by firmware and / or software. In addition, each block, each unit and / or each module can be realized by a combination of dedicated hardware or dedicated hardware that performs some functions of a block, unit and / or module and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs other functions of the block, unit and / or module. In some embodiments, without departing from the scope of this disclosure, a block, unit and / or module can be physically separated into two or more separate blocks, two or more separate units and / or two or more separate modules. Furthermore, in some embodiments, blocks, units and / or modules may be physically separated into more complex blocks, more complex units and / or more complex modules without departing from the scope of the present disclosure.

[0049] When an element (such as a layer) is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" can refer to being physically connected, electrically connected, and / or fluidically connected, with or without intervening elements.

[0050] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, the "first" element discussed below can also be referred to as the "second" element without departing from the teachings of the present disclosure.

[0051] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0052] In the specification and claims, for the purposes of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B." In the specification and claims, for the purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" can be understood to mean "A, B, or A and B." The terms "and" and "or" can be used in a conjunction or disjunction manner and can be understood to be equivalent to "and / or."

[0053] The present disclosure is not limited to the embodiments disclosed below and can be implemented in various forms. Each embodiment disclosed below can be implemented independently or combined with at least one other embodiment before being implemented.

[0054] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless clearly defined in the specification.

[0055] Figure 1 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure. Figure 2 It shows Figure 1 Schematic diagram of an embodiment of a scan driver and an emission driver is shown in FIG.

[0056] Reference Figure 1 and Figure 2 The display device 100 according to an embodiment of the present disclosure may include a pixel unit 110 (or panel), a timing controller 120, a scan driver 130, a data driver 140, an emission driver 150, and a power supply 160. The above components may be implemented as a plurality of separate integrated circuits, and two or more of the above components may be implemented as integrated into one integrated circuit.

[0057] The pixel unit 110 may include pixels PX connected to first scan lines SL11, SL12, ... and SL1n, second scan lines SL21, SL22, ... and SL2n, third scan lines SL31, SL32, ... and SL3n, data lines DL1, DL2, ... and DLm, first emission control lines EL11, EL12, ... and EL1n, second emission control lines EL21, EL22, ... and EL2n, and power lines PL1, PL2 and PL3 (n and m are natural numbers of 3 or greater).

[0058] In an embodiment, the pixels PXij (see FIG. 1 ) located on the i-th horizontal line (or pixel row) and the j-th vertical line (or pixel column) are Figure 3 ) can be connected to the i-th first scan line SL1i (see Figure 3 ), the i-th second scanning line SL2i (see Figure 3 ), the i-th third scanning line SL3i (see Figure 3 ), the i-th first emission control line EL1i (see Figure 3 ), the i-th second emission control line EL2i (see Figure 3 ) and the j-th data line DLj (see Figure 3 )(i is an integer less than or equal to n and greater than 0, and j is an integer less than or equal to m and greater than 0).

[0059] When the first scan lines SL11 to SL1n are supplied with a first scan signal, pixels PX may be selected in units of horizontal lines (for example, pixels PX connected to the same scan line may be arranged as one horizontal line (or pixel row)), and each of the pixels PX selected by the first scan signal may be supplied with a data signal from a data line (one of the data lines DL1 to DLm) connected to the pixel PX. The pixel PX supplied with the data signal may generate light having a brightness corresponding to the voltage of the data signal.

[0060] The scan driver 130 may receive a scan drive signal SCS from the timing controller 120. The scan drive signal SCS may include at least one scan start signal and a clock signal for driving the scan driver 130. The scan driver 130 may generate a first scan signal, a second scan signal, and a third scan signal while shifting the scan start signal in response to the clock signal. Here, "corresponding to" may mean "in response to," and similar descriptions are similar to this herein.

[0061] For this reason, Figure 2 As shown in , the scan driver 130 may include a first scan driver 132 , a second scan driver 134 , and a third scan driver 136 .

[0062] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first scan signal while shifting the first scan start signal FLM1 corresponding to the clock signal. The first scan driver 132 may sequentially supply the first scan signal to the first scan lines SL11 to SL1n.

[0063] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second scan signal while shifting the second scan start signal FLM2 corresponding to the clock signal. The second scan driver 134 may sequentially supply the second scan signal to the second scan lines SL21 to SL2n.

[0064] The third scan driver 136 may receive the third scan start signal FLM3 and generate a third scan signal while shifting the third scan start signal FLM3 in accordance with the clock signal. The third scan driver 136 may sequentially supply the third scan signal to the third scan lines SL31 to SL3n. Each of the first scan signal, the second scan signal, and the third scan signal may be set to a gate-on voltage to turn on the transistor included in the pixel PX.

[0065] In an embodiment, the first scan signal, the second scan signal, and the third scan signal having a low level may be supplied to a P-type transistor, and the first scan signal, the second scan signal, and the third scan signal having a high level may be supplied to an N-type transistor. The transistor supplied with the first scan signal, the second scan signal, or the third scan signal may be turned on in response to the first scan signal, the second scan signal, or the third scan signal. Supplying the first scan signal, the second scan signal, or the third scan signal may mean supplying a gate-on voltage to the first scan line SL1, the second scan line SL2, or the third scan line SL3. Not supplying the first scan signal, the second scan signal, or the third scan signal may mean supplying a gate-off voltage to the first scan line SL1, the second scan line SL2, or the third scan line SL3.

[0066] exist Figure 2 , the first scan driver 132, the second scan driver 134, and the third scan driver 136 are shown to be connected to the first scan line SL1, the second scan line SL2, and the third scan line SL3, respectively. However, the present disclosure is not limited thereto. In another embodiment, at least two of the first scan line SL1, the second scan line SL2, and the third scan line SL3 (at least two of the first scan line SL1, the second scan line SL2, and the third scan line SL3) can be driven by a single scan driver.

[0067] The data driver 140 may receive the output data Dout and the data drive signal DCS from the timing controller 120. The data drive signal DCS may include a sampling signal and / or a timing signal for driving the data driver 140. The data driver 140 may generate a data signal based on the data drive signal DCS and the output data Dout. In an embodiment, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may generate a grayscale signal based on the grayscale of the output data Dout in one horizontal period 1H (see FIG. Figure 4 ) period, the reference power supply Vref is sequentially supplied to the data lines DL1 to DLm (see Figure 4 ) voltage (or reference voltage) and the data signal voltage Vdata (see Figure 4 ). The reference power supply Vref can be set to a constant voltage.

[0068] The emission driver 150 may receive an emission driving signal ECS from the timing controller 120. An emission start signal and a clock signal for driving the emission driver 150 may be included in the emission driving signal ECS. The emission driver 150 may generate a first emission control signal and a second emission control signal while shifting the emission start signal in accordance with the clock signal.

[0069] For this reason, Figure 2 As shown in , the transmit driver 150 may include a first transmit driver 152 and a second transmit driver 154 .

[0070] The first emission driver 152 may receive the first emission start signal EFLM1 and generate a first emission control signal while shifting the first emission start signal EFLM1 corresponding to the clock signal. The first emission driver 152 may sequentially supply the first emission control signal to the first emission control lines EL11 to EL1n.

[0071] The second emission driver 154 may receive the second emission start signal EFLM2 and generate a second emission control signal while shifting the second emission start signal EFLM2 in accordance with the clock signal. The second emission driver 154 may sequentially supply the second emission control signal to the second emission control lines EL21 to EL2n. The first emission control signal and the second emission control signal may be set to a gate-off voltage to enable the transistor included in the pixel PX to be turned off.

[0072] In an embodiment, a first emission control signal having a high level and a second emission control signal having a high level may be supplied to a P-type transistor, and a first emission control signal having a low level and a second emission control signal having a low level may be supplied to an N-type transistor. A transistor supplied with the first emission control signal or the second emission control signal may be turned off in response to the first emission control signal or the second emission control signal. Supplying the first emission control signal or the second emission control signal may mean supplying a gate-off voltage to the first emission control line EL1 or the second emission control line EL2. Not supplying the first emission control signal or the second emission control signal may mean supplying a gate-on voltage to the first emission control line EL1 or the second emission control line EL2.

[0073] exist Figure 2 , the first emission driver 152 and the second emission driver 154 are respectively connected to the first emission control line EL1 and the second emission control line EL2. However, the present disclosure is not limited thereto. In another embodiment, the first emission control line EL1 and the second emission control line EL2 may be driven by one emission driver.

[0074] The timing controller 120 may receive input data Din and a control signal CS from the host system through an interface. In an embodiment, the timing controller 120 may receive the input data Din and the control signal CS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. Various signals including a clock signal may be included in the control signal CS.

[0075] The timing controller 120 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the control signal CS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be supplied to the scan driver 130, the data driver 140, and the emission driver 150, respectively.

[0076] The timing controller 120 may rearrange the input data Din to suit the specifications of the display device 100. In addition, the timing controller 120 may generate output data Dout by correcting the input data Din and supply the output data Dout to the data driver 140. In an embodiment, the timing controller 120 may correct the input data Din corresponding to an optical measurement result measured during a process.

[0077] The power supply 160 may generate various power sources for driving the display apparatus 100. In an embodiment, the power supply 160 may generate a first driving power source VDD, a second driving power source VSS, and an initialization power source Vint.

[0078] The first driving power supply VDD may be a power supply that supplies a driving current to the pixel PX. The second driving power supply VSS may be a power supply supplied with a driving current from the pixel PX. During a period in which the pixel PX is set to be in an emission state, the first driving power supply VDD may be set to a voltage higher than a voltage of the second driving power supply VSS.

[0079] The initialization power source Vint may be used to initialize the light emitting element LD included in each of the pixels PX (see Figure 3 ). In the case where the initialization power supply Vint is supplied to the first electrode of the light emitting element LD, the initialization power supply Vint may have a voltage value at which the light emitting element LD is turned off.

[0080] The first driving power VDD generated by the power supply 160 may be supplied to the first power line PL1, the second driving power VSS generated by the power supply 160 may be supplied to the second power line PL2, and the initialization power Vint may be supplied to the third power line PL3. The first power line PL1, the second power line PL2, and the third power line PL3 may be commonly connected to the plurality of pixels PX, but the present disclosure is not limited thereto.

[0081] In an embodiment, the first power line PL1 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the second power line PL2 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment, the third power line PL3 may be configured with multiple power lines, and the multiple power lines may be connected to different pixels PX. In an embodiment of the present disclosure, each pixel PX may be connected to one of the multiple power lines of the first power line PL1, one of the multiple power lines of the second power line PL2, and one of the multiple power lines of the third power line PL3.

[0082] Figure 3 It shows Figure 1 Schematic diagram of an embodiment of an equivalent circuit of a pixel shown in FIG. Figure 3 , pixels PXij located on the i-th horizontal line and the j-th vertical line will be shown.

[0083] Reference Figure 3, a pixel PXij according to an embodiment of the present disclosure can be connected to corresponding signal lines SL1i, SL2i, SL3i, EL1i, EL2i, and DLj. For example, a pixel PXij can be connected to the i-th first scan line SL1i, the i-th second scan line SL2i, the i-th third scan line SL3i, the i-th first emission control line EL1i, the i-th second emission control line EL2i, and the j-th data line DLj. In an embodiment, the pixel PXij can also be connected to the first power line PL1, the second power line PL2, and the third power line PL3.

[0084] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit for controlling the amount of current supplied to the light emitting element LD.

[0085] The light-emitting element LD may be connected between a first power line PL1 and a second power line PL2. In an embodiment, a first electrode (or anode electrode) of the light-emitting element LD may be electrically connected to the first power line PL1 via a third node N3, a fourth transistor M4, a second node N2, a first transistor M1, and a sixth transistor M6, and a second electrode (or cathode electrode) of the light-emitting element LD may be electrically connected to the second power line PL2. The light-emitting element LD may generate light having a brightness corresponding to the amount of current supplied from the first power line PL1 to the second power line PL2 via the pixel circuit.

[0086] The light emitting element LD may be an organic light emitting diode. In another embodiment, the light emitting element LD may be an inorganic light emitting diode, such as a micro LED (light emitting diode) or a quantum dot light emitting diode. In another embodiment, the light emitting element LD may be an element configured with a combination of organic and inorganic materials. Figure 3 , it is shown that the pixel PXij includes a single light emitting element LD. However, the present disclosure is not limited thereto, and in another embodiment, the pixel PXij may include a plurality of light emitting elements LD, and the plurality of light emitting elements LD may be connected to each other in series, in parallel, or in series and parallel.

[0087] The pixel circuit may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a first capacitor C1, and a second capacitor C2.

[0088] In embodiments, the transistors M1 to M6 may be formed using various types of transistors. In embodiments, the transistors M1 to M6 may be formed using thin film transistors (TFTs), field effect transistors (FETs), bipolar junction transistors (BJTs), and the like.

[0089] In an embodiment, the first to sixth transistors M1 to M6 may be formed with P-type transistors. However, the present disclosure is not limited thereto, and in another embodiment, at least one of the first to sixth transistors M1 to M6 may be replaced with an N-type transistor.

[0090] The first electrode of the first transistor M1 may be connected to the second electrode of the sixth transistor M6, and the second electrode of the first transistor M1 may be connected to the second node N2. The term "connected" includes the meaning of being electrically connected. The gate electrode of the first transistor M1 may be connected to the first node N1. The first transistor M1 may control the amount of current supplied from the first driving power supply VDD to the second driving power supply VSS via the light-emitting element LD according to the voltage of the first node N1.

[0091] The second transistor M2 may be connected between the data line DLj and the first electrode of the first capacitor C1. The gate electrode of the second transistor M2 may be electrically connected to the first scan line SL1i. The second transistor M2 may be turned on when the first scan signal GW is supplied to the first scan line SL1i to electrically connect the data line DLj and the first electrode of the first capacitor C1 to each other.

[0092] The third transistor M3 may be connected between the first node N1 and the second node N2. The gate electrode of the third transistor M3 may be electrically connected to the second scan line SL2i. The third transistor M3 may be turned on when the second scan signal GC is supplied to the second scan line SL2i to electrically connect the first node N1 and the second node N2 to each other. The gate electrode of the first transistor M1 (i.e., the first node N1) and the second electrode of the first transistor M1 (i.e., the second node N2) may be electrically connected to each other, and accordingly, the first transistor M1 may be diode-connected.

[0093] The fourth transistor M4 can be connected between the second node N2 and the third node N3 (i.e., the first electrode of the light-emitting element LD). The gate electrode of the fourth transistor M4 can be electrically connected to the second emission control line EL2i. The fourth transistor M4 can be turned off when the second emission control signal EM2 is supplied to the second emission control line EL2i, and can be turned on when the second emission control signal EM2 is not supplied. When the fourth transistor M4 is turned off, the first transistor M1 and the light-emitting element LD can be electrically disconnected from each other.

[0094] A first electrode of the fifth transistor M5 may be coupled to the third node N3, and a second electrode of the fifth transistor M5 may be electrically coupled to the third power line PL3. A gate electrode of the fifth transistor M5 may be electrically coupled to the third scan line SL3i. The fifth transistor M5 may be turned on when the third scan signal GB is supplied to the third scan line SL3i. When the fifth transistor M5 is turned on, the voltage of the initialization power supply Vint may be supplied to the third node N3.

[0095] A first electrode of the sixth transistor M6 may be electrically connected to the first power line PL1, and a second electrode of the sixth transistor M6 may be connected to the first electrode of the first transistor M1. A gate electrode of the sixth transistor M6 may be electrically connected to the first emission control line EL1i. The sixth transistor M6 may be turned off when the first emission control signal EM1 is supplied to the first emission control line EL1i, and may be turned on when the first emission control signal EM1 is not supplied. When the sixth transistor M6 is turned off, the first power line PL1 and the first transistor M1 may be electrically disconnected from each other.

[0096] A first electrode of the first capacitor C1 may be connected to a second electrode of the second transistor M2, and a second electrode of the first capacitor C1 may be connected to a first node N1. The first capacitor C1 may change the voltage of the first node N1 in accordance with the voltage supplied from the second transistor M2. In an embodiment, the first capacitor C1 may be driven as a coupling capacitor.

[0097] The first electrode of the second capacitor C2 may be electrically connected to the first power line PL1, and the second electrode of the second capacitor C2 may be connected to the first node N1. For example, the second capacitor C2 may be connected between the first power line PL1 and the first node N1. The second capacitor C2 may store the voltage of the first node N1.

[0098] Figure 4 Is shown driving Figure 3 Schematic waveform diagram of an embodiment of the method for a pixel shown in FIG.

[0099] Reference Figure 4 A horizontal period 1H (or a specific horizontal period) in which data signals are supplied to pixels PXij located on the i-th horizontal line and the j-th vertical line can be divided into a first period T1, a second period T2, and a third period T3. The horizontal period 1H can further include a fourth period T4.

[0100] The data driver 140 (eg, Figure 1) can supply the voltage of the reference power supply Vref to the data line DLj during the first period T1 and the second period T2, and supply the voltage Vdata(i) of the data signal during the third period T3. The reference power supply Vref can be set to a voltage between the first driving power supply VDD and the second driving power supply VSS (for example, a specific voltage within the voltage range of the data signal). The voltage Vdata(i) of the data signal can be set to a voltage corresponding to the grayscale within the voltage range of the data signal.

[0101] The scan driver 130 (or the first scan driver 132) (for example, see Figure 2 ) may supply the first scan signal GW to the first scan line SL1i during the first to third periods T1 to T3.

[0102] The scan driver 130 (or the second scan driver 134) (for example, see Figure 2 ) may supply the second scan signal GC to the second scan line SL2i during the first period T1 and the second period T2.

[0103] Scan driver 130 (or third scan driver 136) (for example, see Figure 2 ) The third scan signal GB may be supplied to the third scan line SL3i during a zeroth period T0 before the first period T1 to a fourth period T4 after the third period T3. The zeroth period T0 may be a period included in the previous horizontal period (for example, a period in which data signals are supplied to pixels located on the (i-1)th horizontal line). The fourth period T4 may be a period included in the next horizontal period (for example, a period in which data signals are supplied to pixels located on the (i+1)th horizontal line).

[0104] The transmit driver 150 (or the first transmit driver 152) (for example, see Figure 2 ) may supply the first emission control signal EM1 to the first emission control line EL1i during the zeroth period T0 and the first period T1.

[0105] The transmit driver 150 (or the second transmit driver 154) (for example, see Figure 2 ) may supply the second emission control signal EM2 to the second emission control line EL2i during the second period T2 and the third period T3.

[0106] The zeroth period T0 may be a period in which the voltage of the initialization power supply Vint is supplied to the third node N3 and the second node N2. During the zeroth period T0, the first electrode of the light emitting element LD may be initialized by the voltage of the initialization power supply Vint. The zeroth period T0 may be referred to as a first initialization period.

[0107] The first period T1 may be a period in which the voltage of the initialization power supply Vint is supplied to the first node N1, the second node N2, and the third node N3, and the voltage of the reference power supply Vref is supplied to the first electrode of the first capacitor C1. During the first period T1, the first capacitor C1 may be initialized by the voltage of the reference power supply Vref and the voltage of the initialization power supply Vint. The first period T1 may be referred to as a second initialization period (or initialization period).

[0108] The second period T2 may be a period in which a voltage corresponding to the threshold voltage of the first transistor M1 is stored in the second capacitor C2. The second period T2 may be referred to as a threshold voltage compensation period.

[0109] The third period T3 may be a period in which the voltage Vdata(i) of the data signal is supplied from the data line DLj to the pixel PXij. During the third period T3, a voltage corresponding to the data signal may be applied to the first node N1. The third period T3 may be referred to as a data write period.

[0110] During the fourth period T4, the first transistor M1 can control the amount of current supplied from the first driving power supply VDD to the initialization power supply Vint corresponding to the voltage of the first node N1. This can prevent unnecessary current from being supplied to the light emitting element LD after the third period T3. The fourth period T4 can be referred to as a brightness control period.

[0111] During the fifth period T5, the first transistor M1 can control the amount of current flowing from the first driving power source VDD to the second driving power source VSS via the light-emitting element LD in accordance with the voltage of the first node N1. During the fifth period T5, the light-emitting element LD can emit light at a brightness corresponding to the amount of current. The fifth period T5 can be referred to as an emission period.

[0112] Figures 5A to 5F is a graph showing the pixel Figure 4 Schematic diagram of the operation process corresponding to the driving waveform shown in FIG.

[0113] Reference Figure 5A , during the zeroth period T0 , the first emission control signal EM1 may be supplied to the first emission control line EL1i, and accordingly, the sixth transistor M6 may be turned off.

[0114] During the zeroth period T0, the third scan signal GB may be supplied to the third scan line SL3i, and accordingly, the fifth transistor M5 may be turned on. When the fifth transistor M5 is turned on, the voltage of the initialization power supply Vint may be supplied to the third node N3 and the second node N2.

[0115] When the voltage of the initialization power supply Vint is supplied to the third node N3, the first electrode of the light-emitting element LD can be initialized by the voltage of the initialization power supply Vint. The initialization power supply Vint can be set to a voltage at which the light-emitting element LD does not emit light, and accordingly, the light-emitting element LD can be set to a non-emitting state. In an embodiment, a voltage value obtained by subtracting the second driving power supply VSS from a voltage obtained by adding the absolute threshold voltage of the fifth transistor M5 to the voltage of the initialization power supply Vint can be set to a voltage lower than the threshold voltage of the light-emitting element LD.

[0116] During the zeroth period T0 , the second transistor M2 may be set to be in a turned-off state, and accordingly, the voltage Vdata(i−1) of the data signal corresponding to the previous horizontal line may not be supplied to the pixel PXij.

[0117] Reference Figure 5B , during the first period T1, the first emission control signal EM1 may be supplied to the first emission control line EL1i, and accordingly, the sixth transistor M6 may maintain a turned-off state.

[0118] During the first period T1 , the first scan signal GW may be supplied to the first scan line SL1 i , the second scan signal GC may be supplied to the second scan line SL2 i , and the third scan signal GB may be supplied to the third scan line SL3 i .

[0119] When the first scan signal GW is supplied to the first scan line SL1i, the second transistor M2 may be turned on. When the second transistor M2 is turned on, the data line DLj and the first electrode of the first capacitor C1 may be electrically connected to each other.

[0120] When the second scan signal GC is supplied to the second scan line SL2i, the third transistor M3 may be turned on. When the third transistor M3 is turned on, the first node N1 and the second node N2 may be electrically connected to each other.

[0121] When the third scan signal GB is supplied to the third scan line SL3i, the fifth transistor M5 may be turned on. When the fifth transistor M5 is turned on, the third power line PL3 and the third node N3 may be electrically connected to each other.

[0122] During the first period T1, the voltage of the reference power supply Vref can be supplied to the first electrode of the first capacitor C1, and the voltage of the initialization power supply Vint can be supplied to the first node N1. The first capacitor C1 can be initialized by the reference power supply Vref and the initialization power supply Vint, regardless of the voltage supplied in the previous period (or the previous frame period). Similarly, the second capacitor C2 can be initialized by the initialization power supply Vint and the first driving power supply VDD, regardless of the voltage supplied in the previous period (or the previous frame period).

[0123] The voltage of the initialization power supply Vint applied to the first node N1 (or a voltage obtained by adding the absolute threshold voltage of the fifth transistor M5 to the initialization power supply Vint) can be set to a voltage lower than the voltage of the first driving power supply VDD. In an embodiment, the voltage of the initialization power supply Vint can be set to a voltage at which the first transistor M1 can be turned on when the voltage of the first driving power supply VDD is applied to the first electrode of the first transistor M1.

[0124] Reference Figure 5C , during the second period T2, the second emission control signal EM2 may be supplied to the second emission control line EL2i, and accordingly, the fourth transistor M4 may be turned off.

[0125] During the second period T2, the second transistor M2 may be turned on by the first scan signal GW supplied to the first scan line SL1i, the third transistor M3 may be turned on by the second scan signal GC supplied to the second scan line SL2i, and the fifth transistor M5 may be turned on by the third scan signal GB supplied to the third scan line SL3i. In addition, during the second period T2, the supply of the first emission control signal EM1 to the first emission control line EL1i may be suspended so that the sixth transistor M6 is turned on.

[0126] When the third transistor M3 is turned on, the first transistor M1 can be diode-connected. Since the sixth transistor M6 is set to be in an on state during the second period T2, the voltage of the first driving power supply VDD can be applied to the first electrode of the first transistor M1. When the voltage of the first driving power supply VDD is applied to the first electrode of the first transistor M1, the diode-connected first transistor M1 can be turned on, and accordingly, a voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the first driving power supply VDD can be applied to the first node N1. A voltage corresponding to the threshold voltage of the first transistor M1 can be stored in the second capacitor C2.

[0127] During the second period T2, the voltage of the reference power supply Vref may be supplied to the first electrode of the first capacitor C1. Therefore, during the second period T2, a voltage corresponding to the voltage difference between the reference power supply Vref and the first node N1 may be stored in the first capacitor C1. Since the fifth transistor M5 remains in the on state during the second period T2, the voltage of the initialization power supply Vint may be applied to the third node N3.

[0128] Reference Figure 5D During the third period T3, the second emission control signal EM2 may be supplied to the second emission control line EL2i, and accordingly, the fourth transistor M4 may remain in the off state. In addition, during the third period T3, the first emission control signal EM1 may not be supplied to the first emission control line EL1i, and accordingly, the sixth transistor M6 may remain in the on state.

[0129] During the third period T3 , the turn-on state of the second transistor M2 may be maintained by the first scan signal GW supplied to the first scan line SL1 i , and the turn-on state of the fifth transistor M5 may be maintained by the third scan signal GB supplied to the third scan line SL3 i .

[0130] During the third period T3 , the voltage Vdata(i) of the data signal may be supplied to the data line DLj. The voltage Vdata(i) of the data signal supplied to the data line DLj may be supplied to the first electrode of the first capacitor C1 via the second transistor M2 .

[0131] When the voltage Vdata(i) of the data signal is supplied to the first electrode of the first capacitor C1, the first electrode of the first capacitor C1 can change from the voltage of the reference power supply Vref to the voltage Vdata(i) of the data signal. The voltage of the first node N1 can also change due to the coupling of the first capacitor C1.

[0132] The voltage change of the first node N1 may be determined by the ratio of the first capacitor C1 to the second capacitor C2. In an embodiment, the voltage of the first node N1 may be changed from the voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the first driving power supply VDD to a value obtained by multiplying the voltage change of the first electrode of the first capacitor C1 by C1 / (C1+C2). When the voltage change of the first node N1 is controlled by the ratio of the first capacitor C1 to the second capacitor C2, the voltage range of the data signal can be set to be sufficiently wide.

[0133] In an embodiment, when the data signal is directly supplied to the gate electrode of the first transistor M1, the voltage range of the data signal can be set to be relatively narrow. When the data signal has a narrow voltage range, various grayscales (e.g., 256 grayscales) may be implemented using the narrow voltage range, and accordingly, accurate grayscale representation may be difficult.

[0134] On the other hand, in the embodiment of the present disclosure, when the voltage supplied to the gate electrode of the first transistor M1 is controlled by the ratio of the first capacitor C1 and the second capacitor C2, the voltage range of the data signal can be set to be sufficiently wide. For example, a voltage corresponding to the value obtained by multiplying the voltage of the data signal by C1 / (C1+C2) can be transmitted to the gate electrode of the first transistor M1, and accordingly, the voltage range of the data signal can be set to be wide. When the data signal has a wide voltage range, grayscale can be easily achieved.

[0135] When the pixel PXij is applied to a high-resolution panel, an image may be displayed using a low drive current, and thus the voltage range of the data signal may be narrowed. In the case of the pixel PXij of the present disclosure, the data signal can have a wide voltage range, and accordingly, the pixel PXij can be applied to a high-resolution panel.

[0136] During the third period T3, the second capacitor C2 may store the voltage of the first node N1. The voltage of the first node N1 may be determined by the threshold voltage of the first transistor M1 and the voltage Vdata(i) of the data signal, and accordingly, during the third period T3, a voltage corresponding to the data signal and the threshold voltage of the first transistor M1 may be stored in the second capacitor C2.

[0137] Reference Figure 5E During the fourth period T4, the first emission control signal EM1 may not be supplied to the first emission control line EL1i, and the second emission control signal EM2 may not be supplied to the second emission control line EL2i. Therefore, the sixth transistor M6 and the fourth transistor M4 may be set to be in the on state during the fourth period T4. During the fourth period T4, the third scan signal GB may be supplied to the third scan line SL3i, and accordingly, the fifth transistor M5 may remain in the on state.

[0138] During the fourth period T4, the sixth transistor M6 and the fourth transistor M4, which are located on the current path for supplying current to the light-emitting element LD, can be set to be in a conductive state, and accordingly, the first transistor M1 can control the amount of current supplied from the first driving power supply VDD to the third node N3 in accordance with the voltage applied to the first node N1. Since the fifth transistor M5 is set to be in a conductive state, the current supplied to the third node N3 can be supplied to the initialization power supply Vint. For example, during the fourth period T4, the light-emitting element LD can be set to a non-emitting state, and accordingly, the grayscale representation capability of the display device 100 can be improved.

[0139] For example, after the second period T2 and the third period T3, the voltage of the second node N2 can be set to be approximately the voltage of the first driving power supply VDD. In the case where the voltage of the second node N2 is set to be approximately the voltage of the first driving power supply VDD, unnecessary current may be supplied to the light emitting element LD. In an embodiment, even in the case where a black grayscale is achieved in the pixel PXij, light may be emitted from the light emitting element LD by the voltage of the second node N2. Therefore, in an embodiment of the present disclosure, during the fourth period T4 before the light emitting element LD emits light, the current supplied from the first transistor M1 may be supplied to the initialization power supply Vint, and accordingly, the display device 100 (for example, referring to Figure 1 )’s grayscale representation capability.

[0140] Reference Figure 5F During the fifth period T5, the supply of the third scan signal GB to the third scan line SL3i may be suspended, so that the fifth transistor M5 is set to be in a turned-off state.

[0141] The first transistor M1 may control the amount of current supplied from the first driving power source VDD to the second driving power source VSS via the light emitting element LD corresponding to the voltage of the first node N1. During the fifth period T5, the light emitting element LD may generate light having brightness corresponding to the amount of driving current supplied from the first transistor M1.

[0142] As shown in Equation 1, the amount of current supplied from the first transistor M1 to the light emitting element LD during the fifth period T5 may be determined regardless of the threshold voltage of the first transistor M1 .

[0143] [Formula 1]

[0144]

[0145] In Formula 1, ILD may be a current supplied to the light emitting element LD, and K may be a proportionality constant determined by mobility, parasitic capacitance, channel capacity, and the like of the first transistor M1.

[0146] Referring to Equation 1, it can be seen that the amount of current supplied from the first transistor M1 is determined by the voltage Vdata(i) of the data signal and the reference power supply Vref, regardless of the threshold voltage of the first transistor M1.

[0147] In the pixel PX (for example, refer to Figure 1 ) is applied to a high-resolution panel, the pixel PX may have a small mounting area (eg, several micrometers). Figure 1 ) is connected to different source amplifiers included in the data driver 140, the mounting area of ​​the source amplifier may become wider than the mounting area of ​​the pixel PX. Therefore, in an embodiment of the present disclosure, a distributor or the like may be used to minimize the mounting area of ​​the source amplifier.

[0148] Figure 6 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure. Figure 7 and Figure 8 It shows Figure 6 A schematic diagram of an embodiment of a dispenser is shown in FIG. Figure 6 In, with Figure 1 The same components as those shown in FIG. 1 are denoted by the same reference numerals, and duplicate descriptions will be omitted.

[0149] Reference Figure 6 , a display device 100 a according to an embodiment of the present disclosure may include a pixel unit 110 (or panel), a timing controller 120 , a scan driver 130 , a data driver 140 , an emission driver 150 , a power supply 160 , and a distributor 170 .

[0150] The data driver 140 may receive output data Dout and a data drive signal DCS from the timing controller 120. The data drive signal DCS may include a sampling signal and / or a timing signal for driving the data driver 140. The data driver 140 may generate a data signal based on the data drive signal DCS and the output data Dout. In an embodiment, the data driver 140 may generate an analog data signal based on the grayscale of the output data Dout. The data driver 140 may sequentially supply a plurality of data signals to each of the output lines O1, O2, ... and Ok (k is a natural number less than m and greater than 0) during one horizontal period 1H. In an embodiment, the data driver 140 may sequentially supply three data signals to each of the output lines O1 to Ok within each horizontal period 1H. In addition, the data driver 140 may supply a reference power supply Vref (e.g., reference voltage Vref) to the output lines O1 to Ok within at least two horizontal periods 1H. Figure 4 )) voltage.

[0151] The distributor 170 may be connected to the output lines O1 to Ok and the data lines DL1, DL2, DL3, DL4, DL5, DL6, ..., DLm-2, DLm-1, and DLm. The distributor 170 may supply a plurality of data signals supplied from each of the output lines O1 to Ok to the plurality of data lines. To this end, the distributor 170 may include a plurality of demultiplexers (or multiplexers) 172a, 172b, 172c, ... or a plurality of demultiplexers (or multiplexers) 172aa, 172bb, 172cc, ..., such as Figure 7 and Figure 8 Herein, multiplexers 172a, 172b, 172c, ... may refer to multiplexers 172a, 172b, and 172c, etc., and multiplexers 172aa, 172bb, 172cc, ... may refer to multiplexers 172aa, 172bb, and 172cc, etc.

[0152] In the case where the data signals generated by the data driver 140 are supplied to the data lines DL1 to DLm via the distributor 170, the number of output lines O1 to Ok connected to the data driver 140 can be reduced. In other words, in the case where the data signals generated by the data driver 140 are supplied to the data lines DL1 to DLm via the distributor 170, the number of source amplifiers respectively connected to the output lines O1 to Ok can be reduced, and accordingly, the pixel PX can be applied to a high-resolution panel.

[0153] Reference Figure 7 The distributor 170 may include multiplexers 172a, 172b, 172c, .... The multiplexer 172a may supply the voltage of the reference power supply Vref supplied from the first output line O1 and the data signal to the data lines DL1, DL2, and DL3. The data lines DL1, DL2, and DL3 may be connected to pixels PX(R), PX(G), and PX(B) that emit light of different colors.

[0154] In an embodiment, the first data line DL1 may be electrically connected to a pixel PX(R) of a first color, the second data line DL2 may be electrically connected to a pixel PX(G) of a second color, and the third data line DL3 may be electrically connected to a pixel PX(B) of a third color. In an embodiment, the first color may be red, the second color may be green, and the third color may be blue.

[0155] The multiplexer 172b can supply the voltage of the reference power supply Vref supplied from the second output line O2 and the data signal to the data lines DL4, DL5 and DL6. The data lines DL4, DL5 and DL6 can be connected to pixels PX(R), PX(G) and PX(B) emitting light of different colors.

[0156] The multiplexer 172c can supply the voltage of the reference power supply Vref supplied from the third output line O3 and the data signal to the data lines DL7, DL8 and DL9. The data lines DL7, DL8 and DL9 can be connected to pixels PX(R), PX(G) and PX(B) emitting light of different colors.

[0157] Each of the multiplexers 172a, 172b, and 172c may include a first switch SW1, a second switch SW2, and a third switch SW3. The first switch SW1 may be turned on or off in response to a first control signal CLA, the second switch SW2 may be turned on or off in response to a second control signal CLB, and the third switch SW3 may be turned on or off in response to a third control signal CLC.

[0158] Supplying the first control signal CLA, the second control signal CLB, and the third control signal CLC may mean supplying a voltage (e.g., a low voltage) at which each of the first switch SW1, the second switch SW2, and the third switch SW3 is turned on. Not supplying the first control signal CLA, the second control signal CLB, and the third control signal CLC may mean supplying a voltage (e.g., a high voltage) at which each of the first switch SW1, the second switch SW2, and the third switch SW3 is turned off.

[0159] The first switch SW1 included in the multiplexer 172a may be connected between the first output line O1 and the first data line DL1 and may be connected between the first output line O1 and the first data line DL1 when the slave timing controller 120 (eg, referring to FIG. 1 ) is switched on. Figure 6 ) is turned on when a first control signal CLA (eg, a low voltage) is supplied. When the first switch SW1 is turned on, the first output line O1 and the first data line DL1 may be electrically connected to each other.

[0160] The second switch SW2 included in the multiplexer 172a may be connected between the first output line O1 and the second data line DL2, and may be turned on when a second control signal CLB (e.g., a low voltage) is supplied from the timing controller 120. When the second switch SW2 is turned on, the first output line O1 and the second data line DL2 may be electrically connected to each other.

[0161] The third switch SW3 included in the multiplexer 172a may be connected between the first output line O1 and the third data line DL3, and may be turned on when a third control signal CLC (e.g., a low voltage) is supplied from the timing controller 120. When the third switch SW3 is turned on, the first output line O1 and the third data line DL3 may be electrically connected to each other.

[0162] The first switch SW1 included in the multiplexer 172b can be connected between the second output line O2 and the fourth data line DL4, the second switch SW2 included in the multiplexer 172b can be connected between the second output line O2 and the fifth data line DL5, and the third switch SW3 included in the multiplexer 172b can be connected between the second output line O2 and the sixth data line DL6.

[0163] The first switch SW1 included in the multiplexer 172c can be connected between the third output line O3 and the seventh data line DL7, the second switch SW2 included in the multiplexer 172c can be connected between the third output line O3 and the eighth data line DL8, and the third switch SW3 included in the multiplexer 172c can be connected between the third output line O3 and the ninth data line DL9.

[0164] Reference Figure 8 , the distributor 170 may include multiplexers 172aa, 172bb, 172cc, . . .

[0165] The multiplexer 172aa may supply the voltage of the reference power supply Vref supplied from the first output line O1 and the data signal to the data lines DL1, DL4, and DL7. The data lines DL1, DL4, and DL7 may be connected to pixels PX(R) emitting first color light (emitting light of the same color).

[0166] The multiplexer 172bb can supply the voltage of the reference power supply Vref supplied from the second output line O2 and the data signal to the data lines DL2, DL5 and DL8. The data lines DL2, DL5 and DL8 can be connected to pixels PX (G) emitting second color light (emitting light of the same color).

[0167] The multiplexer 172cc may supply the voltage of the reference power supply Vref supplied from the third output line O3 and the data signal to the data lines DL3, DL6, and DL9. The data lines DL3, DL6, and DL9 may be connected to pixels PX(B) emitting light of a third color (emitting light of the same color).

[0168] Each of the multiplexers 172aa, 172bb, 172cc, ... may include a first switch SW1, a second switch SW2, and a third switch SW3. The first switch SW1 may be turned on or off in response to a first control signal CLA, the second switch SW2 may be turned on or off in response to a second control signal CLB, and the third switch SW3 may be turned on or off in response to a third control signal CLC.

[0169] The first switch SW1 included in the multiplexer 172aa may be connected between the first output line O1 and the first data line DL1 and turned on when the first control signal CLA is supplied from the timing controller 120. When the first switch SW1 is turned on, the first output line O1 and the first data line DL1 may be electrically connected to each other.

[0170] The second switch SW2 included in the multiplexer 172aa may be connected between the first output line O1 and the fourth data line DL4 and turned on when the second control signal CLB is supplied from the timing controller 120. When the second switch SW2 is turned on, the first output line O1 and the fourth data line DL4 may be electrically connected to each other.

[0171] The third switch SW3 included in the multiplexer 172aa may be connected between the first output line O1 and the seventh data line DL7 and turned on when the third control signal CLC is supplied from the timing controller 120. When the third switch SW3 is turned on, the first output line O1 and the seventh data line DL7 may be electrically connected to each other.

[0172] The first switch SW1 included in the multiplexer 172bb can be connected between the second output line O2 and the second data line DL2, the second switch SW2 included in the multiplexer 172bb can be connected between the second output line O2 and the fifth data line DL5, and the third switch SW3 included in the multiplexer 172bb can be connected between the second output line O2 and the eighth data line DL8.

[0173] The first switch SW1 included in the multiplexer 172cc can be connected between the third output line O3 and the third data line DL3, the second switch SW2 in the multiplexer 172cc can be connected between the third output line O3 and the sixth data line DL6, and the third switch SW3 included in the multiplexer 172cc can be connected between the third output line O3 and the ninth data line DL9.

[0174] Figure 9 is a schematic diagram showing pixels located on the (i-1)th horizontal line and the i-th horizontal line. Figure 10 Is shown driving Figure 9 Schematic waveform diagram of the pixel method shown in FIG.

[0175] Reference Figures 6 to 10In an embodiment of the present disclosure, pixels located on at least two horizontal lines may share a first period T1 and a second period T2. In an embodiment, the first period T1 and the second period T2 of the pixel PXi-1j located on the (i-1)th horizontal line and the pixel PXij located on the i-th horizontal line may overlap with each other. In an embodiment, the pixel PXi-1j located on the (i-1)th horizontal line and the pixel PXij located on the i-th horizontal line may be simultaneously supplied with a reference power supply Vref (e.g., reference power Vref). Figure 4 ) voltage.

[0176] During the first and second periods T1 and T2, the data driver 140 may supply a voltage of the reference power supply Vref to each of the output lines O1 to Ok. During the first and second periods T1 and T2, the timing controller 120 may supply the first and third control signals CLA and CLC (or the first, second, and third control signals CLA, CLB, and CLC) to the distributor 170. During the first and second periods T1 and T2, the first to third switches SW1 to SW3 included in each of the multiplexers 172a, 172b, 172c, ... or 172aa, 172bb, 172cc, ... may be turned on. During the first and second periods T1 and T2, the voltage of the reference power supply Vref may be supplied to the data lines DL1 to DLm.

[0177] During the first period T1 , the first emission control signal EM1 may be supplied to the first emission control lines EL1i-1 and EL1i, and accordingly, the sixth transistor M6 included in each of the pixels PXi-1j and PXij may be turned off.

[0178] During the first period T1, the first scan signal GW may be supplied to the first scan lines SL1i-1 and SL1i, the second scan signal GC may be supplied to the second scan lines SL2i-1 and SL2i, and the third scan signal GB may be supplied to the third scan lines SL3i-1 and SL3i.

[0179] When the first scan signal GW is supplied to the first scan lines SL1i-1 and SL1i, the second transistor M2 included in each of the pixels PXi-1j and PXij may be turned on. When the second scan signal GC is supplied to the second scan lines SL2i-1 and SL2i, the third transistor M3 included in each of the pixels PXi-1j and PXij may be turned on. When the third scan signal GB is supplied to the third scan lines SL3i-1 and SL3i, the fifth transistor M5 included in each of the pixels PXi-1j and PXij may be turned on.

[0180] During the first period T1, the voltage of the reference power supply Vref can be supplied to the first electrode of the first capacitor C1 included in each of the pixels PXi-1j and PXij, and the voltage of the initialization power supply Vint can be supplied to the first node N1. The first capacitor C1 included in each of the pixels PXi-1j and PXij can be initialized by the reference power supply Vref and the initialization power supply Vint, regardless of the voltage supplied in the previous period (or previous frame period). Similarly, the second capacitor C2 included in each of the pixels PXi-1j and PXij can be initialized by the initialization power supply Vint and the first driving power supply VDD, regardless of the voltage supplied in the previous period (or previous frame period).

[0181] During the second period T2 , the second emission control signal EM2 may be supplied to the second emission control lines EL2 i - 1 and EL2 i , and accordingly, the fourth transistor M4 included in each of the pixels PXi- 1 j and PXij may be turned off.

[0182] During the second period T2, the second transistor M2 included in each of the pixels PXi-1j and PXij may be turned on by the first scan signal GW supplied to the first scan lines SL1i-1 and SL1i, the third transistor M3 included in each of the pixels PXi-1j and PXij may be turned on by the second scan signal GC supplied to the second scan lines SL2i-1 and SL2i, and the fifth transistor M5 included in each of the pixels PXi-1j and PXij may be turned on by the third scan signal GB supplied to the third scan lines SL3i-1 and SL3i. In addition, during the second period T2, the supply of the first emission control signal EM1 to the first emission control lines EL1i-1 and EL1i may be suspended so that the sixth transistor M6 included in each of the pixels PXi-1j and PXij is turned on.

[0183] When the third transistor M3 included in each of pixels PXi-1j and PXij is turned on, the first transistor M1 included in each of pixels PXi-1j and PXij can be diode-connected. Since the sixth transistor M6 included in each of pixels PXi-1j and PXij is set to be in an on state during the second period T2, the voltage of the first driving power supply VDD can be applied to the first electrode of the first transistor M1 included in each of pixels PXi-1j and PXij. When the voltage of the first driving power supply VDD is applied to the first electrode of the first transistor M1, the diode-connected first transistor M1 can be turned on, and accordingly, a voltage obtained by subtracting the absolute threshold voltage of the first transistor M1 from the first driving power supply VDD can be applied to the first node N1. A voltage corresponding to the threshold voltage of the first transistor M1 can be stored in the second capacitor C2 included in each of pixels PXi-1j and PXij.

[0184] During the second period T2, the voltage of the reference power supply Vref may be supplied to the first electrode of the first capacitor C1 included in each of the pixels PXi-1j and PXij. Therefore, during the second period T2, a voltage corresponding to the voltage difference between the reference power supply Vref and the first node N1 may be stored in the first capacitor C1. Since the fifth transistor M5 included in each of the pixels PXi-1j and PXij remains in the on state during the second period T2, the voltage of the initialization power supply Vint may be applied to the third node N3.

[0185] During the third period T3 and the fourth period T4, the first scan signal GW may not be supplied to the first scan line SL1i, and accordingly, the voltages Vdataa, Vdatab, and Vdatac of the data signal may not be supplied to the pixel PXij located on the i-th horizontal line. During the third period T3, the third period T3a, and the fourth period T4a, the third scan signal GB may be supplied to the third scan line SL3i, and accordingly, the fifth transistor M5 included in the pixel PXij may maintain a turned-on state.

[0186] The third period T3 may be included in the previous horizontal period and may be a period in which the voltages Vdataa, Vdatab, and Vdatac of the data signal are supplied to the pixel PXi-1j located on the (i-1)th horizontal line. The third period T3a may be included in the current horizontal period and may be a period in which the voltages Vdataa, Vdatab, and Vdatac of the data signal are supplied to the pixel PXij located on the i-th horizontal line.

[0187] The fourth period T4 may be a brightness control period, and the fifth period T5 may be an emission period of the pixel PXi-1j. The fourth period T4 may overlap with the third period T3a. The fifth period T5 may overlap with the third period T3a, the fourth period T4a, and the fifth period T5a.

[0188] In the third period T3, the second emission control signal EM2 may be supplied to the second emission control line EL2i-1, and accordingly, the fourth transistor M4 included in the pixel PXi-1j may be maintained in the off state. In addition, in the third period T3, the second transistor M2 included in the pixel PXi-1j may be set to be in the on state by the first scan signal GW supplied to the first scan line SL1i-1.

[0189] During the third period T3, the timing controller 120 may sequentially supply the first control signal CLA, the second control signal CLB, and the third control signal CLC. During the third period T3, the voltages Vdataa, Vdatab, and Vdatac of the data signals may be sequentially supplied to the data lines connected to the multiplexers 172a, 172b, 172c, ... or 172aa, 172bb, 172cc, ..., and accordingly, the voltages of the data signals may be stored in the pixels PXi-1j. The operation process of the third period T3 is similar to that of the reference period T3. Figure 5D In addition, the operation process of the fourth period T4 and the fifth period T5 is similar to that of the reference period T4. Figure 5E and Figure 5F The described embodiments are similar, and therefore, repeated descriptions will be omitted.

[0190] During the third period T3a, the second emission control signal EM2 may be supplied to the second emission control line EL2i, and accordingly, the fourth transistor M4 included in the pixel PXij may be maintained in the off state. In the third period T3a, the second transistor M2 included in the pixel PXij may be set to be in the on state by the first scan signal GW supplied to the first scan line SL1i.

[0191] During the third period T3a, the timing controller 120 may sequentially supply the first control signal CLA, the second control signal CLB, and the third control signal CLC. During the third period T3a, the voltages Vdataa, Vdatab, and Vdatac of the data signals may be sequentially supplied to the data lines connected to the multiplexers 172a, 172b, 172c, ... or 172aa, 172bb, 172cc, ..., and accordingly, the voltages of the data signals may be stored in the pixels PXij. The operation process of the third period T3a is similar to that of the reference period. Figure 5DIn addition, the operation process of the fourth period T4a and the fifth period T5a is the same as that of the reference period T4a. Figure 5E and Figure 5F The described embodiments are similar, and therefore, repeated descriptions will be omitted.

[0192] Therefore, in the embodiment of the present disclosure, the pixels PXi-1j and PXij located on two horizontal lines can share the first period T1 and the second period T2, so that the driving time of the distributor 170 (or the multiplexers 172a, 172b, 172c, ... or 172aa, 172bb, 172cc, ...) can be ensured. Figure 10 , the pixels PXi-1j and PXij on two horizontal lines share the first period T1 and the second period T2, but the present disclosure is not limited thereto. For example, pixels on at least three horizontal lines may share the first period T1 and the second period T2, and accordingly, the driving time of the distributor 170 may be ensured.

[0193] Figure 11 FIG is a schematic diagram showing the output channels of a data driver. Figure 11 In FIG, an output channel connected to a first output line O1 is shown.

[0194] Reference Figure 11 , the output channel of the data driver 140 according to an embodiment of the present disclosure may include a buffer BF (or a source amplifier), a first decoder 182 , and a second decoder 184 .

[0195] The output terminal of the buffer BF may be connected to the output line O1. The input terminal of the buffer BF may be connected to the first decoder 182 via the first switch SW1a. The input terminal of the buffer BF may be connected to the second decoder 184 via the second switch SW2a. The buffer BF may supply the data signal supplied from the first decoder 182 or the reference power supply Vref (e.g., reference voltage Vref) supplied from the second decoder 184 to the output line O1. Figure 4 ) voltage.

[0196] The first decoder 182 may correspond to the slave timing controller 120 (eg, Figure 6 ) input output data Dout (for example, refer to Figure 6 ) selects a gamma voltage supplied from a gamma supply part (not shown) and supplies the selected gamma voltage to the buffer BF via the first switch SW1a. The gamma voltage selected by the output data Dout may be a data signal.

[0197] The second decoder 184 may select a specific voltage among the gamma voltages generated by the gamma supply part as the voltage of the reference power source Vref and supply the voltage of the reference power source Vref to the buffer BF via the second switch SW2 a .

[0198] The first switch SW1a may be connected between the first decoder 182 and the buffer BF. The first switch SW1a may be switched in response to the voltage control signal VCS supplied from the timing controller 120. Figure 10 It is turned on during the third period T3 and the third period T3a shown in FIG.

[0199] The second switch SW2a may be connected between the second decoder 184 and the buffer BF. The second switch SW2a may be switched in response to the voltage control signal VCS supplied from the timing controller 120. Figure 10 It is turned on during the first period T1 and the second period T2 shown in FIG.

[0200] In an embodiment of the present disclosure, the data signal and the reference power Vref can be supplied to the output line O1 via the same buffer BF. The offset of the buffer BF included in the data signal and the offset of the reference power Vref included in the buffer BF can be offset, and accordingly, the display quality can be improved.

[0201] Figure 12 and Figure 13 is a schematic diagram illustrating a connection between a timing controller and a distributor according to an embodiment of the present disclosure.

[0202] Reference Figure 12 , the timing controller 120 (eg, referring to Figure 6 ) can supply the control signals CLA, CLB and CLC (or at least one of the control signals CLA, CLB and CLC) to the main line ML.

[0203] The first main buffer MBF1 may be installed at a first side of the main line ML, and the second main buffer MBF2 may be installed at a second side of the main line ML. The first side may be one side (e.g., the left side) of the main line ML, and the second side may be the other side (e.g., the right side) of the main line ML. The timing controller 120 may supply control signals CLA, CLB, and CLC to the main line ML via the first main buffer MBF1 and the second main buffer MBF2.

[0204] Multiple branch lines BL may branch from the main line ML. A sub-buffer SBF may be connected to one of the branch lines BL. Each of the sub-buffers SBF may be connected to multiple multiplexers DEMUX. The sub-buffer SBF may supply control signals CLA, CLB, and CLC from the main line ML to the multiplexers DEMUX connected to the sub-buffer SBF.

[0205] In an embodiment of the present disclosure, main buffers MBF1 and MBF2 can be used to supply control signals CLA, CLB, and CLC to the main line ML, and a sub-buffer SBF can be added to the branch line BL branching from the main line ML to supply the control signals CLA, CLB, and CLC to the multiplexer DEMUX. The delay of the control signals CLA, CLB, and CLC can be minimized.

[0206] The multiplexer DEMUX located at the center of the main line ML may be connected to two sub-buffers SBF. In an embodiment, the multiplexer DEMUX located at the center of the main line ML may be supplied with control signals CLA, CLB, and CLC from the sub-buffers SBF located at the first and second sides of the multiplexer DEMUX. However, the present disclosure is not limited thereto, and as Figure 13 As shown in , the multiplexer DEMUX located at the central portion of the main line ML may be electrically connected to one sub-buffer SBF.

[0207] Despite Figure 12 and Figure 13 , an embodiment in which the control signals CLA, CLB, and CLC are supplied to one main line ML is shown, but the present disclosure is not limited thereto. In another embodiment, three main lines ML may be formed (or arranged) corresponding to each of the control signals CLA, CLB, and CLC, and the sub-buffer SBF may be formed (or arranged) to be connected to one of the branch lines BL branching from one of the three main lines ML.

[0208] Figure 14A is a schematic diagram illustrating a delay of a control signal according to a comparative example. Figure 14B It shows that according to Figure 12 Schematic diagram of the delay of the control signal of the embodiment of the present disclosure shown in FIG. Figure 14A and Figure 14B , the Y-axis may be voltage V, and the X-axis may be time. Figure 14A The comparative example shown in shows a case where a plurality of main buffers are formed on the main line ML. Figure 14A and Figure 14B In FIG, it is assumed that one horizontal period 1H is 2.79 μs.

[0209] Reference Figure 14A and Figure 14BIn a comparative example, the control signal CLA may have a delay of approximately 85.56 ns at the edge and center of the main line ML. In contrast, in an embodiment of the present disclosure, the control signal CLA may have a delay of approximately 7.6 ns at the edge and center of the main line ML. For example, in the present disclosure, the delays of the control signals CLA, CLB, and CLC may be minimized, and accordingly, the distributor 170 may be driven stably.

[0210] Figures 15 to 18 is a schematic diagram illustrating an electronic device according to various embodiments of the present disclosure.

[0211] Reference Figure 15 , the display device 100a according to the embodiment of the present disclosure (for example, referring to Figure 6 ) can be applied to smart glasses. Smart glasses may include a frame 111 and a lens portion 112. Smart glasses may be wearable electronic devices that can be worn on the user's face and may have a structure in which a portion of the frame 111 can be folded or unfolded. For example, the smart glasses may be a wearable device for augmented reality (AR).

[0212] The frame 111 may include a housing 111b supporting the lens portion 112 and legs 111a for a user to wear the smart glasses. The legs 111a may be connected to the housing 111b via a hinge to be folded or unfolded.

[0213] A battery, a touch panel, a microphone, and / or a camera may be placed in the frame 111. A projector for outputting light and / or a processor for controlling a light signal may be placed in the frame 111.

[0214] The lens portion 112 may be an optical member that allows light to be transmitted therethrough or allows light to be reflected therefrom. The lens portion 112 may include glass and / or a transparent synthetic resin.

[0215] The display device 100a according to an embodiment of the present disclosure may be applied to the lens portion 112. In an embodiment, the user may recognize an image displayed by an optical signal transmitted from the projector of the frame 111 through the lens portion 112. For example, the user may recognize information including time, date, and the like displayed on the lens portion 112.

[0216] Reference Figure 16 The display device 100a according to an embodiment of the present disclosure may be applied to a head-mounted display (HMD). The HMD may include a headband 121 and a display housing 122. For example, the HMD may be a wearable electronic device that can be worn on the user's head.

[0217] The headband 121 can be connected to the display housing 122 to secure the display housing 112. The headband 121 can include a horizontal strap and a vertical strap to secure the HMD to the user's head. The horizontal strap can be provided to wrap around the sides of the user's head, and the vertical strap can be provided to wrap around the top of the user's head. However, the present disclosure is not necessarily limited to this, and the headband 121 can be implemented in the shape of an eyeglass frame or a helmet.

[0218] The display housing 122 can accommodate a display device and can include at least one lens. The at least one lens can provide an image to a user. For example, the display device 100a according to an embodiment of the present disclosure can be applied to a left-eye lens and a right-eye lens implemented in the display housing 122.

[0219] Reference Figure 17 The display device 100a according to an embodiment of the present disclosure may be applied to a smart watch. The smart watch may include a display portion 131 and a strap portion 133. The smart watch may be a wearable electronic device and may be mounted on a user's wrist. The display device 100a according to an embodiment of the present disclosure may be applied to the display portion 131. For example, the display portion 131 may provide image data including information such as time and date.

[0220] Reference Figure 18 The display device 100a according to an embodiment of the present disclosure may be applied to a car display. In an embodiment, the car display may be an electronic device provided inside / outside a vehicle to provide image data.

[0221] For example, the display device 100a according to an embodiment of the present disclosure can be applied to at least one of an infotainment panel 141, an instrument panel 142, a passenger display 143, a head-up display 144, a side mirror display 145, and a reading seat display 146 provided in a vehicle.

[0222] Figure 19 is a schematic block diagram illustrating an electronic device 1000 including a display device according to an embodiment.

[0223] Reference Figure 19 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be Figure 1 The electronic device 1000 may also include various ports for communicating with a video card, a sound card, a memory card, a USB device, or other systems.

[0224] For example, the electronic device 1000 may be a cellular phone, a video phone, a smart pad, a smart watch, a navigation device for a vehicle, a computer monitor, a notebook computer, a head-mounted display device, or the like.

[0225] The processor 1010 may perform specific calculations or tasks. In an embodiment, the processor 1010 may include at least one of a central processing unit, an application processor, a graphics processing unit, a communication processor, an image signal processor, a controller, and the like. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, and the like. In an embodiment, the processor 1010 may be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus. In an embodiment, the processor 1010 may provide input image data to the display device 1060. Therefore, the display device 1060 may display an image based on the input image data provided from the processor 1010.

[0226] The memory device 1020 may store data required to perform operations of the electronic device 1000. The memory device 1020 may be used as a working memory and / or a buffer memory for the processor 1010. For example, the memory device 1020 may include one or more volatile memory devices such as a dynamic random access memory (DRAM) device, a static random access memory device (SRAM), and a mobile DRAM device.

[0227] The storage device 1030 may store data in response to a control signal or data from the processor 1010. The storage device 1030 may include one or more non-volatile memory devices that retain data even when the electronic device 1000 is powered off. In some embodiments, the storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0228] The I / O device 1040 may include input devices such as a keyboard, a keypad, a touch pad, a touch screen, and a mouse, and output devices such as a speaker and a printer. In an embodiment, the display device 1060 may be integrated with the I / O device 1040.

[0229] The power supply 1050 may supply power required to perform operations of the electronic device 1000. For example, the power supply 1050 may include a power management integrated circuit (PMIC). In an embodiment, the power supply 1050 may supply power to the display device 1060.

[0230] The display device 1060 may display images in response to image data signals and / or control signals from the processor 1010. The display device 1060 may be connected to other components through a bus or other communication link.

[0231] In the display device and the method of driving the display device according to the present disclosure, data signals can be supplied to pixels using coupling of capacitors, and accordingly, the voltage range of the data signal can be sufficiently ensured so that the pixels can be applied to high-resolution panels.

[0232] In the display device and the method of driving the display device according to the present disclosure, pixels on at least two horizontal lines may be initialized (and threshold voltage compensated) simultaneously using a multiplexer, and thus a stable driving time may be ensured.

[0233] In a display device and a method of driving a display device according to the present disclosure, at least one control signal for controlling a multiplexer can be supplied to a main line and can be supplied to the multiplexer using a sub-buffer connected to a branch line branching from the main line. Thus, delay of the control signal can be minimized.

[0234] The above description is an example of the technical features of the present disclosure, and those skilled in the art to which the present disclosure pertains will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above may be implemented separately or in combination with each other.

[0235] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be interpreted that all technical spirits within the scope of equivalents are included in the scope of this disclosure.

Claims

1. A display device, comprising: a data driver that supplies a reference voltage and a plurality of data signals to each of the plurality of output lines; a distributor including a plurality of demultiplexers, the distributor supplying the reference voltage and the plurality of data signals supplied from each of the plurality of output lines to a plurality of data lines in response to a plurality of control signals; a timing controller, the timing controller supplying the plurality of control signals; as well as a plurality of pixels connected to the plurality of scan lines and the plurality of data lines, The reference voltage is supplied to the plurality of pixels located on at least two different horizontal lines at the same time.

2. The display device according to claim 1, wherein each of the plurality of pixels is driven selectively in an initialization period, a threshold voltage compensation period, and a data writing period, and The reference voltage is supplied to the pixel during the initialization period and the threshold voltage compensation period.

3. The display device according to claim 2, wherein: The initialization period and the threshold voltage compensation period of the plurality of pixels located on the at least two different horizontal lines overlap with each other.

4. The display device according to claim 2, wherein The data writing periods of the plurality of pixels located on the at least two different horizontal lines do not overlap with each other.

5. The display device according to claim 2, wherein Each of the plurality of demultiplexers includes a plurality of switches, each of the plurality of switches being connected to one of the plurality of data lines and being turned on or off in response to the control signal, The data driver supplies the reference voltage to the output line during the initialization period and the threshold voltage compensation period, and The timing controller simultaneously supplies the plurality of control signals during the initialization period and the threshold voltage compensation period to cause the plurality of switches to be turned on simultaneously. The display device according to claim 5 , wherein: The data driver sequentially supplies the plurality of data signals to each of the plurality of output lines during the data write period, and The timing controller sequentially supplies the plurality of control signals during the data write period to cause the plurality of switches to be sequentially turned on.

7. The display device according to claim 6, wherein: Each of the plurality of demultiplexers is connected to the plurality of data lines, and Each of the plurality of data lines is connected to the pixel emitting light of a different color.

8. The display device according to claim 6, wherein: Each of the plurality of demultiplexers is connected to the plurality of data lines, and Each of the plurality of data lines is connected to the pixels emitting light of the same color.

9. The display device according to claim 1, further comprising: a main line, the main line being located between the timing controller and the distributor; a plurality of main buffers arranged at one side and the other side of the main line, the plurality of main buffers supplying at least one of the plurality of control signals supplied from the timing controller to the main line; a plurality of branch lines, the plurality of branch lines branching out from the main line; as well as A sub-buffer is located on each of the plurality of branch lines, the sub-buffer being connected to at least one of the plurality of demultiplexers.

10. The display device according to claim 2, wherein: The channel of the data driver includes: a first decoder that generates the plurality of data signals; a second decoder, the second decoder generating the reference voltage; a first switch connected between a source amplifier and the first decoder; and a second switch connected between the source amplifier and the second decoder, and An output terminal of the source amplifier is connected to one of the plurality of output lines, and wherein the first switch is turned on during the data writing period in response to a voltage control signal supplied from the timing controller, and The second switch is turned on during the initialization period and the threshold voltage compensation period in response to the voltage control signal.

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