Shift register and driving method thereof, gate driving circuit and display panel

Abstract

The invention provides a shift register and a driving method thereof, a gate driving circuit and a display panel. The shifting register comprises an input sub-circuit, a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and an output sub-circuit, the input sub-circuit responds to a first clock signal, and the potential of a first node is controlled through an input signal; the first control sub-circuit responds to an input signal and controls the potential of a second node by using a first power supply signal; the second control sub-circuit responds to the potential of the second node and controls the potential of the third node by using the first effective potential; the third control sub-circuit responds to the potential of the first node and controls the potential of a third node by using the first effective potential or the second effective potential; the output sub-circuit responds to the potential of the first node and outputs the second power supply signal through the signal output end, or responds to the potential of the third node and outputs the first effective potential or the second effective potential through the signal output end.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register and a driving method thereof, a gate driving circuit, and a display panel. Background Art

[0002] Gate drive on array (GOA) technology is a common technique used in display products. It integrates gate drive circuitry onto a substrate to achieve row-by-row scanning of the gates of transistors in the pixel drive circuit. The gate drive circuit comprises multiple cascaded shift registers. However, the output signal (OUT signal) of some existing GOA circuits has an intermediate potential (i.e., a step potential between the rising and falling edges), which can cause horizontal streaks. The higher the step voltage, the more pronounced the streaks are at high brightness. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a shift register and a driving method thereof, a gate driving circuit and a display panel.

[0004] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a shift register, which includes an input subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit and an output subcircuit;

[0005] The input sub-circuit is configured to control the potential of the first node using an input signal in response to a first clock signal;

[0006] The first control subcircuit is configured to control the potential of the second node using a first power supply signal in response to the input signal;

[0007] The second control subcircuit is configured to control the potential of the third node using a first effective potential in response to the potential of the second node;

[0008] The third control subcircuit is configured to control the potential of the third node using the first effective potential or the second effective potential in response to the potential of the first node;

[0009] The output subcircuit is configured to output the second power supply signal through the signal output terminal in response to the potential of the first node, or to output the first effective potential or the second effective potential through the signal output terminal in response to the potential of the third node.

[0010] In some embodiments, the first effective potential is a low potential, and the second effective potential is a high potential;

[0011] The potential of the first power supply signal is the same as the second effective potential, and the potential of the second power supply signal is the same as the first effective potential.

[0012] In some embodiments, the second control subcircuit is configured to control the potential of the third node using a first effective potential of a second clock signal in response to the potential of the second node.

[0013] In some embodiments, the second control subcircuit includes a third transistor and a first storage capacitor;

[0014] The first electrode of the third transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node;

[0015] The first plate of the first storage capacitor is electrically connected to the second clock signal terminal, and the second plate is electrically connected to the second node.

[0016] In some embodiments, the shift register has some sub-timing phases in the timing control phase, and the first clock signal and the second clock signal are both the first effective potential.

[0017] In some embodiments, in the timing control stage, the rising edge of the first clock signal is located in the sub-timing stage where the first valid potential of the second clock signal is located, and the falling edge of the second clock signal is located in the sub-timing stage where the first valid potential of the first clock signal is located.

[0018] In some embodiments, the second control subcircuit is configured to control the potential of the third node in response to the potential of the second node using a second power signal transmitted by a second power line; the potential of the second power signal output by the second power line is the first effective potential.

[0019] In some embodiments, the second control subcircuit includes a third transistor and a first storage capacitor;

[0020] The first electrode of the third transistor is electrically connected to the second power line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node;

[0021] The first plate of the first storage capacitor is electrically connected to a second clock signal terminal that transmits the second clock signal, and the second plate is electrically connected to the second node.

[0022] In some embodiments, the third control subcircuit is specifically configured to control the potential of the third node using the first clock signal in response to the potential of the first node.

[0023] In some embodiments, the third control subcircuit includes a fifth transistor;

[0024] The first electrode of the fifth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

[0025] In some embodiments, the third control subcircuit is specifically configured to control the potential of the third node in response to the potential of the first node using the first power signal transmitted by the first power line; the potential of the first power signal output by the first power line is the second effective potential.

[0026] In some embodiments, the third control subcircuit includes a fifth transistor;

[0027] The fifth transistor has a first electrode electrically connected to the first power line, a second electrode electrically connected to the third node, and a control electrode electrically connected to the first node.

[0028] In some embodiments, the third control sub-circuit is further configured to control the potential of the first node using a second clock signal in response to the potential of the first node.

[0029] In some embodiments, the third control subcircuit further includes a ninth transistor and a second storage capacitor;

[0030] The first electrode of the ninth transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first node;

[0031] The first plate of the second storage capacitor is electrically connected to the first node, and the second plate is electrically connected to the fourth node.

[0032] In some embodiments, the output subcircuit is specifically configured to output the second power signal through the signal output terminal in response to the potential of the first node, or to output the first clock signal through the signal output terminal in response to the potential of the third node.

[0033] In some embodiments, the output sub-circuit includes a sixth transistor, a third storage capacitor, and a seventh transistor;

[0034] The first electrode of the sixth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node;

[0035] The first plate of the third storage capacitor is electrically connected to the first clock signal terminal, and the second plate is electrically connected to the third node;

[0036] The first electrode of the seventh transistor is electrically connected to the second power line transmitting the second power signal, the second electrode is electrically connected to the signal output end, and the control electrode is electrically connected to the first node.

[0037] In some embodiments, the output subcircuit is specifically configured to output the second power signal through the signal output end in response to the potential of the first node, or to output the first power signal through the signal output end in response to the potential of the third node; the potential of the second power signal is the first effective potential; the potential of the first power signal is the second effective potential.

[0038] In some embodiments, the output sub-circuit includes a sixth transistor, a third storage capacitor, and a seventh transistor;

[0039] The first electrode of the sixth transistor is electrically connected to the first power line transmitting the first power signal, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node;

[0040] The first plate of the third storage capacitor is electrically connected to the first power line, and the second plate is electrically connected to the third node;

[0041] The first electrode of the seventh transistor is electrically connected to the second power line transmitting the second power signal, the second electrode is electrically connected to the signal output end, and the control electrode is electrically connected to the first node.

[0042] In some embodiments, the shift register further includes an isolation subcircuit; the isolation subcircuit includes a fourth transistor and an eighth transistor;

[0043] A first electrode of the fourth transistor is electrically connected to the first node, a second electrode is electrically connected to the fifth node, and a control electrode is electrically connected to a second power line transmitting the second power signal;

[0044] The first electrode of the eighth transistor is electrically connected to the third node, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the second power line;

[0045] The fifth node and the sixth node are both electrically connected to the output sub-circuit.

[0046] In some embodiments, the third control subcircuit includes a fifth transistor;

[0047] The first electrode of the fifth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the fifth node; or,

[0048] A first electrode of the fifth transistor is electrically connected to a first power line transmitting the first power signal, a second electrode is electrically connected to the sixth node, and a control electrode is electrically connected to the fifth node.

[0049] In some embodiments, the third control subcircuit further includes a ninth transistor and a second storage capacitor;

[0050] The first electrode of the ninth transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the fifth node;

[0051] The first plate of the second storage capacitor is electrically connected to the fifth node, and the second plate is electrically connected to the fourth node.

[0052] In some embodiments, the third control subcircuit includes a fifth transistor;

[0053] The first electrode of the fifth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the first node; or,

[0054] The first electrode of the fifth transistor is electrically connected to the first power line transmitting the first power signal, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the first node.

[0055] In some embodiments, the third control subcircuit further includes a ninth transistor and a second storage capacitor;

[0056] The first electrode of the ninth transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the fifth node;

[0057] The first plate of the second storage capacitor is electrically connected to the fifth node, and the second plate is electrically connected to the fourth node.

[0058] In some embodiments, the input subcircuit includes a first transistor; the first control subcircuit includes a second transistor;

[0059] The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal terminal that transmits the first clock signal;

[0060] A first electrode of the second transistor is electrically connected to a first power line transmitting the first power signal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the signal input terminal.

[0061] In a second aspect, an embodiment of the present disclosure further provides a driving method of a shift register, wherein the timing control stage of the shift register includes a first sub-stage, a second sub-stage, a third sub-stage, a fourth sub-stage and a fifth sub-stage;

[0062] In the first sub-phase, the potential of the input signal and the potential of the second clock signal are both the second effective potential, and the first clock signal is the first effective potential; the input sub-circuit writes the input signal to the first node under the control of the first clock signal; and the output sub-circuit maintains the output potential of the previous sub-phase under the control of the potential of the first node;

[0063] In the second sub-phase, the potential of the input signal is the second effective potential, and the potential of the second node, the potential of the first clock signal, and the potential of the second clock signal are all the first effective potential; the input sub-circuit writes the input signal to the first node under the control of the first clock signal; the second control sub-circuit writes the second clock signal or the second power supply signal to the third node under the control of the potential of the second node; and the output sub-circuit maintains the output potential of the previous sub-phase under the control of the potential of the third node and the first clock signal;

[0064] In the third sub-phase, the potential of the input signal and the potential of the first clock signal are both the second effective potential, and the potential of the second node and the potential of the second clock signal are the first effective potential; the second control sub-circuit writes the second clock signal or the second power supply signal to the third node under the control of the potential of the second node; and the output sub-circuit outputs the first clock signal through the signal output terminal under the control of the potential of the third node and the first clock signal;

[0065] In the fourth sub-stage, the potential of the input signal and the potential of the first clock signal are both a first effective potential, and the potential of the second clock signal is a second effective potential; the input sub-circuit writes the input signal to the first node under the control of the first clock signal; the first control sub-circuit writes a first power supply signal to the second node under the control of the input signal; the third control sub-circuit controls the potential of the third node using the first clock signal under the control of the potential of the first node; and the output sub-circuit outputs the first clock signal through the signal output terminal under the control of the potential of the third node and the first clock signal.

[0066] In the fifth sub-stage, the potential of the input signal and the potential of the second clock signal are both first effective potentials, and the potential of the first clock signal is a second effective potential; the first control sub-circuit writes a first power supply signal to the second node under the control of the input signal; the third control sub-circuit controls the potential of the third node using the first clock signal under the control of the first node; and the output sub-circuit outputs the second power supply signal through the signal output end under the control of the first node.

[0067] In a third aspect, an embodiment of the present disclosure further provides a gate driving circuit, comprising N cascaded shift registers as described in any one of the first aspects;

[0068] Except for the first stage shift register, the signal input end of the i+1th stage shift register is electrically connected to the signal output end of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0069] In some embodiments, in addition to the first stage shift register, the first clock signal terminal of the (i+1)th stage shift register is electrically connected to the second clock signal terminal of the i-th stage shift register.

[0070] In a fourth aspect, an embodiment of the present disclosure further provides a display panel, which includes the gate driving circuit as described in the third aspect.

[0071] In some embodiments, the display panel further includes M clock signal lines, where M is a positive integer greater than or equal to 3;

[0072] The M clock signal lines are divided into M clock signal line groups, and each of the 1 to M-1 clock signal line groups includes two adjacent clock signal lines; the M-th clock signal line group includes the first clock signal line and the M-th clock signal line;

[0073] The N cascaded shift registers in the gate drive circuit are divided into a plurality of groups, each group including M cascaded shift registers, and the first clock signal terminal and the second clock signal terminal of the k-th shift register are electrically connected to different clock signal lines in the k-th group of clock signal lines; k is a positive integer between 1 and M;

[0074] For N cascaded shift registers, the first clock signal terminal of the i+1th stage shift register and the second clock signal terminal of the i-th stage shift register are both electrically connected to the same clock signal line; i is a positive integer between 1 and N-1;

[0075] For any group of M+1 cascaded shift registers, the first clock signal terminal of the first shift register and the second clock signal terminal of the M+1th shift register are electrically connected to the same clock signal line.

[0076] In some embodiments, M is any integer between 3 and 20.

[0077] In some embodiments, the display panel further includes two clock signal lines;

[0078] The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group includes two cascaded shift registers, and the first clock signal end of the first shift register and the second clock signal end of the second shift register are electrically connected to one clock signal line, and the first clock signal end of the second shift register and the second clock signal end of the second shift register are electrically connected to another clock signal line.

[0079] In some embodiments, the display panel further comprises pixel units arranged in an array, wherein the pixel units comprise light-emitting devices and pixel driving circuits for driving the light-emitting devices;

[0080] The N cascaded shift registers are respectively configured to drive N rows of pixel units;

[0081] The signal output end of the shift register is electrically connected to the control electrode of the threshold compensation transistor in the pixel driving circuit; or, the signal output end of the shift register is electrically connected to the control electrode of the light emitting control transistor in the pixel driving circuit; or, the signal output end of the shift register is electrically connected to the control electrode of the reset transistor in the pixel driving circuit.

[0082] In a fifth aspect, an embodiment of the present disclosure further provides a display device, which includes the display panel as described in the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 A schematic diagram of a shift register provided in an embodiment of the present disclosure.

[0084] Figure 2 This is a circuit diagram of a shift register according to Example 1 of an embodiment of the present disclosure.

[0085] Figure 3 This is a circuit diagram of a shift register according to Example 2 of an embodiment of the present disclosure.

[0086] Figure 4 This is a circuit diagram of a shift register according to Example 3 of an embodiment of the present disclosure.

[0087] Figure 5 A timing diagram of an exemplary shift register provided in an embodiment of the present disclosure.

[0088] Figure 6 This is a circuit diagram of a shift register according to Example 4 of an embodiment of the present disclosure.

[0089] Figure 7 This is a circuit diagram of a shift register according to Example 5 of an embodiment of the present disclosure.

[0090] Figure 8 This is a circuit diagram of a shift register according to Example 6 of an embodiment of the present disclosure.

[0091] Figure 9 This is a circuit diagram of a shift register according to Example 7 of an embodiment of the present disclosure.

[0092] Figure 10 This is a circuit diagram of a shift register according to Example 8 of an embodiment of the present disclosure.

[0093] Figure 11 This is a circuit diagram of a shift register according to Example 9 of an embodiment of the present disclosure.

[0094] Figure 12 This is a circuit diagram of a shift register according to Example 10 of an embodiment of the present disclosure.

[0095] Figure 13 A circuit diagram of a shift register according to Example 11 of an embodiment of the present disclosure.

[0096] Figure 14 A circuit diagram of a shift register according to Example 12 of an embodiment of the present disclosure.

[0097] Figure 15 This is a simulation waveform diagram of signals and nodes in the circuit provided by the embodiment of the present disclosure.

[0098] Figure 16 A timing diagram of another exemplary shift register provided in an embodiment of the present disclosure.

[0099] Figure 17 A schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure.

[0100] Figure 18 A schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0101] Figure 19 A schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0102] Figure 20 A schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0103] Figure 21 for Figure 20 The corresponding gate drive circuit working timing diagram.

[0104] Figure 22 A schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0105] Figure 23 for Figure 22 The corresponding gate drive circuit working timing diagram.

[0106] Figure 24 A schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure.

[0107] Figure 25 for Figure 24 The corresponding gate drive circuit working timing diagram.

[0108] Figure 26 A schematic diagram of a pixel driving circuit provided in an embodiment of the present disclosure.

[0109] Figure 27 Schematic diagram of a gate drive circuit driven by four clock signal lines provided in an embodiment of the present disclosure.

[0110] Figure 28 Schematic diagram of a gate drive circuit driven by five clock signal lines provided in an embodiment of the present disclosure.

[0111] Figure 29 Schematic diagram of a gate drive circuit driven by six clock signal lines provided in an embodiment of the present disclosure.

[0112] Figure 30 A schematic diagram of a gate drive circuit driven by two clock signal lines provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0113] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Unless otherwise defined, technical terms or scientific terms used in the present disclosure should have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0114] The terms "first," "second," and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.

[0115] It should be noted that the first power supply signal and the second power supply signal referred to in this disclosure are both constant voltage signals provided by a constant power supply, one of which is a high-potential voltage signal and the other is a low-potential voltage signal. The two voltages have the same absolute value but opposite polarity, for example, the high-potential voltage signal is +5 volts (V) and the low-potential voltage signal is -5 V. For ease of understanding, this disclosure uses the example of a first power supply signal being a high-potential voltage signal and a second power supply signal being a low-potential voltage signal as an example.

[0116] It should be noted that the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the source and drain are turned on when a low-level signal is input to the gate; when an N-type transistor is used, the source and drain are turned on when a high-level signal is input to the gate. For ease of understanding, the present disclosure uses a P-type transistor as an example for explanation, and the same is true for an N-type transistor, so no further details are given.

[0117] In the present disclosure, one of the first effective potential and the second effective potential is a high potential, and the other is a low potential. The two potentials have the same absolute value but opposite polarity. Taking a P-type transistor as an example, the first effective potential is a low potential, such as -5V, and the second effective potential is a high potential, such as +5V. The present disclosure illustrates an example in which the high potential of the first power supply signal is the same as the second effective potential, and the low potential of the second power supply signal is the same as the first effective potential.

[0118] The GOA circuits in related technologies have several issues: First, they require a large number of transistors, occupying a large space and resulting in a wide panel border, which does not meet user requirements for narrow borders. Second, the output signal of the GOA circuit cannot directly change from a high level to a low level, but instead has an intermediate potential (i.e., a step potential), which causes horizontal streaks. Furthermore, if the step voltage is too high, it can cause high-brightness horizontal streaks to appear even when the light is normally on.

[0119] In view of this, the embodiment of the present disclosure provides a shift register, which essentially simplifies the circuit structure of the shift register and realizes a narrow frame; at the same time, it directly realizes the jump from the second effective potential to the first effective potential, eliminates the step potential, and thus solves the problem of poor horizontal stripes on the panel.

[0120] Figure 1 A schematic diagram of a shift register provided by an embodiment of the present disclosure is shown in FIG. Figure 1As shown, the shift register includes an input sub-circuit 1 , a first control sub-circuit 2 , a second control sub-circuit 3 , a third control sub-circuit 4 and an output sub-circuit 5 .

[0121] Input sub-circuit 1 is electrically connected to a signal input terminal, a first clock signal terminal, and a first node N1. Input sub-circuit 1 can receive an input signal STV from the signal input terminal and a first clock signal CK1 transmitted from the first clock signal terminal. Input sub-circuit 1 is configured to control the potential of first node N1 using input signal STV in response to the first clock signal CK1.

[0122] The first control sub-circuit 2 is electrically connected to the signal input terminal, the first power line, and the second node N2. The first control sub-circuit 2 can receive an input signal STV from the signal input terminal and a first power signal VGH transmitted from the first power line. The first control sub-circuit 2 is configured to control the potential of the second node N2 using the first power signal VGH in response to the input signal STV.

[0123] The second control subcircuit 3 is electrically connected to the second node N2; the second control subcircuit 3 is configured to respond to the potential of the second node N2 and control the potential of the third node N3 using the first effective potential. The first effective potential can be the second clock signal CK2 transmitted by the second clock signal terminal (for details, see Figure 2 or Figure 4 Alternatively, the first effective potential may be a second power signal VGL transmitted by the second power line (see Figure 3 shown) provides a low potential.

[0124] The third control subcircuit 4 is electrically connected to the first node N1 and the third node N3. The third control subcircuit 4 is configured to respond to the potential of the first node N1 and control the potential of the third node N1 using the first effective potential or the second effective potential. The first effective potential can be the first clock signal CK1 transmitted by the first clock signal terminal (for details, see Figure 2 or Figure 3 The second effective potential may be the first clock signal CK1 transmitted by the first clock signal terminal (see Figure 2 or Figure 3 Alternatively, the second effective potential may also be the first power signal VGH transmitted by the first power line (see Figure 4 The high potential provided by

[0125] The output sub-circuit 5 is electrically connected to the first node N1, the third node N3, and the second power line. The output sub-circuit 5 can receive the second power signal VGL transmitted from the second power line. The output sub-circuit 5 is configured to output the second power signal VGL through the signal output terminal OUT in response to the potential of the first node N1, or to output the first effective potential or the second effective potential through the signal output terminal OUT in response to the potential of the third node N3. Here, the first effective potential can be the low potential provided by the first clock signal CK1 transmitted by the first clock signal terminal (for details, see Figure 2 or Figure 3 The second effective potential can be a high potential provided by the first clock signal CK1 (see Figure 2 or Figure 3 Alternatively, the second effective potential may also be a high potential provided by the first power signal VGH (see Figure 4 shown).

[0126] According to the circuit structure of the shift register described above, in the disclosed embodiment, the signal outputted from the signal output terminal OUT can directly realize the jump from the second effective potential to the first effective potential, thereby eliminating the step potential and solving the problem of bad horizontal stripes on the panel.

[0127] In some embodiments, Figure 2 The circuit diagram of the shift register under Example 1 provided in the embodiment of the present disclosure is as follows: Figure 2 As shown, the input sub-circuit 1 is configured to control the potential of the first node N1 using the input signal STV in response to the first clock signal CK1. The first control sub-circuit 2 is configured to control the potential of the second node N2 using the first power supply signal VGH in response to the input signal STV. The second control sub-circuit 3 is configured to control the potential of the third node N3 using the first effective potential of the second clock signal CK2 in response to the potential of the second node N2. The third control sub-circuit 4 is configured to control the potential of the third node N3 using the first clock signal CK1 in response to the potential of the first node N1. The output sub-circuit 5 is configured to output the second power supply signal VGL through the signal output terminal OUT in response to the potential of the first node N1, or to output the first clock signal CK1 through the signal output terminal OUT in response to the potential of the third node N3.

[0128] The input subcircuit 1 includes a first transistor T1; the first control subcircuit 2 includes a second transistor T2; the second control subcircuit 3 includes a third transistor T3 and a first storage capacitor C1; the third control subcircuit 4 includes a fifth transistor T5; and the output subcircuit 5 includes a sixth transistor T6, a third storage capacitor C3, and a seventh transistor T7. The first electrode of the first transistor T1 is electrically connected to the signal input terminal, the second electrode of the first transistor T1 is electrically connected to the first node N1, and the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1. The first electrode of the second transistor T2 is electrically connected to the first power line for transmitting the first power signal VGH, the second electrode of the second transistor T2 is electrically connected to the second node N2, and the control electrode of the second transistor T2 is electrically connected to the signal input terminal. The first electrode of the third transistor T3 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, the second electrode of the third transistor T3 is electrically connected to the third node N3, and the control electrode of the third transistor T3 is electrically connected to the second node N2. The first plate of the first storage capacitor C1 is electrically connected to the second clock signal terminal, and the second plate of the first storage capacitor C1 is electrically connected to the second node N2. A first electrode of the fifth transistor T5 is electrically connected to a first clock signal terminal for transmitting a first clock signal CK1, a second electrode of the fifth transistor T5 is electrically connected to a third node, and a control electrode of the fifth transistor T5 is electrically connected to the first node. A first electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, a second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and a control electrode of the sixth transistor T6 is electrically connected to the third node. A first plate of the third storage capacitor C3 is electrically connected to the first clock signal terminal, and a second plate of the third storage capacitor C3 is electrically connected to a third node N3. A first electrode of the seventh transistor T7 is electrically connected to a second power line for transmitting a second power signal VGL, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT, and a control electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0129] Figure 5 An exemplary timing diagram of a shift register provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the timing control phase includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, a fourth sub-phase t4, and a fifth sub-phase t5. The first clock signal CK1 and the second clock signal CK2 are both pulse signals. In the timing control phase, the rising edge of the first clock signal CK1 (i.e., the time node when the signal transitions from a low level to a high level) is located in the sub-timing phase where the first valid potential of the second clock signal CK2 is located, and the falling edge of the second clock signal CK2 (i.e., the time node when the signal transitions from a high level to a low level) is located in the sub-timing phase where the first valid potential of the first clock signal CK1 is located.

[0130] During the third sub-phase t3, the potential of the second clock signal CK2 reaches the first effective potential, the third transistor T3 is turned on, and the first effective potential (low potential) of the second clock signal CK2 is written to the third node N3, thereby turning on the sixth transistor T6 and causing the signal output terminal OUT to output the first clock signal CK1, which was at a high level during phase t3. During the fourth sub-phase t4, after the first clock signal CK1 transitions from a high level to a low level, the third node N3 is further pulled down to below the first effective potential through the coupling effect of the third capacitor C3, thereby fully turning on the sixth transistor T6 and causing the signal output terminal OUT to output the first clock signal CK1, which was at a low level during phase t4. This achieves a direct transition of the output signal from a high level to a low level, eliminating the step potential and improving the panel's horizontal stripes.

[0131] In addition, this embodiment can improve the horizontal stripe defect by only using the 6T2C circuit structure, and further realize the narrow frame of the panel to meet user needs.

[0132] In some embodiments, Figure 3 The circuit diagram of the shift register under Example 2 provided in the embodiment of the present disclosure is as follows: Figure 3 As shown, the input sub-circuit 1 is configured to control the potential of the first node N1 using the input signal STV in response to the first clock signal CK1. The first control sub-circuit 2 is configured to control the potential of the second node N2 using the first power signal VGH in response to the input signal STV. The second control sub-circuit 3 is configured to control the potential of the third node N3 using the second power signal VGL transmitted through the second power line in response to the potential of the second node N2 provided by the second clock signal CK2. The third control sub-circuit 4 is configured to control the potential of the third node N3 using the first clock signal CK1 in response to the potential of the first node N1. The output sub-circuit 5 is configured to output the second power signal VGL through the signal output terminal OUT in response to the potential of the first node N1, or to output the first clock signal CK1 through the signal output terminal OUT in response to the potential of the third node N3.

[0133] The input subcircuit 1 includes a first transistor T1; the first control subcircuit 2 includes a second transistor T2; the second control subcircuit 3 includes a third transistor T3 and a first storage capacitor C1; the third control subcircuit 4 includes a fifth transistor T5; and the output subcircuit 5 includes a sixth transistor T6, a third storage capacitor C3, and a seventh transistor T7. The first electrode of the first transistor T1 is electrically connected to the signal input terminal, the second electrode of the first transistor T1 is electrically connected to the first node N1, and the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1. The first electrode of the second transistor T2 is electrically connected to the first power line for transmitting the first power signal VGH, the second electrode of the second transistor T2 is electrically connected to the second node N2, and the control electrode of the second transistor T2 is electrically connected to the signal input terminal. The first electrode of the third transistor T3 is electrically connected to the second power line for transmitting the second power signal VGL, the second electrode of the third transistor T3 is electrically connected to the third node N3, and the control electrode of the third transistor T3 is electrically connected to the second node N2. The first plate of the first storage capacitor C1 is electrically connected to the second clock signal terminal, and the second plate of the first storage capacitor C1 is electrically connected to the second node N2. A first electrode of the fifth transistor T5 is electrically connected to a first clock signal terminal for transmitting a first clock signal CK1, a second electrode of the fifth transistor T5 is electrically connected to a third node, and a control electrode of the fifth transistor T5 is electrically connected to the first node. A first electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, a second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and a control electrode of the sixth transistor T6 is electrically connected to the third node. A first plate of the third storage capacitor C3 is electrically connected to the first clock signal terminal, and a second plate of the third storage capacitor C3 is electrically connected to a third node N3. A first electrode of the seventh transistor T7 is electrically connected to a second power line for transmitting a second power signal VGL, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT, and a control electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0134] like Figure 5 As shown, in the third sub-phase t3, the potential of the second clock signal CK2 is the first effective potential, the third transistor T3 is turned on, and the first effective potential (low potential) of the second power supply signal VGL is written to the third node N3, thereby turning on the sixth transistor T6, and the signal output terminal OUT outputs the first clock signal CK1, which is at a high level during phase t3. In the fourth sub-phase t4, after the first clock signal CK1 jumps from a high level to a low level, the third node N3 is further pulled down to below the first effective potential through the coupling effect of the third capacitor C3, thereby fully turning on the sixth transistor T6, and the signal output terminal OUT outputs the first clock signal CK1, which is at a low level during phase t4. This achieves a direct jump from a high level to a low level of the output signal, eliminating the step potential and improving the horizontal stripe defect of the panel.

[0135] In addition, this embodiment can improve the horizontal stripe defect by only using the 6T2C circuit structure, and further realize the narrow frame of the panel to meet user needs.

[0136] In some embodiments, Figure 4 The circuit diagram of the shift register under Example 3 provided in the embodiment of the present disclosure is as follows: Figure 4 As shown, the input sub-circuit 1 is configured to control the potential of the first node N1 using the input signal STV in response to the first clock signal CK1. The first control sub-circuit 2 is configured to control the potential of the second node N2 using the first power supply signal VGH in response to the input signal STV. The second control sub-circuit 3 is configured to control the potential of the third node N3 using the first effective potential of the second clock signal CK2 in response to the potential of the second node N2. The third control sub-circuit 4 is configured to control the potential of the third node N3 using the first power supply signal VGH in response to the potential of the first node N1. The output sub-circuit 5 is configured to output the second power supply signal VGL through the signal output terminal OUT in response to the potential of the first node N1, or to output the first power supply signal VGH through the signal output terminal OUT in response to the potential of the third node N3.

[0137] The input subcircuit 1 includes a first transistor T1; the first control subcircuit 2 includes a second transistor T2; the second control subcircuit 3 includes a third transistor T3 and a first storage capacitor C1; the third control subcircuit 4 includes a fifth transistor T5; and the output subcircuit 5 includes a sixth transistor T6, a third storage capacitor C3, and a seventh transistor T7. The first electrode of the first transistor T1 is electrically connected to the signal input terminal, the second electrode of the first transistor T1 is electrically connected to the first node N1, and the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1. The first electrode of the second transistor T2 is electrically connected to the first power line for transmitting the first power signal VGH, the second electrode of the second transistor T2 is electrically connected to the second node N2, and the control electrode of the second transistor T2 is electrically connected to the signal input terminal. The first electrode of the third transistor T3 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, the second electrode of the third transistor T3 is electrically connected to the third node N3, and the control electrode of the third transistor T3 is electrically connected to the second node N2. The first plate of the first storage capacitor C1 is electrically connected to the second clock signal terminal, and the second plate of the first storage capacitor C1 is electrically connected to the second node N2. A first electrode of the fifth transistor T5 is electrically connected to a first power line transmitting a first power signal VGH, a second electrode of the fifth transistor T5 is electrically connected to a third node, and a control electrode of the fifth transistor T5 is electrically connected to the first node. A first electrode of the sixth transistor T6 is electrically connected to the first power line transmitting the first power signal VGH, a second electrode of the sixth transistor T6 is electrically connected to a signal output terminal OUT, and a control electrode of the sixth transistor T6 is electrically connected to a third node. A first plate of the third storage capacitor C3 is electrically connected to the first clock signal terminal, and a second plate of the third storage capacitor C3 is electrically connected to a third node N3. A first electrode of the seventh transistor T7 is electrically connected to a second power line transmitting a second power signal VGL, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT, and a control electrode of the seventh transistor T7 is electrically connected to the first node N1.

[0138] This embodiment adopts a 6T2C circuit structure, which can achieve a narrow panel border to meet user needs.

[0139] Figure 6 This is a circuit diagram of a shift register according to Example 4 provided in an embodiment of the present disclosure. Figure 7 This is a circuit diagram of a shift register according to Example 5 provided in an embodiment of the present disclosure. Figure 8 This is a circuit diagram of a shift register according to Example 6 of an embodiment of the present disclosure.

[0140] In some embodiments, as Figure 6 、 Figure 7 or Figure 8As shown, the third control subcircuit 4 is further configured to control the potential of the first node N1 using the second clock signal CK2 in response to the potential of the first node N1. Optionally, the third control subcircuit 4 also includes a ninth transistor T9 and a second storage capacitor C2; a first electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal transmitting the second clock signal CK2, a second electrode of the ninth transistor T9 is electrically connected to the fourth node N4, and a control electrode of the ninth transistor T9 is electrically connected to the first node N1. A first plate of the second storage capacitor C2 is electrically connected to the first node N1, and a second plate of the second storage capacitor C2 is electrically connected to the fourth node N4.

[0141] Compared to Example 1, Example 4 adds a ninth transistor T9 and a second storage capacitor C2, while the other circuit structures are the same as those in Example 1, and the repeated parts are not repeated. Compared to Example 2, Example 5 adds a ninth transistor T9 and a second storage capacitor C2, while the other circuit structures are the same as those in Example 2, and the repeated parts are not repeated. Compared to Example 3, Example 6 adds a ninth transistor T9 and a second storage capacitor C2, while the other circuit structures are the same as those in Example 3, and the repeated parts are not repeated.

[0142] like Figure 5 As shown, in the fifth sub-stage t5, the first clock signal CK1 jumps from a low potential to a high potential, the first transistor T1 is turned off, the first node N1 maintains the first effective potential of the previous stage, and the ninth transistor T9 is turned on. Since the second clock signal CK2 jumps from a high potential to a low potential at this time, the first node N1 can be quickly pulled down to less than the first effective potential through the coupling effect of the second storage capacitor C2, so that the seventh transistor T7 can be fully turned on to output the second power signal VGL

[0143] Figure 9 This is a circuit diagram of a shift register according to Example 7 provided in an embodiment of the present disclosure. Figure 10 This is a circuit diagram of a shift register according to Example 8 provided in an embodiment of the present disclosure. Figure 11 This is a circuit diagram of a shift register according to Example 9 of an embodiment of the present disclosure. Figure 12 A circuit diagram of a shift register according to Example 10 provided in an embodiment of the present disclosure is provided. Figure 13 A circuit diagram of a shift register according to Example 11 provided in an embodiment of the present disclosure is provided. Figure 14 A circuit diagram of a shift register according to Example 12 of an embodiment of the present disclosure. Figure 15 This is a simulation waveform diagram of signals and nodes in the circuit provided by the embodiment of the present disclosure.

[0144] In some embodiments, as Figures 9 to 11As shown, the shift register further includes an isolation sub-circuit 6; the isolation sub-circuit 6 is configured to isolate the first node N1 from the output sub-circuit 5 electrically connected to the first node N1, isolate the third node N3 from the output sub-circuit 5 electrically connected to the third node N3, and isolate the first node N1 from at least part of the third control sub-circuit 4 electrically connected to the first node N1. After isolation, the isolation sub-circuit 6 electrically connects the first node N1 to the fifth node N5, and the output sub-circuit 5 is electrically connected to the fifth node N5; the isolation sub-circuit 6 electrically connects the third node N3 to the sixth node N6, and the output sub-circuit 5 is electrically connected to the sixth node N6; and the third control sub-circuit 4 electrically connects the fifth node N5 to the sixth node N6.

[0145] Here, the isolation sub-circuit 6 is arranged between the input sub-circuit 1 and the output sub-circuit 5, and between the second control sub-circuit 3 and the output sub-circuit 5. The isolation sub-circuit 6 is mainly used to protect the input sub-circuit 1 and the second control sub-circuit 3, and prevent the source-drain voltage difference between the first transistor T1 and the third transistor T3 from being too large during operation, thereby causing device failure.

[0146] Optionally, the isolation sub-circuit 6 includes a fourth transistor T4 and an eighth transistor T8; wherein a first electrode of the fourth transistor T4 is electrically connected to the first node N1, a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5, and a control electrode of the fourth transistor T4 is electrically connected to a second power line transmitting the second power signal VGL; a first electrode of the eighth transistor T8 is electrically connected to the third node N3, a second electrode of the eighth transistor T8 is electrically connected to the sixth node N6, and a control electrode of the eighth transistor T8 is electrically connected to the second power line transmitting the second power signal VGL. The fifth node N5 and the sixth node N6 are both electrically connected to the output sub-circuit 5.

[0147] In addition, if Figures 9 to 11 As shown, the fourth transistor T4 separates the first transistor T1 and the ninth transistor T9. Figure 5 As shown, it can be ensured that when the ninth transistor T9 is continuously turned on in the fifth sub-phase t5, the second clock signal CK2 pulls down the potential of the fifth node N5, and does not directly pull down the potential of the first node N1, thereby preventing the source-drain voltage difference of the first transistor T1 from being too large, thereby protecting the first transistor T1 from failure.

[0148] Since the second power signal VGL is a constant low-level signal, the fourth transistor T4 and the eighth transistor T8 are in a normally-on state. The fourth transistor T4 is turned on under the control of the second power signal VGL and writes the potential of the first node N1 to the fifth node N5. The eighth transistor T8 is turned on under the control of the second power signal VGL and writes the potential of the third node N3 to the sixth node N6.

[0149] It should be noted that due to the presence of the fourth transistor T4, the potential of the first node N1 is attenuated after passing through the fourth transistor T4, resulting in a potential at the fifth node N5 that is different from the potential at the first node N1. For example, if the potential at the first node N1 is -5V, the potential at the fifth node N5 is greater than -5V, but its absolute value is less than 5V; if the potential at the first node N1 is +5V, the potential at the fifth node N5 is less than +5V. Similarly, due to the presence of the eighth transistor T8, the potential at the third node N3 is attenuated after passing through the eighth transistor T8, resulting in a potential at the sixth node N6 that is different from the potential at the third node N3.

[0150] In some embodiments, as Figure 9 As shown, the second control sub-circuit 3 is configured to control the potential of the third node N3 using the first effective potential of the second clock signal CK2 in response to the potential of the second node N2. The third control sub-circuit 4 is specifically configured to control the potential of the sixth node N6 using the second effective potential of the first clock signal CK1 in response to the potential of the fifth node N5, and to control the potentials of the fourth node N4 and the fifth node N5 using the second clock signal CK2. The output sub-circuit 5 is specifically configured to output the second power supply signal VGL through the signal output terminal OUT in response to the potential of the fifth node N5, or to output the first clock signal CK1 through the signal output terminal OUT in response to the potential of the sixth node N6.

[0151] The circuit structures of the input sub-circuit 1 , the first control sub-circuit 2 and the isolation sub-circuit 6 can refer to those described in the above example 1, and the repeated parts will not be repeated here.

[0152] A first electrode of the third transistor T3 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, a second electrode of the third transistor T3 is electrically connected to the third node N3, and a control electrode of the third transistor T3 is electrically connected to the second node N2. A first plate of the first storage capacitor C1 is electrically connected to the second clock signal terminal, and a second plate of the first storage capacitor C1 is electrically connected to the second node N2. A first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, a second electrode of the fifth transistor T5 is electrically connected to the sixth node N6, and a control electrode of the fifth transistor T5 is electrically connected to the fifth node N5. A first electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, a second electrode of the ninth transistor T9 is electrically connected to the fourth node N4, and a control electrode of the ninth transistor T9 is electrically connected to the fifth node N5. A first plate of the second storage capacitor C2 is electrically connected to the fifth node N5, and a second plate of the second storage capacitor C2 is electrically connected to the fourth node N4. A first electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, a second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and a control electrode of the sixth transistor T6 is electrically connected to the sixth node N6. A first plate of the third storage capacitor C3 is electrically connected to the first clock signal terminal, and a second plate of the third storage capacitor C3 is electrically connected to the sixth node N6. A first electrode of the seventh transistor T7 is electrically connected to the second power line transmitting the second power signal VGL, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT, and a control electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0153] Here, the control electrode of the fifth transistor T5 and the control electrode of the ninth transistor T9 are both electrically connected to the fifth node N5. Figure 5 As shown, in the fourth sub-phase t4, the ninth transistor T9 is turned on, and the potential of the fifth node N5 is rapidly increased through the coupling effect of the second storage capacitor C2, thereby ensuring that the seventh transistor T7 is completely turned off and eliminating the potential step. In the fifth sub-phase t5, the ninth transistor T9 is continuously turned on. At this time, the second clock signal CK2 jumps from a high potential to a low potential. As a result, the fifth node N5 is rapidly pulled down to less than the first effective potential through the coupling effect of the second storage capacitor C2, so that both the seventh transistor T7 and the fifth transistor T5 are fully turned on, and the signal output terminal OUT outputs the second power supply signal VGL. At the same time, the sixth node N6 is quickly written with the second effective potential of the first clock signal CK1, thereby completely turning off the sixth transistor T6 and ensuring that the signal output terminal OUT stably outputs the second power supply signal VGL.

[0154] Alternatively, as Figure 12As shown, the difference from the above-mentioned Example 7 is that the control electrode of the fifth transistor T5 is electrically connected to the first node N1. Specifically, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, the second electrode of the fifth transistor T5 is electrically connected to the sixth node N6, and the control electrode of the fifth transistor T5 is electrically connected to the first node N1. Figure 5 As shown, in the fourth sub-phase t4, the first transistor T1 is turned on, and the first effective potential is written to the first node N1. As a result, the fifth transistor T5 electrically connected to the first node N1 can quickly respond by turning on and writing the first effective potential to the sixth node N6, thereby eliminating the potential attenuation caused by the eighth transistor T8 and ensuring that the sixth transistor T6 is fully turned on. Similarly, in the fifth sub-phase t5, the first transistor T1 is turned off, and the first node N1 maintains the low potential of the previous phase. As a result, the fifth transistor T5 electrically connected to the first node N1 can quickly respond by turning on and writing the second effective potential to the sixth node N6, thereby quickly raising the potential of the sixth node N6 and timely turning off the sixth transistor T6.

[0155] like Figure 5 As shown, when the sixth transistor T6 is turned on, the first effective potential or the second effective potential of the first clock signal CK1 can be provided to the signal output terminal OUT. For example, in the third sub-stage t3, the sixth transistor T6 is turned on, and the potential of the first clock signal CK1 is the second effective potential. Therefore, the signal output terminal OUT outputs a high-level signal. For another example, in the fourth sub-stage t4, after the first clock signal CK1 jumps from a high level to a low level, the sixth node N6 is further pulled down to less than the first effective potential through the coupling effect of the third storage capacitor C3, so that the sixth transistor T6 is fully turned on, and the potential of the first clock signal CK1 is the first effective potential. Therefore, the signal output terminal OUT can fully output a low-level signal, realizing a direct jump from a high level to a low level, eliminating the step potential, and improving the panel horizontal stripe defect.

[0156] Optionally, the shift register has some sub-timing stages in the timing control stage, such as the second sub-stage t2, in which the first clock signal CK1 and the second clock signal CK2 are both at the first effective potential. The potential of the second node N2 is pulled down through coupling by the first storage capacitor C1, thereby turning on the third transistor T3 and writing the first effective potential to the third node N3. The eighth transistor T8 is a normally open transistor, so the potential of the third node N3 is further written to the sixth node N6. However, the potential of the sixth node N6 decays and fails to reach the first effective potential (e.g., greater than -5V but less than 0). Furthermore, because the first electrode of the sixth transistor T6 is at the first effective potential at this time, the gate-source voltage Vgs of the sixth transistor T6 is V_6-VGL>0V, the sixth transistor T6 is not turned on, and the signal output terminal OUT ultimately continues to output the signal of the previous sub-stage, i.e., the low-level signal of the first sub-stage t1, ensuring stable signal output.

[0157] Optionally, during the timing control phase, the rising edge of the first clock signal CK1 (i.e., the time point when the signal transitions from a low level to a high level) is located within the sub-timing phase where the first valid potential of the second clock signal CK2 is located, and the falling edge of the second clock signal CK2 (i.e., the time point when the signal transitions from a high level to a low level) is located within the sub-timing phase where the first valid potential of the first clock signal CK1 is located. In this way, the clock timing from the second sub-phase t2 to the third sub-phase t3, and the clock timing from the fourth sub-phase t4 to the fifth sub-phase t5, can be generated. By controlling the shift register based on this clock timing, the potential step of the output signal at the signal output terminal OUT can be eliminated.

[0158] For ease of understanding, the specific working principle of the circuit structure of Example 7 is fully described below. Figure 5 As shown, the timing control phase includes a first sub-phase t1 , a second sub-phase t2 , a third sub-phase t3 , a fourth sub-phase t4 and a fifth sub-phase t5 .

[0159] First sub-stage t1: The potential of the input signal STV and the potential of the second clock signal CK2 are both the second effective potential, and the first clock signal CK1 is the first effective potential. The first transistor T1 is turned on, and the second transistor T2 is turned off; the second effective potential (e.g., +5V) is written to the first node N1. The fourth transistor T4 is a normally open transistor, so the potential of the first node N1 is further written to the fifth node N5, thereby controlling the seventh transistor T7, the fifth transistor T5, and the ninth transistor T9 to be turned off. At the same time, the first storage capacitor C1 pulls the potential of the second node N2 up to the second clock signal CK2 (high level), and the third transistor T3 is turned off. Finally, the signal output terminal OUT continues to output the signal of the previous sub-stage, such as a low-level signal.

[0160] Second sub-phase t2: The potential of the input signal STV is at the second effective potential, and the potentials of the first clock signal CK1 and the second clock signal CK2 are both at the first effective potential. The first transistor T1 is turned on, and the second transistor T2 is turned off. The second effective potential (e.g., +5V) is written to the first node N1. Since the fourth transistor T4 is a normally-on transistor, the potential of the first node N1 is further written to the fifth node N5, thereby turning off the seventh transistor T7, the fifth transistor T5, and the ninth transistor T9. Simultaneously, since the potential of the second clock signal CK2 is at the first effective potential, the coupling effect of the first storage capacitor C1 pulls the potential of the second node N2 down to below the first effective potential, turning on the third transistor T3 and writing the first effective potential to the third node N3. Furthermore, since the eighth transistor T8 is a normally-on transistor, the potential of the third node N3 is further written to the sixth node N6. However, the potential of the sixth node N6 decays and fails to reach the first effective potential (e.g., greater than -5V but less than 0). Because the first electrode of the sixth transistor T6 is at the first effective potential at this time, the gate-source voltage Vgs of the sixth transistor T6 = V_6 - VGL > 0V, the sixth transistor T6 is not turned on, and finally the signal output terminal OUT keeps outputting the signal of the previous sub-stage, that is, the low-level signal of the first sub-stage t1.

[0161] Third sub-phase t3: The potential of the input signal STV and the potential of the first clock signal CK1 are both at the second effective potential, and the potential of the second clock signal CK2 is at the first effective potential. The first transistor T1 and the second transistor T2 are both turned off, the first node N1 maintains the high potential of the previous phase, the fourth transistor T4 is normally open, the fifth node N5 maintains the high potential of the previous phase, and the seventh transistor T7 and the ninth transistor T9 are both turned off; the third transistor T3 remains on, the eighth transistor T8 is normally open, and the sixth node N6 continues to be written to the first effective potential. Because the first electrode of the sixth transistor T6 is at the second effective potential at this time, the gate-source voltage Vgs of the sixth transistor T6 = V_6 - VGH < 0V, so the sixth transistor T6 is turned on, and the signal output terminal OUT outputs the second effective potential of the first clock signal CK1.

[0162] Fourth sub-stage t4: The potential of the input signal STV and the potential of the first clock signal CK1 are both the first effective potential, and the potential of the second clock signal CK2 is the second effective potential. The first transistor T1 and the second transistor T2 are both turned on. The first node N1 is written with the first effective potential (e.g., -5V). The fourth transistor T4 is a normally open transistor, so the potential of the first node N1 is further written to the fifth node N5. However, the potential of the fifth node N5 decays and fails to reach the first effective potential (e.g., greater than -5V but less than 0). Because the source of the seventh transistor T7 is now the signal output terminal OUT (i.e., a constant low-level signal, such as -5), the gate-source voltage Vgs of the seventh transistor T7 is V_5-(-5)>0V, and the seventh transistor T7 is not turned on. At the same time, the second transistor T2 is turned on, the first power supply signal VGH (i.e., a high-level signal) is written to the second node N2, and the third transistor T3 is turned off; since the first clock signal CK1 connected to the first plate of the third storage capacitor C3 jumps from the second effective potential to the first effective potential, the sixth node N6 can be bootstrapped and pulled down to less than the first effective potential through the third storage capacitor C3, so that the sixth transistor T6 is fully turned on, and the signal output terminal OUT outputs the first effective potential of the first clock signal CK1 at this time, thereby realizing a direct jump of the output signal from a high level to a low level, eliminating the step potential, and thus improving the horizontal stripe defect.

[0163] At the same time, due to the decay of the potential of the fifth node N5, the fifth transistor T5 is also not fully turned on. However, despite the decay of the potential of the fifth node N5, the first electrode of the ninth transistor T9 is now at the second effective potential. Therefore, the gate-source voltage Vgs of the ninth transistor T9 is V_5-VGH<0V, and the ninth transistor T9 can be fully turned on, and the second effective potential is written to the fourth node N4.

[0164] Fifth sub-phase t5: The potential of the input signal STV and the potential of the second clock signal CK2 are both at the first effective potential, and the potential of the first clock signal CK1 is at the second effective potential. The first transistor T1 is turned off, the ninth transistor T9 is continuously turned on, and the first effective potential of the second clock signal CK2 is written to the fourth node N4. Since the second clock signal CK2 connected to the second storage capacitor C2 transitions from the second effective potential to the first effective potential, the second storage capacitor C2 can be used to bootstrap the fifth node N5 to a level below the first effective potential. This fully turns on both the seventh transistor T7 and the fifth transistor T5, and the signal output terminal OUT outputs the second power supply signal VGL. The fifth transistor T5 is turned on, and the second effective potential of the first clock signal CK1 is written to the sixth node N6, ensuring that the sixth transistor T6 is completely turned off. Furthermore, the second transistor T2 is turned on, the first power supply signal VGH is written to the second node N2, and the third transistor T3 is turned off.

[0165] The potential simulation waveforms of the first node N1 to the sixth node N6 can be found in Figure 15 According to the above driving mode, the signal output terminal OUT outputs a high level with a fixed width and no steps.

[0166] In some embodiments, as Figure 10 As shown, the second control sub-circuit 3 is configured to control the potential of the third node N3 using the second power signal VGL transmitted by the second power line in response to the potential of the second node N2; the potential of the second power signal VGL output by the second power line is a first effective potential. The third control sub-circuit 4 is specifically configured to control the potential of the sixth node N6 using the second effective potential of the first clock signal CK1 in response to the potential of the fifth node N5, and to control the potentials of the fourth node N4 and the fifth node N5 using the second clock signal CK2. The output sub-circuit 5 is specifically configured to output the second power signal VGL through the signal output terminal OUT in response to the potential of the fifth node N5, or to output the first clock signal CK1 through the signal output terminal OUT in response to the potential of the sixth node N6.

[0167] The circuit structures of the input sub-circuit 1 , the first control sub-circuit 2 and the isolation sub-circuit 6 can refer to those described in the above example 1, and the repeated parts will not be repeated here.

[0168] A first electrode of the third transistor T3 is electrically connected to the second power line, a second electrode of the third transistor T3 is electrically connected to the third node N3, and a control electrode of the third transistor T3 is electrically connected to the second node N2. A first plate of the first storage capacitor C1 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, and a second plate of the first storage capacitor C1 is electrically connected to the second node N2. A first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, a second electrode of the fifth transistor T5 is electrically connected to the sixth node N6, and a control electrode of the fifth transistor T5 is electrically connected to the fifth node N5. A first electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, a second electrode of the ninth transistor T9 is electrically connected to the fourth node N4, and a control electrode of the ninth transistor T9 is electrically connected to the fifth node N5. A first plate of the second storage capacitor C2 is electrically connected to the fifth node N5, and a second plate of the second storage capacitor C2 is electrically connected to the fourth node N4. A first electrode of the sixth transistor T6 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, a second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and a control electrode of the sixth transistor T6 is electrically connected to the sixth node N6. A first plate of the third storage capacitor C3 is electrically connected to the first clock signal terminal, and a second plate of the third storage capacitor C3 is electrically connected to the sixth node N6. A first electrode of the seventh transistor T7 is electrically connected to the second power line transmitting the second power signal VGL, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT, and a control electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0169] Here, the control electrode of the fifth transistor T5 and the control electrode of the ninth transistor T9 are both electrically connected to the fifth node N5. Figure 5 As shown, in the fourth sub-phase t4, the ninth transistor T9 is turned on. The coupling effect of the second storage capacitor C2 can rapidly raise the potential of the fifth node N5, thereby ensuring that the seventh transistor T7 is completely turned off and eliminating the potential step. In the fifth sub-phase t5, the ninth transistor T9 is continuously turned on. At this time, the second clock signal CK2 jumps from a high potential to a low potential. As a result, the fifth node N5 can be rapidly lowered to less than the first effective potential through the coupling effect of the second storage capacitor C2, so that both the seventh transistor T7 and the fifth transistor T5 are fully turned on, and the signal output terminal OUT outputs the second power supply signal VGL. Simultaneously, the second effective potential is written to the sixth node N6, thereby completely turning off the sixth transistor T6 and ensuring that the signal output terminal OUT stably outputs the second power supply signal VGL.

[0170] Alternatively, as Figure 13As shown, the difference from the above-mentioned Example 8 is that the control electrode of the fifth transistor T5 is electrically connected to the first node N1. Specifically, the first electrode of the fifth transistor T5 is electrically connected to the first clock signal terminal for transmitting the first clock signal CK1, the second electrode of the fifth transistor T5 is electrically connected to the sixth node N6, and the control electrode of the fifth transistor T5 is electrically connected to the first node N1. Figure 5 As shown, in the fourth sub-phase t4, the first transistor T1 is turned on, and the first effective potential is written to the first node N1. As a result, the fifth transistor T5 electrically connected to the first node N1 can quickly respond by turning on and writing the first effective potential to the sixth node N6, thereby eliminating the potential attenuation caused by the eighth transistor T8 and ensuring that the sixth transistor T6 is fully turned on. Similarly, in the fifth sub-phase t5, the first transistor T1 is turned off, and the first node N1 maintains the low potential of the previous phase. As a result, the fifth transistor T5 electrically connected to the first node N1 can quickly respond by turning on and writing the second effective potential to the sixth node N6, thereby quickly raising the potential of the sixth node N6 and timely turning off the sixth transistor T6.

[0171] The circuit structure of Example 8 adopts Figure 5 The timing control method shown is as follows: in the first sub-stage t1, the potential of the input signal STV and the potential of the second clock signal CK2 are both the second effective potential, and the first clock signal CK1 is the first effective potential. In the second sub-stage t2, the potential of the input signal STV is the second effective potential, and the potential of the first clock signal CK1 and the potential of the second clock signal CK2 are both the first effective potential. In the third sub-stage t3, the potential of the input signal STV and the potential of the first clock signal CK1 are both the second effective potential, and the potential of the second clock signal CK2 is the first effective potential. In the fourth sub-stage t4, the potential of the input signal STV and the potential of the first clock signal CK1 are both the first effective potential, and the potential of the second clock signal CK2 is the second effective potential. In the fifth sub-stage t5, the potential of the input signal STV and the potential of the second clock signal CK2 are both the first effective potential, and the potential of the first clock signal CK1 is the second effective potential.

[0172] The on-off states of the transistors in each sub-stage of this embodiment are identical to those in Example 7, and the repeated descriptions are omitted. Thus, the circuit structure of this embodiment eliminates the potential step in the middle section of the output signal, thereby improving the panel's horizontal stripes. Furthermore, this embodiment also utilizes a 9T3C circuit structure, enabling a narrow panel border.

[0173] The difference between the circuit structure of this embodiment and that of Example 1 is that the first electrode of the third transistor T3 is electrically connected to the second power line transmitting the second power signal VGL, thereby continuously providing a constant low-level signal to the first electrode of the third transistor T3. In the first sub-phase t1, the third transistor T3 is turned off; in the second sub-phase t2, the third transistor T3 is turned on, thereby writing the second power signal VGL (which is the same as the power signal VGL) to the third node N3. Figure 1 The circuit structure writes the first effective potential of the second clock signal CK2 in the second sub-stage t2); in the third sub-stage t3, the third transistor T3 is continuously turned on and continues to write the second power supply signal VGL to the third node N3; in the fourth sub-stage t4 and the fifth sub-stage t5, the third transistor T3 is turned off.

[0174] In the circuit structures of Examples 7 and 10, as well as Examples 8 and 11, the output duration of the high-level signal is short under timing control, and thus can be used to provide a high-level signal to the N-type transistors (such as the threshold compensation transistor M2, see Figure 26 ) provides a scanning signal.

[0175] In some embodiments, as Figure 11 As shown, the second control sub-circuit 3 is configured to control the potential of the third node N3 using the first effective potential of the second clock signal CK2 in response to the potential of the second node N2. The third control sub-circuit 4 is specifically configured to control the potential of the sixth node N6 using the first power signal VGH transmitted by the first power line in response to the potential of the first node N1, and to control the potentials of the fourth node N4 and the fifth node N5 using the second clock signal CK2. The output sub-circuit 5 is specifically configured to output the second power signal VGL through the signal output terminal OUT in response to the potential of the fifth node N5, or to output the first power signal VGH through the signal output terminal OUT in response to the potential of the sixth node N6.

[0176] The circuit structures of the input sub-circuit 1 , the first control sub-circuit 2 and the isolation sub-circuit 6 can refer to those described in the above example 1, and the repeated parts will not be repeated here.

[0177] A first electrode of the third transistor T3 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, a second electrode of the third transistor T3 is electrically connected to the third node N3, and a control electrode of the third transistor T3 is electrically connected to the second node N2. A first plate of the first storage capacitor C1 is electrically connected to the second clock signal terminal, and a second plate of the first storage capacitor C1 is electrically connected to the second node N2. A first electrode of the fifth transistor T5 is electrically connected to the first power line, a second electrode of the fifth transistor T5 is electrically connected to the sixth node N6, and a control electrode of the fifth transistor T5 is electrically connected to the first node N1. A first electrode of the ninth transistor T9 is electrically connected to the second clock signal terminal for transmitting the second clock signal CK2, a second electrode of the ninth transistor T9 is electrically connected to the fourth node N4, and a control electrode of the ninth transistor T9 is electrically connected to the fifth node N5. A first plate of the second storage capacitor C2 is electrically connected to the fifth node N5, and a second plate is electrically connected to the fourth node N4. A first electrode of the sixth transistor T6 is electrically connected to the first power line for transmitting the first power signal VGH, a second electrode of the sixth transistor T6 is electrically connected to the signal output terminal OUT, and a control electrode of the sixth transistor T6 is electrically connected to the sixth node N6. A first plate of the third storage capacitor C3 is electrically connected to the first power line, and a second plate of the third storage capacitor C3 is electrically connected to the sixth node N6. A first electrode of the seventh transistor T7 is electrically connected to the second power line transmitting the second power signal VGL, a second electrode of the seventh transistor T7 is electrically connected to the signal output terminal OUT, and a control electrode of the seventh transistor T7 is electrically connected to the fifth node N5.

[0178] Here, a first electrode of the fifth transistor T5 is electrically connected to the first power line transmitting the first power signal VGH, a second electrode of the fifth transistor T5 is electrically connected to the sixth node N6, and a control electrode of the fifth transistor T5 is electrically connected to the first node N1. Figure 16 Another exemplary timing diagram of a shift register provided in the embodiment of the present disclosure is as follows: Figure 16 As shown, in the third sub-phase t3, the first transistor T1 is turned on, and the first effective potential is written to the first node N1. As a result, the fifth transistor T5 electrically connected to the first node N1 can quickly respond by turning on and writing the second effective potential of the first power supply signal VGH to the sixth node N6, thereby promptly turning off the sixth transistor T6. Similarly, in the fourth sub-phase t5, the first transistor T1 is turned off, and the first node N1 maintains the low potential of the previous phase. As a result, the fifth transistor T5 electrically connected to the first node N1 can quickly respond by turning on and continuing to write the second effective potential to the sixth node N6, ensuring that the potential of the sixth node N6 is continuously pulled high, keeping the sixth transistor T6 continuously in the off state.

[0179] In addition, in the fourth sub-stage t4, the first transistor T1 is turned off and the ninth transistor T9 is turned on. At this time, the second clock signal CK2 jumps from a high potential to a low potential. In this way, the potential of the fifth node N5 can be quickly lowered through the coupling effect of the second storage capacitor C2, that is, lowered to less than the first effective potential. At this time, the first node N1 maintains the first effective potential of the previous stage. Therefore, the low potential of the first node N1 is higher than the low potential of the fifth node N5. Based on this, the gate-source voltage generated by the control electrode of the fifth transistor T5 being electrically connected to the first node N1 is Vgs_1=V N1 Since a long-term excessive voltage difference can easily cause the threshold voltage Vth of the fifth transistor T5 to shift, thereby affecting device performance, in this embodiment, when the control electrode of the fifth transistor T5 is electrically connected to the first node N1, the voltage difference between the gate-source voltage Vgs_1 can be reduced to ensure device performance.

[0180] Alternatively, as Figure 14 As shown, the difference from the above-mentioned Example 9 is that the control electrodes of the fifth transistor T5 and the ninth transistor T9 are both electrically connected to the fifth node N5. Figure 16 As shown, in the fourth sub-stage t4, the ninth transistor T9 is continuously turned on. At this time, the second clock signal CK2 jumps from a high potential to a low potential. In this way, the potential of the fifth node N5 can be quickly lowered through the coupling effect of the second storage capacitor C2, that is, lowered to less than the first effective potential, so that the seventh transistor T7 and the fifth transistor T5 are fully turned on, and the signal output terminal OUT outputs the second power supply signal VGL; at the same time, the sixth node N6 is quickly written with the second effective potential of the first power supply signal VGH, thereby completely turning off the sixth transistor T6, ensuring that the signal output terminal OUT stably outputs the second power supply signal VGL.

[0181] like Figure 16As shown, the first clock signal CK1 and the second clock signal CK2 are both pulse signals. In one cycle of the first clock signal CK1, the duration of the first effective potential is less than the duration of the second effective potential. In one cycle of the second clock signal CK2, the duration of the first effective potential is less than the duration of the second effective potential. In one cycle, the duration of the first effective potential of the first clock signal CK1 is equal to the duration of the first effective potential of the second clock signal CK2; the duration of the second effective potential of the first clock signal CK1 is equal to the duration of the second effective potential of the second clock signal CK2. The rising edge and the falling edge of the first clock signal CK1 are both located in the sub-timing stage where the second effective potential of the second clock signal CK2 is located. Similarly, the rising edge and the falling edge of the second clock signal CK2 are also located in the sub-timing stage where the second effective potential of the first clock signal CK1 is located. In this way, under this timing control, the GOA circuit of Example 3 can output a high-level signal for a long time, and can therefore be used to supply power to P-type transistors in the pixel driving circuit (such as light-emitting control transistors and reset transistors, etc., see Figure 26 ) provides a scanning signal.

[0182] The following is a complete description of the specific working principle of the circuit structure of Example 9. Figure 16 As shown, the timing control phase includes a first sub-phase t1 , a second sub-phase t2 , a third sub-phase t3 and a fourth sub-phase t4 .

[0183] First sub-phase t1: The potential of the input signal STV and the potential of the second clock signal CK2 are both at the second effective potential, and the potential of the first clock signal CK1 is at the first effective potential. The first transistor T1 is turned on, and the second effective potential is written to the first node N1 and the fifth node N5. This controls the fifth transistor T5 to be turned off, the ninth transistor T9 to be turned off, and the seventh transistor T7 to be turned off. Simultaneously, the first storage capacitor C1 pulls the potential of the second node N2 up to the level of the second clock signal CK2 (high level), and the third transistor T3 is turned off. Ultimately, the signal output terminal OUT continues to output the signal of the previous sub-phase, such as a low-level signal.

[0184] Second sub-phase t2: The potential of the input signal STV and the potential of the first clock signal CK1 are both at the second effective potential, and the potential of the second clock signal CK2 is at the first effective potential. Because the second clock signal CK2 connected to the first storage capacitor C1 transitions from the second effective potential to the first effective potential, the potential of the second node N2 is pulled down by the coupling effect of the first storage capacitor C1, turning on the third transistor T3. The first effective potential is written to the third node N3 and the sixth node N6, turning on the sixth transistor T6, and the signal output terminal OUT outputs the first power supply signal VGH, i.e., a high-level signal.

[0185] Third sub-phase t3: The potential of the input signal STV and the potential of the first clock signal CK1 are both the first effective potential, and the potential of the second clock signal CK2 is the second effective potential. The first transistor T1 and the second transistor T2 are both turned on, and the third transistor T3 is turned off. The first node N1 is written to the first effective potential (e.g., -5V). The fourth transistor T4 is a normally open transistor, so the potential of the first node N1 is further written to the fifth node N5. However, the potential of the fifth node N5 decays and fails to reach the first effective potential (e.g., greater than -5V but less than 0). Although the potential of the fifth node N5 decays (e.g., greater than -5V but less than 0), the gate-source voltage Vgs of the fifth transistor T5 is V_5-VGH<0V, so the fifth transistor T5 is fully turned on, and the first power supply signal VGH is written to the sixth node N6, ensuring that the sixth transistor T6 is completely turned off. Because the source of the seventh transistor T7 is the signal output terminal OUT, and the signal output terminal OUT is at a high level (e.g., +5) in the second sub-phase t2, the gate-source voltage Vgs of the seventh transistor T7 is V_5-(+5)<0V, turning on the seventh transistor T7. However, as VGL is output, the source voltage of the seventh transistor T7 decreases, and the seventh transistor T7 cannot fully turn on, thus forming a step. At the same time, although the potential of the fifth node N5 decays, the first electrode of the ninth transistor T9 is at the second effective potential. Therefore, the gate-source voltage Vgs of the ninth transistor T9 is V_5-VGH<0V, and the ninth transistor T9 can fully turn on. Turning on the ninth transistor T9 can pull up the potential of the fifth node N5, similarly preventing the seventh transistor T7 from fully turning on, forming a step potential.

[0186] Fourth sub-phase t4: The potential of the input signal STV and the potential of the second clock signal CK2 are both at the first effective potential, and the potential of the first clock signal CK1 is at the second effective potential. The first transistor T1 is turned off, the ninth transistor T9 is continuously turned on, and the first effective potential of the second clock signal CK2 is written to the fourth node N4. Since the second clock signal CK2 connected to the second storage capacitor C2 transitions from the second effective potential to the first effective potential, the second storage capacitor C2 can be used to bootstrap the fifth node N5 to a level below the first effective potential, fully turning on the seventh transistor T7 and the fifth transistor T5. The signal output terminal OUT outputs the second power supply signal VGL. The fifth transistor T5 is turned on, and the first power supply signal VGH is written to the sixth node N6, ensuring that the sixth transistor T6 is completely turned off. The fourth transistor T4 and the eighth transistor T8 are both normally open transistors. The second transistor T2 is turned on, the first power supply signal VGH is written to the second node N2, and the third transistor T3 is turned off.

[0187] In this embodiment, according to the above driving method, the signal output terminal OUT can output a high level with any width.

[0188] The three exemplary shift registers provided in the embodiments of the present disclosure all adopt a 9T3C (9 transistors and 3 storage capacitors) circuit. Compared with the GOA circuit of the prior art, the panel border is reduced to meet user needs.

[0189] In addition, the embodiment of the present disclosure also provides a shift register driving method, which is mainly used to drive and control the shift registers of Examples 1 and 2, Examples 4 and 5, and Examples 7 and 8. Figure 5 As shown, the timing control phase of the shift register includes a first sub-phase t1, a second sub-phase t2, a third sub-phase t3, a fourth sub-phase t4 and a fifth sub-phase t5.

[0190] In the first sub-stage t1, the potential of the input signal STV and the potential of the second clock signal CK2 are both the second effective potential, and the first clock signal CK1 is the first effective potential; the input sub-circuit 1 writes the input signal STV to the first node N1 under the control of the first clock signal CK1; the output sub-circuit 5 maintains the output potential of the previous sub-stage under the control of the potential of the first node N1.

[0191] In the second sub-stage t2, the potential of the input signal STV is the second effective potential, and the potential of the second node N2, the potential of the first clock signal CK1, and the potential of the second clock signal CK2 are all the first effective potentials; the input sub-circuit 1 writes the input signal STV to the first node N1 under the control of the first clock signal CK1; the second control sub-circuit 3 writes the second clock signal CK2 or the second power supply signal VGL to the third node N3 under the control of the potential of the second node N2; the output sub-circuit 5 maintains the output potential of the previous sub-stage under the control of the potential of the third node N3 and the first clock signal CK1.

[0192] In the second sub-stage t2, for the shift register of Example 1, the second control sub-circuit 3 writes the second clock signal CK2 to the third node N3 under the control of the potential of the second node N2; for the shift register of Example 2, the second control sub-circuit 3 writes the second power supply signal VGL to the third node N3 under the control of the potential of the second node N2.

[0193] In the second sub-phase t2, due to the potential of the third node N3 and the control of the first clock signal CK1, the sixth transistor T6 is not turned on, thereby ensuring that the output sub-circuit 5 maintains the low potential outputted in the previous sub-phase, achieving stable signal output. For example, this better adapts to drive the threshold compensation transistor M2 in the pixel driving circuit, ensuring stable light emission of the light-emitting device.

[0194] In the third sub-stage t3, the potential of the input signal STV and the potential of the first clock signal CK1 are both the second effective potential, and the potential of the second node N2 and the potential of the second clock signal CK2 are the first effective potential; the second control sub-circuit 3, under the control of the potential of the second node N2, writes the second clock signal CK2 or the second power supply signal VGL to the third node N3; the output sub-circuit 5, under the control of the potential of the third node N3 and the first clock signal CK1, outputs the first clock signal CK1 through the signal output terminal OUT.

[0195] In the third sub-stage t3, for the shift register of Example 1, the second control sub-circuit 3 writes the second clock signal CK2 to the third node N3 under the control of the potential of the second node N2; for the shift register of Example 2, the second control sub-circuit 3 writes the second power supply signal VGL to the third node N3 under the control of the potential of the second node N2.

[0196] In the third sub-phase t3 , due to the potential of the third node N3 and the control of the first clock signal CK1 , the sixth transistor T6 can be fully turned on, thereby outputting the second effective potential of the first clock signal CK1 .

[0197] In the fourth sub-phase t4, the potential of the input signal STV and the potential of the first clock signal CK1 are both the first effective potential, and the potential of the second clock signal CK2 is the second effective potential; under the control of the first clock signal CK1, the input sub-circuit 1 writes the input signal STV to the first node N1; under the control of the input signal STV, the first control sub-circuit 2 writes the first power supply signal VGH to the second node N2; under the control of the potential of the first node N1, the third control sub-circuit 4 controls the potential of the third node N3 using the first clock signal CK1; and under the control of the potential of the third node N3 and the first clock signal CK1, the output sub-circuit 5 outputs the first clock signal CK1 through the signal output terminal OUT.

[0198] In the fourth sub-stage t4, since the first clock signal CK1 connected to the first plate of the third storage capacitor C3 jumps from the second effective potential to the first effective potential, the sixth node N6 is further pulled down to less than the first effective potential through the coupling effect of the third storage capacitor C3. Therefore, the sixth transistor T6 is fully turned on, and the signal output terminal OUT outputs the first effective potential of the first clock signal CK1 at this time, realizing the direct jump of the output signal from the high level to the low level, eliminating the step potential, and thus improving the horizontal stripe defect.

[0199] In the fifth sub-stage t5, the potential of the input signal STV and the potential of the second clock signal CK2 are both the first effective potential, and the potential of the first clock signal CK1 is the second effective potential; under the control of the input signal STV, the first control sub-circuit 2 writes the first power supply signal VGH to the second node N2; under the control of the first node N1, the third control sub-circuit 4 controls the potential of the third node N3 using the first clock signal CK1; and under the control of the first node N1, the output sub-circuit 5 outputs the second power supply signal VGL through the signal output terminal OUT.

[0200] In the fifth sub-phase t5, the first control sub-circuit 2 controls the second control sub-circuit 3 to not write a voltage to the third node N3. Under control of the first node N1, the third control sub-circuit 4 uses the first clock signal CK1 to write a second effective potential to the third node N3, ensuring that the sixth transistor T6 is completely turned off. Under control of the first clock signal CK1, the input sub-circuit 1 does not write a voltage to the first node N1, causing the first node N1 to maintain the low voltage of the previous sub-phase. The seventh transistor T7 turns on, outputting the second power supply signal VGL through the signal output terminal OUT.

[0201] It should be noted that, with regard to the on-off states of the transistors in the input sub-circuit 1, the first control sub-circuit 2, the second control sub-circuit 3, the third control sub-circuit 4 and the output sub-circuit 5, please refer to the detailed description of the above-mentioned shift register, and the repeated parts will not be repeated here.

[0202] In addition, the above timing sequence is also applicable to Examples 4, 5, 7, 8, 12 and 13. Please refer to the detailed description of the working timing sequence of Example 7 of the above shift register, and the repeated parts will not be repeated.

[0203] In addition, an embodiment of the present disclosure further provides a gate drive circuit, which specifically includes N cascaded shift registers as provided in any of the above embodiments (such as Example 7, Example 8 or Example 9).

[0204] Figure 17 A schematic diagram of a gate drive circuit provided in an embodiment of the present disclosure includes N cascaded shift registers of Example 7. Figure 18 A schematic diagram of another gate driving circuit provided in an embodiment of the present disclosure, which includes N cascaded shift registers of Example 8. Figure 19 Schematic diagram of a gate drive circuit provided by an embodiment of the present disclosure, which includes N cascaded shift registers of Example 9. Figures 17 to 19 As shown, in addition to the first-stage shift register, the signal input terminal of the i+1-stage shift register is<i+1> Electrically connected to the signal output terminal OUT of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0205] like Figure 17 and Figure 18 As shown, the gate drive circuit is configured to provide a gate driver circuit to each pixel drive circuit N-type transistor (such as the threshold compensation transistor M2, see Figure 26 The control electrode of the circuit breaker provides a turn-on or turn-off signal, such as Figure 19 As shown, the gate drive circuit is configured to provide a gate driver circuit to each pixel drive circuit P-type transistor (such as a light emitting control transistor and a reset transistor, etc., see Figure 26 The control electrode (as shown) provides an on or off signal so that the pixel driving circuit controls the light-emitting device to emit light.

[0206] It should be noted that the light-emitting devices involved in the embodiments of the present disclosure may include but are not limited to organic light-emitting diodes (OLED), quantum dot light-emitting diodes (QLED) or micro light-emitting diodes (MicroLED), etc.

[0207] Optionally, the light-emitting device is an OLED device.

[0208] For the description of the specific structure of the shift register, please refer to the detailed description of the shift register above, and the repeated parts will not be repeated here.

[0209] In some embodiments, in addition to the first-stage shift register, the first clock signal terminal of the (i+1)-stage shift register is electrically connected to the second clock signal terminal of the i-stage shift register. Thus, the first clock signal terminal of the (i+1)-stage shift register and the second clock signal terminal of the i-stage shift register are electrically connected to the same clock signal line.

[0210] like Figures 17 to 19 As shown, taking the example of using two clock signal lines to provide clock signals, such as a first clock signal line CLK1 and a second clock signal line CLK2. The first clock signal terminals of the odd-numbered shift registers are electrically connected to the first clock signal line CLK1, and the second clock signal terminals are electrically connected to the second clock signal line CLK2. The first clock signal terminals of the even-numbered shift registers are electrically connected to the second clock signal line CLK2, and the second clock signal terminals are electrically connected to the first clock signal line CLK1.

[0211] For example, Figure 17As shown, the control electrode of the first transistor T1 of the i-th stage shift register, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are all electrically connected to the first clock signal line CLK1. At this time, the control electrode of the first transistor T1 of the i+1-th stage shift register, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are all electrically connected to the second clock signal line CLK2. The first electrode of the third transistor T3 of the i-th stage shift register and the first electrode of the ninth transistor T9 are both electrically connected to the second clock signal line CLK2. At this time, the first electrode of the third transistor T3 of the i+1-th stage shift register and the first electrode of the ninth transistor T9 are both electrically connected to the first clock signal line CLK1. For another example, Figure 18 As shown, the control electrode of the first transistor T1 of the i-th stage shift register, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are all electrically connected to the first clock signal line CLK1. At this time, the control electrode of the first transistor T1 of the i+1-th stage shift register, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are all electrically connected to the second clock signal line CLK2. The first plate of the first storage capacitor C1 of the i-th stage shift register and the first electrode of the ninth transistor T9 are both electrically connected to the second clock signal line CLK2. At this time, the first plate of the first storage capacitor C1 of the i-th stage shift register and the first electrode of the ninth transistor T9 are both electrically connected to the first clock signal line CLK1. For another example, Figure 19 As shown, the control electrode of the first transistor T1 of the i-th stage shift register is electrically connected to the first clock signal line CLK1. At this time, the control electrode of the first transistor T1 of the i+1-th stage shift register is electrically connected to the second clock signal line CLK2. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the i-th stage shift register are both electrically connected to the second clock signal line CLK2. At this time, the first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the i+1-th stage shift register are both electrically connected to the first clock signal line CLK1.

[0212] The present disclosure adopts a row-by-row scanning driving method, so the first clock signal end of the i+1-th stage shift register and the second clock signal end of the i-th stage shift register can be electrically connected to the same clock signal line. At different times, the clock signal line transmits clock signals of different level states, which realizes row-by-row driving while also saving the number of clock signal lines, saving wiring space and cost.

[0213] The working sequence of driving the cascade shift register is as follows Figure 5 and Figure 15 Driven by two clock signal lines, the high level time of the output signal output by each level shift register is 1H, where H represents the unit time length, and can be an N-type transistor in the pixel driving circuit (such as the threshold compensation transistor M2, see Figure 26) provides a scanning signal.

[0214] In some embodiments, four clock signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, and the fourth clock signal line CLK4, can be used to drive the cascade shift register. For example, the gate drive circuit includes the shift register of cascade example 1. For details on the electrical connection between the cascade shift register and the four clock signal lines, see Figure 20 As shown, its working timing is shown in Figure 21 shown.

[0215] Specifically, if Figure 20 As shown, N cascaded shift registers are divided into multiple groups, each group including four cascaded shift registers. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the first stage shift register are all electrically connected to the first clock signal line CLK1. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the first stage shift register are all electrically connected to the second clock signal line CLK2. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the second stage shift register are all electrically connected to the second clock signal line CLK2. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the second stage shift register are all electrically connected to the third clock signal line CLK3. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the third stage shift register are all electrically connected to the third clock signal line CLK3. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the third stage shift register are all electrically connected to the fourth clock signal line CLK4. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the fourth stage shift register are all electrically connected to the fourth clock signal line CLK4. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the fourth stage shift register are all electrically connected to the first clock signal line CLK1.

[0216] Optionally, the four clock signal lines are divided into four clock signal line groups, each of which includes two adjacent clock signal lines. The first clock signal line group includes a first clock signal line CLK1 and a second clock signal line CLK2. The second clock signal line group includes a second clock signal line CLK2 and a third clock signal line CLK3. The third clock signal line group includes a third clock signal line CLK3 and a fourth clock signal line CLK4. The fourth clock signal line group includes a fourth clock signal line CLK4 and the first clock signal line CLK1. The shift register is arranged in a one-to-one correspondence with the clock signal line groups, and the clock signal lines in the clock signal line groups are used to provide a first clock signal CKL to a first clock signal terminal in the shift register and a second clock signal CK2 to a second clock signal terminal.

[0217] like Figure 21 As shown, the signal waveforms of two adjacent clock signal lines refer to the waveforms of the first clock signal CK1 and the second clock signal CK2 in the above-mentioned shift register. When driven by four clock signal lines, the output signals of the shift registers at each level (taking the output signals of the signal output terminals OUT1 to OUT4 of a group of shift registers as an example) have a long high level time, such as 5H, which can be a high level time for the N-type transistors in the pixel driving circuit (such as the threshold compensation transistor M2, see Figure 26 As shown) and / or P-type transistors (such as light-emitting control transistors and reset transistors, etc., see Figure 26 ) provides a scanning signal.

[0218] Alternatively, as Figure 21As shown, in the timing control stage, the rising edge of the clock signal transmitted by the first clock signal line CLK1 (i.e., the time node of the transition from low level to high level) is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the second clock signal line CLK2 is located, and the falling edge of the clock signal transmitted by the second clock signal line CLK2 (i.e., the time node of the transition from high level to low level) is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the first clock signal line CLK1 is located. The rising edge of the clock signal transmitted by the second clock signal line CLK2 is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the third clock signal line CLK3 is located, and the falling edge of the clock signal transmitted by the third clock signal line CLK3 is located in the sub-timing stage where the first valid potential of the clock signal 2 transmitted by the second clock signal line CLK2 is located. The rising edge of the clock signal transmitted by the third clock signal line CLK3 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fourth clock signal line CLK4 is located, and the falling edge of the clock signal transmitted by the fourth clock signal line CLK4 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the third clock signal line CLK3 is located. In this way, during the clock control phase of each stage of the shift register, an output signal with the step potential eliminated can be output.

[0219] In some embodiments, five clock signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, and the fifth clock signal line CLK5, can be used to drive the cascade shift register. For example, the gate drive circuit includes the shift register of cascade example 1. For details on the electrical connection between the cascade shift register and the five clock signal lines, see Figure 22 As shown, its working timing is shown in Figure 23 shown.

[0220] Specifically, if Figure 22As shown, N cascaded shift registers are divided into multiple groups, each group including five cascaded shift registers. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the first stage shift register are all electrically connected to the first clock signal line CLK1. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the first stage shift register are all electrically connected to the second clock signal line CLK2. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the second stage shift register are all electrically connected to the second clock signal line CLK2. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the second stage shift register are all electrically connected to the third clock signal line CLK3. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the third stage shift register are all electrically connected to the third clock signal line CLK3. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the third stage shift register are all electrically connected to the fourth clock signal line CLK4. The control electrode of the first transistor T1 of the fourth-stage shift register, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are all electrically connected to the fourth clock signal line CLK4. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the fourth-stage shift register are all electrically connected to the fifth clock signal line CLK5. The control electrode of the first transistor T1 of the fifth-stage shift register, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 are all electrically connected to the fifth clock signal line CLK5. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the fifth-stage shift register are all electrically connected to the first clock signal line CLK1.

[0221] Optionally, the five clock signal lines are divided into five clock signal line groups, each of which includes two adjacent clock signal lines. The first clock signal line group includes a first clock signal line CLK1 and a second clock signal line CLK2. The second clock signal line group includes a second clock signal line CLK2 and a third clock signal line CLK3. The third clock signal line group includes a third clock signal line CLK3 and a fourth clock signal line CLK4. The fourth clock signal line group includes a fourth clock signal line CLK4 and the first clock signal line CLK1. The fifth clock signal line group includes a fifth clock signal line CLK5 and the first clock signal line CLK1. The shift register is arranged in a one-to-one correspondence with the clock signal line group, and the clock signal lines in the clock signal line group are used to provide a first clock signal CKL to a first clock signal terminal in the shift register and a second clock signal CK2 to a second clock signal terminal.

[0222] like Figure 23As shown, the signal waveforms of two adjacent clock signal lines refer to the waveforms of the first clock signal CK1 and the second clock signal CK2 in the above-mentioned shift register. When driven by five clock signal lines, the high level time of the output signal output by each level of the shift register (taking the output signal of the signal output terminals OUT1 to OUT5 of a group of shift registers as an example) is relatively long, such as 7H, which can be a high level time for the N-type transistor in the pixel driving circuit (such as the threshold compensation transistor M2, see Figure 26 As shown) and / or P-type transistors (such as light-emitting control transistors and reset transistors, etc., see Figure 26 ) provides a scanning signal.

[0223] Alternatively, as Figure 23 As shown, in the timing control stage, the rising edge of the clock signal transmitted by the first clock signal line CLK1 (i.e., the time node of the transition from low level to high level) is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the second clock signal line CLK2 is located, and the falling edge of the clock signal transmitted by the second clock signal line CLK2 (i.e., the time node of the transition from high level to low level) is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the first clock signal line CLK1 is located. The rising edge of the clock signal transmitted by the second clock signal line CLK2 is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the third clock signal line CLK3 is located, and the falling edge of the clock signal transmitted by the third clock signal line CLK3 is located in the sub-timing stage where the first valid potential of the clock signal 2 transmitted by the second clock signal line CLK2 is located. The rising edge of the clock signal transmitted by the third clock signal line CLK3 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fourth clock signal line CLK4 is located, and the falling edge of the clock signal transmitted by the fourth clock signal line CLK4 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the third clock signal line CLK3 is located. The rising edge of the clock signal transmitted by the fourth clock signal line CLK4 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fifth clock signal line CLK5 is located, and the falling edge of the clock signal transmitted by the fifth clock signal line CLK5 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fourth clock signal line CLK4 is located. In this way, during the clock control phase of each level of the shift register, an output signal with step potential eliminated can be output.

[0224] In some embodiments, six clock signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5, and the sixth clock signal line CLK6, can be used to drive the cascade shift register. Taking the gate drive circuit including the shift register of cascade example 1 as an example, the electrical connection method of the cascade shift register and the six clock signal lines is shown in FIG. Figure 24 As shown, its working timing is shown in Figure 25 shown.

[0225] Specifically, if Figure 24 As shown, N cascaded shift registers are divided into multiple groups, each group including five cascaded shift registers. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the first stage shift register are all electrically connected to the first clock signal line CLK1. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the first stage shift register are all electrically connected to the second clock signal line CLK2. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the second stage shift register are all electrically connected to the second clock signal line CLK2. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the second stage shift register are all electrically connected to the third clock signal line CLK3. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the third stage shift register are all electrically connected to the third clock signal line CLK3. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the third stage shift register are all electrically connected to the fourth clock signal line CLK4. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the fourth-stage shift register are all electrically connected to the fourth clock signal line CLK4. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the fourth-stage shift register are all electrically connected to the fifth clock signal line CLK5. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the fifth-stage shift register are all electrically connected to the fifth clock signal line CLK5. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the fifth-stage shift register are all electrically connected to the sixth clock signal line CLK6. The control electrode of the first transistor T1, the first electrode of the fifth transistor T5, and the first electrode of the sixth transistor T6 of the sixth-stage shift register are all electrically connected to the sixth clock signal line CLK6. The first electrode of the third transistor T3 and the first electrode of the ninth transistor T9 of the sixth-stage shift register are all electrically connected to the first clock signal line CLK1.

[0226] Optionally, the six clock signal lines are divided into six clock signal line groups, each of the 1-5 clock signal line groups including two adjacent clock signal lines; the first clock signal line group includes a first clock signal line CLK1 and a second clock signal line CLK2; the second clock signal line group includes a second clock signal line CLK2 and a third clock signal line CLK3; the third clock signal line group includes a third clock signal line CLK3 and a fourth clock signal line CLK4; the fourth clock signal line group includes a fourth clock signal line CLK4 and the first clock signal line CLK1; the fifth clock signal line group includes a fifth clock signal line CLK5 and a sixth clock signal line CLK6; and the sixth clock signal line group includes a sixth clock signal line CLK6 and the first clock signal line CLK1. The shift register is arranged in a one-to-one correspondence with the clock signal line groups, and the clock signal lines in the clock signal line groups are used to provide a first clock signal CKL to a first clock signal terminal in the shift register and a second clock signal CK2 to a second clock signal terminal.

[0227] like Figure 25 As shown, the signal waveforms of two adjacent clock signal lines refer to the waveforms of the first clock signal CK1 and the second clock signal CK2 in the above-mentioned shift register. When driven by six clock signal lines, the high level time of the output signal output by each level of the shift register is relatively long, such as 9H, which can be a high level time for the N-type transistor in the pixel driving circuit (such as the threshold compensation transistor M2, see Figure 26 As shown) and / or P-type transistors (such as light-emitting control transistors and reset transistors, etc., see Figure 26 ) provides a scanning signal.

[0228] Alternatively, as Figure 25As shown, in the timing control stage, the rising edge of the clock signal transmitted by the first clock signal line CLK1 (i.e., the time node of the transition from low level to high level) is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the second clock signal line CLK2 is located, and the falling edge of the clock signal transmitted by the second clock signal line CLK2 (i.e., the time node of the transition from high level to low level) is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the first clock signal line CLK1 is located. The rising edge of the clock signal transmitted by the second clock signal line CLK2 is located in the sub-timing stage where the first valid potential of the clock signal transmitted by the third clock signal line CLK3 is located, and the falling edge of the clock signal transmitted by the third clock signal line CLK3 is located in the sub-timing stage where the first valid potential of the clock signal 2 transmitted by the second clock signal line CLK2 is located. The rising edge of the clock signal transmitted by the third clock signal line CLK3 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fourth clock signal line CLK4 is located, and the falling edge of the clock signal transmitted by the fourth clock signal line CLK4 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the third clock signal line CLK3 is located. The rising edge of the clock signal transmitted by the fourth clock signal line CLK4 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fifth clock signal line CLK5 is located, and the falling edge of the clock signal transmitted by the fifth clock signal line CLK5 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fourth clock signal line CLK4 is located. The rising edge of the clock signal transmitted by the fifth clock signal line CLK5 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the sixth clock signal line CLK6 is located, and the falling edge of the clock signal transmitted by the sixth clock signal line CLK6 is located in the sub-timing phase where the first valid potential of the clock signal transmitted by the fifth clock signal line CLK5 is located. In this way, during the clock control phase of each stage of the shift register, an output signal with the step potential eliminated can be output.

[0229] Of course, the gate drive circuit provided in the embodiment of the present disclosure can also adopt a clock signal driving scheme provided by seven clock signal lines, eight clock signal lines, nine clock signal lines, etc., and its driving principle is the same as the driving principle of four clock signal lines, and the repeated parts will not be repeated.

[0230] In addition, an embodiment of the present disclosure further provides a display panel, which includes the gate driving circuit of any one of the above embodiments.

[0231] In some embodiments, the display panel further includes M clock signal lines, where M is a positive integer greater than or equal to 3; the M clock signal lines are divided into M groups of clock signal line groups, and each of the 1 to M-1 groups of clock signal line groups includes two adjacent clock signal lines; the M-th group of clock signal line groups includes a first clock signal line and an M-th clock signal line; the N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group includes M cascaded shift registers, and the first clock signal terminal and the second clock signal terminal of the k-th shift register are connected to each other. The clock signal terminal is electrically connected to different clock signal lines in the kth group of clock signal line groups; k is a positive integer between 1 and M; for N cascaded shift registers, the first clock signal terminal of the i+1th stage shift register and the second clock signal terminal of the i-th stage shift register are both electrically connected to the same clock signal line; i is a positive integer between 1 and N-1; for any group of M+1 cascaded shift registers, the first clock signal terminal of the 1st shift register and the second clock signal terminal of the M+1th shift register are electrically connected to the same clock signal line.

[0232] Optionally, M is any integer between 3 and 20.

[0233] For example, M=4. Figure 27 As shown, taking four clock signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3 and the fourth clock signal line CLK4 as an example, the first group of clock signal line groups includes the first clock signal line CLK1 and the second clock signal line CLK2; the second group of clock signal line groups includes the second clock signal line CLK2 and the third clock signal line CLK3; the third group of clock signal line groups includes the third clock signal line CLK3 and the fourth clock signal line CLK4; and the fourth group of clock signal line groups includes the fourth clock signal line CLK4 and the first clock signal line CLK1. The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group includes 4 cascaded shift registers, the first clock signal end A of the first shift register GOA_1 is electrically connected to the first clock signal line CLK1, and the second clock signal end B of the first shift register GOA_1 is electrically connected to the second clock signal line CLK2; the first clock signal end A of the second shift register GOA_2 is electrically connected to the second clock signal line CLK2, and the second clock signal end B of the second shift register GOA_2 is electrically connected to the third clock signal line CLK3; the first clock signal end A of the third shift register GOA_3 is electrically connected to the third clock signal line CLK3, and the second clock signal end B of the third shift register GOA_3 is electrically connected to the fourth clock signal line CLK4; the first clock signal end A of the fourth shift register GOA_4 is electrically connected to the fourth clock signal line CLK4, and the second clock signal end B of the fourth shift register GOA_4 is electrically connected to the first clock signal line CLK1.

[0234] For example, M=5. Figure 28 As shown, taking five clock signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4 and the fifth clock signal line CLK5 as an example, the first group of clock signal line groups includes the first clock signal line CLK1 and the second clock signal line CLK2; the second group of clock signal line groups includes the second clock signal line CLK2 and the third clock signal line CLK3; the third group of clock signal line groups includes the third clock signal line CLK3 and the fourth clock signal line CLK4; the fourth group of clock signal line groups includes the fourth clock signal line CLK4 and the fifth clock signal line CLK5; and the fifth group of clock signal line groups includes the fifth clock signal line CLK5 and the first clock signal line CLK1. The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group includes 4 cascaded shift registers, the first clock signal end A of the first shift register GOA_1 is electrically connected to the first clock signal line CLK1, and the second clock signal end B of the first shift register GOA_1 is electrically connected to the second clock signal line CLK2; the first clock signal end A of the second shift register GOA_2 is electrically connected to the second clock signal line CLK2, and the second clock signal end B of the second shift register GOA_2 is electrically connected to the third clock signal line CLK3; the first clock signal end A of the third shift register GOA_3 is electrically connected to the second clock signal line CLK4, and the second clock signal end B of the third shift register GOA_3 is electrically connected to the third clock signal line CLK5; the first clock signal end A of the third shift register GOA_3 is electrically connected to the first clock signal line CLK5, and the second clock signal end B of the third shift register GOA_3 is electrically connected to the second clock signal line CLK6. The clock signal terminal A is electrically connected to the third clock signal line CLK3, and the second clock signal terminal B of the third shift register GOA_3 is electrically connected to the fourth clock signal line CLK4; the first clock signal terminal A of the fourth shift register GOA_4 is electrically connected to the fourth clock signal line CLK4, and the second clock signal terminal B of the fourth shift register GOA_4 is electrically connected to the fifth clock signal line CLK5; the first clock signal terminal A of the fifth shift register GOA_5 is electrically connected to the fifth clock signal line CLK5, and the second clock signal terminal B of the fifth shift register GOA_5 is electrically connected to the first clock signal line CLK1.

[0235] For example, M=6. Figure 29As shown, taking six clock signal lines, such as the first clock signal line CLK1, the second clock signal line CLK2, the third clock signal line CLK3, the fourth clock signal line CLK4, the fifth clock signal line CLK5 and the sixth clock signal line CLK6 as an example, the first group of clock signal line groups includes the first clock signal line CLK1 and the second clock signal line CLK2; the second group of clock signal line groups includes the second clock signal line CLK2 and the third clock signal line CLK3; the third group of clock signal line groups includes the third clock signal line CLK3 and the fourth clock signal line CLK4; the fourth group of clock signal line groups includes the fourth clock signal line CLK4 and the fifth clock signal line CLK5; the fifth group of clock signal line groups includes the fifth clock signal line CLK5 and the sixth clock signal line CLK6; and the sixth group of clock signal line groups includes the sixth clock signal line CLK6 and the first clock signal line CLK1. The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group includes 4 cascaded shift registers, the first clock signal end A of the first shift register GOA_1 is electrically connected to the first clock signal line CLK1, and the second clock signal end B of the first shift register GOA_1 is electrically connected to the second clock signal line CLK2; the first clock signal end A of the second shift register GOA_2 is electrically connected to the second clock signal line CLK2, and the second clock signal end B of the second shift register GOA_2 is electrically connected to the third clock signal line CLK3; the first clock signal end A of the third shift register GOA_3 is electrically connected to the third clock signal line CLK3, and the second clock signal end B of the third shift register GOA_3 is electrically connected to the third clock signal line CLK3. The clock signal terminal B is electrically connected to the fourth clock signal line CLK4; the first clock signal terminal A of the fourth shift register GOA_4 is electrically connected to the fourth clock signal line CLK4, and the second clock signal terminal B of the fourth shift register GOA_4 is electrically connected to the fifth clock signal line CLK5; the first clock signal terminal A of the fifth shift register GOA_5 is electrically connected to the fifth clock signal line CLK5, and the second clock signal terminal B of the fifth shift register GOA_5 is electrically connected to the sixth clock signal line CLK6; the first clock signal terminal A of the sixth shift register GOA_6 is electrically connected to the sixth clock signal line CLK6, and the second clock signal terminal B of the sixth shift register GOA_6 is electrically connected to the first clock signal line CLK1.

[0236] For another example, M can also be 3, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, etc.

[0237] In some embodiments, M=2; the display panel further includes two clock signal lines, namely a first clock signal line CLK1 and a second clock signal line CLK2. The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group including two cascaded shift registers, wherein the first clock signal terminal of the first shift register and the second clock signal terminal of the second shift register are electrically connected to the first clock signal line CLK1, and the first clock signal terminal of the second shift register and the second clock signal terminal of the second shift register are electrically connected to the second clock signal line.

[0238] like Figure 30 As shown, the first clock signal line group includes a first clock signal line CLK1 and a second clock signal line CLK2; the second clock signal line group includes a second clock signal line CLK2 and a third clock signal line CLK3. The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group including two cascaded shift registers. The first clock signal terminal A of the first shift register GOA_1 is electrically connected to the first clock signal line CLK1, and the second clock signal terminal B of the first shift register GOA_1 is electrically connected to the second clock signal line CLK2; the first clock signal terminal A of the second shift register GOA_2 is electrically connected to the second clock signal line CLK2, and the second clock signal terminal B of the second shift register GOA_2 is electrically connected to the third clock signal line CLK1.

[0239] In some embodiments, the display panel further comprises pixel units arranged in an array, wherein the pixel units comprise light emitting devices and pixel driving circuits for driving the light emitting devices. The N cascaded shift registers are respectively configured to drive N rows of pixel units. The pixel driving circuit may be, for example, Figure 26 Of course, the pixel driving circuit disclosed herein is not limited to 7T1C, and other driving modes may be selected, such as 4T2C (i.e., 4 transistors and 2 capacitors) structure, 3T1C (i.e., 3 transistors and 1 capacitor) structure, 5T1C (i.e., 5 transistors and 1 capacitor) structure, 8T1C (i.e., 8 transistors and 1 capacitor) structure, or 8T2C (i.e., 8 transistors and 2 capacitors) structure.

[0240] like Figure 26As shown, taking a 7T1C pixel driving circuit as an example, it specifically includes a first reset transistor M1, a threshold compensation transistor M2, a driving transistor M3, a data write transistor M4, a first emission control transistor M5, a second emission control transistor M6, a second reset transistor M7, and a fourth storage capacitor Cst. The second electrode of the data write transistor M4 is electrically connected to the first electrode of the driving transistor M3, the first electrode of the data write transistor M4 is electrically connected to the data line Data, and the control electrode of the data write transistor M4 is electrically connected to the first scan signal line Gate1. The first electrode of the first emission control transistor M5 is electrically connected to the first power supply voltage terminal VDD, the second electrode of the first emission control transistor M5 is electrically connected to the first electrode of the driving transistor M3, and the control electrode of the first emission control transistor M5 is electrically connected to the first emission control signal line EM1. The first plate of the fourth storage capacitor Cst is electrically connected to the first power supply voltage terminal VDD, and the second plate of the fourth storage capacitor Cst is electrically connected to the control electrode of the driving transistor M3. A first electrode of the threshold compensation transistor M2 is electrically connected to the second electrode of the driving transistor M3, a second electrode of the threshold compensation transistor M2 is electrically connected to the control electrode of the driving transistor M3, and the control electrode of the threshold compensation transistor M2 is electrically connected to the second scanning signal line Gate2. A first electrode of the second emission control transistor M6 is electrically connected to the second electrode of the driving transistor M3, a second electrode of the second emission control transistor M6 is electrically connected to the anode of the light-emitting device OLED, and a control electrode of the second emission control transistor M6 is electrically connected to the second emission control signal line EM2. A first electrode of the first reset transistor M1 is electrically connected to the first reset power supply terminal Vinit1, a second electrode of the first reset transistor M1 is electrically connected to the control electrode of the driving transistor M3, and a control electrode of the first reset transistor M1 is electrically connected to the first reset control signal line Rst1. A first electrode of the second reset transistor M7 is electrically connected to the second reset power supply terminal Vinit2, a second electrode of the second reset transistor M7 is electrically connected to the anode of the light-emitting device OLED, and a control electrode of the second reset transistor M7 is electrically connected to the second reset control signal line Rst2. The cathode of the light-emitting device OLED is electrically connected to the second power supply voltage terminal VSS.

[0241] Optionally, the signal output terminal OUT of the shift register is electrically connected to the gate electrode of the threshold compensation transistor M2 in the pixel driving circuit, that is, the second scanning signal line Gate2. The two clock signal lines drive the shift registers at each level, thereby driving the threshold compensation transistor M2 in the pixel driving circuit to turn on and off.

[0242] Optionally, the signal output terminal OUT of the shift register is electrically connected to the control electrode of the light-emitting control transistor in the pixel driving circuit. For example, the signal output terminal OUT of the shift register is electrically connected to the control electrode of the first light-emitting control transistor M5, that is, the first light-emitting control signal line EM1. For another example, the signal output terminal OUT of the shift register is electrically connected to the control electrode of the second light-emitting control transistor M6, that is, the second light-emitting control signal line EM2. The M clock signal lines drive each level of the shift register to output a high-level signal for a relatively long time (e.g., 5 hours corresponding to 4CLK, 7 hours corresponding to 5CLK, and 9 hours corresponding to 6CLK) to meet the requirements of the first light-emitting control transistor M5 and / or the second light-emitting control transistor M6 for controlling the light-emitting device OLED.

[0243] Optionally, the signal output terminal OUT of the shift register is electrically connected to the control electrode of the reset transistor in the pixel driving circuit. For example, the signal output terminal OUT of the shift register is electrically connected to the control electrode of the first reset transistor M1, that is, the first reset control signal line Rst1. For another example, the signal output terminal OUT of the shift register is electrically connected to the control electrode of the second reset transistor M7, that is, the second reset control signal line Rst2. The above-mentioned M clock signal lines drive the shift registers at each level to output a high-level signal for a longer time (such as 5 hours corresponding to 4CLK, 7 hours corresponding to 5CLK, and 9 hours corresponding to 6CLK) to meet the reset control of the first reset transistor M1 and / or the second reset transistor M7.

[0244] In addition, embodiments of the present disclosure further provide a display device comprising the display panel of any of the aforementioned embodiments. The display device may be, for example, a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted device, or any other product with a display function. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0245] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A shift register comprising an input subcircuit, a first control subcircuit, a second control subcircuit, a third control subcircuit, and an output subcircuit; The input sub-circuit is configured to control the potential of the first node using an input signal in response to a first clock signal; The first control subcircuit is configured to control the potential of the second node using a first power supply signal in response to the input signal; The second control subcircuit is configured to control the potential of the third node using a first effective potential in response to the potential of the second node; The third control subcircuit is configured to control the potential of the third node using the first effective potential or the second effective potential in response to the potential of the first node; The output subcircuit is configured to output the second power supply signal through the signal output terminal in response to the potential of the first node, or to output the first effective potential or the second effective potential through the signal output terminal in response to the potential of the third node.

2. The shift register according to claim 1, wherein: The first effective potential is a low potential, and the second effective potential is a high potential; The potential of the first power supply signal is the same as the second effective potential, and the potential of the second power supply signal is the same as the first effective potential.

3. The shift register according to claim 1, wherein: The second control sub-circuit is configured to control the potential of the third node using a first effective potential of a second clock signal in response to the potential of the second node.

4. The shift register according to claim 3, wherein: The second control subcircuit includes a third transistor and a first storage capacitor; The first electrode of the third transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; The first plate of the first storage capacitor is electrically connected to the second clock signal terminal, and the second plate is electrically connected to the second node.

5. The shift register according to claim 3, wherein: The shift register has some sub-timing phases in the timing control phase, and the first clock signal and the second clock signal are both the first effective potential. The shift register according to claim 5 , wherein: In the timing control stage, the rising edge of the first clock signal is located in the sub-timing stage where the first valid potential of the second clock signal is located, and the falling edge of the second clock signal is located in the sub-timing stage where the first valid potential of the first clock signal is located.

7. The shift register according to claim 1, wherein: The second control subcircuit is configured to control the potential of the third node using a second power signal transmitted by a second power line in response to the potential of the second node; The potential of the second power signal output by the second power line is the first effective potential.

8. The shift register according to claim 7, wherein: The second control subcircuit includes a third transistor and a first storage capacitor; The first electrode of the third transistor is electrically connected to the second power line, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the second node; The first plate of the first storage capacitor is electrically connected to a second clock signal terminal that transmits the second clock signal, and the second plate is electrically connected to the second node.

9. The shift register according to claim 1, wherein: The third control subcircuit is specifically configured to control the potential of the third node using the first clock signal in response to the potential of the first node.

10. The shift register according to claim 9, wherein: The third control subcircuit includes a fifth transistor; The first electrode of the fifth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the third node, and the control electrode is electrically connected to the first node.

11. The shift register according to claim 1, wherein: The third control subcircuit is specifically configured to control the potential of the third node in response to the potential of the first node using the first power signal transmitted by the first power line; the potential of the first power signal output by the first power line is the second effective potential.

12. The shift register according to claim 11, wherein: The third control subcircuit includes a fifth transistor; The fifth transistor has a first electrode electrically connected to the first power line, a second electrode electrically connected to the third node, and a control electrode electrically connected to the first node.

13. The shift register according to claim 9 or 11, wherein: The third control sub-circuit is further configured to control the potential of the first node using a second clock signal in response to the potential of the first node.

14. The shift register according to claim 13, wherein: The third control subcircuit further includes a ninth transistor and a second storage capacitor; The first electrode of the ninth transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the first node; The first plate of the second storage capacitor is electrically connected to the first node, and the second plate is electrically connected to the fourth node.

15. The shift register according to claim 1, wherein: The output sub-circuit is specifically configured to output the second power signal through the signal output terminal in response to the potential of the first node, or to output the first clock signal through the signal output terminal in response to the potential of the third node.

16. The shift register according to claim 15, wherein: The output sub-circuit includes a sixth transistor, a third storage capacitor and a seventh transistor; The first electrode of the sixth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node; The first plate of the third storage capacitor is electrically connected to the first clock signal terminal, and the second plate is electrically connected to the third node; The first electrode of the seventh transistor is electrically connected to the second power line transmitting the second power signal, the second electrode is electrically connected to the signal output end, and the control electrode is electrically connected to the first node.

17. The shift register according to claim 1, wherein: The output sub-circuit is specifically configured to output the second power signal through the signal output terminal in response to the potential of the first node, or to output the first power signal through the signal output terminal in response to the potential of the third node; The potential of the second power signal is the first effective potential; The potential of the first power signal is the second effective potential.

18. The shift register according to claim 17, wherein: The output sub-circuit includes a sixth transistor, a third storage capacitor and a seventh transistor; The first electrode of the sixth transistor is electrically connected to the first power line transmitting the first power signal, the second electrode is electrically connected to the signal output terminal, and the control electrode is electrically connected to the third node; The first plate of the third storage capacitor is electrically connected to the first power line, and the second plate is electrically connected to the third node; The first electrode of the seventh transistor is electrically connected to the second power line transmitting the second power signal, the second electrode is electrically connected to the signal output end, and the control electrode is electrically connected to the first node.

19. The shift register according to any one of claims 1 to 8 and 15 to 18, wherein: The shift register further includes an isolation subcircuit; the isolation subcircuit includes a fourth transistor and an eighth transistor; A first electrode of the fourth transistor is electrically connected to the first node, a second electrode is electrically connected to the fifth node, and a control electrode is electrically connected to a second power line transmitting the second power signal; The first electrode of the eighth transistor is electrically connected to the third node, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the second power line; The fifth node and the sixth node are both electrically connected to the output sub-circuit.

20. The shift register according to claim 19, wherein: The third control subcircuit includes a fifth transistor; The first electrode of the fifth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the fifth node; or, A first electrode of the fifth transistor is electrically connected to a first power line transmitting the first power signal, a second electrode is electrically connected to the sixth node, and a control electrode is electrically connected to the fifth node.

21. The shift register according to claim 20, wherein: The third control subcircuit further includes a ninth transistor and a second storage capacitor; The first electrode of the ninth transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the fifth node; The first plate of the second storage capacitor is electrically connected to the fifth node, and the second plate is electrically connected to the fourth node.

22. The shift register according to claim 19, wherein: The third control subcircuit includes a fifth transistor; The first electrode of the fifth transistor is electrically connected to the first clock signal terminal transmitting the first clock signal, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the first node; or, The first electrode of the fifth transistor is electrically connected to the first power line transmitting the first power signal, the second electrode is electrically connected to the sixth node, and the control electrode is electrically connected to the first node.

23. The shift register according to claim 22, wherein: The third control subcircuit further includes a ninth transistor and a second storage capacitor; The first electrode of the ninth transistor is electrically connected to the second clock signal terminal transmitting the second clock signal, the second electrode is electrically connected to the fourth node, and the control electrode is electrically connected to the fifth node; The first plate of the second storage capacitor is electrically connected to the fifth node, and the second plate is electrically connected to the fourth node.

24. The shift register according to claim 1, wherein: The input subcircuit includes a first transistor; the first control subcircuit includes a second transistor; The first electrode of the first transistor is electrically connected to the signal input terminal, the second electrode is electrically connected to the first node, and the control electrode is electrically connected to the first clock signal terminal that transmits the first clock signal; A first electrode of the second transistor is electrically connected to a first power line transmitting the first power signal, a second electrode is electrically connected to the second node, and a control electrode is electrically connected to the signal input terminal.

25. A shift register driving method, for driving and controlling the shift register according to any one of claims 1 to 10, 13 to 16, and 19 to 24; wherein: The timing control stage of the shift register includes a first sub-stage, a second sub-stage, a third sub-stage, a fourth sub-stage and a fifth sub-stage; In the first sub-phase, the potential of the input signal and the potential of the second clock signal are both the second effective potential, and the first clock signal is the first effective potential; The input sub-circuit writes the input signal to the first node under the control of the first clock signal; The output sub-circuit maintains outputting the potential of the previous sub-stage under the control of the potential of the first node; In the second sub-phase, the potential of the input signal is a second effective potential, and the potential of the second node, the potential of the first clock signal, and the potential of the second clock signal are all first effective potentials; the input sub-circuit writes the input signal to the first node under the control of the first clock signal; The second control subcircuit writes the second clock signal or the second power supply signal to the third node under the control of the potential of the second node; the output subcircuit maintains the output potential of the previous sub-stage under the control of the potential of the third node and the first clock signal; In the third sub-phase, the potential of the input signal and the potential of the first clock signal are both second effective potentials, and the potential of the second node and the potential of the second clock signal are first effective potentials; The second control subcircuit writes the second clock signal or the second power supply signal to the third node under the control of the potential of the second node; The output subcircuit outputs the first clock signal through the signal output terminal under the control of the potential of the third node and the first clock signal; In the fourth sub-phase, the potential of the input signal and the potential of the first clock signal are both first effective potentials, and the potential of the second clock signal is a second effective potential; the input sub-circuit writes the input signal to the first node under the control of the first clock signal; The first control subcircuit writes a first power signal to the second node under the control of the input signal; The third control subcircuit controls the potential of the third node using the first clock signal under the control of the potential of the first node; The output subcircuit outputs the first clock signal through the signal output terminal under the control of the potential of the third node and the first clock signal; In the fifth sub-phase, the potential of the input signal and the potential of the second clock signal are both first effective potentials, and the potential of the first clock signal is a second effective potential; The first control subcircuit writes a first power signal to the second node under the control of the input signal; The third control subcircuit controls the potential of the third node using the first clock signal under the control of the first node; The output sub-circuit outputs the second power signal through the signal output terminal under the control of the first node.

26. A gate drive circuit comprising N cascaded shift registers according to any one of claims 1 to 24; Except for the first stage shift register, the signal input end of the i+1th stage shift register is electrically connected to the signal output end of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer between 1 and N-1.

27. The gate driving circuit according to claim 26, wherein: Except for the first stage shift register, the first clock signal terminal of the (i+1)th stage shift register is electrically connected to the second clock signal terminal of the i-th stage shift register.

28. A display panel comprising the gate driving circuit according to claim 26 or 27.

29. The display panel according to claim 28, wherein: The display panel further includes M clock signal lines, where M is a positive integer greater than or equal to 3; The M clock signal lines are divided into M clock signal line groups, and each of the 1 to M-1 clock signal line groups includes two adjacent clock signal lines; the M-th clock signal line group includes the first clock signal line and the M-th clock signal line; The N cascaded shift registers in the gate drive circuit are divided into a plurality of groups, each group including M cascaded shift registers, and the first clock signal terminal and the second clock signal terminal of the k-th shift register are electrically connected to different clock signal lines in the k-th group of clock signal lines; k is a positive integer between 1 and M; For N cascaded shift registers, the first clock signal terminal of the i+1th stage shift register and the second clock signal terminal of the i-th stage shift register are both electrically connected to the same clock signal line; i is a positive integer between 1 and N-1; For any group of M+1 cascaded shift registers, the first clock signal terminal of the first shift register and the second clock signal terminal of the M+1th shift register are electrically connected to the same clock signal line.

30. The display panel according to claim 28, wherein M is any integer from 3 to 20.

31. The display panel according to claim 28, wherein The display panel also includes two clock signal lines; The N cascaded shift registers in the gate drive circuit are divided into multiple groups, each group includes two cascaded shift registers, and the first clock signal end of the first shift register and the second clock signal end of the second shift register are electrically connected to one clock signal line, and the first clock signal end of the second shift register and the second clock signal end of the second shift register are electrically connected to another clock signal line.

32. The display panel according to any one of claims 29 to 31, wherein: The display panel further includes pixel units arranged in an array, wherein the pixel units include light-emitting devices and pixel driving circuits for driving the light-emitting devices; The N cascaded shift registers are respectively configured to drive N rows of pixel units; The signal output end of the shift register is electrically connected to the control electrode of the threshold compensation transistor in the pixel driving circuit; or, the signal output end of the shift register is electrically connected to the control electrode of the light emitting control transistor in the pixel driving circuit; or, the signal output end of the shift register is electrically connected to the control electrode of the reset transistor in the pixel driving circuit.

33. A display device comprising the display panel according to any one of claims 28 to 32.

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